2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
35 #include "ir_visitor.h"
36 #include "ir_expression_flattening.h"
37 #include "ir_uniform.h"
38 #include "glsl_types.h"
39 #include "glsl_parser_extras.h"
40 #include "../glsl/program.h"
41 #include "ir_optimization.h"
45 #include "main/mtypes.h"
46 #include "main/shaderapi.h"
47 #include "main/shaderobj.h"
48 #include "main/uniforms.h"
50 #include "program/hash_table.h"
51 #include "program/prog_instruction.h"
52 #include "program/prog_optimize.h"
53 #include "program/prog_print.h"
54 #include "program/program.h"
55 #include "program/prog_parameter.h"
56 #include "program/sampler.h"
59 static int swizzle_for_size(int size
);
67 * This struct is a corresponding struct to Mesa prog_src_register, with
72 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
86 this->file
= PROGRAM_UNDEFINED
;
93 explicit src_reg(dst_reg reg
);
95 gl_register_file file
; /**< PROGRAM_* from Mesa */
96 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
97 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
98 int negate
; /**< NEGATE_XYZW mask from mesa */
99 /** Register index should be offset by the integer in this reg. */
105 dst_reg(gl_register_file file
, int writemask
)
109 this->writemask
= writemask
;
110 this->cond_mask
= COND_TR
;
111 this->reladdr
= NULL
;
116 this->file
= PROGRAM_UNDEFINED
;
119 this->cond_mask
= COND_TR
;
120 this->reladdr
= NULL
;
123 explicit dst_reg(src_reg reg
);
125 gl_register_file file
; /**< PROGRAM_* from Mesa */
126 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
127 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
129 /** Register index should be offset by the integer in this reg. */
133 } /* anonymous namespace */
135 src_reg::src_reg(dst_reg reg
)
137 this->file
= reg
.file
;
138 this->index
= reg
.index
;
139 this->swizzle
= SWIZZLE_XYZW
;
141 this->reladdr
= reg
.reladdr
;
144 dst_reg::dst_reg(src_reg reg
)
146 this->file
= reg
.file
;
147 this->index
= reg
.index
;
148 this->writemask
= WRITEMASK_XYZW
;
149 this->cond_mask
= COND_TR
;
150 this->reladdr
= reg
.reladdr
;
155 class ir_to_mesa_instruction
: public exec_node
{
157 DECLARE_RALLOC_CXX_OPERATORS(ir_to_mesa_instruction
)
162 /** Pointer to the ir source this tree came from for debugging */
164 GLboolean cond_update
;
166 int sampler
; /**< sampler index */
167 int tex_target
; /**< One of TEXTURE_*_INDEX */
168 GLboolean tex_shadow
;
171 class variable_storage
: public exec_node
{
173 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
174 : file(file
), index(index
), var(var
)
179 gl_register_file file
;
181 ir_variable
*var
; /* variable that maps to this, if any */
184 class function_entry
: public exec_node
{
186 ir_function_signature
*sig
;
189 * identifier of this function signature used by the program.
191 * At the point that Mesa instructions for function calls are
192 * generated, we don't know the address of the first instruction of
193 * the function body. So we make the BranchTarget that is called a
194 * small integer and rewrite them during set_branchtargets().
199 * Pointer to first instruction of the function body.
201 * Set during function body emits after main() is processed.
203 ir_to_mesa_instruction
*bgn_inst
;
206 * Index of the first instruction of the function body in actual
209 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
213 /** Storage for the return value. */
217 class ir_to_mesa_visitor
: public ir_visitor
{
219 ir_to_mesa_visitor();
220 ~ir_to_mesa_visitor();
222 function_entry
*current_function
;
224 struct gl_context
*ctx
;
225 struct gl_program
*prog
;
226 struct gl_shader_program
*shader_program
;
227 struct gl_shader_compiler_options
*options
;
231 variable_storage
*find_variable_storage(const ir_variable
*var
);
233 src_reg
get_temp(const glsl_type
*type
);
234 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
236 src_reg
src_reg_for_float(float val
);
239 * \name Visit methods
241 * As typical for the visitor pattern, there must be one \c visit method for
242 * each concrete subclass of \c ir_instruction. Virtual base classes within
243 * the hierarchy should not have \c visit methods.
246 virtual void visit(ir_variable
*);
247 virtual void visit(ir_loop
*);
248 virtual void visit(ir_loop_jump
*);
249 virtual void visit(ir_function_signature
*);
250 virtual void visit(ir_function
*);
251 virtual void visit(ir_expression
*);
252 virtual void visit(ir_swizzle
*);
253 virtual void visit(ir_dereference_variable
*);
254 virtual void visit(ir_dereference_array
*);
255 virtual void visit(ir_dereference_record
*);
256 virtual void visit(ir_assignment
*);
257 virtual void visit(ir_constant
*);
258 virtual void visit(ir_call
*);
259 virtual void visit(ir_return
*);
260 virtual void visit(ir_discard
*);
261 virtual void visit(ir_texture
*);
262 virtual void visit(ir_if
*);
263 virtual void visit(ir_emit_vertex
*);
264 virtual void visit(ir_end_primitive
*);
265 virtual void visit(ir_barrier
*);
270 /** List of variable_storage */
273 /** List of function_entry */
274 exec_list function_signatures
;
275 int next_signature_id
;
277 /** List of ir_to_mesa_instruction */
278 exec_list instructions
;
280 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
282 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
283 dst_reg dst
, src_reg src0
);
285 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
286 dst_reg dst
, src_reg src0
, src_reg src1
);
288 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
290 src_reg src0
, src_reg src1
, src_reg src2
);
293 * Emit the correct dot-product instruction for the type of arguments
295 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
301 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
302 dst_reg dst
, src_reg src0
);
304 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
305 dst_reg dst
, src_reg src0
, src_reg src1
);
307 bool try_emit_mad(ir_expression
*ir
,
309 bool try_emit_mad_for_and_not(ir_expression
*ir
,
312 void emit_swz(ir_expression
*ir
);
314 bool process_move_condition(ir_rvalue
*ir
);
316 void copy_propagate(void);
321 } /* anonymous namespace */
323 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
325 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
327 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
330 swizzle_for_size(int size
)
332 static const int size_swizzles
[4] = {
333 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
334 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
335 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
336 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
339 assert((size
>= 1) && (size
<= 4));
340 return size_swizzles
[size
- 1];
343 ir_to_mesa_instruction
*
344 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
346 src_reg src0
, src_reg src1
, src_reg src2
)
348 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
351 /* If we have to do relative addressing, we want to load the ARL
352 * reg directly for one of the regs, and preload the other reladdr
353 * sources into temps.
355 num_reladdr
+= dst
.reladdr
!= NULL
;
356 num_reladdr
+= src0
.reladdr
!= NULL
;
357 num_reladdr
+= src1
.reladdr
!= NULL
;
358 num_reladdr
+= src2
.reladdr
!= NULL
;
360 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
361 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
362 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
365 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
368 assert(num_reladdr
== 0);
377 this->instructions
.push_tail(inst
);
383 ir_to_mesa_instruction
*
384 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
385 dst_reg dst
, src_reg src0
, src_reg src1
)
387 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
390 ir_to_mesa_instruction
*
391 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
392 dst_reg dst
, src_reg src0
)
394 assert(dst
.writemask
!= 0);
395 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
398 ir_to_mesa_instruction
*
399 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
401 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
404 ir_to_mesa_instruction
*
405 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
406 dst_reg dst
, src_reg src0
, src_reg src1
,
409 static const enum prog_opcode dot_opcodes
[] = {
410 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
413 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
417 * Emits Mesa scalar opcodes to produce unique answers across channels.
419 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
420 * channel determines the result across all channels. So to do a vec4
421 * of this operation, we want to emit a scalar per source channel used
422 * to produce dest channels.
425 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
427 src_reg orig_src0
, src_reg orig_src1
)
430 int done_mask
= ~dst
.writemask
;
432 /* Mesa RCP is a scalar operation splatting results to all channels,
433 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
436 for (i
= 0; i
< 4; i
++) {
437 GLuint this_mask
= (1 << i
);
438 ir_to_mesa_instruction
*inst
;
439 src_reg src0
= orig_src0
;
440 src_reg src1
= orig_src1
;
442 if (done_mask
& this_mask
)
445 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
446 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
447 for (j
= i
+ 1; j
< 4; j
++) {
448 /* If there is another enabled component in the destination that is
449 * derived from the same inputs, generate its value on this pass as
452 if (!(done_mask
& (1 << j
)) &&
453 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
454 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
455 this_mask
|= (1 << j
);
458 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
459 src0_swiz
, src0_swiz
);
460 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
461 src1_swiz
, src1_swiz
);
463 inst
= emit(ir
, op
, dst
, src0
, src1
);
464 inst
->dst
.writemask
= this_mask
;
465 done_mask
|= this_mask
;
470 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
471 dst_reg dst
, src_reg src0
)
473 src_reg undef
= undef_src
;
475 undef
.swizzle
= SWIZZLE_XXXX
;
477 emit_scalar(ir
, op
, dst
, src0
, undef
);
481 ir_to_mesa_visitor::src_reg_for_float(float val
)
483 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
485 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
486 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
492 type_size(const struct glsl_type
*type
)
497 switch (type
->base_type
) {
500 case GLSL_TYPE_FLOAT
:
502 if (type
->is_matrix()) {
503 return type
->matrix_columns
;
505 /* Regardless of size of vector, it gets a vec4. This is bad
506 * packing for things like floats, but otherwise arrays become a
507 * mess. Hopefully a later pass over the code can pack scalars
508 * down if appropriate.
513 case GLSL_TYPE_DOUBLE
:
514 if (type
->is_matrix()) {
515 if (type
->vector_elements
> 2)
516 return type
->matrix_columns
* 2;
518 return type
->matrix_columns
;
520 if (type
->vector_elements
> 2)
526 case GLSL_TYPE_ARRAY
:
527 assert(type
->length
> 0);
528 return type_size(type
->fields
.array
) * type
->length
;
529 case GLSL_TYPE_STRUCT
:
531 for (i
= 0; i
< type
->length
; i
++) {
532 size
+= type_size(type
->fields
.structure
[i
].type
);
535 case GLSL_TYPE_SAMPLER
:
536 case GLSL_TYPE_IMAGE
:
537 /* Samplers take up one slot in UNIFORMS[], but they're baked in
541 case GLSL_TYPE_ATOMIC_UINT
:
543 case GLSL_TYPE_ERROR
:
544 case GLSL_TYPE_INTERFACE
:
545 case GLSL_TYPE_FUNCTION
:
546 assert(!"Invalid type in type_size");
554 * In the initial pass of codegen, we assign temporary numbers to
555 * intermediate results. (not SSA -- variable assignments will reuse
556 * storage). Actual register allocation for the Mesa VM occurs in a
557 * pass over the Mesa IR later.
560 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
564 src
.file
= PROGRAM_TEMPORARY
;
565 src
.index
= next_temp
;
567 next_temp
+= type_size(type
);
569 if (type
->is_array() || type
->is_record()) {
570 src
.swizzle
= SWIZZLE_NOOP
;
572 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
580 ir_to_mesa_visitor::find_variable_storage(const ir_variable
*var
)
582 foreach_in_list(variable_storage
, entry
, &this->variables
) {
583 if (entry
->var
== var
)
591 ir_to_mesa_visitor::visit(ir_variable
*ir
)
593 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
594 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
596 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
597 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
600 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
602 const ir_state_slot
*const slots
= ir
->get_state_slots();
603 assert(slots
!= NULL
);
605 /* Check if this statevar's setup in the STATE file exactly
606 * matches how we'll want to reference it as a
607 * struct/array/whatever. If not, then we need to move it into
608 * temporary storage and hope that it'll get copy-propagated
611 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
612 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
617 variable_storage
*storage
;
619 if (i
== ir
->get_num_state_slots()) {
620 /* We'll set the index later. */
621 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
622 this->variables
.push_tail(storage
);
626 /* The variable_storage constructor allocates slots based on the size
627 * of the type. However, this had better match the number of state
628 * elements that we're going to copy into the new temporary.
630 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
632 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
634 this->variables
.push_tail(storage
);
635 this->next_temp
+= type_size(ir
->type
);
637 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
641 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
642 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
643 (gl_state_index
*)slots
[i
].tokens
);
645 if (storage
->file
== PROGRAM_STATE_VAR
) {
646 if (storage
->index
== -1) {
647 storage
->index
= index
;
649 assert(index
== storage
->index
+ (int)i
);
652 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
653 src
.swizzle
= slots
[i
].swizzle
;
654 emit(ir
, OPCODE_MOV
, dst
, src
);
655 /* even a float takes up a whole vec4 reg in a struct/array. */
660 if (storage
->file
== PROGRAM_TEMPORARY
&&
661 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
662 linker_error(this->shader_program
,
663 "failed to load builtin uniform `%s' "
664 "(%d/%d regs loaded)\n",
665 ir
->name
, dst
.index
- storage
->index
,
666 type_size(ir
->type
));
672 ir_to_mesa_visitor::visit(ir_loop
*ir
)
674 emit(NULL
, OPCODE_BGNLOOP
);
676 visit_exec_list(&ir
->body_instructions
, this);
678 emit(NULL
, OPCODE_ENDLOOP
);
682 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
685 case ir_loop_jump::jump_break
:
686 emit(NULL
, OPCODE_BRK
);
688 case ir_loop_jump::jump_continue
:
689 emit(NULL
, OPCODE_CONT
);
696 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
703 ir_to_mesa_visitor::visit(ir_function
*ir
)
705 /* Ignore function bodies other than main() -- we shouldn't see calls to
706 * them since they should all be inlined before we get to ir_to_mesa.
708 if (strcmp(ir
->name
, "main") == 0) {
709 const ir_function_signature
*sig
;
712 sig
= ir
->matching_signature(NULL
, &empty
, false);
716 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
723 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
725 int nonmul_operand
= 1 - mul_operand
;
728 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
729 if (!expr
|| expr
->operation
!= ir_binop_mul
)
732 expr
->operands
[0]->accept(this);
734 expr
->operands
[1]->accept(this);
736 ir
->operands
[nonmul_operand
]->accept(this);
739 this->result
= get_temp(ir
->type
);
740 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
746 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
748 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
749 * implemented using multiplication, and logical-or is implemented using
750 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
751 * As result, the logical expression (a & !b) can be rewritten as:
755 * - (a * 1) - (a * b)
759 * This final expression can be implemented as a single MAD(a, -b, a)
763 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
765 const int other_operand
= 1 - try_operand
;
768 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
769 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
772 ir
->operands
[other_operand
]->accept(this);
774 expr
->operands
[0]->accept(this);
777 b
.negate
= ~b
.negate
;
779 this->result
= get_temp(ir
->type
);
780 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
786 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
787 src_reg
*reg
, int *num_reladdr
)
792 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
794 if (*num_reladdr
!= 1) {
795 src_reg temp
= get_temp(glsl_type::vec4_type
);
797 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
805 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
807 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
808 * This means that each of the operands is either an immediate value of -1,
809 * 0, or 1, or is a component from one source register (possibly with
812 uint8_t components
[4] = { 0 };
813 bool negate
[4] = { false };
814 ir_variable
*var
= NULL
;
816 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
817 ir_rvalue
*op
= ir
->operands
[i
];
819 assert(op
->type
->is_scalar());
822 switch (op
->ir_type
) {
823 case ir_type_constant
: {
825 assert(op
->type
->is_scalar());
827 const ir_constant
*const c
= op
->as_constant();
829 components
[i
] = SWIZZLE_ONE
;
830 } else if (c
->is_zero()) {
831 components
[i
] = SWIZZLE_ZERO
;
832 } else if (c
->is_negative_one()) {
833 components
[i
] = SWIZZLE_ONE
;
836 assert(!"SWZ constant must be 0.0 or 1.0.");
843 case ir_type_dereference_variable
: {
844 ir_dereference_variable
*const deref
=
845 (ir_dereference_variable
*) op
;
847 assert((var
== NULL
) || (deref
->var
== var
));
848 components
[i
] = SWIZZLE_X
;
854 case ir_type_expression
: {
855 ir_expression
*const expr
= (ir_expression
*) op
;
857 assert(expr
->operation
== ir_unop_neg
);
860 op
= expr
->operands
[0];
864 case ir_type_swizzle
: {
865 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
867 components
[i
] = swiz
->mask
.x
;
873 assert(!"Should not get here.");
881 ir_dereference_variable
*const deref
=
882 new(mem_ctx
) ir_dereference_variable(var
);
884 this->result
.file
= PROGRAM_UNDEFINED
;
886 if (this->result
.file
== PROGRAM_UNDEFINED
) {
887 printf("Failed to get tree for expression operand:\n");
896 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
900 src
.negate
= ((unsigned(negate
[0]) << 0)
901 | (unsigned(negate
[1]) << 1)
902 | (unsigned(negate
[2]) << 2)
903 | (unsigned(negate
[3]) << 3));
905 /* Storage for our result. Ideally for an assignment we'd be using the
906 * actual storage for the result here, instead.
908 const src_reg result_src
= get_temp(ir
->type
);
909 dst_reg result_dst
= dst_reg(result_src
);
911 /* Limit writes to the channels that will be used by result_src later.
912 * This does limit this temp's use as a temporary for multi-instruction
915 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
917 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
918 this->result
= result_src
;
922 ir_to_mesa_visitor::visit(ir_expression
*ir
)
924 unsigned int operand
;
925 src_reg op
[ARRAY_SIZE(ir
->operands
)];
929 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
931 if (ir
->operation
== ir_binop_add
) {
932 if (try_emit_mad(ir
, 1))
934 if (try_emit_mad(ir
, 0))
938 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
940 if (ir
->operation
== ir_binop_logic_and
) {
941 if (try_emit_mad_for_and_not(ir
, 1))
943 if (try_emit_mad_for_and_not(ir
, 0))
947 if (ir
->operation
== ir_quadop_vector
) {
952 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
953 this->result
.file
= PROGRAM_UNDEFINED
;
954 ir
->operands
[operand
]->accept(this);
955 if (this->result
.file
== PROGRAM_UNDEFINED
) {
956 printf("Failed to get tree for expression operand:\n");
957 ir
->operands
[operand
]->print();
961 op
[operand
] = this->result
;
963 /* Matrix expression operands should have been broken down to vector
964 * operations already.
966 assert(!ir
->operands
[operand
]->type
->is_matrix());
969 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
970 if (ir
->operands
[1]) {
971 vector_elements
= MAX2(vector_elements
,
972 ir
->operands
[1]->type
->vector_elements
);
975 this->result
.file
= PROGRAM_UNDEFINED
;
977 /* Storage for our result. Ideally for an assignment we'd be using
978 * the actual storage for the result here, instead.
980 result_src
= get_temp(ir
->type
);
981 /* convenience for the emit functions below. */
982 result_dst
= dst_reg(result_src
);
983 /* Limit writes to the channels that will be used by result_src later.
984 * This does limit this temp's use as a temporary for multi-instruction
987 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
989 switch (ir
->operation
) {
990 case ir_unop_logic_not
:
991 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
992 * older GPUs implement SEQ using multiple instructions (i915 uses two
993 * SGE instructions and a MUL instruction). Since our logic values are
994 * 0.0 and 1.0, 1-x also implements !x.
996 op
[0].negate
= ~op
[0].negate
;
997 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
1000 op
[0].negate
= ~op
[0].negate
;
1004 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1007 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1010 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1014 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1018 assert(!"not reached: should be handled by ir_explog_to_explog2");
1021 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1024 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1027 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1031 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1034 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1037 case ir_unop_saturate
: {
1038 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_MOV
,
1040 inst
->saturate
= true;
1043 case ir_unop_noise
: {
1044 const enum prog_opcode opcode
=
1045 prog_opcode(OPCODE_NOISE1
1046 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1047 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1049 emit(ir
, opcode
, result_dst
, op
[0]);
1054 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1057 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1061 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1064 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1067 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1068 assert(ir
->type
->is_integer());
1069 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1073 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1075 case ir_binop_greater
:
1076 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1078 case ir_binop_lequal
:
1079 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1081 case ir_binop_gequal
:
1082 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1084 case ir_binop_equal
:
1085 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1087 case ir_binop_nequal
:
1088 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1090 case ir_binop_all_equal
:
1091 /* "==" operator producing a scalar boolean. */
1092 if (ir
->operands
[0]->type
->is_vector() ||
1093 ir
->operands
[1]->type
->is_vector()) {
1094 src_reg temp
= get_temp(glsl_type::vec4_type
);
1095 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1097 /* After the dot-product, the value will be an integer on the
1098 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1100 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1102 /* Negating the result of the dot-product gives values on the range
1103 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1104 * achieved using SGE.
1106 src_reg sge_src
= result_src
;
1107 sge_src
.negate
= ~sge_src
.negate
;
1108 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1110 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1113 case ir_binop_any_nequal
:
1114 /* "!=" operator producing a scalar boolean. */
1115 if (ir
->operands
[0]->type
->is_vector() ||
1116 ir
->operands
[1]->type
->is_vector()) {
1117 src_reg temp
= get_temp(glsl_type::vec4_type
);
1118 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1120 /* After the dot-product, the value will be an integer on the
1121 * range [0,4]. Zero stays zero, and positive values become 1.0.
1123 ir_to_mesa_instruction
*const dp
=
1124 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1125 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1126 /* The clamping to [0,1] can be done for free in the fragment
1127 * shader with a saturate.
1129 dp
->saturate
= true;
1131 /* Negating the result of the dot-product gives values on the range
1132 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1133 * achieved using SLT.
1135 src_reg slt_src
= result_src
;
1136 slt_src
.negate
= ~slt_src
.negate
;
1137 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1140 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1145 assert(ir
->operands
[0]->type
->is_vector());
1147 /* After the dot-product, the value will be an integer on the
1148 * range [0,4]. Zero stays zero, and positive values become 1.0.
1150 ir_to_mesa_instruction
*const dp
=
1151 emit_dp(ir
, result_dst
, op
[0], op
[0],
1152 ir
->operands
[0]->type
->vector_elements
);
1153 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1154 /* The clamping to [0,1] can be done for free in the fragment
1155 * shader with a saturate.
1157 dp
->saturate
= true;
1159 /* Negating the result of the dot-product gives values on the range
1160 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1161 * is achieved using SLT.
1163 src_reg slt_src
= result_src
;
1164 slt_src
.negate
= ~slt_src
.negate
;
1165 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1170 case ir_binop_logic_xor
:
1171 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1174 case ir_binop_logic_or
: {
1175 /* After the addition, the value will be an integer on the
1176 * range [0,2]. Zero stays zero, and positive values become 1.0.
1178 ir_to_mesa_instruction
*add
=
1179 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1180 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1181 /* The clamping to [0,1] can be done for free in the fragment
1182 * shader with a saturate.
1184 add
->saturate
= true;
1186 /* Negating the result of the addition gives values on the range
1187 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1188 * is achieved using SLT.
1190 src_reg slt_src
= result_src
;
1191 slt_src
.negate
= ~slt_src
.negate
;
1192 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1197 case ir_binop_logic_and
:
1198 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1199 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1203 assert(ir
->operands
[0]->type
->is_vector());
1204 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1205 emit_dp(ir
, result_dst
, op
[0], op
[1],
1206 ir
->operands
[0]->type
->vector_elements
);
1210 /* sqrt(x) = x * rsq(x). */
1211 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1212 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1213 /* For incoming channels <= 0, set the result to 0. */
1214 op
[0].negate
= ~op
[0].negate
;
1215 emit(ir
, OPCODE_CMP
, result_dst
,
1216 op
[0], result_src
, src_reg_for_float(0.0));
1219 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1227 /* Mesa IR lacks types, ints are stored as truncated floats. */
1232 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1236 emit(ir
, OPCODE_SNE
, result_dst
,
1237 op
[0], src_reg_for_float(0.0));
1239 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1240 case ir_unop_bitcast_f2u
:
1241 case ir_unop_bitcast_i2f
:
1242 case ir_unop_bitcast_u2f
:
1245 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1248 op
[0].negate
= ~op
[0].negate
;
1249 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1250 result_src
.negate
= ~result_src
.negate
;
1253 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1256 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1258 case ir_unop_pack_snorm_2x16
:
1259 case ir_unop_pack_snorm_4x8
:
1260 case ir_unop_pack_unorm_2x16
:
1261 case ir_unop_pack_unorm_4x8
:
1262 case ir_unop_pack_half_2x16
:
1263 case ir_unop_pack_double_2x32
:
1264 case ir_unop_unpack_snorm_2x16
:
1265 case ir_unop_unpack_snorm_4x8
:
1266 case ir_unop_unpack_unorm_2x16
:
1267 case ir_unop_unpack_unorm_4x8
:
1268 case ir_unop_unpack_half_2x16
:
1269 case ir_unop_unpack_half_2x16_split_x
:
1270 case ir_unop_unpack_half_2x16_split_y
:
1271 case ir_unop_unpack_double_2x32
:
1272 case ir_binop_pack_half_2x16_split
:
1273 case ir_unop_bitfield_reverse
:
1274 case ir_unop_bit_count
:
1275 case ir_unop_find_msb
:
1276 case ir_unop_find_lsb
:
1284 case ir_unop_frexp_sig
:
1285 case ir_unop_frexp_exp
:
1286 assert(!"not supported");
1289 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1292 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1295 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1298 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1299 * hardware backends have no way to avoid Mesa IR generation
1300 * even if they don't use it, we need to emit "something" and
1303 case ir_binop_lshift
:
1304 case ir_binop_rshift
:
1305 case ir_binop_bit_and
:
1306 case ir_binop_bit_xor
:
1307 case ir_binop_bit_or
:
1308 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1311 case ir_unop_bit_not
:
1312 case ir_unop_round_even
:
1313 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1316 case ir_binop_ubo_load
:
1317 assert(!"not supported");
1321 /* ir_triop_lrp operands are (x, y, a) while
1322 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1324 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1327 case ir_binop_vector_extract
:
1331 case ir_triop_bitfield_extract
:
1332 case ir_triop_vector_insert
:
1333 case ir_quadop_bitfield_insert
:
1334 case ir_binop_ldexp
:
1336 case ir_binop_carry
:
1337 case ir_binop_borrow
:
1338 case ir_binop_imul_high
:
1339 case ir_unop_interpolate_at_centroid
:
1340 case ir_binop_interpolate_at_offset
:
1341 case ir_binop_interpolate_at_sample
:
1342 case ir_unop_dFdx_coarse
:
1343 case ir_unop_dFdx_fine
:
1344 case ir_unop_dFdy_coarse
:
1345 case ir_unop_dFdy_fine
:
1346 assert(!"not supported");
1349 case ir_quadop_vector
:
1350 /* This operation should have already been handled.
1352 assert(!"Should not get here.");
1356 this->result
= result_src
;
1361 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1367 /* Note that this is only swizzles in expressions, not those on the left
1368 * hand side of an assignment, which do write masking. See ir_assignment
1372 ir
->val
->accept(this);
1374 assert(src
.file
!= PROGRAM_UNDEFINED
);
1375 assert(ir
->type
->vector_elements
> 0);
1377 for (i
= 0; i
< 4; i
++) {
1378 if (i
< ir
->type
->vector_elements
) {
1381 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1384 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1387 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1390 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1394 /* If the type is smaller than a vec4, replicate the last
1397 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1401 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1407 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1409 variable_storage
*entry
= find_variable_storage(ir
->var
);
1410 ir_variable
*var
= ir
->var
;
1413 switch (var
->data
.mode
) {
1414 case ir_var_uniform
:
1415 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1416 var
->data
.location
);
1417 this->variables
.push_tail(entry
);
1419 case ir_var_shader_in
:
1420 /* The linker assigns locations for varyings and attributes,
1421 * including deprecated builtins (like gl_Color),
1422 * user-assigned generic attributes (glBindVertexLocation),
1423 * and user-defined varyings.
1425 assert(var
->data
.location
!= -1);
1426 entry
= new(mem_ctx
) variable_storage(var
,
1428 var
->data
.location
);
1430 case ir_var_shader_out
:
1431 assert(var
->data
.location
!= -1);
1432 entry
= new(mem_ctx
) variable_storage(var
,
1434 var
->data
.location
);
1436 case ir_var_system_value
:
1437 entry
= new(mem_ctx
) variable_storage(var
,
1438 PROGRAM_SYSTEM_VALUE
,
1439 var
->data
.location
);
1442 case ir_var_temporary
:
1443 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1445 this->variables
.push_tail(entry
);
1447 next_temp
+= type_size(var
->type
);
1452 printf("Failed to make storage for %s\n", var
->name
);
1457 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1461 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1465 int element_size
= type_size(ir
->type
);
1467 index
= ir
->array_index
->constant_expression_value();
1469 ir
->array
->accept(this);
1473 src
.index
+= index
->value
.i
[0] * element_size
;
1475 /* Variable index array dereference. It eats the "vec4" of the
1476 * base of the array and an index that offsets the Mesa register
1479 ir
->array_index
->accept(this);
1483 if (element_size
== 1) {
1484 index_reg
= this->result
;
1486 index_reg
= get_temp(glsl_type::float_type
);
1488 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1489 this->result
, src_reg_for_float(element_size
));
1492 /* If there was already a relative address register involved, add the
1493 * new and the old together to get the new offset.
1495 if (src
.reladdr
!= NULL
) {
1496 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1498 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1499 index_reg
, *src
.reladdr
);
1501 index_reg
= accum_reg
;
1504 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1505 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1508 /* If the type is smaller than a vec4, replicate the last channel out. */
1509 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1510 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1512 src
.swizzle
= SWIZZLE_NOOP
;
1518 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1521 const glsl_type
*struct_type
= ir
->record
->type
;
1524 ir
->record
->accept(this);
1526 for (i
= 0; i
< struct_type
->length
; i
++) {
1527 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1529 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1532 /* If the type is smaller than a vec4, replicate the last channel out. */
1533 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1534 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1536 this->result
.swizzle
= SWIZZLE_NOOP
;
1538 this->result
.index
+= offset
;
1542 * We want to be careful in assignment setup to hit the actual storage
1543 * instead of potentially using a temporary like we might with the
1544 * ir_dereference handler.
1547 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1549 /* The LHS must be a dereference. If the LHS is a variable indexed array
1550 * access of a vector, it must be separated into a series conditional moves
1551 * before reaching this point (see ir_vec_index_to_cond_assign).
1553 assert(ir
->as_dereference());
1554 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1556 assert(!deref_array
->array
->type
->is_vector());
1559 /* Use the rvalue deref handler for the most part. We'll ignore
1560 * swizzles in it and write swizzles using writemask, though.
1563 return dst_reg(v
->result
);
1567 * Process the condition of a conditional assignment
1569 * Examines the condition of a conditional assignment to generate the optimal
1570 * first operand of a \c CMP instruction. If the condition is a relational
1571 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1572 * used as the source for the \c CMP instruction. Otherwise the comparison
1573 * is processed to a boolean result, and the boolean result is used as the
1574 * operand to the CMP instruction.
1577 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1579 ir_rvalue
*src_ir
= ir
;
1581 bool switch_order
= false;
1583 ir_expression
*const expr
= ir
->as_expression();
1584 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1585 bool zero_on_left
= false;
1587 if (expr
->operands
[0]->is_zero()) {
1588 src_ir
= expr
->operands
[1];
1589 zero_on_left
= true;
1590 } else if (expr
->operands
[1]->is_zero()) {
1591 src_ir
= expr
->operands
[0];
1592 zero_on_left
= false;
1596 * (a < 0) T F F ( a < 0) T F F
1597 * (0 < a) F F T (-a < 0) F F T
1598 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1599 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1600 * (a > 0) F F T (-a < 0) F F T
1601 * (0 > a) T F F ( a < 0) T F F
1602 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1603 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1605 * Note that exchanging the order of 0 and 'a' in the comparison simply
1606 * means that the value of 'a' should be negated.
1609 switch (expr
->operation
) {
1611 switch_order
= false;
1612 negate
= zero_on_left
;
1615 case ir_binop_greater
:
1616 switch_order
= false;
1617 negate
= !zero_on_left
;
1620 case ir_binop_lequal
:
1621 switch_order
= true;
1622 negate
= !zero_on_left
;
1625 case ir_binop_gequal
:
1626 switch_order
= true;
1627 negate
= zero_on_left
;
1631 /* This isn't the right kind of comparison afterall, so make sure
1632 * the whole condition is visited.
1640 src_ir
->accept(this);
1642 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1643 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1644 * choose which value OPCODE_CMP produces without an extra instruction
1645 * computing the condition.
1648 this->result
.negate
= ~this->result
.negate
;
1650 return switch_order
;
1654 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1660 ir
->rhs
->accept(this);
1663 l
= get_assignment_lhs(ir
->lhs
, this);
1665 /* FINISHME: This should really set to the correct maximal writemask for each
1666 * FINISHME: component written (in the loops below). This case can only
1667 * FINISHME: occur for matrices, arrays, and structures.
1669 if (ir
->write_mask
== 0) {
1670 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1671 l
.writemask
= WRITEMASK_XYZW
;
1672 } else if (ir
->lhs
->type
->is_scalar()) {
1673 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1674 * FINISHME: W component of fragment shader output zero, work correctly.
1676 l
.writemask
= WRITEMASK_XYZW
;
1679 int first_enabled_chan
= 0;
1682 assert(ir
->lhs
->type
->is_vector());
1683 l
.writemask
= ir
->write_mask
;
1685 for (int i
= 0; i
< 4; i
++) {
1686 if (l
.writemask
& (1 << i
)) {
1687 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1692 /* Swizzle a small RHS vector into the channels being written.
1694 * glsl ir treats write_mask as dictating how many channels are
1695 * present on the RHS while Mesa IR treats write_mask as just
1696 * showing which channels of the vec4 RHS get written.
1698 for (int i
= 0; i
< 4; i
++) {
1699 if (l
.writemask
& (1 << i
))
1700 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1702 swizzles
[i
] = first_enabled_chan
;
1704 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1705 swizzles
[2], swizzles
[3]);
1708 assert(l
.file
!= PROGRAM_UNDEFINED
);
1709 assert(r
.file
!= PROGRAM_UNDEFINED
);
1711 if (ir
->condition
) {
1712 const bool switch_order
= this->process_move_condition(ir
->condition
);
1713 src_reg condition
= this->result
;
1715 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1717 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1719 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1726 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1727 emit(ir
, OPCODE_MOV
, l
, r
);
1736 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1739 GLfloat stack_vals
[4] = { 0 };
1740 GLfloat
*values
= stack_vals
;
1743 /* Unfortunately, 4 floats is all we can get into
1744 * _mesa_add_unnamed_constant. So, make a temp to store an
1745 * aggregate constant and move each constant value into it. If we
1746 * get lucky, copy propagation will eliminate the extra moves.
1749 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1750 src_reg temp_base
= get_temp(ir
->type
);
1751 dst_reg temp
= dst_reg(temp_base
);
1753 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
1754 int size
= type_size(field_value
->type
);
1758 field_value
->accept(this);
1761 for (i
= 0; i
< (unsigned int)size
; i
++) {
1762 emit(ir
, OPCODE_MOV
, temp
, src
);
1768 this->result
= temp_base
;
1772 if (ir
->type
->is_array()) {
1773 src_reg temp_base
= get_temp(ir
->type
);
1774 dst_reg temp
= dst_reg(temp_base
);
1775 int size
= type_size(ir
->type
->fields
.array
);
1779 for (i
= 0; i
< ir
->type
->length
; i
++) {
1780 ir
->array_elements
[i
]->accept(this);
1782 for (int j
= 0; j
< size
; j
++) {
1783 emit(ir
, OPCODE_MOV
, temp
, src
);
1789 this->result
= temp_base
;
1793 if (ir
->type
->is_matrix()) {
1794 src_reg mat
= get_temp(ir
->type
);
1795 dst_reg mat_column
= dst_reg(mat
);
1797 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1798 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1799 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1801 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1802 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1803 (gl_constant_value
*) values
,
1804 ir
->type
->vector_elements
,
1806 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1815 src
.file
= PROGRAM_CONSTANT
;
1816 switch (ir
->type
->base_type
) {
1817 case GLSL_TYPE_FLOAT
:
1818 values
= &ir
->value
.f
[0];
1820 case GLSL_TYPE_UINT
:
1821 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1822 values
[i
] = ir
->value
.u
[i
];
1826 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1827 values
[i
] = ir
->value
.i
[i
];
1830 case GLSL_TYPE_BOOL
:
1831 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1832 values
[i
] = ir
->value
.b
[i
];
1836 assert(!"Non-float/uint/int/bool constant");
1839 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1840 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1841 (gl_constant_value
*) values
,
1842 ir
->type
->vector_elements
,
1843 &this->result
.swizzle
);
1847 ir_to_mesa_visitor::visit(ir_call
*)
1849 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
1853 ir_to_mesa_visitor::visit(ir_texture
*ir
)
1855 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
1856 dst_reg result_dst
, coord_dst
;
1857 ir_to_mesa_instruction
*inst
= NULL
;
1858 prog_opcode opcode
= OPCODE_NOP
;
1860 if (ir
->op
== ir_txs
)
1861 this->result
= src_reg_for_float(0.0);
1863 ir
->coordinate
->accept(this);
1865 /* Put our coords in a temp. We'll need to modify them for shadow,
1866 * projection, or LOD, so the only case we'd use it as is is if
1867 * we're doing plain old texturing. Mesa IR optimization should
1868 * handle cleaning up our mess in that case.
1870 coord
= get_temp(glsl_type::vec4_type
);
1871 coord_dst
= dst_reg(coord
);
1872 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1874 if (ir
->projector
) {
1875 ir
->projector
->accept(this);
1876 projector
= this->result
;
1879 /* Storage for our result. Ideally for an assignment we'd be using
1880 * the actual storage for the result here, instead.
1882 result_src
= get_temp(glsl_type::vec4_type
);
1883 result_dst
= dst_reg(result_src
);
1888 opcode
= OPCODE_TEX
;
1891 opcode
= OPCODE_TXB
;
1892 ir
->lod_info
.bias
->accept(this);
1893 lod_info
= this->result
;
1896 /* Pretend to be TXL so the sampler, coordinate, lod are available */
1898 opcode
= OPCODE_TXL
;
1899 ir
->lod_info
.lod
->accept(this);
1900 lod_info
= this->result
;
1903 opcode
= OPCODE_TXD
;
1904 ir
->lod_info
.grad
.dPdx
->accept(this);
1906 ir
->lod_info
.grad
.dPdy
->accept(this);
1910 assert(!"Unexpected ir_txf_ms opcode");
1913 assert(!"Unexpected ir_lod opcode");
1916 assert(!"Unexpected ir_tg4 opcode");
1918 case ir_query_levels
:
1919 assert(!"Unexpected ir_query_levels opcode");
1923 const glsl_type
*sampler_type
= ir
->sampler
->type
;
1925 if (ir
->projector
) {
1926 if (opcode
== OPCODE_TEX
) {
1927 /* Slot the projector in as the last component of the coord. */
1928 coord_dst
.writemask
= WRITEMASK_W
;
1929 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
1930 coord_dst
.writemask
= WRITEMASK_XYZW
;
1931 opcode
= OPCODE_TXP
;
1933 src_reg coord_w
= coord
;
1934 coord_w
.swizzle
= SWIZZLE_WWWW
;
1936 /* For the other TEX opcodes there's no projective version
1937 * since the last slot is taken up by lod info. Do the
1938 * projective divide now.
1940 coord_dst
.writemask
= WRITEMASK_W
;
1941 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
1943 /* In the case where we have to project the coordinates "by hand,"
1944 * the shadow comparitor value must also be projected.
1946 src_reg tmp_src
= coord
;
1947 if (ir
->shadow_comparitor
) {
1948 /* Slot the shadow value in as the second to last component of the
1951 ir
->shadow_comparitor
->accept(this);
1953 tmp_src
= get_temp(glsl_type::vec4_type
);
1954 dst_reg tmp_dst
= dst_reg(tmp_src
);
1956 /* Projective division not allowed for array samplers. */
1957 assert(!sampler_type
->sampler_array
);
1959 tmp_dst
.writemask
= WRITEMASK_Z
;
1960 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
1962 tmp_dst
.writemask
= WRITEMASK_XY
;
1963 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
1966 coord_dst
.writemask
= WRITEMASK_XYZ
;
1967 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
1969 coord_dst
.writemask
= WRITEMASK_XYZW
;
1970 coord
.swizzle
= SWIZZLE_XYZW
;
1974 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
1975 * comparitor was put in the correct place (and projected) by the code,
1976 * above, that handles by-hand projection.
1978 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
1979 /* Slot the shadow value in as the second to last component of the
1982 ir
->shadow_comparitor
->accept(this);
1984 /* XXX This will need to be updated for cubemap array samplers. */
1985 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
1986 sampler_type
->sampler_array
) {
1987 coord_dst
.writemask
= WRITEMASK_W
;
1989 coord_dst
.writemask
= WRITEMASK_Z
;
1992 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1993 coord_dst
.writemask
= WRITEMASK_XYZW
;
1996 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
1997 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
1998 coord_dst
.writemask
= WRITEMASK_W
;
1999 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
2000 coord_dst
.writemask
= WRITEMASK_XYZW
;
2003 if (opcode
== OPCODE_TXD
)
2004 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
2006 inst
= emit(ir
, opcode
, result_dst
, coord
);
2008 if (ir
->shadow_comparitor
)
2009 inst
->tex_shadow
= GL_TRUE
;
2011 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
2012 this->shader_program
,
2015 switch (sampler_type
->sampler_dimensionality
) {
2016 case GLSL_SAMPLER_DIM_1D
:
2017 inst
->tex_target
= (sampler_type
->sampler_array
)
2018 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2020 case GLSL_SAMPLER_DIM_2D
:
2021 inst
->tex_target
= (sampler_type
->sampler_array
)
2022 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2024 case GLSL_SAMPLER_DIM_3D
:
2025 inst
->tex_target
= TEXTURE_3D_INDEX
;
2027 case GLSL_SAMPLER_DIM_CUBE
:
2028 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2030 case GLSL_SAMPLER_DIM_RECT
:
2031 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2033 case GLSL_SAMPLER_DIM_BUF
:
2034 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2036 case GLSL_SAMPLER_DIM_EXTERNAL
:
2037 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2040 assert(!"Should not get here.");
2043 this->result
= result_src
;
2047 ir_to_mesa_visitor::visit(ir_return
*ir
)
2049 /* Non-void functions should have been inlined. We may still emit RETs
2050 * from main() unless the EmitNoMainReturn option is set.
2052 assert(!ir
->get_value());
2053 emit(ir
, OPCODE_RET
);
2057 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2059 if (ir
->condition
) {
2060 ir
->condition
->accept(this);
2061 this->result
.negate
= ~this->result
.negate
;
2062 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2064 emit(ir
, OPCODE_KIL_NV
);
2069 ir_to_mesa_visitor::visit(ir_if
*ir
)
2071 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2072 ir_to_mesa_instruction
*prev_inst
;
2074 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2076 ir
->condition
->accept(this);
2077 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2079 if (this->options
->EmitCondCodes
) {
2080 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2082 /* See if we actually generated any instruction for generating
2083 * the condition. If not, then cook up a move to a temp so we
2084 * have something to set cond_update on.
2086 if (cond_inst
== prev_inst
) {
2087 src_reg temp
= get_temp(glsl_type::bool_type
);
2088 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2090 cond_inst
->cond_update
= GL_TRUE
;
2092 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2093 if_inst
->dst
.cond_mask
= COND_NE
;
2095 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2098 this->instructions
.push_tail(if_inst
);
2100 visit_exec_list(&ir
->then_instructions
, this);
2102 if (!ir
->else_instructions
.is_empty()) {
2103 emit(ir
->condition
, OPCODE_ELSE
);
2104 visit_exec_list(&ir
->else_instructions
, this);
2107 emit(ir
->condition
, OPCODE_ENDIF
);
2111 ir_to_mesa_visitor::visit(ir_emit_vertex
*)
2113 assert(!"Geometry shaders not supported.");
2117 ir_to_mesa_visitor::visit(ir_end_primitive
*)
2119 assert(!"Geometry shaders not supported.");
2123 ir_to_mesa_visitor::visit(ir_barrier
*)
2125 unreachable("GLSL barrier() not supported.");
2128 ir_to_mesa_visitor::ir_to_mesa_visitor()
2130 result
.file
= PROGRAM_UNDEFINED
;
2132 next_signature_id
= 1;
2133 current_function
= NULL
;
2134 mem_ctx
= ralloc_context(NULL
);
2137 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2139 ralloc_free(mem_ctx
);
2142 static struct prog_src_register
2143 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2145 struct prog_src_register mesa_reg
;
2147 mesa_reg
.File
= reg
.file
;
2148 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2149 mesa_reg
.Index
= reg
.index
;
2150 mesa_reg
.Swizzle
= reg
.swizzle
;
2151 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2152 mesa_reg
.Negate
= reg
.negate
;
2154 mesa_reg
.HasIndex2
= GL_FALSE
;
2155 mesa_reg
.RelAddr2
= 0;
2156 mesa_reg
.Index2
= 0;
2162 set_branchtargets(ir_to_mesa_visitor
*v
,
2163 struct prog_instruction
*mesa_instructions
,
2164 int num_instructions
)
2166 int if_count
= 0, loop_count
= 0;
2167 int *if_stack
, *loop_stack
;
2168 int if_stack_pos
= 0, loop_stack_pos
= 0;
2171 for (i
= 0; i
< num_instructions
; i
++) {
2172 switch (mesa_instructions
[i
].Opcode
) {
2176 case OPCODE_BGNLOOP
:
2181 mesa_instructions
[i
].BranchTarget
= -1;
2188 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2189 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2191 for (i
= 0; i
< num_instructions
; i
++) {
2192 switch (mesa_instructions
[i
].Opcode
) {
2194 if_stack
[if_stack_pos
] = i
;
2198 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2199 if_stack
[if_stack_pos
- 1] = i
;
2202 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2205 case OPCODE_BGNLOOP
:
2206 loop_stack
[loop_stack_pos
] = i
;
2209 case OPCODE_ENDLOOP
:
2211 /* Rewrite any breaks/conts at this nesting level (haven't
2212 * already had a BranchTarget assigned) to point to the end
2215 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2216 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2217 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2218 if (mesa_instructions
[j
].BranchTarget
== -1) {
2219 mesa_instructions
[j
].BranchTarget
= i
;
2223 /* The loop ends point at each other. */
2224 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2225 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2228 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
2229 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2230 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2242 print_program(struct prog_instruction
*mesa_instructions
,
2243 ir_instruction
**mesa_instruction_annotation
,
2244 int num_instructions
)
2246 ir_instruction
*last_ir
= NULL
;
2250 for (i
= 0; i
< num_instructions
; i
++) {
2251 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2252 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2254 fprintf(stdout
, "%3d: ", i
);
2256 if (last_ir
!= ir
&& ir
) {
2259 for (j
= 0; j
< indent
; j
++) {
2260 fprintf(stdout
, " ");
2266 fprintf(stdout
, " "); /* line number spacing. */
2269 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2270 PROG_PRINT_DEBUG
, NULL
);
2276 class add_uniform_to_shader
: public program_resource_visitor
{
2278 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2279 struct gl_program_parameter_list
*params
,
2280 gl_shader_stage shader_type
)
2281 : shader_program(shader_program
), params(params
), idx(-1),
2282 shader_type(shader_type
)
2287 void process(ir_variable
*var
)
2290 this->program_resource_visitor::process(var
);
2292 var
->data
.location
= this->idx
;
2296 virtual void visit_field(const glsl_type
*type
, const char *name
,
2299 struct gl_shader_program
*shader_program
;
2300 struct gl_program_parameter_list
*params
;
2302 gl_shader_stage shader_type
;
2305 } /* anonymous namespace */
2308 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2315 if (type
->is_vector() || type
->is_scalar()) {
2316 size
= type
->vector_elements
;
2317 if (type
->is_double())
2320 size
= type_size(type
) * 4;
2323 gl_register_file file
;
2324 if (type
->without_array()->is_sampler()) {
2325 file
= PROGRAM_SAMPLER
;
2327 file
= PROGRAM_UNIFORM
;
2330 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2332 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2335 /* Sampler uniform values are stored in prog->SamplerUnits,
2336 * and the entry in that array is selected by this index we
2337 * store in ParameterValues[].
2339 if (file
== PROGRAM_SAMPLER
) {
2342 this->shader_program
->UniformHash
->get(location
,
2343 params
->Parameters
[index
].Name
);
2349 struct gl_uniform_storage
*storage
=
2350 &this->shader_program
->UniformStorage
[location
];
2352 assert(storage
->sampler
[shader_type
].active
);
2354 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2355 params
->ParameterValues
[index
+ j
][0].f
=
2356 storage
->sampler
[shader_type
].index
+ j
;
2360 /* The first part of the uniform that's processed determines the base
2361 * location of the whole uniform (for structures).
2368 * Generate the program parameters list for the user uniforms in a shader
2370 * \param shader_program Linked shader program. This is only used to
2371 * emit possible link errors to the info log.
2372 * \param sh Shader whose uniforms are to be processed.
2373 * \param params Parameter list to be filled in.
2376 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2378 struct gl_shader
*sh
,
2379 struct gl_program_parameter_list
2382 add_uniform_to_shader
add(shader_program
, params
, sh
->Stage
);
2384 foreach_in_list(ir_instruction
, node
, sh
->ir
) {
2385 ir_variable
*var
= node
->as_variable();
2387 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
2388 || var
->is_in_uniform_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2396 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2397 struct gl_shader_program
*shader_program
,
2398 struct gl_program_parameter_list
*params
)
2400 /* After adding each uniform to the parameter list, connect the storage for
2401 * the parameter with the tracking structure used by the API for the
2404 unsigned last_location
= unsigned(~0);
2405 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2406 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2411 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2417 struct gl_uniform_storage
*storage
=
2418 &shader_program
->UniformStorage
[location
];
2420 /* Do not associate any uniform storage to built-in uniforms */
2421 if (storage
->builtin
)
2424 if (location
!= last_location
) {
2425 enum gl_uniform_driver_format format
= uniform_native
;
2427 unsigned columns
= 0;
2428 int dmul
= 4 * sizeof(float);
2429 switch (storage
->type
->base_type
) {
2430 case GLSL_TYPE_UINT
:
2431 assert(ctx
->Const
.NativeIntegers
);
2432 format
= uniform_native
;
2437 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2441 case GLSL_TYPE_DOUBLE
:
2442 if (storage
->type
->vector_elements
> 2)
2445 case GLSL_TYPE_FLOAT
:
2446 format
= uniform_native
;
2447 columns
= storage
->type
->matrix_columns
;
2449 case GLSL_TYPE_BOOL
:
2450 format
= uniform_native
;
2453 case GLSL_TYPE_SAMPLER
:
2454 case GLSL_TYPE_IMAGE
:
2455 format
= uniform_native
;
2458 case GLSL_TYPE_ATOMIC_UINT
:
2459 case GLSL_TYPE_ARRAY
:
2460 case GLSL_TYPE_VOID
:
2461 case GLSL_TYPE_STRUCT
:
2462 case GLSL_TYPE_ERROR
:
2463 case GLSL_TYPE_INTERFACE
:
2464 case GLSL_TYPE_FUNCTION
:
2465 assert(!"Should not get here.");
2469 _mesa_uniform_attach_driver_storage(storage
,
2473 ¶ms
->ParameterValues
[i
]);
2475 /* After attaching the driver's storage to the uniform, propagate any
2476 * data from the linker's backing store. This will cause values from
2477 * initializers in the source code to be copied over.
2479 _mesa_propagate_uniforms_to_driver_storage(storage
,
2481 MAX2(1, storage
->array_elements
));
2483 last_location
= location
;
2489 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2490 * channels for copy propagation and updates following instructions to
2491 * use the original versions.
2493 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2494 * will occur. As an example, a TXP production before this pass:
2496 * 0: MOV TEMP[1], INPUT[4].xyyy;
2497 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2498 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2502 * 0: MOV TEMP[1], INPUT[4].xyyy;
2503 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2504 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2506 * which allows for dead code elimination on TEMP[1]'s writes.
2509 ir_to_mesa_visitor::copy_propagate(void)
2511 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2512 ir_to_mesa_instruction
*,
2513 this->next_temp
* 4);
2514 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2517 foreach_in_list(ir_to_mesa_instruction
, inst
, &this->instructions
) {
2518 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2519 || inst
->dst
.index
< this->next_temp
);
2521 /* First, do any copy propagation possible into the src regs. */
2522 for (int r
= 0; r
< 3; r
++) {
2523 ir_to_mesa_instruction
*first
= NULL
;
2525 int acp_base
= inst
->src
[r
].index
* 4;
2527 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2528 inst
->src
[r
].reladdr
)
2531 /* See if we can find entries in the ACP consisting of MOVs
2532 * from the same src register for all the swizzled channels
2533 * of this src register reference.
2535 for (int i
= 0; i
< 4; i
++) {
2536 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2537 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2544 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2549 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2550 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2558 /* We've now validated that we can copy-propagate to
2559 * replace this src register reference. Do it.
2561 inst
->src
[r
].file
= first
->src
[0].file
;
2562 inst
->src
[r
].index
= first
->src
[0].index
;
2565 for (int i
= 0; i
< 4; i
++) {
2566 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2567 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2568 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2571 inst
->src
[r
].swizzle
= swizzle
;
2576 case OPCODE_BGNLOOP
:
2577 case OPCODE_ENDLOOP
:
2578 /* End of a basic block, clear the ACP entirely. */
2579 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2588 /* Clear all channels written inside the block from the ACP, but
2589 * leaving those that were not touched.
2591 for (int r
= 0; r
< this->next_temp
; r
++) {
2592 for (int c
= 0; c
< 4; c
++) {
2593 if (!acp
[4 * r
+ c
])
2596 if (acp_level
[4 * r
+ c
] >= level
)
2597 acp
[4 * r
+ c
] = NULL
;
2600 if (inst
->op
== OPCODE_ENDIF
)
2605 /* Continuing the block, clear any written channels from
2608 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2609 /* Any temporary might be written, so no copy propagation
2610 * across this instruction.
2612 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2613 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2614 inst
->dst
.reladdr
) {
2615 /* Any output might be written, so no copy propagation
2616 * from outputs across this instruction.
2618 for (int r
= 0; r
< this->next_temp
; r
++) {
2619 for (int c
= 0; c
< 4; c
++) {
2620 if (!acp
[4 * r
+ c
])
2623 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2624 acp
[4 * r
+ c
] = NULL
;
2627 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2628 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2629 /* Clear where it's used as dst. */
2630 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2631 for (int c
= 0; c
< 4; c
++) {
2632 if (inst
->dst
.writemask
& (1 << c
)) {
2633 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2638 /* Clear where it's used as src. */
2639 for (int r
= 0; r
< this->next_temp
; r
++) {
2640 for (int c
= 0; c
< 4; c
++) {
2641 if (!acp
[4 * r
+ c
])
2644 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2646 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2647 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2648 inst
->dst
.writemask
& (1 << src_chan
))
2650 acp
[4 * r
+ c
] = NULL
;
2658 /* If this is a copy, add it to the ACP. */
2659 if (inst
->op
== OPCODE_MOV
&&
2660 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2661 !(inst
->dst
.file
== inst
->src
[0].file
&&
2662 inst
->dst
.index
== inst
->src
[0].index
) &&
2663 !inst
->dst
.reladdr
&&
2665 !inst
->src
[0].reladdr
&&
2666 !inst
->src
[0].negate
) {
2667 for (int i
= 0; i
< 4; i
++) {
2668 if (inst
->dst
.writemask
& (1 << i
)) {
2669 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2670 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2676 ralloc_free(acp_level
);
2682 * Convert a shader's GLSL IR into a Mesa gl_program.
2684 static struct gl_program
*
2685 get_mesa_program(struct gl_context
*ctx
,
2686 struct gl_shader_program
*shader_program
,
2687 struct gl_shader
*shader
)
2689 ir_to_mesa_visitor v
;
2690 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2691 ir_instruction
**mesa_instruction_annotation
;
2693 struct gl_program
*prog
;
2694 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
2695 const char *target_string
= _mesa_shader_stage_to_string(shader
->Stage
);
2696 struct gl_shader_compiler_options
*options
=
2697 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
2699 validate_ir_tree(shader
->ir
);
2701 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2704 prog
->Parameters
= _mesa_new_parameter_list();
2707 v
.shader_program
= shader_program
;
2708 v
.options
= options
;
2710 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2713 /* Emit Mesa IR for main(). */
2714 visit_exec_list(shader
->ir
, &v
);
2715 v
.emit(NULL
, OPCODE_END
);
2717 prog
->NumTemporaries
= v
.next_temp
;
2719 unsigned num_instructions
= v
.instructions
.length();
2722 (struct prog_instruction
*)calloc(num_instructions
,
2723 sizeof(*mesa_instructions
));
2724 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2729 /* Convert ir_mesa_instructions into prog_instructions.
2731 mesa_inst
= mesa_instructions
;
2733 foreach_in_list(const ir_to_mesa_instruction
, inst
, &v
.instructions
) {
2734 mesa_inst
->Opcode
= inst
->op
;
2735 mesa_inst
->CondUpdate
= inst
->cond_update
;
2737 mesa_inst
->Saturate
= GL_TRUE
;
2738 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2739 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2740 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2741 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2742 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2743 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2744 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2745 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2746 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2747 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2748 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2749 mesa_instruction_annotation
[i
] = inst
->ir
;
2751 /* Set IndirectRegisterFiles. */
2752 if (mesa_inst
->DstReg
.RelAddr
)
2753 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2755 /* Update program's bitmask of indirectly accessed register files */
2756 for (unsigned src
= 0; src
< 3; src
++)
2757 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2758 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2760 switch (mesa_inst
->Opcode
) {
2762 if (options
->MaxIfDepth
== 0) {
2763 linker_warning(shader_program
,
2764 "Couldn't flatten if-statement. "
2765 "This will likely result in software "
2766 "rasterization.\n");
2769 case OPCODE_BGNLOOP
:
2770 if (options
->EmitNoLoops
) {
2771 linker_warning(shader_program
,
2772 "Couldn't unroll loop. "
2773 "This will likely result in software "
2774 "rasterization.\n");
2778 if (options
->EmitNoCont
) {
2779 linker_warning(shader_program
,
2780 "Couldn't lower continue-statement. "
2781 "This will likely result in software "
2782 "rasterization.\n");
2786 prog
->NumAddressRegs
= 1;
2795 if (!shader_program
->LinkStatus
)
2799 if (!shader_program
->LinkStatus
) {
2803 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2805 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2806 fprintf(stderr
, "\n");
2807 fprintf(stderr
, "GLSL IR for linked %s program %d:\n", target_string
,
2808 shader_program
->Name
);
2809 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
2810 fprintf(stderr
, "\n");
2811 fprintf(stderr
, "\n");
2812 fprintf(stderr
, "Mesa IR for linked %s program %d:\n", target_string
,
2813 shader_program
->Name
);
2814 print_program(mesa_instructions
, mesa_instruction_annotation
,
2819 prog
->Instructions
= mesa_instructions
;
2820 prog
->NumInstructions
= num_instructions
;
2822 /* Setting this to NULL prevents a possible double free in the fail_exit
2825 mesa_instructions
= NULL
;
2827 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
2829 prog
->SamplersUsed
= shader
->active_samplers
;
2830 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2831 _mesa_update_shader_textures_used(shader_program
, prog
);
2833 /* Set the gl_FragDepth layout. */
2834 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2835 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2836 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2839 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2841 if ((ctx
->_Shader
->Flags
& GLSL_NO_OPT
) == 0) {
2842 _mesa_optimize_program(ctx
, prog
);
2845 /* This has to be done last. Any operation that can cause
2846 * prog->ParameterValues to get reallocated (e.g., anything that adds a
2847 * program constant) has to happen before creating this linkage.
2849 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
2850 if (!shader_program
->LinkStatus
) {
2857 free(mesa_instructions
);
2858 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
2866 * Called via ctx->Driver.LinkShader()
2867 * This actually involves converting GLSL IR into Mesa gl_programs with
2868 * code lowering and other optimizations.
2871 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2873 assert(prog
->LinkStatus
);
2875 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2876 if (prog
->_LinkedShaders
[i
] == NULL
)
2880 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
2881 const struct gl_shader_compiler_options
*options
=
2882 &ctx
->Const
.ShaderCompilerOptions
[prog
->_LinkedShaders
[i
]->Stage
];
2888 do_mat_op_to_vec(ir
);
2889 lower_instructions(ir
, (MOD_TO_FLOOR
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
2890 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
2891 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
2893 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
2895 progress
= do_common_optimization(ir
, true, true,
2896 options
, ctx
->Const
.NativeIntegers
)
2899 progress
= lower_quadop_vector(ir
, true) || progress
;
2901 if (options
->MaxIfDepth
== 0)
2902 progress
= lower_discard(ir
) || progress
;
2904 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
2906 if (options
->EmitNoNoise
)
2907 progress
= lower_noise(ir
) || progress
;
2909 /* If there are forms of indirect addressing that the driver
2910 * cannot handle, perform the lowering pass.
2912 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
2913 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
2915 lower_variable_index_to_cond_assign(ir
,
2916 options
->EmitNoIndirectInput
,
2917 options
->EmitNoIndirectOutput
,
2918 options
->EmitNoIndirectTemp
,
2919 options
->EmitNoIndirectUniform
)
2922 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
2923 progress
= lower_vector_insert(ir
, true) || progress
;
2926 validate_ir_tree(ir
);
2929 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2930 struct gl_program
*linked_prog
;
2932 if (prog
->_LinkedShaders
[i
] == NULL
)
2935 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
2938 _mesa_copy_linked_program_data((gl_shader_stage
) i
, prog
, linked_prog
);
2940 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
2942 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
2943 _mesa_shader_stage_to_program(i
),
2949 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
2952 return prog
->LinkStatus
;
2956 * Link a GLSL shader program. Called via glLinkProgram().
2959 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2963 _mesa_clear_shader_program_data(prog
);
2965 prog
->LinkStatus
= GL_TRUE
;
2967 for (i
= 0; i
< prog
->NumShaders
; i
++) {
2968 if (!prog
->Shaders
[i
]->CompileStatus
) {
2969 linker_error(prog
, "linking with uncompiled shader");
2973 if (prog
->LinkStatus
) {
2974 link_shaders(ctx
, prog
);
2977 if (prog
->LinkStatus
) {
2978 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
2979 prog
->LinkStatus
= GL_FALSE
;
2983 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2984 if (!prog
->LinkStatus
) {
2985 fprintf(stderr
, "GLSL shader program %d failed to link\n", prog
->Name
);
2988 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
2989 fprintf(stderr
, "GLSL shader program %d info log:\n", prog
->Name
);
2990 fprintf(stderr
, "%s\n", prog
->InfoLog
);