2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 * \file ir_to_mesa.cpp
29 * Translate GLSL IR to Mesa's gl_program representation.
33 #include "main/compiler.h"
34 #include "main/mtypes.h"
35 #include "main/shaderapi.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "compiler/glsl/ast.h"
39 #include "compiler/glsl/ir.h"
40 #include "compiler/glsl/ir_expression_flattening.h"
41 #include "compiler/glsl/ir_visitor.h"
42 #include "compiler/glsl/ir_optimization.h"
43 #include "compiler/glsl/ir_uniform.h"
44 #include "compiler/glsl/glsl_parser_extras.h"
45 #include "compiler/glsl_types.h"
46 #include "compiler/glsl/linker.h"
47 #include "compiler/glsl/program.h"
48 #include "program/hash_table.h"
49 #include "program/prog_instruction.h"
50 #include "program/prog_optimize.h"
51 #include "program/prog_print.h"
52 #include "program/program.h"
53 #include "program/prog_parameter.h"
54 #include "program/sampler.h"
57 static int swizzle_for_size(int size
);
65 * This struct is a corresponding struct to Mesa prog_src_register, with
70 src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
74 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
75 this->swizzle
= swizzle_for_size(type
->vector_elements
);
77 this->swizzle
= SWIZZLE_XYZW
;
84 this->file
= PROGRAM_UNDEFINED
;
91 explicit src_reg(dst_reg reg
);
93 gl_register_file file
; /**< PROGRAM_* from Mesa */
94 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
95 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
96 int negate
; /**< NEGATE_XYZW mask from mesa */
97 /** Register index should be offset by the integer in this reg. */
103 dst_reg(gl_register_file file
, int writemask
)
107 this->writemask
= writemask
;
108 this->cond_mask
= COND_TR
;
109 this->reladdr
= NULL
;
114 this->file
= PROGRAM_UNDEFINED
;
117 this->cond_mask
= COND_TR
;
118 this->reladdr
= NULL
;
121 explicit dst_reg(src_reg reg
);
123 gl_register_file file
; /**< PROGRAM_* from Mesa */
124 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
125 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
127 /** Register index should be offset by the integer in this reg. */
131 } /* anonymous namespace */
133 src_reg::src_reg(dst_reg reg
)
135 this->file
= reg
.file
;
136 this->index
= reg
.index
;
137 this->swizzle
= SWIZZLE_XYZW
;
139 this->reladdr
= reg
.reladdr
;
142 dst_reg::dst_reg(src_reg reg
)
144 this->file
= reg
.file
;
145 this->index
= reg
.index
;
146 this->writemask
= WRITEMASK_XYZW
;
147 this->cond_mask
= COND_TR
;
148 this->reladdr
= reg
.reladdr
;
153 class ir_to_mesa_instruction
: public exec_node
{
155 DECLARE_RALLOC_CXX_OPERATORS(ir_to_mesa_instruction
)
160 /** Pointer to the ir source this tree came from for debugging */
162 GLboolean cond_update
;
164 int sampler
; /**< sampler index */
165 int tex_target
; /**< One of TEXTURE_*_INDEX */
166 GLboolean tex_shadow
;
169 class variable_storage
: public exec_node
{
171 variable_storage(ir_variable
*var
, gl_register_file file
, int index
)
172 : file(file
), index(index
), var(var
)
177 gl_register_file file
;
179 ir_variable
*var
; /* variable that maps to this, if any */
182 class function_entry
: public exec_node
{
184 ir_function_signature
*sig
;
187 * identifier of this function signature used by the program.
189 * At the point that Mesa instructions for function calls are
190 * generated, we don't know the address of the first instruction of
191 * the function body. So we make the BranchTarget that is called a
192 * small integer and rewrite them during set_branchtargets().
197 * Pointer to first instruction of the function body.
199 * Set during function body emits after main() is processed.
201 ir_to_mesa_instruction
*bgn_inst
;
204 * Index of the first instruction of the function body in actual
207 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
211 /** Storage for the return value. */
215 class ir_to_mesa_visitor
: public ir_visitor
{
217 ir_to_mesa_visitor();
218 ~ir_to_mesa_visitor();
220 function_entry
*current_function
;
222 struct gl_context
*ctx
;
223 struct gl_program
*prog
;
224 struct gl_shader_program
*shader_program
;
225 struct gl_shader_compiler_options
*options
;
229 variable_storage
*find_variable_storage(const ir_variable
*var
);
231 src_reg
get_temp(const glsl_type
*type
);
232 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
234 src_reg
src_reg_for_float(float val
);
237 * \name Visit methods
239 * As typical for the visitor pattern, there must be one \c visit method for
240 * each concrete subclass of \c ir_instruction. Virtual base classes within
241 * the hierarchy should not have \c visit methods.
244 virtual void visit(ir_variable
*);
245 virtual void visit(ir_loop
*);
246 virtual void visit(ir_loop_jump
*);
247 virtual void visit(ir_function_signature
*);
248 virtual void visit(ir_function
*);
249 virtual void visit(ir_expression
*);
250 virtual void visit(ir_swizzle
*);
251 virtual void visit(ir_dereference_variable
*);
252 virtual void visit(ir_dereference_array
*);
253 virtual void visit(ir_dereference_record
*);
254 virtual void visit(ir_assignment
*);
255 virtual void visit(ir_constant
*);
256 virtual void visit(ir_call
*);
257 virtual void visit(ir_return
*);
258 virtual void visit(ir_discard
*);
259 virtual void visit(ir_texture
*);
260 virtual void visit(ir_if
*);
261 virtual void visit(ir_emit_vertex
*);
262 virtual void visit(ir_end_primitive
*);
263 virtual void visit(ir_barrier
*);
268 /** List of variable_storage */
271 /** List of function_entry */
272 exec_list function_signatures
;
273 int next_signature_id
;
275 /** List of ir_to_mesa_instruction */
276 exec_list instructions
;
278 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
);
280 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
281 dst_reg dst
, src_reg src0
);
283 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
284 dst_reg dst
, src_reg src0
, src_reg src1
);
286 ir_to_mesa_instruction
*emit(ir_instruction
*ir
, enum prog_opcode op
,
288 src_reg src0
, src_reg src1
, src_reg src2
);
291 * Emit the correct dot-product instruction for the type of arguments
293 ir_to_mesa_instruction
* emit_dp(ir_instruction
*ir
,
299 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
300 dst_reg dst
, src_reg src0
);
302 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
303 dst_reg dst
, src_reg src0
, src_reg src1
);
305 bool try_emit_mad(ir_expression
*ir
,
307 bool try_emit_mad_for_and_not(ir_expression
*ir
,
310 void emit_swz(ir_expression
*ir
);
312 bool process_move_condition(ir_rvalue
*ir
);
314 void copy_propagate(void);
319 } /* anonymous namespace */
321 static src_reg undef_src
= src_reg(PROGRAM_UNDEFINED
, 0, NULL
);
323 static dst_reg undef_dst
= dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
);
325 static dst_reg address_reg
= dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
);
328 swizzle_for_size(int size
)
330 static const int size_swizzles
[4] = {
331 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
332 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
333 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
334 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
337 assert((size
>= 1) && (size
<= 4));
338 return size_swizzles
[size
- 1];
341 ir_to_mesa_instruction
*
342 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
344 src_reg src0
, src_reg src1
, src_reg src2
)
346 ir_to_mesa_instruction
*inst
= new(mem_ctx
) ir_to_mesa_instruction();
349 /* If we have to do relative addressing, we want to load the ARL
350 * reg directly for one of the regs, and preload the other reladdr
351 * sources into temps.
353 num_reladdr
+= dst
.reladdr
!= NULL
;
354 num_reladdr
+= src0
.reladdr
!= NULL
;
355 num_reladdr
+= src1
.reladdr
!= NULL
;
356 num_reladdr
+= src2
.reladdr
!= NULL
;
358 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
359 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
360 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
363 emit(ir
, OPCODE_ARL
, address_reg
, *dst
.reladdr
);
366 assert(num_reladdr
== 0);
375 this->instructions
.push_tail(inst
);
381 ir_to_mesa_instruction
*
382 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
383 dst_reg dst
, src_reg src0
, src_reg src1
)
385 return emit(ir
, op
, dst
, src0
, src1
, undef_src
);
388 ir_to_mesa_instruction
*
389 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
,
390 dst_reg dst
, src_reg src0
)
392 assert(dst
.writemask
!= 0);
393 return emit(ir
, op
, dst
, src0
, undef_src
, undef_src
);
396 ir_to_mesa_instruction
*
397 ir_to_mesa_visitor::emit(ir_instruction
*ir
, enum prog_opcode op
)
399 return emit(ir
, op
, undef_dst
, undef_src
, undef_src
, undef_src
);
402 ir_to_mesa_instruction
*
403 ir_to_mesa_visitor::emit_dp(ir_instruction
*ir
,
404 dst_reg dst
, src_reg src0
, src_reg src1
,
407 static const enum prog_opcode dot_opcodes
[] = {
408 OPCODE_DP2
, OPCODE_DP3
, OPCODE_DP4
411 return emit(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
415 * Emits Mesa scalar opcodes to produce unique answers across channels.
417 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
418 * channel determines the result across all channels. So to do a vec4
419 * of this operation, we want to emit a scalar per source channel used
420 * to produce dest channels.
423 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
425 src_reg orig_src0
, src_reg orig_src1
)
428 int done_mask
= ~dst
.writemask
;
430 /* Mesa RCP is a scalar operation splatting results to all channels,
431 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
434 for (i
= 0; i
< 4; i
++) {
435 GLuint this_mask
= (1 << i
);
436 ir_to_mesa_instruction
*inst
;
437 src_reg src0
= orig_src0
;
438 src_reg src1
= orig_src1
;
440 if (done_mask
& this_mask
)
443 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
444 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
445 for (j
= i
+ 1; j
< 4; j
++) {
446 /* If there is another enabled component in the destination that is
447 * derived from the same inputs, generate its value on this pass as
450 if (!(done_mask
& (1 << j
)) &&
451 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
452 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
453 this_mask
|= (1 << j
);
456 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
457 src0_swiz
, src0_swiz
);
458 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
459 src1_swiz
, src1_swiz
);
461 inst
= emit(ir
, op
, dst
, src0
, src1
);
462 inst
->dst
.writemask
= this_mask
;
463 done_mask
|= this_mask
;
468 ir_to_mesa_visitor::emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
469 dst_reg dst
, src_reg src0
)
471 src_reg undef
= undef_src
;
473 undef
.swizzle
= SWIZZLE_XXXX
;
475 emit_scalar(ir
, op
, dst
, src0
, undef
);
479 ir_to_mesa_visitor::src_reg_for_float(float val
)
481 src_reg
src(PROGRAM_CONSTANT
, -1, NULL
);
483 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
484 (const gl_constant_value
*)&val
, 1, &src
.swizzle
);
490 type_size(const struct glsl_type
*type
)
495 switch (type
->base_type
) {
498 case GLSL_TYPE_FLOAT
:
500 if (type
->is_matrix()) {
501 return type
->matrix_columns
;
503 /* Regardless of size of vector, it gets a vec4. This is bad
504 * packing for things like floats, but otherwise arrays become a
505 * mess. Hopefully a later pass over the code can pack scalars
506 * down if appropriate.
511 case GLSL_TYPE_DOUBLE
:
512 if (type
->is_matrix()) {
513 if (type
->vector_elements
> 2)
514 return type
->matrix_columns
* 2;
516 return type
->matrix_columns
;
518 if (type
->vector_elements
> 2)
524 case GLSL_TYPE_ARRAY
:
525 assert(type
->length
> 0);
526 return type_size(type
->fields
.array
) * type
->length
;
527 case GLSL_TYPE_STRUCT
:
529 for (i
= 0; i
< type
->length
; i
++) {
530 size
+= type_size(type
->fields
.structure
[i
].type
);
533 case GLSL_TYPE_SAMPLER
:
534 case GLSL_TYPE_IMAGE
:
535 case GLSL_TYPE_SUBROUTINE
:
536 /* Samplers take up one slot in UNIFORMS[], but they're baked in
540 case GLSL_TYPE_ATOMIC_UINT
:
542 case GLSL_TYPE_ERROR
:
543 case GLSL_TYPE_INTERFACE
:
544 assert(!"Invalid type in type_size");
552 * In the initial pass of codegen, we assign temporary numbers to
553 * intermediate results. (not SSA -- variable assignments will reuse
554 * storage). Actual register allocation for the Mesa VM occurs in a
555 * pass over the Mesa IR later.
558 ir_to_mesa_visitor::get_temp(const glsl_type
*type
)
562 src
.file
= PROGRAM_TEMPORARY
;
563 src
.index
= next_temp
;
565 next_temp
+= type_size(type
);
567 if (type
->is_array() || type
->is_record()) {
568 src
.swizzle
= SWIZZLE_NOOP
;
570 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
578 ir_to_mesa_visitor::find_variable_storage(const ir_variable
*var
)
580 foreach_in_list(variable_storage
, entry
, &this->variables
) {
581 if (entry
->var
== var
)
589 ir_to_mesa_visitor::visit(ir_variable
*ir
)
591 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
592 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
594 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
595 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
598 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
600 const ir_state_slot
*const slots
= ir
->get_state_slots();
601 assert(slots
!= NULL
);
603 /* Check if this statevar's setup in the STATE file exactly
604 * matches how we'll want to reference it as a
605 * struct/array/whatever. If not, then we need to move it into
606 * temporary storage and hope that it'll get copy-propagated
609 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
610 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
615 variable_storage
*storage
;
617 if (i
== ir
->get_num_state_slots()) {
618 /* We'll set the index later. */
619 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
620 this->variables
.push_tail(storage
);
624 /* The variable_storage constructor allocates slots based on the size
625 * of the type. However, this had better match the number of state
626 * elements that we're going to copy into the new temporary.
628 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
630 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_TEMPORARY
,
632 this->variables
.push_tail(storage
);
633 this->next_temp
+= type_size(ir
->type
);
635 dst
= dst_reg(src_reg(PROGRAM_TEMPORARY
, storage
->index
, NULL
));
639 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
640 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
641 (gl_state_index
*)slots
[i
].tokens
);
643 if (storage
->file
== PROGRAM_STATE_VAR
) {
644 if (storage
->index
== -1) {
645 storage
->index
= index
;
647 assert(index
== storage
->index
+ (int)i
);
650 src_reg
src(PROGRAM_STATE_VAR
, index
, NULL
);
651 src
.swizzle
= slots
[i
].swizzle
;
652 emit(ir
, OPCODE_MOV
, dst
, src
);
653 /* even a float takes up a whole vec4 reg in a struct/array. */
658 if (storage
->file
== PROGRAM_TEMPORARY
&&
659 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
660 linker_error(this->shader_program
,
661 "failed to load builtin uniform `%s' "
662 "(%d/%d regs loaded)\n",
663 ir
->name
, dst
.index
- storage
->index
,
664 type_size(ir
->type
));
670 ir_to_mesa_visitor::visit(ir_loop
*ir
)
672 emit(NULL
, OPCODE_BGNLOOP
);
674 visit_exec_list(&ir
->body_instructions
, this);
676 emit(NULL
, OPCODE_ENDLOOP
);
680 ir_to_mesa_visitor::visit(ir_loop_jump
*ir
)
683 case ir_loop_jump::jump_break
:
684 emit(NULL
, OPCODE_BRK
);
686 case ir_loop_jump::jump_continue
:
687 emit(NULL
, OPCODE_CONT
);
694 ir_to_mesa_visitor::visit(ir_function_signature
*ir
)
701 ir_to_mesa_visitor::visit(ir_function
*ir
)
703 /* Ignore function bodies other than main() -- we shouldn't see calls to
704 * them since they should all be inlined before we get to ir_to_mesa.
706 if (strcmp(ir
->name
, "main") == 0) {
707 const ir_function_signature
*sig
;
710 sig
= ir
->matching_signature(NULL
, &empty
, false);
714 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
721 ir_to_mesa_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
723 int nonmul_operand
= 1 - mul_operand
;
726 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
727 if (!expr
|| expr
->operation
!= ir_binop_mul
)
730 expr
->operands
[0]->accept(this);
732 expr
->operands
[1]->accept(this);
734 ir
->operands
[nonmul_operand
]->accept(this);
737 this->result
= get_temp(ir
->type
);
738 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, c
);
744 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
746 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
747 * implemented using multiplication, and logical-or is implemented using
748 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
749 * As result, the logical expression (a & !b) can be rewritten as:
753 * - (a * 1) - (a * b)
757 * This final expression can be implemented as a single MAD(a, -b, a)
761 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
763 const int other_operand
= 1 - try_operand
;
766 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
767 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
770 ir
->operands
[other_operand
]->accept(this);
772 expr
->operands
[0]->accept(this);
775 b
.negate
= ~b
.negate
;
777 this->result
= get_temp(ir
->type
);
778 emit(ir
, OPCODE_MAD
, dst_reg(this->result
), a
, b
, a
);
784 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction
*ir
,
785 src_reg
*reg
, int *num_reladdr
)
790 emit(ir
, OPCODE_ARL
, address_reg
, *reg
->reladdr
);
792 if (*num_reladdr
!= 1) {
793 src_reg temp
= get_temp(glsl_type::vec4_type
);
795 emit(ir
, OPCODE_MOV
, dst_reg(temp
), *reg
);
803 ir_to_mesa_visitor::emit_swz(ir_expression
*ir
)
805 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
806 * This means that each of the operands is either an immediate value of -1,
807 * 0, or 1, or is a component from one source register (possibly with
810 uint8_t components
[4] = { 0 };
811 bool negate
[4] = { false };
812 ir_variable
*var
= NULL
;
814 for (unsigned i
= 0; i
< ir
->type
->vector_elements
; i
++) {
815 ir_rvalue
*op
= ir
->operands
[i
];
817 assert(op
->type
->is_scalar());
820 switch (op
->ir_type
) {
821 case ir_type_constant
: {
823 assert(op
->type
->is_scalar());
825 const ir_constant
*const c
= op
->as_constant();
827 components
[i
] = SWIZZLE_ONE
;
828 } else if (c
->is_zero()) {
829 components
[i
] = SWIZZLE_ZERO
;
830 } else if (c
->is_negative_one()) {
831 components
[i
] = SWIZZLE_ONE
;
834 assert(!"SWZ constant must be 0.0 or 1.0.");
841 case ir_type_dereference_variable
: {
842 ir_dereference_variable
*const deref
=
843 (ir_dereference_variable
*) op
;
845 assert((var
== NULL
) || (deref
->var
== var
));
846 components
[i
] = SWIZZLE_X
;
852 case ir_type_expression
: {
853 ir_expression
*const expr
= (ir_expression
*) op
;
855 assert(expr
->operation
== ir_unop_neg
);
858 op
= expr
->operands
[0];
862 case ir_type_swizzle
: {
863 ir_swizzle
*const swiz
= (ir_swizzle
*) op
;
865 components
[i
] = swiz
->mask
.x
;
871 assert(!"Should not get here.");
879 ir_dereference_variable
*const deref
=
880 new(mem_ctx
) ir_dereference_variable(var
);
882 this->result
.file
= PROGRAM_UNDEFINED
;
884 if (this->result
.file
== PROGRAM_UNDEFINED
) {
885 printf("Failed to get tree for expression operand:\n");
894 src
.swizzle
= MAKE_SWIZZLE4(components
[0],
898 src
.negate
= ((unsigned(negate
[0]) << 0)
899 | (unsigned(negate
[1]) << 1)
900 | (unsigned(negate
[2]) << 2)
901 | (unsigned(negate
[3]) << 3));
903 /* Storage for our result. Ideally for an assignment we'd be using the
904 * actual storage for the result here, instead.
906 const src_reg result_src
= get_temp(ir
->type
);
907 dst_reg result_dst
= dst_reg(result_src
);
909 /* Limit writes to the channels that will be used by result_src later.
910 * This does limit this temp's use as a temporary for multi-instruction
913 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
915 emit(ir
, OPCODE_SWZ
, result_dst
, src
);
916 this->result
= result_src
;
920 ir_to_mesa_visitor::visit(ir_expression
*ir
)
922 unsigned int operand
;
923 src_reg op
[ARRAY_SIZE(ir
->operands
)];
927 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
929 if (ir
->operation
== ir_binop_add
) {
930 if (try_emit_mad(ir
, 1))
932 if (try_emit_mad(ir
, 0))
936 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
938 if (ir
->operation
== ir_binop_logic_and
) {
939 if (try_emit_mad_for_and_not(ir
, 1))
941 if (try_emit_mad_for_and_not(ir
, 0))
945 if (ir
->operation
== ir_quadop_vector
) {
950 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
951 this->result
.file
= PROGRAM_UNDEFINED
;
952 ir
->operands
[operand
]->accept(this);
953 if (this->result
.file
== PROGRAM_UNDEFINED
) {
954 printf("Failed to get tree for expression operand:\n");
955 ir
->operands
[operand
]->print();
959 op
[operand
] = this->result
;
961 /* Matrix expression operands should have been broken down to vector
962 * operations already.
964 assert(!ir
->operands
[operand
]->type
->is_matrix());
967 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
968 if (ir
->operands
[1]) {
969 vector_elements
= MAX2(vector_elements
,
970 ir
->operands
[1]->type
->vector_elements
);
973 this->result
.file
= PROGRAM_UNDEFINED
;
975 /* Storage for our result. Ideally for an assignment we'd be using
976 * the actual storage for the result here, instead.
978 result_src
= get_temp(ir
->type
);
979 /* convenience for the emit functions below. */
980 result_dst
= dst_reg(result_src
);
981 /* Limit writes to the channels that will be used by result_src later.
982 * This does limit this temp's use as a temporary for multi-instruction
985 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
987 switch (ir
->operation
) {
988 case ir_unop_logic_not
:
989 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
990 * older GPUs implement SEQ using multiple instructions (i915 uses two
991 * SGE instructions and a MUL instruction). Since our logic values are
992 * 0.0 and 1.0, 1-x also implements !x.
994 op
[0].negate
= ~op
[0].negate
;
995 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], src_reg_for_float(1.0));
998 op
[0].negate
= ~op
[0].negate
;
1002 emit(ir
, OPCODE_ABS
, result_dst
, op
[0]);
1005 emit(ir
, OPCODE_SSG
, result_dst
, op
[0]);
1008 emit_scalar(ir
, OPCODE_RCP
, result_dst
, op
[0]);
1012 emit_scalar(ir
, OPCODE_EX2
, result_dst
, op
[0]);
1016 assert(!"not reached: should be handled by ir_explog_to_explog2");
1019 emit_scalar(ir
, OPCODE_LG2
, result_dst
, op
[0]);
1022 emit_scalar(ir
, OPCODE_SIN
, result_dst
, op
[0]);
1025 emit_scalar(ir
, OPCODE_COS
, result_dst
, op
[0]);
1029 emit(ir
, OPCODE_DDX
, result_dst
, op
[0]);
1032 emit(ir
, OPCODE_DDY
, result_dst
, op
[0]);
1035 case ir_unop_saturate
: {
1036 ir_to_mesa_instruction
*inst
= emit(ir
, OPCODE_MOV
,
1038 inst
->saturate
= true;
1041 case ir_unop_noise
: {
1042 const enum prog_opcode opcode
=
1043 prog_opcode(OPCODE_NOISE1
1044 + (ir
->operands
[0]->type
->vector_elements
) - 1);
1045 assert((opcode
>= OPCODE_NOISE1
) && (opcode
<= OPCODE_NOISE4
));
1047 emit(ir
, opcode
, result_dst
, op
[0]);
1052 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1055 emit(ir
, OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1059 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1062 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1065 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1066 assert(ir
->type
->is_integer());
1067 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1071 emit(ir
, OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1073 case ir_binop_greater
:
1074 emit(ir
, OPCODE_SGT
, result_dst
, op
[0], op
[1]);
1076 case ir_binop_lequal
:
1077 emit(ir
, OPCODE_SLE
, result_dst
, op
[0], op
[1]);
1079 case ir_binop_gequal
:
1080 emit(ir
, OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1082 case ir_binop_equal
:
1083 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1085 case ir_binop_nequal
:
1086 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1088 case ir_binop_all_equal
:
1089 /* "==" operator producing a scalar boolean. */
1090 if (ir
->operands
[0]->type
->is_vector() ||
1091 ir
->operands
[1]->type
->is_vector()) {
1092 src_reg temp
= get_temp(glsl_type::vec4_type
);
1093 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1095 /* After the dot-product, the value will be an integer on the
1096 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1098 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1100 /* Negating the result of the dot-product gives values on the range
1101 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1102 * achieved using SGE.
1104 src_reg sge_src
= result_src
;
1105 sge_src
.negate
= ~sge_src
.negate
;
1106 emit(ir
, OPCODE_SGE
, result_dst
, sge_src
, src_reg_for_float(0.0));
1108 emit(ir
, OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1111 case ir_binop_any_nequal
:
1112 /* "!=" operator producing a scalar boolean. */
1113 if (ir
->operands
[0]->type
->is_vector() ||
1114 ir
->operands
[1]->type
->is_vector()) {
1115 src_reg temp
= get_temp(glsl_type::vec4_type
);
1116 if (ir
->operands
[0]->type
->is_boolean() &&
1117 ir
->operands
[1]->as_constant() &&
1118 ir
->operands
[1]->as_constant()->is_zero()) {
1121 emit(ir
, OPCODE_SNE
, dst_reg(temp
), op
[0], op
[1]);
1124 /* After the dot-product, the value will be an integer on the
1125 * range [0,4]. Zero stays zero, and positive values become 1.0.
1127 ir_to_mesa_instruction
*const dp
=
1128 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1129 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1130 /* The clamping to [0,1] can be done for free in the fragment
1131 * shader with a saturate.
1133 dp
->saturate
= true;
1135 /* Negating the result of the dot-product gives values on the range
1136 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1137 * achieved using SLT.
1139 src_reg slt_src
= result_src
;
1140 slt_src
.negate
= ~slt_src
.negate
;
1141 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1144 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1148 case ir_binop_logic_xor
:
1149 emit(ir
, OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1152 case ir_binop_logic_or
: {
1153 /* After the addition, the value will be an integer on the
1154 * range [0,2]. Zero stays zero, and positive values become 1.0.
1156 ir_to_mesa_instruction
*add
=
1157 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1158 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1159 /* The clamping to [0,1] can be done for free in the fragment
1160 * shader with a saturate.
1162 add
->saturate
= true;
1164 /* Negating the result of the addition gives values on the range
1165 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1166 * is achieved using SLT.
1168 src_reg slt_src
= result_src
;
1169 slt_src
.negate
= ~slt_src
.negate
;
1170 emit(ir
, OPCODE_SLT
, result_dst
, slt_src
, src_reg_for_float(0.0));
1175 case ir_binop_logic_and
:
1176 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1177 emit(ir
, OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1181 assert(ir
->operands
[0]->type
->is_vector());
1182 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1183 emit_dp(ir
, result_dst
, op
[0], op
[1],
1184 ir
->operands
[0]->type
->vector_elements
);
1188 /* sqrt(x) = x * rsq(x). */
1189 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1190 emit(ir
, OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1191 /* For incoming channels <= 0, set the result to 0. */
1192 op
[0].negate
= ~op
[0].negate
;
1193 emit(ir
, OPCODE_CMP
, result_dst
,
1194 op
[0], result_src
, src_reg_for_float(0.0));
1197 emit_scalar(ir
, OPCODE_RSQ
, result_dst
, op
[0]);
1205 /* Mesa IR lacks types, ints are stored as truncated floats. */
1210 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1214 emit(ir
, OPCODE_SNE
, result_dst
,
1215 op
[0], src_reg_for_float(0.0));
1217 case ir_unop_bitcast_f2i
: // Ignore these 4, they can't happen here anyway
1218 case ir_unop_bitcast_f2u
:
1219 case ir_unop_bitcast_i2f
:
1220 case ir_unop_bitcast_u2f
:
1223 emit(ir
, OPCODE_TRUNC
, result_dst
, op
[0]);
1226 op
[0].negate
= ~op
[0].negate
;
1227 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1228 result_src
.negate
= ~result_src
.negate
;
1231 emit(ir
, OPCODE_FLR
, result_dst
, op
[0]);
1234 emit(ir
, OPCODE_FRC
, result_dst
, op
[0]);
1236 case ir_unop_pack_snorm_2x16
:
1237 case ir_unop_pack_snorm_4x8
:
1238 case ir_unop_pack_unorm_2x16
:
1239 case ir_unop_pack_unorm_4x8
:
1240 case ir_unop_pack_half_2x16
:
1241 case ir_unop_pack_double_2x32
:
1242 case ir_unop_unpack_snorm_2x16
:
1243 case ir_unop_unpack_snorm_4x8
:
1244 case ir_unop_unpack_unorm_2x16
:
1245 case ir_unop_unpack_unorm_4x8
:
1246 case ir_unop_unpack_half_2x16
:
1247 case ir_unop_unpack_half_2x16_split_x
:
1248 case ir_unop_unpack_half_2x16_split_y
:
1249 case ir_unop_unpack_double_2x32
:
1250 case ir_binop_pack_half_2x16_split
:
1251 case ir_unop_bitfield_reverse
:
1252 case ir_unop_bit_count
:
1253 case ir_unop_find_msb
:
1254 case ir_unop_find_lsb
:
1262 case ir_unop_frexp_sig
:
1263 case ir_unop_frexp_exp
:
1264 assert(!"not supported");
1267 emit(ir
, OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1270 emit(ir
, OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1273 emit_scalar(ir
, OPCODE_POW
, result_dst
, op
[0], op
[1]);
1276 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1277 * hardware backends have no way to avoid Mesa IR generation
1278 * even if they don't use it, we need to emit "something" and
1281 case ir_binop_lshift
:
1282 case ir_binop_rshift
:
1283 case ir_binop_bit_and
:
1284 case ir_binop_bit_xor
:
1285 case ir_binop_bit_or
:
1286 emit(ir
, OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1289 case ir_unop_bit_not
:
1290 case ir_unop_round_even
:
1291 emit(ir
, OPCODE_MOV
, result_dst
, op
[0]);
1294 case ir_binop_ubo_load
:
1295 assert(!"not supported");
1299 /* ir_triop_lrp operands are (x, y, a) while
1300 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1302 emit(ir
, OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
1305 case ir_binop_vector_extract
:
1307 case ir_triop_bitfield_extract
:
1308 case ir_triop_vector_insert
:
1309 case ir_quadop_bitfield_insert
:
1310 case ir_binop_ldexp
:
1312 case ir_binop_carry
:
1313 case ir_binop_borrow
:
1314 case ir_binop_imul_high
:
1315 case ir_unop_interpolate_at_centroid
:
1316 case ir_binop_interpolate_at_offset
:
1317 case ir_binop_interpolate_at_sample
:
1318 case ir_unop_dFdx_coarse
:
1319 case ir_unop_dFdx_fine
:
1320 case ir_unop_dFdy_coarse
:
1321 case ir_unop_dFdy_fine
:
1322 case ir_unop_subroutine_to_int
:
1323 case ir_unop_get_buffer_size
:
1324 assert(!"not supported");
1327 case ir_unop_ssbo_unsized_array_length
:
1328 case ir_quadop_vector
:
1329 /* This operation should have already been handled.
1331 assert(!"Should not get here.");
1335 this->result
= result_src
;
1340 ir_to_mesa_visitor::visit(ir_swizzle
*ir
)
1346 /* Note that this is only swizzles in expressions, not those on the left
1347 * hand side of an assignment, which do write masking. See ir_assignment
1351 ir
->val
->accept(this);
1353 assert(src
.file
!= PROGRAM_UNDEFINED
);
1354 assert(ir
->type
->vector_elements
> 0);
1356 for (i
= 0; i
< 4; i
++) {
1357 if (i
< ir
->type
->vector_elements
) {
1360 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1363 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1366 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1369 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1373 /* If the type is smaller than a vec4, replicate the last
1376 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1380 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1386 ir_to_mesa_visitor::visit(ir_dereference_variable
*ir
)
1388 variable_storage
*entry
= find_variable_storage(ir
->var
);
1389 ir_variable
*var
= ir
->var
;
1392 switch (var
->data
.mode
) {
1393 case ir_var_uniform
:
1394 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
1395 var
->data
.location
);
1396 this->variables
.push_tail(entry
);
1398 case ir_var_shader_in
:
1399 /* The linker assigns locations for varyings and attributes,
1400 * including deprecated builtins (like gl_Color),
1401 * user-assigned generic attributes (glBindVertexLocation),
1402 * and user-defined varyings.
1404 assert(var
->data
.location
!= -1);
1405 entry
= new(mem_ctx
) variable_storage(var
,
1407 var
->data
.location
);
1409 case ir_var_shader_out
:
1410 assert(var
->data
.location
!= -1);
1411 entry
= new(mem_ctx
) variable_storage(var
,
1413 var
->data
.location
);
1415 case ir_var_system_value
:
1416 entry
= new(mem_ctx
) variable_storage(var
,
1417 PROGRAM_SYSTEM_VALUE
,
1418 var
->data
.location
);
1421 case ir_var_temporary
:
1422 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_TEMPORARY
,
1424 this->variables
.push_tail(entry
);
1426 next_temp
+= type_size(var
->type
);
1431 printf("Failed to make storage for %s\n", var
->name
);
1436 this->result
= src_reg(entry
->file
, entry
->index
, var
->type
);
1440 ir_to_mesa_visitor::visit(ir_dereference_array
*ir
)
1444 int element_size
= type_size(ir
->type
);
1446 index
= ir
->array_index
->constant_expression_value();
1448 ir
->array
->accept(this);
1452 src
.index
+= index
->value
.i
[0] * element_size
;
1454 /* Variable index array dereference. It eats the "vec4" of the
1455 * base of the array and an index that offsets the Mesa register
1458 ir
->array_index
->accept(this);
1462 if (element_size
== 1) {
1463 index_reg
= this->result
;
1465 index_reg
= get_temp(glsl_type::float_type
);
1467 emit(ir
, OPCODE_MUL
, dst_reg(index_reg
),
1468 this->result
, src_reg_for_float(element_size
));
1471 /* If there was already a relative address register involved, add the
1472 * new and the old together to get the new offset.
1474 if (src
.reladdr
!= NULL
) {
1475 src_reg accum_reg
= get_temp(glsl_type::float_type
);
1477 emit(ir
, OPCODE_ADD
, dst_reg(accum_reg
),
1478 index_reg
, *src
.reladdr
);
1480 index_reg
= accum_reg
;
1483 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1484 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1487 /* If the type is smaller than a vec4, replicate the last channel out. */
1488 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1489 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1491 src
.swizzle
= SWIZZLE_NOOP
;
1497 ir_to_mesa_visitor::visit(ir_dereference_record
*ir
)
1500 const glsl_type
*struct_type
= ir
->record
->type
;
1503 ir
->record
->accept(this);
1505 for (i
= 0; i
< struct_type
->length
; i
++) {
1506 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1508 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1511 /* If the type is smaller than a vec4, replicate the last channel out. */
1512 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1513 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1515 this->result
.swizzle
= SWIZZLE_NOOP
;
1517 this->result
.index
+= offset
;
1521 * We want to be careful in assignment setup to hit the actual storage
1522 * instead of potentially using a temporary like we might with the
1523 * ir_dereference handler.
1526 get_assignment_lhs(ir_dereference
*ir
, ir_to_mesa_visitor
*v
)
1528 /* The LHS must be a dereference. If the LHS is a variable indexed array
1529 * access of a vector, it must be separated into a series conditional moves
1530 * before reaching this point (see ir_vec_index_to_cond_assign).
1532 assert(ir
->as_dereference());
1533 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1535 assert(!deref_array
->array
->type
->is_vector());
1538 /* Use the rvalue deref handler for the most part. We'll ignore
1539 * swizzles in it and write swizzles using writemask, though.
1542 return dst_reg(v
->result
);
1546 * Process the condition of a conditional assignment
1548 * Examines the condition of a conditional assignment to generate the optimal
1549 * first operand of a \c CMP instruction. If the condition is a relational
1550 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1551 * used as the source for the \c CMP instruction. Otherwise the comparison
1552 * is processed to a boolean result, and the boolean result is used as the
1553 * operand to the CMP instruction.
1556 ir_to_mesa_visitor::process_move_condition(ir_rvalue
*ir
)
1558 ir_rvalue
*src_ir
= ir
;
1560 bool switch_order
= false;
1562 ir_expression
*const expr
= ir
->as_expression();
1563 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
1564 bool zero_on_left
= false;
1566 if (expr
->operands
[0]->is_zero()) {
1567 src_ir
= expr
->operands
[1];
1568 zero_on_left
= true;
1569 } else if (expr
->operands
[1]->is_zero()) {
1570 src_ir
= expr
->operands
[0];
1571 zero_on_left
= false;
1575 * (a < 0) T F F ( a < 0) T F F
1576 * (0 < a) F F T (-a < 0) F F T
1577 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
1578 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
1579 * (a > 0) F F T (-a < 0) F F T
1580 * (0 > a) T F F ( a < 0) T F F
1581 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1582 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1584 * Note that exchanging the order of 0 and 'a' in the comparison simply
1585 * means that the value of 'a' should be negated.
1588 switch (expr
->operation
) {
1590 switch_order
= false;
1591 negate
= zero_on_left
;
1594 case ir_binop_greater
:
1595 switch_order
= false;
1596 negate
= !zero_on_left
;
1599 case ir_binop_lequal
:
1600 switch_order
= true;
1601 negate
= !zero_on_left
;
1604 case ir_binop_gequal
:
1605 switch_order
= true;
1606 negate
= zero_on_left
;
1610 /* This isn't the right kind of comparison afterall, so make sure
1611 * the whole condition is visited.
1619 src_ir
->accept(this);
1621 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1622 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1623 * choose which value OPCODE_CMP produces without an extra instruction
1624 * computing the condition.
1627 this->result
.negate
= ~this->result
.negate
;
1629 return switch_order
;
1633 ir_to_mesa_visitor::visit(ir_assignment
*ir
)
1639 ir
->rhs
->accept(this);
1642 l
= get_assignment_lhs(ir
->lhs
, this);
1644 /* FINISHME: This should really set to the correct maximal writemask for each
1645 * FINISHME: component written (in the loops below). This case can only
1646 * FINISHME: occur for matrices, arrays, and structures.
1648 if (ir
->write_mask
== 0) {
1649 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
1650 l
.writemask
= WRITEMASK_XYZW
;
1651 } else if (ir
->lhs
->type
->is_scalar()) {
1652 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1653 * FINISHME: W component of fragment shader output zero, work correctly.
1655 l
.writemask
= WRITEMASK_XYZW
;
1658 int first_enabled_chan
= 0;
1661 assert(ir
->lhs
->type
->is_vector());
1662 l
.writemask
= ir
->write_mask
;
1664 for (int i
= 0; i
< 4; i
++) {
1665 if (l
.writemask
& (1 << i
)) {
1666 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
1671 /* Swizzle a small RHS vector into the channels being written.
1673 * glsl ir treats write_mask as dictating how many channels are
1674 * present on the RHS while Mesa IR treats write_mask as just
1675 * showing which channels of the vec4 RHS get written.
1677 for (int i
= 0; i
< 4; i
++) {
1678 if (l
.writemask
& (1 << i
))
1679 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
1681 swizzles
[i
] = first_enabled_chan
;
1683 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
1684 swizzles
[2], swizzles
[3]);
1687 assert(l
.file
!= PROGRAM_UNDEFINED
);
1688 assert(r
.file
!= PROGRAM_UNDEFINED
);
1690 if (ir
->condition
) {
1691 const bool switch_order
= this->process_move_condition(ir
->condition
);
1692 src_reg condition
= this->result
;
1694 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1696 emit(ir
, OPCODE_CMP
, l
, condition
, src_reg(l
), r
);
1698 emit(ir
, OPCODE_CMP
, l
, condition
, r
, src_reg(l
));
1705 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1706 emit(ir
, OPCODE_MOV
, l
, r
);
1715 ir_to_mesa_visitor::visit(ir_constant
*ir
)
1718 GLfloat stack_vals
[4] = { 0 };
1719 GLfloat
*values
= stack_vals
;
1722 /* Unfortunately, 4 floats is all we can get into
1723 * _mesa_add_unnamed_constant. So, make a temp to store an
1724 * aggregate constant and move each constant value into it. If we
1725 * get lucky, copy propagation will eliminate the extra moves.
1728 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1729 src_reg temp_base
= get_temp(ir
->type
);
1730 dst_reg temp
= dst_reg(temp_base
);
1732 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
1733 int size
= type_size(field_value
->type
);
1737 field_value
->accept(this);
1740 for (i
= 0; i
< (unsigned int)size
; i
++) {
1741 emit(ir
, OPCODE_MOV
, temp
, src
);
1747 this->result
= temp_base
;
1751 if (ir
->type
->is_array()) {
1752 src_reg temp_base
= get_temp(ir
->type
);
1753 dst_reg temp
= dst_reg(temp_base
);
1754 int size
= type_size(ir
->type
->fields
.array
);
1758 for (i
= 0; i
< ir
->type
->length
; i
++) {
1759 ir
->array_elements
[i
]->accept(this);
1761 for (int j
= 0; j
< size
; j
++) {
1762 emit(ir
, OPCODE_MOV
, temp
, src
);
1768 this->result
= temp_base
;
1772 if (ir
->type
->is_matrix()) {
1773 src_reg mat
= get_temp(ir
->type
);
1774 dst_reg mat_column
= dst_reg(mat
);
1776 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1777 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1778 values
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
1780 src
= src_reg(PROGRAM_CONSTANT
, -1, NULL
);
1781 src
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1782 (gl_constant_value
*) values
,
1783 ir
->type
->vector_elements
,
1785 emit(ir
, OPCODE_MOV
, mat_column
, src
);
1794 src
.file
= PROGRAM_CONSTANT
;
1795 switch (ir
->type
->base_type
) {
1796 case GLSL_TYPE_FLOAT
:
1797 values
= &ir
->value
.f
[0];
1799 case GLSL_TYPE_UINT
:
1800 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1801 values
[i
] = ir
->value
.u
[i
];
1805 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1806 values
[i
] = ir
->value
.i
[i
];
1809 case GLSL_TYPE_BOOL
:
1810 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1811 values
[i
] = ir
->value
.b
[i
];
1815 assert(!"Non-float/uint/int/bool constant");
1818 this->result
= src_reg(PROGRAM_CONSTANT
, -1, ir
->type
);
1819 this->result
.index
= _mesa_add_unnamed_constant(this->prog
->Parameters
,
1820 (gl_constant_value
*) values
,
1821 ir
->type
->vector_elements
,
1822 &this->result
.swizzle
);
1826 ir_to_mesa_visitor::visit(ir_call
*)
1828 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
1832 ir_to_mesa_visitor::visit(ir_texture
*ir
)
1834 src_reg result_src
, coord
, lod_info
, projector
, dx
, dy
;
1835 dst_reg result_dst
, coord_dst
;
1836 ir_to_mesa_instruction
*inst
= NULL
;
1837 prog_opcode opcode
= OPCODE_NOP
;
1839 if (ir
->op
== ir_txs
)
1840 this->result
= src_reg_for_float(0.0);
1842 ir
->coordinate
->accept(this);
1844 /* Put our coords in a temp. We'll need to modify them for shadow,
1845 * projection, or LOD, so the only case we'd use it as is is if
1846 * we're doing plain old texturing. Mesa IR optimization should
1847 * handle cleaning up our mess in that case.
1849 coord
= get_temp(glsl_type::vec4_type
);
1850 coord_dst
= dst_reg(coord
);
1851 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1853 if (ir
->projector
) {
1854 ir
->projector
->accept(this);
1855 projector
= this->result
;
1858 /* Storage for our result. Ideally for an assignment we'd be using
1859 * the actual storage for the result here, instead.
1861 result_src
= get_temp(glsl_type::vec4_type
);
1862 result_dst
= dst_reg(result_src
);
1867 opcode
= OPCODE_TEX
;
1870 opcode
= OPCODE_TXB
;
1871 ir
->lod_info
.bias
->accept(this);
1872 lod_info
= this->result
;
1875 /* Pretend to be TXL so the sampler, coordinate, lod are available */
1877 opcode
= OPCODE_TXL
;
1878 ir
->lod_info
.lod
->accept(this);
1879 lod_info
= this->result
;
1882 opcode
= OPCODE_TXD
;
1883 ir
->lod_info
.grad
.dPdx
->accept(this);
1885 ir
->lod_info
.grad
.dPdy
->accept(this);
1889 assert(!"Unexpected ir_txf_ms opcode");
1892 assert(!"Unexpected ir_lod opcode");
1895 assert(!"Unexpected ir_tg4 opcode");
1897 case ir_query_levels
:
1898 assert(!"Unexpected ir_query_levels opcode");
1900 case ir_samples_identical
:
1901 unreachable("Unexpected ir_samples_identical opcode");
1902 case ir_texture_samples
:
1903 unreachable("Unexpected ir_texture_samples opcode");
1906 const glsl_type
*sampler_type
= ir
->sampler
->type
;
1908 if (ir
->projector
) {
1909 if (opcode
== OPCODE_TEX
) {
1910 /* Slot the projector in as the last component of the coord. */
1911 coord_dst
.writemask
= WRITEMASK_W
;
1912 emit(ir
, OPCODE_MOV
, coord_dst
, projector
);
1913 coord_dst
.writemask
= WRITEMASK_XYZW
;
1914 opcode
= OPCODE_TXP
;
1916 src_reg coord_w
= coord
;
1917 coord_w
.swizzle
= SWIZZLE_WWWW
;
1919 /* For the other TEX opcodes there's no projective version
1920 * since the last slot is taken up by lod info. Do the
1921 * projective divide now.
1923 coord_dst
.writemask
= WRITEMASK_W
;
1924 emit(ir
, OPCODE_RCP
, coord_dst
, projector
);
1926 /* In the case where we have to project the coordinates "by hand,"
1927 * the shadow comparitor value must also be projected.
1929 src_reg tmp_src
= coord
;
1930 if (ir
->shadow_comparitor
) {
1931 /* Slot the shadow value in as the second to last component of the
1934 ir
->shadow_comparitor
->accept(this);
1936 tmp_src
= get_temp(glsl_type::vec4_type
);
1937 dst_reg tmp_dst
= dst_reg(tmp_src
);
1939 /* Projective division not allowed for array samplers. */
1940 assert(!sampler_type
->sampler_array
);
1942 tmp_dst
.writemask
= WRITEMASK_Z
;
1943 emit(ir
, OPCODE_MOV
, tmp_dst
, this->result
);
1945 tmp_dst
.writemask
= WRITEMASK_XY
;
1946 emit(ir
, OPCODE_MOV
, tmp_dst
, coord
);
1949 coord_dst
.writemask
= WRITEMASK_XYZ
;
1950 emit(ir
, OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
1952 coord_dst
.writemask
= WRITEMASK_XYZW
;
1953 coord
.swizzle
= SWIZZLE_XYZW
;
1957 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
1958 * comparitor was put in the correct place (and projected) by the code,
1959 * above, that handles by-hand projection.
1961 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== OPCODE_TXP
)) {
1962 /* Slot the shadow value in as the second to last component of the
1965 ir
->shadow_comparitor
->accept(this);
1967 /* XXX This will need to be updated for cubemap array samplers. */
1968 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
1969 sampler_type
->sampler_array
) {
1970 coord_dst
.writemask
= WRITEMASK_W
;
1972 coord_dst
.writemask
= WRITEMASK_Z
;
1975 emit(ir
, OPCODE_MOV
, coord_dst
, this->result
);
1976 coord_dst
.writemask
= WRITEMASK_XYZW
;
1979 if (opcode
== OPCODE_TXL
|| opcode
== OPCODE_TXB
) {
1980 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
1981 coord_dst
.writemask
= WRITEMASK_W
;
1982 emit(ir
, OPCODE_MOV
, coord_dst
, lod_info
);
1983 coord_dst
.writemask
= WRITEMASK_XYZW
;
1986 if (opcode
== OPCODE_TXD
)
1987 inst
= emit(ir
, opcode
, result_dst
, coord
, dx
, dy
);
1989 inst
= emit(ir
, opcode
, result_dst
, coord
);
1991 if (ir
->shadow_comparitor
)
1992 inst
->tex_shadow
= GL_TRUE
;
1994 inst
->sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1995 this->shader_program
,
1998 switch (sampler_type
->sampler_dimensionality
) {
1999 case GLSL_SAMPLER_DIM_1D
:
2000 inst
->tex_target
= (sampler_type
->sampler_array
)
2001 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
2003 case GLSL_SAMPLER_DIM_2D
:
2004 inst
->tex_target
= (sampler_type
->sampler_array
)
2005 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
2007 case GLSL_SAMPLER_DIM_3D
:
2008 inst
->tex_target
= TEXTURE_3D_INDEX
;
2010 case GLSL_SAMPLER_DIM_CUBE
:
2011 inst
->tex_target
= TEXTURE_CUBE_INDEX
;
2013 case GLSL_SAMPLER_DIM_RECT
:
2014 inst
->tex_target
= TEXTURE_RECT_INDEX
;
2016 case GLSL_SAMPLER_DIM_BUF
:
2017 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2019 case GLSL_SAMPLER_DIM_EXTERNAL
:
2020 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
2023 assert(!"Should not get here.");
2026 this->result
= result_src
;
2030 ir_to_mesa_visitor::visit(ir_return
*ir
)
2032 /* Non-void functions should have been inlined. We may still emit RETs
2033 * from main() unless the EmitNoMainReturn option is set.
2035 assert(!ir
->get_value());
2036 emit(ir
, OPCODE_RET
);
2040 ir_to_mesa_visitor::visit(ir_discard
*ir
)
2042 if (ir
->condition
) {
2043 ir
->condition
->accept(this);
2044 this->result
.negate
= ~this->result
.negate
;
2045 emit(ir
, OPCODE_KIL
, undef_dst
, this->result
);
2047 emit(ir
, OPCODE_KIL_NV
);
2052 ir_to_mesa_visitor::visit(ir_if
*ir
)
2054 ir_to_mesa_instruction
*cond_inst
, *if_inst
;
2055 ir_to_mesa_instruction
*prev_inst
;
2057 prev_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2059 ir
->condition
->accept(this);
2060 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
2062 if (this->options
->EmitCondCodes
) {
2063 cond_inst
= (ir_to_mesa_instruction
*)this->instructions
.get_tail();
2065 /* See if we actually generated any instruction for generating
2066 * the condition. If not, then cook up a move to a temp so we
2067 * have something to set cond_update on.
2069 if (cond_inst
== prev_inst
) {
2070 src_reg temp
= get_temp(glsl_type::bool_type
);
2071 cond_inst
= emit(ir
->condition
, OPCODE_MOV
, dst_reg(temp
), result
);
2073 cond_inst
->cond_update
= GL_TRUE
;
2075 if_inst
= emit(ir
->condition
, OPCODE_IF
);
2076 if_inst
->dst
.cond_mask
= COND_NE
;
2078 if_inst
= emit(ir
->condition
, OPCODE_IF
, undef_dst
, this->result
);
2081 this->instructions
.push_tail(if_inst
);
2083 visit_exec_list(&ir
->then_instructions
, this);
2085 if (!ir
->else_instructions
.is_empty()) {
2086 emit(ir
->condition
, OPCODE_ELSE
);
2087 visit_exec_list(&ir
->else_instructions
, this);
2090 emit(ir
->condition
, OPCODE_ENDIF
);
2094 ir_to_mesa_visitor::visit(ir_emit_vertex
*)
2096 assert(!"Geometry shaders not supported.");
2100 ir_to_mesa_visitor::visit(ir_end_primitive
*)
2102 assert(!"Geometry shaders not supported.");
2106 ir_to_mesa_visitor::visit(ir_barrier
*)
2108 unreachable("GLSL barrier() not supported.");
2111 ir_to_mesa_visitor::ir_to_mesa_visitor()
2113 result
.file
= PROGRAM_UNDEFINED
;
2115 next_signature_id
= 1;
2116 current_function
= NULL
;
2117 mem_ctx
= ralloc_context(NULL
);
2120 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2122 ralloc_free(mem_ctx
);
2125 static struct prog_src_register
2126 mesa_src_reg_from_ir_src_reg(src_reg reg
)
2128 struct prog_src_register mesa_reg
;
2130 mesa_reg
.File
= reg
.file
;
2131 assert(reg
.index
< (1 << INST_INDEX_BITS
));
2132 mesa_reg
.Index
= reg
.index
;
2133 mesa_reg
.Swizzle
= reg
.swizzle
;
2134 mesa_reg
.RelAddr
= reg
.reladdr
!= NULL
;
2135 mesa_reg
.Negate
= reg
.negate
;
2137 mesa_reg
.HasIndex2
= GL_FALSE
;
2138 mesa_reg
.RelAddr2
= 0;
2139 mesa_reg
.Index2
= 0;
2145 set_branchtargets(ir_to_mesa_visitor
*v
,
2146 struct prog_instruction
*mesa_instructions
,
2147 int num_instructions
)
2149 int if_count
= 0, loop_count
= 0;
2150 int *if_stack
, *loop_stack
;
2151 int if_stack_pos
= 0, loop_stack_pos
= 0;
2154 for (i
= 0; i
< num_instructions
; i
++) {
2155 switch (mesa_instructions
[i
].Opcode
) {
2159 case OPCODE_BGNLOOP
:
2164 mesa_instructions
[i
].BranchTarget
= -1;
2171 if_stack
= rzalloc_array(v
->mem_ctx
, int, if_count
);
2172 loop_stack
= rzalloc_array(v
->mem_ctx
, int, loop_count
);
2174 for (i
= 0; i
< num_instructions
; i
++) {
2175 switch (mesa_instructions
[i
].Opcode
) {
2177 if_stack
[if_stack_pos
] = i
;
2181 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2182 if_stack
[if_stack_pos
- 1] = i
;
2185 mesa_instructions
[if_stack
[if_stack_pos
- 1]].BranchTarget
= i
;
2188 case OPCODE_BGNLOOP
:
2189 loop_stack
[loop_stack_pos
] = i
;
2192 case OPCODE_ENDLOOP
:
2194 /* Rewrite any breaks/conts at this nesting level (haven't
2195 * already had a BranchTarget assigned) to point to the end
2198 for (j
= loop_stack
[loop_stack_pos
]; j
< i
; j
++) {
2199 if (mesa_instructions
[j
].Opcode
== OPCODE_BRK
||
2200 mesa_instructions
[j
].Opcode
== OPCODE_CONT
) {
2201 if (mesa_instructions
[j
].BranchTarget
== -1) {
2202 mesa_instructions
[j
].BranchTarget
= i
;
2206 /* The loop ends point at each other. */
2207 mesa_instructions
[i
].BranchTarget
= loop_stack
[loop_stack_pos
];
2208 mesa_instructions
[loop_stack
[loop_stack_pos
]].BranchTarget
= i
;
2211 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
2212 if (entry
->sig_id
== mesa_instructions
[i
].BranchTarget
) {
2213 mesa_instructions
[i
].BranchTarget
= entry
->inst
;
2225 print_program(struct prog_instruction
*mesa_instructions
,
2226 ir_instruction
**mesa_instruction_annotation
,
2227 int num_instructions
)
2229 ir_instruction
*last_ir
= NULL
;
2233 for (i
= 0; i
< num_instructions
; i
++) {
2234 struct prog_instruction
*mesa_inst
= mesa_instructions
+ i
;
2235 ir_instruction
*ir
= mesa_instruction_annotation
[i
];
2237 fprintf(stdout
, "%3d: ", i
);
2239 if (last_ir
!= ir
&& ir
) {
2242 for (j
= 0; j
< indent
; j
++) {
2243 fprintf(stdout
, " ");
2249 fprintf(stdout
, " "); /* line number spacing. */
2252 indent
= _mesa_fprint_instruction_opt(stdout
, mesa_inst
, indent
,
2253 PROG_PRINT_DEBUG
, NULL
);
2259 class add_uniform_to_shader
: public program_resource_visitor
{
2261 add_uniform_to_shader(struct gl_shader_program
*shader_program
,
2262 struct gl_program_parameter_list
*params
,
2263 gl_shader_stage shader_type
)
2264 : shader_program(shader_program
), params(params
), idx(-1),
2265 shader_type(shader_type
)
2270 void process(ir_variable
*var
)
2273 this->program_resource_visitor::process(var
);
2275 var
->data
.location
= this->idx
;
2279 virtual void visit_field(const glsl_type
*type
, const char *name
,
2282 struct gl_shader_program
*shader_program
;
2283 struct gl_program_parameter_list
*params
;
2285 gl_shader_stage shader_type
;
2288 } /* anonymous namespace */
2291 add_uniform_to_shader::visit_field(const glsl_type
*type
, const char *name
,
2298 if (type
->is_vector() || type
->is_scalar()) {
2299 size
= type
->vector_elements
;
2300 if (type
->is_double())
2303 size
= type_size(type
) * 4;
2306 gl_register_file file
;
2307 if (type
->without_array()->is_sampler()) {
2308 file
= PROGRAM_SAMPLER
;
2310 file
= PROGRAM_UNIFORM
;
2313 int index
= _mesa_lookup_parameter_index(params
, -1, name
);
2315 index
= _mesa_add_parameter(params
, file
, name
, size
, type
->gl_type
,
2318 /* Sampler uniform values are stored in prog->SamplerUnits,
2319 * and the entry in that array is selected by this index we
2320 * store in ParameterValues[].
2322 if (file
== PROGRAM_SAMPLER
) {
2325 this->shader_program
->UniformHash
->get(location
,
2326 params
->Parameters
[index
].Name
);
2332 struct gl_uniform_storage
*storage
=
2333 &this->shader_program
->UniformStorage
[location
];
2335 assert(storage
->type
->is_sampler() &&
2336 storage
->opaque
[shader_type
].active
);
2338 for (unsigned int j
= 0; j
< size
/ 4; j
++)
2339 params
->ParameterValues
[index
+ j
][0].f
=
2340 storage
->opaque
[shader_type
].index
+ j
;
2344 /* The first part of the uniform that's processed determines the base
2345 * location of the whole uniform (for structures).
2352 * Generate the program parameters list for the user uniforms in a shader
2354 * \param shader_program Linked shader program. This is only used to
2355 * emit possible link errors to the info log.
2356 * \param sh Shader whose uniforms are to be processed.
2357 * \param params Parameter list to be filled in.
2360 _mesa_generate_parameters_list_for_uniforms(struct gl_shader_program
2362 struct gl_shader
*sh
,
2363 struct gl_program_parameter_list
2366 add_uniform_to_shader
add(shader_program
, params
, sh
->Stage
);
2368 foreach_in_list(ir_instruction
, node
, sh
->ir
) {
2369 ir_variable
*var
= node
->as_variable();
2371 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
2372 || var
->is_in_buffer_block() || (strncmp(var
->name
, "gl_", 3) == 0))
2380 _mesa_associate_uniform_storage(struct gl_context
*ctx
,
2381 struct gl_shader_program
*shader_program
,
2382 struct gl_program_parameter_list
*params
)
2384 /* After adding each uniform to the parameter list, connect the storage for
2385 * the parameter with the tracking structure used by the API for the
2388 unsigned last_location
= unsigned(~0);
2389 for (unsigned i
= 0; i
< params
->NumParameters
; i
++) {
2390 if (params
->Parameters
[i
].Type
!= PROGRAM_UNIFORM
)
2395 shader_program
->UniformHash
->get(location
, params
->Parameters
[i
].Name
);
2401 struct gl_uniform_storage
*storage
=
2402 &shader_program
->UniformStorage
[location
];
2404 /* Do not associate any uniform storage to built-in uniforms */
2405 if (storage
->builtin
)
2408 if (location
!= last_location
) {
2409 enum gl_uniform_driver_format format
= uniform_native
;
2411 unsigned columns
= 0;
2412 int dmul
= 4 * sizeof(float);
2413 switch (storage
->type
->base_type
) {
2414 case GLSL_TYPE_UINT
:
2415 assert(ctx
->Const
.NativeIntegers
);
2416 format
= uniform_native
;
2421 (ctx
->Const
.NativeIntegers
) ? uniform_native
: uniform_int_float
;
2425 case GLSL_TYPE_DOUBLE
:
2426 if (storage
->type
->vector_elements
> 2)
2429 case GLSL_TYPE_FLOAT
:
2430 format
= uniform_native
;
2431 columns
= storage
->type
->matrix_columns
;
2433 case GLSL_TYPE_BOOL
:
2434 format
= uniform_native
;
2437 case GLSL_TYPE_SAMPLER
:
2438 case GLSL_TYPE_IMAGE
:
2439 case GLSL_TYPE_SUBROUTINE
:
2440 format
= uniform_native
;
2443 case GLSL_TYPE_ATOMIC_UINT
:
2444 case GLSL_TYPE_ARRAY
:
2445 case GLSL_TYPE_VOID
:
2446 case GLSL_TYPE_STRUCT
:
2447 case GLSL_TYPE_ERROR
:
2448 case GLSL_TYPE_INTERFACE
:
2449 assert(!"Should not get here.");
2453 _mesa_uniform_attach_driver_storage(storage
,
2457 ¶ms
->ParameterValues
[i
]);
2459 /* After attaching the driver's storage to the uniform, propagate any
2460 * data from the linker's backing store. This will cause values from
2461 * initializers in the source code to be copied over.
2463 _mesa_propagate_uniforms_to_driver_storage(storage
,
2465 MAX2(1, storage
->array_elements
));
2467 last_location
= location
;
2473 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2474 * channels for copy propagation and updates following instructions to
2475 * use the original versions.
2477 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2478 * will occur. As an example, a TXP production before this pass:
2480 * 0: MOV TEMP[1], INPUT[4].xyyy;
2481 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2482 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2486 * 0: MOV TEMP[1], INPUT[4].xyyy;
2487 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2488 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2490 * which allows for dead code elimination on TEMP[1]'s writes.
2493 ir_to_mesa_visitor::copy_propagate(void)
2495 ir_to_mesa_instruction
**acp
= rzalloc_array(mem_ctx
,
2496 ir_to_mesa_instruction
*,
2497 this->next_temp
* 4);
2498 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
2501 foreach_in_list(ir_to_mesa_instruction
, inst
, &this->instructions
) {
2502 assert(inst
->dst
.file
!= PROGRAM_TEMPORARY
2503 || inst
->dst
.index
< this->next_temp
);
2505 /* First, do any copy propagation possible into the src regs. */
2506 for (int r
= 0; r
< 3; r
++) {
2507 ir_to_mesa_instruction
*first
= NULL
;
2509 int acp_base
= inst
->src
[r
].index
* 4;
2511 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
2512 inst
->src
[r
].reladdr
)
2515 /* See if we can find entries in the ACP consisting of MOVs
2516 * from the same src register for all the swizzled channels
2517 * of this src register reference.
2519 for (int i
= 0; i
< 4; i
++) {
2520 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2521 ir_to_mesa_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
2528 assert(acp_level
[acp_base
+ src_chan
] <= level
);
2533 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
2534 first
->src
[0].index
!= copy_chan
->src
[0].index
) {
2542 /* We've now validated that we can copy-propagate to
2543 * replace this src register reference. Do it.
2545 inst
->src
[r
].file
= first
->src
[0].file
;
2546 inst
->src
[r
].index
= first
->src
[0].index
;
2549 for (int i
= 0; i
< 4; i
++) {
2550 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
2551 ir_to_mesa_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
2552 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) <<
2555 inst
->src
[r
].swizzle
= swizzle
;
2560 case OPCODE_BGNLOOP
:
2561 case OPCODE_ENDLOOP
:
2562 /* End of a basic block, clear the ACP entirely. */
2563 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2572 /* Clear all channels written inside the block from the ACP, but
2573 * leaving those that were not touched.
2575 for (int r
= 0; r
< this->next_temp
; r
++) {
2576 for (int c
= 0; c
< 4; c
++) {
2577 if (!acp
[4 * r
+ c
])
2580 if (acp_level
[4 * r
+ c
] >= level
)
2581 acp
[4 * r
+ c
] = NULL
;
2584 if (inst
->op
== OPCODE_ENDIF
)
2589 /* Continuing the block, clear any written channels from
2592 if (inst
->dst
.file
== PROGRAM_TEMPORARY
&& inst
->dst
.reladdr
) {
2593 /* Any temporary might be written, so no copy propagation
2594 * across this instruction.
2596 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
2597 } else if (inst
->dst
.file
== PROGRAM_OUTPUT
&&
2598 inst
->dst
.reladdr
) {
2599 /* Any output might be written, so no copy propagation
2600 * from outputs across this instruction.
2602 for (int r
= 0; r
< this->next_temp
; r
++) {
2603 for (int c
= 0; c
< 4; c
++) {
2604 if (!acp
[4 * r
+ c
])
2607 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
2608 acp
[4 * r
+ c
] = NULL
;
2611 } else if (inst
->dst
.file
== PROGRAM_TEMPORARY
||
2612 inst
->dst
.file
== PROGRAM_OUTPUT
) {
2613 /* Clear where it's used as dst. */
2614 if (inst
->dst
.file
== PROGRAM_TEMPORARY
) {
2615 for (int c
= 0; c
< 4; c
++) {
2616 if (inst
->dst
.writemask
& (1 << c
)) {
2617 acp
[4 * inst
->dst
.index
+ c
] = NULL
;
2622 /* Clear where it's used as src. */
2623 for (int r
= 0; r
< this->next_temp
; r
++) {
2624 for (int c
= 0; c
< 4; c
++) {
2625 if (!acp
[4 * r
+ c
])
2628 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
2630 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
.file
&&
2631 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
.index
&&
2632 inst
->dst
.writemask
& (1 << src_chan
))
2634 acp
[4 * r
+ c
] = NULL
;
2642 /* If this is a copy, add it to the ACP. */
2643 if (inst
->op
== OPCODE_MOV
&&
2644 inst
->dst
.file
== PROGRAM_TEMPORARY
&&
2645 !(inst
->dst
.file
== inst
->src
[0].file
&&
2646 inst
->dst
.index
== inst
->src
[0].index
) &&
2647 !inst
->dst
.reladdr
&&
2649 !inst
->src
[0].reladdr
&&
2650 !inst
->src
[0].negate
) {
2651 for (int i
= 0; i
< 4; i
++) {
2652 if (inst
->dst
.writemask
& (1 << i
)) {
2653 acp
[4 * inst
->dst
.index
+ i
] = inst
;
2654 acp_level
[4 * inst
->dst
.index
+ i
] = level
;
2660 ralloc_free(acp_level
);
2666 * Convert a shader's GLSL IR into a Mesa gl_program.
2668 static struct gl_program
*
2669 get_mesa_program(struct gl_context
*ctx
,
2670 struct gl_shader_program
*shader_program
,
2671 struct gl_shader
*shader
)
2673 ir_to_mesa_visitor v
;
2674 struct prog_instruction
*mesa_instructions
, *mesa_inst
;
2675 ir_instruction
**mesa_instruction_annotation
;
2677 struct gl_program
*prog
;
2678 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
2679 const char *target_string
= _mesa_shader_stage_to_string(shader
->Stage
);
2680 struct gl_shader_compiler_options
*options
=
2681 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
2683 validate_ir_tree(shader
->ir
);
2685 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
2688 prog
->Parameters
= _mesa_new_parameter_list();
2691 v
.shader_program
= shader_program
;
2692 v
.options
= options
;
2694 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
2697 /* Emit Mesa IR for main(). */
2698 visit_exec_list(shader
->ir
, &v
);
2699 v
.emit(NULL
, OPCODE_END
);
2701 prog
->NumTemporaries
= v
.next_temp
;
2703 unsigned num_instructions
= v
.instructions
.length();
2706 (struct prog_instruction
*)calloc(num_instructions
,
2707 sizeof(*mesa_instructions
));
2708 mesa_instruction_annotation
= ralloc_array(v
.mem_ctx
, ir_instruction
*,
2713 /* Convert ir_mesa_instructions into prog_instructions.
2715 mesa_inst
= mesa_instructions
;
2717 foreach_in_list(const ir_to_mesa_instruction
, inst
, &v
.instructions
) {
2718 mesa_inst
->Opcode
= inst
->op
;
2719 mesa_inst
->CondUpdate
= inst
->cond_update
;
2721 mesa_inst
->Saturate
= GL_TRUE
;
2722 mesa_inst
->DstReg
.File
= inst
->dst
.file
;
2723 mesa_inst
->DstReg
.Index
= inst
->dst
.index
;
2724 mesa_inst
->DstReg
.CondMask
= inst
->dst
.cond_mask
;
2725 mesa_inst
->DstReg
.WriteMask
= inst
->dst
.writemask
;
2726 mesa_inst
->DstReg
.RelAddr
= inst
->dst
.reladdr
!= NULL
;
2727 mesa_inst
->SrcReg
[0] = mesa_src_reg_from_ir_src_reg(inst
->src
[0]);
2728 mesa_inst
->SrcReg
[1] = mesa_src_reg_from_ir_src_reg(inst
->src
[1]);
2729 mesa_inst
->SrcReg
[2] = mesa_src_reg_from_ir_src_reg(inst
->src
[2]);
2730 mesa_inst
->TexSrcUnit
= inst
->sampler
;
2731 mesa_inst
->TexSrcTarget
= inst
->tex_target
;
2732 mesa_inst
->TexShadow
= inst
->tex_shadow
;
2733 mesa_instruction_annotation
[i
] = inst
->ir
;
2735 /* Set IndirectRegisterFiles. */
2736 if (mesa_inst
->DstReg
.RelAddr
)
2737 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->DstReg
.File
;
2739 /* Update program's bitmask of indirectly accessed register files */
2740 for (unsigned src
= 0; src
< 3; src
++)
2741 if (mesa_inst
->SrcReg
[src
].RelAddr
)
2742 prog
->IndirectRegisterFiles
|= 1 << mesa_inst
->SrcReg
[src
].File
;
2744 switch (mesa_inst
->Opcode
) {
2746 if (options
->MaxIfDepth
== 0) {
2747 linker_warning(shader_program
,
2748 "Couldn't flatten if-statement. "
2749 "This will likely result in software "
2750 "rasterization.\n");
2753 case OPCODE_BGNLOOP
:
2754 if (options
->EmitNoLoops
) {
2755 linker_warning(shader_program
,
2756 "Couldn't unroll loop. "
2757 "This will likely result in software "
2758 "rasterization.\n");
2762 if (options
->EmitNoCont
) {
2763 linker_warning(shader_program
,
2764 "Couldn't lower continue-statement. "
2765 "This will likely result in software "
2766 "rasterization.\n");
2770 prog
->NumAddressRegs
= 1;
2779 if (!shader_program
->LinkStatus
)
2783 if (!shader_program
->LinkStatus
) {
2787 set_branchtargets(&v
, mesa_instructions
, num_instructions
);
2789 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2790 fprintf(stderr
, "\n");
2791 fprintf(stderr
, "GLSL IR for linked %s program %d:\n", target_string
,
2792 shader_program
->Name
);
2793 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
2794 fprintf(stderr
, "\n");
2795 fprintf(stderr
, "\n");
2796 fprintf(stderr
, "Mesa IR for linked %s program %d:\n", target_string
,
2797 shader_program
->Name
);
2798 print_program(mesa_instructions
, mesa_instruction_annotation
,
2803 prog
->Instructions
= mesa_instructions
;
2804 prog
->NumInstructions
= num_instructions
;
2806 /* Setting this to NULL prevents a possible double free in the fail_exit
2809 mesa_instructions
= NULL
;
2811 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
2813 prog
->SamplersUsed
= shader
->active_samplers
;
2814 prog
->ShadowSamplers
= shader
->shadow_samplers
;
2815 _mesa_update_shader_textures_used(shader_program
, prog
);
2817 /* Set the gl_FragDepth layout. */
2818 if (target
== GL_FRAGMENT_PROGRAM_ARB
) {
2819 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)prog
;
2820 fp
->FragDepthLayout
= shader_program
->FragDepthLayout
;
2823 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
2825 if ((ctx
->_Shader
->Flags
& GLSL_NO_OPT
) == 0) {
2826 _mesa_optimize_program(ctx
, prog
);
2829 /* This has to be done last. Any operation that can cause
2830 * prog->ParameterValues to get reallocated (e.g., anything that adds a
2831 * program constant) has to happen before creating this linkage.
2833 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
2834 if (!shader_program
->LinkStatus
) {
2841 free(mesa_instructions
);
2842 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
2850 * Called via ctx->Driver.LinkShader()
2851 * This actually involves converting GLSL IR into Mesa gl_programs with
2852 * code lowering and other optimizations.
2855 _mesa_ir_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2857 assert(prog
->LinkStatus
);
2859 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2860 if (prog
->_LinkedShaders
[i
] == NULL
)
2864 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
2865 const struct gl_shader_compiler_options
*options
=
2866 &ctx
->Const
.ShaderCompilerOptions
[prog
->_LinkedShaders
[i
]->Stage
];
2872 do_mat_op_to_vec(ir
);
2873 lower_instructions(ir
, (MOD_TO_FLOOR
| DIV_TO_MUL_RCP
| EXP_TO_EXP2
2874 | LOG_TO_LOG2
| INT_DIV_TO_MUL_RCP
2875 | ((options
->EmitNoPow
) ? POW_TO_EXP2
: 0)));
2877 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
2879 progress
= do_common_optimization(ir
, true, true,
2880 options
, ctx
->Const
.NativeIntegers
)
2883 progress
= lower_quadop_vector(ir
, true) || progress
;
2885 if (options
->MaxIfDepth
== 0)
2886 progress
= lower_discard(ir
) || progress
;
2888 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
2890 if (options
->EmitNoNoise
)
2891 progress
= lower_noise(ir
) || progress
;
2893 /* If there are forms of indirect addressing that the driver
2894 * cannot handle, perform the lowering pass.
2896 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
2897 || options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
)
2899 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
2900 options
->EmitNoIndirectInput
,
2901 options
->EmitNoIndirectOutput
,
2902 options
->EmitNoIndirectTemp
,
2903 options
->EmitNoIndirectUniform
)
2906 progress
= do_vec_index_to_cond_assign(ir
) || progress
;
2907 progress
= lower_vector_insert(ir
, true) || progress
;
2910 validate_ir_tree(ir
);
2913 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2914 struct gl_program
*linked_prog
;
2916 if (prog
->_LinkedShaders
[i
] == NULL
)
2919 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
2922 _mesa_copy_linked_program_data((gl_shader_stage
) i
, prog
, linked_prog
);
2924 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
2926 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
2927 _mesa_shader_stage_to_program(i
),
2933 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
2936 return prog
->LinkStatus
;
2940 * Link a GLSL shader program. Called via glLinkProgram().
2943 _mesa_glsl_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
2947 _mesa_clear_shader_program_data(prog
);
2949 prog
->LinkStatus
= GL_TRUE
;
2951 for (i
= 0; i
< prog
->NumShaders
; i
++) {
2952 if (!prog
->Shaders
[i
]->CompileStatus
) {
2953 linker_error(prog
, "linking with uncompiled shader");
2957 if (prog
->LinkStatus
) {
2958 link_shaders(ctx
, prog
);
2961 if (prog
->LinkStatus
) {
2962 if (!ctx
->Driver
.LinkShader(ctx
, prog
)) {
2963 prog
->LinkStatus
= GL_FALSE
;
2965 build_program_resource_list(prog
);
2969 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
2970 if (!prog
->LinkStatus
) {
2971 fprintf(stderr
, "GLSL shader program %d failed to link\n", prog
->Name
);
2974 if (prog
->InfoLog
&& prog
->InfoLog
[0] != 0) {
2975 fprintf(stderr
, "GLSL shader program %d info log:\n", prog
->Name
);
2976 fprintf(stderr
, "%s\n", prog
->InfoLog
);