src/mesa/program/prog_instruction.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 1999-2008  Brian Paul   All Rights Reserved.
   5  * Copyright (C) 1999-2009  VMware, Inc.  All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  23  * OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26
  27 #include <stdio.h>
  28 #include "main/glheader.h"
  29 #include "util/imports.h"
  30 #include "prog_instruction.h"
  31 #include "prog_parameter.h"
  32
  33
  34 /**
  35  * Initialize program instruction fields to defaults.
  36  * \param inst  first instruction to initialize
  37  * \param count  number of instructions to initialize
  38  */
  39 void
  40 _mesa_init_instructions(struct prog_instruction *inst, GLuint count)
  41 {
  42    GLuint i;
  43
  44    memset(inst, 0, count * sizeof(struct prog_instruction));
  45
  46    for (i = 0; i < count; i++) {
  47       inst[i].SrcReg[0].File = PROGRAM_UNDEFINED;
  48       inst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
  49       inst[i].SrcReg[1].File = PROGRAM_UNDEFINED;
  50       inst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
  51       inst[i].SrcReg[2].File = PROGRAM_UNDEFINED;
  52       inst[i].SrcReg[2].Swizzle = SWIZZLE_NOOP;
  53
  54       inst[i].DstReg.File = PROGRAM_UNDEFINED;
  55       inst[i].DstReg.WriteMask = WRITEMASK_XYZW;
  56
  57       inst[i].Saturate = GL_FALSE;
  58    }
  59 }
  60
  61
  62 /**
  63  * Copy an array of program instructions.
  64  * \param dest  pointer to destination.
  65  * \param src  pointer to source.
  66  * \param n  number of instructions to copy.
  67  * \return pointer to destination.
  68  */
  69 struct prog_instruction *
  70 _mesa_copy_instructions(struct prog_instruction *dest,
  71                         const struct prog_instruction *src, GLuint n)
  72 {
  73    memcpy(dest, src, n * sizeof(struct prog_instruction));
  74    return dest;
  75 }
  76
  77
  78 /**
  79  * Basic info about each instruction
  80  */
  81 struct instruction_info
  82 {
  83    enum prog_opcode Opcode;
  84    const char *Name;
  85    GLuint NumSrcRegs;
  86    GLuint NumDstRegs;
  87 };
  88
  89 /**
  90  * Instruction info
  91  * \note Opcode should equal array index!
  92  */
  93 static const struct instruction_info InstInfo[MAX_OPCODE] = {
  94    { OPCODE_NOP,    "NOP",     0, 0 },
  95    { OPCODE_ABS,    "ABS",     1, 1 },
  96    { OPCODE_ADD,    "ADD",     2, 1 },
  97    { OPCODE_ARL,    "ARL",     1, 1 },
  98    { OPCODE_BGNLOOP,"BGNLOOP", 0, 0 },
  99    { OPCODE_BGNSUB, "BGNSUB",  0, 0 },
 100    { OPCODE_BRK,    "BRK",     0, 0 },
 101    { OPCODE_CAL,    "CAL",     0, 0 },
 102    { OPCODE_CMP,    "CMP",     3, 1 },
 103    { OPCODE_CONT,   "CONT",    0, 0 },
 104    { OPCODE_COS,    "COS",     1, 1 },
 105    { OPCODE_DDX,    "DDX",     1, 1 },
 106    { OPCODE_DDY,    "DDY",     1, 1 },
 107    { OPCODE_DP2,    "DP2",     2, 1 },
 108    { OPCODE_DP3,    "DP3",     2, 1 },
 109    { OPCODE_DP4,    "DP4",     2, 1 },
 110    { OPCODE_DPH,    "DPH",     2, 1 },
 111    { OPCODE_DST,    "DST",     2, 1 },
 112    { OPCODE_ELSE,   "ELSE",    0, 0 },
 113    { OPCODE_END,    "END",     0, 0 },
 114    { OPCODE_ENDIF,  "ENDIF",   0, 0 },
 115    { OPCODE_ENDLOOP,"ENDLOOP", 0, 0 },
 116    { OPCODE_ENDSUB, "ENDSUB",  0, 0 },
 117    { OPCODE_EX2,    "EX2",     1, 1 },
 118    { OPCODE_EXP,    "EXP",     1, 1 },
 119    { OPCODE_FLR,    "FLR",     1, 1 },
 120    { OPCODE_FRC,    "FRC",     1, 1 },
 121    { OPCODE_IF,     "IF",      1, 0 },
 122    { OPCODE_KIL,    "KIL",     1, 0 },
 123    { OPCODE_LG2,    "LG2",     1, 1 },
 124    { OPCODE_LIT,    "LIT",     1, 1 },
 125    { OPCODE_LOG,    "LOG",     1, 1 },
 126    { OPCODE_LRP,    "LRP",     3, 1 },
 127    { OPCODE_MAD,    "MAD",     3, 1 },
 128    { OPCODE_MAX,    "MAX",     2, 1 },
 129    { OPCODE_MIN,    "MIN",     2, 1 },
 130    { OPCODE_MOV,    "MOV",     1, 1 },
 131    { OPCODE_MUL,    "MUL",     2, 1 },
 132    { OPCODE_NOISE1, "NOISE1",  1, 1 },
 133    { OPCODE_NOISE2, "NOISE2",  1, 1 },
 134    { OPCODE_NOISE3, "NOISE3",  1, 1 },
 135    { OPCODE_NOISE4, "NOISE4",  1, 1 },
 136    { OPCODE_POW,    "POW",     2, 1 },
 137    { OPCODE_RCP,    "RCP",     1, 1 },
 138    { OPCODE_RET,    "RET",     0, 0 },
 139    { OPCODE_RSQ,    "RSQ",     1, 1 },
 140    { OPCODE_SCS,    "SCS",     1, 1 },
 141    { OPCODE_SGE,    "SGE",     2, 1 },
 142    { OPCODE_SIN,    "SIN",     1, 1 },
 143    { OPCODE_SLT,    "SLT",     2, 1 },
 144    { OPCODE_SSG,    "SSG",     1, 1 },
 145    { OPCODE_SUB,    "SUB",     2, 1 },
 146    { OPCODE_SWZ,    "SWZ",     1, 1 },
 147    { OPCODE_TEX,    "TEX",     1, 1 },
 148    { OPCODE_TXB,    "TXB",     1, 1 },
 149    { OPCODE_TXD,    "TXD",     3, 1 },
 150    { OPCODE_TXL,    "TXL",     1, 1 },
 151    { OPCODE_TXP,    "TXP",     1, 1 },
 152    { OPCODE_TRUNC,  "TRUNC",   1, 1 },
 153    { OPCODE_XPD,    "XPD",     2, 1 }
 154 };
 155
 156
 157 /**
 158  * Return the number of src registers for the given instruction/opcode.
 159  */
 160 GLuint
 161 _mesa_num_inst_src_regs(enum prog_opcode opcode)
 162 {
 163    assert(opcode < MAX_OPCODE);
 164    assert(opcode == InstInfo[opcode].Opcode);
 165    assert(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
 166    return InstInfo[opcode].NumSrcRegs;
 167 }
 168
 169
 170 /**
 171  * Return the number of dst registers for the given instruction/opcode.
 172  */
 173 GLuint
 174 _mesa_num_inst_dst_regs(enum prog_opcode opcode)
 175 {
 176    assert(opcode < MAX_OPCODE);
 177    assert(opcode == InstInfo[opcode].Opcode);
 178    assert(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
 179    return InstInfo[opcode].NumDstRegs;
 180 }
 181
 182
 183 GLboolean
 184 _mesa_is_tex_instruction(enum prog_opcode opcode)
 185 {
 186    return (opcode == OPCODE_TEX ||
 187            opcode == OPCODE_TXB ||
 188            opcode == OPCODE_TXD ||
 189            opcode == OPCODE_TXL ||
 190            opcode == OPCODE_TXP);
 191 }
 192
 193
 194 /**
 195  * Check if there's a potential src/dst register data dependency when
 196  * using SOA execution.
 197  * Example:
 198  *   MOV T, T.yxwz;
 199  * This would expand into:
 200  *   MOV t0, t1;
 201  *   MOV t1, t0;
 202  *   MOV t2, t3;
 203  *   MOV t3, t2;
 204  * The second instruction will have the wrong value for t0 if executed as-is.
 205  */
 206 GLboolean
 207 _mesa_check_soa_dependencies(const struct prog_instruction *inst)
 208 {
 209    GLuint i, chan;
 210
 211    if (inst->DstReg.WriteMask == WRITEMASK_X ||
 212        inst->DstReg.WriteMask == WRITEMASK_Y ||
 213        inst->DstReg.WriteMask == WRITEMASK_Z ||
 214        inst->DstReg.WriteMask == WRITEMASK_W ||
 215        inst->DstReg.WriteMask == 0x0) {
 216       /* no chance of data dependency */
 217       return GL_FALSE;
 218    }
 219
 220    /* loop over src regs */
 221    for (i = 0; i < 3; i++) {
 222       if (inst->SrcReg[i].File == inst->DstReg.File &&
 223           inst->SrcReg[i].Index == inst->DstReg.Index) {
 224          /* loop over dest channels */
 225          GLuint channelsWritten = 0x0;
 226          for (chan = 0; chan < 4; chan++) {
 227             if (inst->DstReg.WriteMask & (1 << chan)) {
 228                /* check if we're reading a channel that's been written */
 229                GLuint swizzle = GET_SWZ(inst->SrcReg[i].Swizzle, chan);
 230                if (swizzle <= SWIZZLE_W &&
 231                    (channelsWritten & (1 << swizzle))) {
 232                   return GL_TRUE;
 233                }
 234
 235                channelsWritten |= (1 << chan);
 236             }
 237          }
 238       }
 239    }
 240    return GL_FALSE;
 241 }
 242
 243
 244 /**
 245  * Return string name for given program opcode.
 246  */
 247 const char *
 248 _mesa_opcode_string(enum prog_opcode opcode)
 249 {
 250    if (opcode < MAX_OPCODE)
 251       return InstInfo[opcode].Name;
 252    else {
 253       static char s[20];
 254       snprintf(s, sizeof(s), "OP%u", opcode);
 255       return s;
 256    }
 257 }
 258