2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_to_tgsi_temprename.h"
57 #include "util/hash_table.h"
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
64 #define MAX_GLSL_TEXTURE_OFFSET 4
67 #include "util/u_atomic.h"
68 #include "util/simple_mtx.h"
72 /* Prepare to make it possible to specify log file */
73 static std::ofstream stats_log
;
75 /* Helper function to check whether we want to write some statistics
76 * of the shader conversion.
79 static simple_mtx_t print_stats_mutex
= _SIMPLE_MTX_INITIALIZER_NP
;
81 static inline bool print_stats_enabled ()
83 static int stats_enabled
= 0;
86 simple_mtx_lock(&print_stats_mutex
);
88 const char *stats_filename
= getenv("GLSL_TO_TGSI_PRINT_STATS");
90 bool write_header
= std::ifstream(stats_filename
).fail();
91 stats_log
.open(stats_filename
, std::ios_base::out
| std::ios_base::app
);
92 stats_enabled
= stats_log
.good() ? 1 : -1;
94 stats_log
<< "arrays,temps,temps in arrays,total,instructions\n";
99 simple_mtx_unlock(&print_stats_mutex
);
101 return stats_enabled
> 0;
103 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
105 #define PRINT_STATS(X)
109 static unsigned is_precise(const ir_variable
*ir
)
113 return ir
->data
.precise
|| ir
->data
.invariant
;
116 class variable_storage
{
117 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
120 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
121 unsigned array_id
= 0)
122 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
124 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
127 gl_register_file file
;
130 /* Explicit component location. This is given in terms of the GLSL-style
131 * swizzles where each double is a single component, i.e. for 64-bit types
132 * it can only be 0 or 1.
135 ir_variable
*var
; /* variable that maps to this, if any */
139 class immediate_storage
: public exec_node
{
141 immediate_storage(gl_constant_value
*values
, int size32
, GLenum type
)
143 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
144 this->size32
= size32
;
148 /* doubles are stored across 2 gl_constant_values */
149 gl_constant_value values
[4];
150 int size32
; /**< Number of 32-bit components (1-4) */
151 GLenum type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
154 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
155 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
159 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
162 unsigned gs_out_streams
;
163 enum glsl_interp_mode interp
;
164 enum glsl_base_type base_type
;
165 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
169 static struct inout_decl
*
170 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
172 assert(array_id
!= 0);
174 for (unsigned i
= 0; i
< count
; i
++) {
175 struct inout_decl
*decl
= &decls
[i
];
177 if (array_id
== decl
->array_id
) {
185 static enum glsl_base_type
186 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
189 return GLSL_TYPE_ERROR
;
190 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
192 return decl
->base_type
;
193 return GLSL_TYPE_ERROR
;
196 struct hwatomic_decl
{
203 struct glsl_to_tgsi_visitor
: public ir_visitor
{
205 glsl_to_tgsi_visitor();
206 ~glsl_to_tgsi_visitor();
208 struct gl_context
*ctx
;
209 struct gl_program
*prog
;
210 struct gl_shader_program
*shader_program
;
211 struct gl_linked_shader
*shader
;
212 struct gl_shader_compiler_options
*options
;
216 unsigned *array_sizes
;
217 unsigned max_num_arrays
;
220 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
222 unsigned num_input_arrays
;
223 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
224 unsigned num_outputs
;
225 unsigned num_output_arrays
;
227 struct hwatomic_decl atomic_info
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
228 unsigned num_atomics
;
229 unsigned num_atomic_arrays
;
230 int num_address_regs
;
231 uint32_t samplers_used
;
232 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
233 enum tgsi_texture_type sampler_targets
[PIPE_MAX_SAMPLERS
];
235 enum tgsi_texture_type image_targets
[PIPE_MAX_SHADER_IMAGES
];
236 enum pipe_format image_formats
[PIPE_MAX_SHADER_IMAGES
];
237 bool image_wr
[PIPE_MAX_SHADER_IMAGES
];
238 bool indirect_addr_consts
;
239 int wpos_transform_const
;
241 bool native_integers
;
244 bool use_shared_memory
;
248 bool tg4_component_in_swizzle
;
250 variable_storage
*find_variable_storage(ir_variable
*var
);
252 int add_constant(gl_register_file file
, gl_constant_value values
[8],
253 int size
, GLenum datatype
, uint16_t *swizzle_out
);
255 st_src_reg
get_temp(const glsl_type
*type
);
256 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
258 st_src_reg
st_src_reg_for_double(double val
);
259 st_src_reg
st_src_reg_for_float(float val
);
260 st_src_reg
st_src_reg_for_int(int val
);
261 st_src_reg
st_src_reg_for_int64(int64_t val
);
262 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
265 * \name Visit methods
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
272 virtual void visit(ir_variable
*);
273 virtual void visit(ir_loop
*);
274 virtual void visit(ir_loop_jump
*);
275 virtual void visit(ir_function_signature
*);
276 virtual void visit(ir_function
*);
277 virtual void visit(ir_expression
*);
278 virtual void visit(ir_swizzle
*);
279 virtual void visit(ir_dereference_variable
*);
280 virtual void visit(ir_dereference_array
*);
281 virtual void visit(ir_dereference_record
*);
282 virtual void visit(ir_assignment
*);
283 virtual void visit(ir_constant
*);
284 virtual void visit(ir_call
*);
285 virtual void visit(ir_return
*);
286 virtual void visit(ir_discard
*);
287 virtual void visit(ir_demote
*);
288 virtual void visit(ir_texture
*);
289 virtual void visit(ir_if
*);
290 virtual void visit(ir_emit_vertex
*);
291 virtual void visit(ir_end_primitive
*);
292 virtual void visit(ir_barrier
*);
295 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
297 void visit_atomic_counter_intrinsic(ir_call
*);
298 void visit_ssbo_intrinsic(ir_call
*);
299 void visit_membar_intrinsic(ir_call
*);
300 void visit_shared_intrinsic(ir_call
*);
301 void visit_image_intrinsic(ir_call
*);
302 void visit_generic_intrinsic(ir_call
*, enum tgsi_opcode op
);
306 /** List of variable_storage */
307 struct hash_table
*variables
;
309 /** List of immediate_storage */
310 exec_list immediates
;
311 unsigned num_immediates
;
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions
;
316 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
317 st_dst_reg dst
= undef_dst
,
318 st_src_reg src0
= undef_src
,
319 st_src_reg src1
= undef_src
,
320 st_src_reg src2
= undef_src
,
321 st_src_reg src3
= undef_src
);
323 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
324 st_dst_reg dst
, st_dst_reg dst1
,
325 st_src_reg src0
= undef_src
,
326 st_src_reg src1
= undef_src
,
327 st_src_reg src2
= undef_src
,
328 st_src_reg src3
= undef_src
);
330 enum tgsi_opcode
get_opcode(enum tgsi_opcode op
,
332 st_src_reg src0
, st_src_reg src1
);
335 * Emit the correct dot-product instruction for the type of arguments
337 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
343 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
344 st_dst_reg dst
, st_src_reg src0
);
346 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
347 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
349 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
351 void get_deref_offsets(ir_dereference
*ir
,
352 unsigned *array_size
,
357 void calc_deref_offsets(ir_dereference
*tail
,
358 unsigned *array_elements
,
360 st_src_reg
*indirect
,
362 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
363 bool handle_bound_deref(ir_dereference
*ir
);
365 bool try_emit_mad(ir_expression
*ir
,
367 bool try_emit_mad_for_and_not(ir_expression
*ir
,
370 void emit_swz(ir_expression
*ir
);
372 bool process_move_condition(ir_rvalue
*ir
);
374 void simplify_cmp(void);
376 void rename_temp_registers(struct rename_reg_pair
*renames
);
377 void get_first_temp_read(int *first_reads
);
378 void get_first_temp_write(int *first_writes
);
379 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
380 void get_last_temp_write(int *last_writes
);
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
390 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
391 st_dst_reg
*l
, st_src_reg
*r
,
392 st_src_reg
*cond
, bool cond_swap
);
399 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
401 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
403 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
407 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
411 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
415 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
418 prog
->data
->LinkStatus
= LINKING_FAILURE
;
422 swizzle_for_size(int size
)
424 static const int size_swizzles
[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
426 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
427 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
428 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
431 assert((size
>= 1) && (size
<= 4));
432 return size_swizzles
[size
- 1];
436 glsl_to_tgsi_instruction
*
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
438 st_dst_reg dst
, st_dst_reg dst1
,
439 st_src_reg src0
, st_src_reg src1
,
440 st_src_reg src2
, st_src_reg src3
)
442 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
443 int num_reladdr
= 0, i
, j
;
444 bool dst_is_64bit
[2];
446 op
= get_opcode(op
, dst
, src0
, src1
);
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
452 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
453 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
454 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
455 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
456 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
457 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
459 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
460 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
461 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
462 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
464 if (dst
.reladdr
|| dst
.reladdr2
) {
466 emit_arl(ir
, address_reg
, *dst
.reladdr
);
468 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
472 assert(num_reladdr
== 0);
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
478 inst
->precise
= this->precise
;
479 inst
->info
= tgsi_get_opcode_info(op
);
486 inst
->is_64bit_expanded
= false;
489 inst
->tex_offsets
= NULL
;
490 inst
->tex_offset_num_offset
= 0;
492 inst
->tex_shadow
= 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
496 inst
->tex_type
= GLSL_TYPE_FLOAT
;
498 /* Update indirect addressing status used by TGSI */
499 if (dst
.reladdr
|| dst
.reladdr2
) {
501 case PROGRAM_STATE_VAR
:
502 case PROGRAM_CONSTANT
:
503 case PROGRAM_UNIFORM
:
504 this->indirect_addr_consts
= true;
506 case PROGRAM_IMMEDIATE
:
507 assert(!"immediates should not have indirect addressing");
514 for (i
= 0; i
< 4; i
++) {
515 if (inst
->src
[i
].reladdr
) {
516 switch (inst
->src
[i
].file
) {
517 case PROGRAM_STATE_VAR
:
518 case PROGRAM_CONSTANT
:
519 case PROGRAM_UNIFORM
:
520 this->indirect_addr_consts
= true;
522 case PROGRAM_IMMEDIATE
:
523 assert(!"immediates should not have indirect addressing");
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
550 for (j
= 0; j
< 2; j
++) {
551 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
552 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&&
553 inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
554 enum glsl_base_type type
= find_array_type(this->outputs
,
556 inst
->dst
[j
].array_id
);
557 if (glsl_base_type_is_64bit(type
))
558 dst_is_64bit
[j
] = true;
562 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
563 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
564 glsl_to_tgsi_instruction
*dinst
= NULL
;
565 int initial_src_swz
[4], initial_src_idx
[4];
566 int initial_dst_idx
[2], initial_dst_writemask
[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
569 ? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j
= 0; j
< 2; j
++) {
573 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
574 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
577 for (j
= 0; j
< 4; j
++) {
578 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
579 initial_src_idx
[j
] = inst
->src
[j
].index
;
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
589 int i
= u_bit_scan(&writemask
);
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
||
594 inst
->op
== TGSI_OPCODE_STORE
) &&
595 addr
.file
== PROGRAM_UNDEFINED
) {
596 /* We have to advance the buffer address by 16 */
597 addr
= get_temp(glsl_type::uint_type
);
598 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
599 inst
->src
[0], st_src_reg_for_int(16));
602 /* first time use previous instruction */
606 /* create a new instructions for subsequent attempts */
607 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
612 this->instructions
.push_tail(dinst
);
613 dinst
->is_64bit_expanded
= true;
615 /* modify the destination if we are splitting */
616 for (j
= 0; j
< 2; j
++) {
617 if (dst_is_64bit
[j
]) {
618 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
619 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
621 if (dinst
->op
== TGSI_OPCODE_LOAD
||
622 dinst
->op
== TGSI_OPCODE_STORE
)
623 dinst
->src
[0] = addr
;
624 if (dinst
->op
!= TGSI_OPCODE_STORE
)
625 dinst
->dst
[j
].index
++;
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
631 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
635 /* modify the src registers */
636 for (j
= 0; j
< 4; j
++) {
637 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
639 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
640 dinst
->src
[j
].index
= initial_src_idx
[j
];
642 dinst
->src
[j
].double_reg2
= true;
643 dinst
->src
[j
].index
++;
647 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
,
648 SWIZZLE_Z
, SWIZZLE_W
);
650 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
651 SWIZZLE_X
, SWIZZLE_Y
);
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
658 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
||
659 op
== TGSI_OPCODE_I2D
||
660 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
661 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
662 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
663 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
670 this->instructions
.push_tail(inst
);
677 glsl_to_tgsi_instruction
*
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
680 st_src_reg src0
, st_src_reg src1
,
681 st_src_reg src2
, st_src_reg src3
)
683 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op
,
693 st_src_reg src0
, st_src_reg src1
)
695 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
697 if (op
== TGSI_OPCODE_MOV
)
700 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
701 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
702 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
703 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
705 if (is_resource_instruction(op
))
707 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
708 type
= GLSL_TYPE_INT64
;
709 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
710 type
= GLSL_TYPE_UINT64
;
711 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
712 type
= GLSL_TYPE_DOUBLE
;
713 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
714 type
= GLSL_TYPE_FLOAT
;
715 else if (native_integers
)
716 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
731 op = TGSI_OPCODE_##f; \
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
749 op = TGSI_OPCODE_##c; \
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
758 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
759 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
760 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
761 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
762 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
763 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
764 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
765 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
766 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
767 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
768 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
769 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
770 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
771 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
772 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
773 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
775 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
776 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
777 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
778 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
779 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
780 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
781 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
782 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
783 case7(ATOMUADD
,ATOMFADD
,ATOMUADD
,ATOMUADD
,LAST
, LAST
, LAST
);
785 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
786 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
787 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
788 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
794 assert(op
!= TGSI_OPCODE_LAST
);
798 glsl_to_tgsi_instruction
*
799 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
800 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
803 static const enum tgsi_opcode dot_opcodes
[] = {
804 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
807 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
821 st_src_reg orig_src0
, st_src_reg orig_src1
)
824 int done_mask
= ~dst
.writemask
;
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
830 for (i
= 0; i
< 4; i
++) {
831 GLuint this_mask
= (1 << i
);
832 st_src_reg src0
= orig_src0
;
833 st_src_reg src1
= orig_src1
;
835 if (done_mask
& this_mask
)
838 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
839 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
840 for (j
= i
+ 1; j
< 4; j
++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
845 if (!(done_mask
& (1 << j
)) &&
846 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
847 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
848 this_mask
|= (1 << j
);
851 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
852 src0_swiz
, src0_swiz
);
853 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
854 src1_swiz
, src1_swiz
);
856 dst
.writemask
= this_mask
;
857 emit_asm(ir
, op
, dst
, src0
, src1
);
858 done_mask
|= this_mask
;
863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
864 st_dst_reg dst
, st_src_reg src0
)
866 st_src_reg undef
= undef_src
;
868 undef
.swizzle
= SWIZZLE_XXXX
;
870 emit_scalar(ir
, op
, dst
, src0
, undef
);
874 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
875 st_dst_reg dst
, st_src_reg src0
)
877 enum tgsi_opcode op
= TGSI_OPCODE_ARL
;
879 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
880 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
883 op
= TGSI_OPCODE_UARL
;
886 assert(dst
.file
== PROGRAM_ADDRESS
);
887 if (dst
.index
>= this->num_address_regs
)
888 this->num_address_regs
= dst
.index
+ 1;
890 emit_asm(NULL
, op
, dst
, src0
);
894 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
895 gl_constant_value values
[8], int size
,
897 uint16_t *swizzle_out
)
899 if (file
== PROGRAM_CONSTANT
) {
900 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
901 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
,
902 values
, size
, datatype
,
905 *swizzle_out
= swizzle
;
909 assert(file
== PROGRAM_IMMEDIATE
);
912 immediate_storage
*entry
;
913 int size32
= size
* ((datatype
== GL_DOUBLE
||
914 datatype
== GL_INT64_ARB
||
915 datatype
== GL_UNSIGNED_INT64_ARB
) ? 2 : 1);
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
921 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
922 immediate_storage
*tmp
= entry
;
924 for (i
= 0; i
* 4 < size32
; i
++) {
925 int slot_size
= MIN2(size32
- (i
* 4), 4);
926 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
928 if (memcmp(tmp
->values
, &values
[i
* 4],
929 slot_size
* sizeof(gl_constant_value
)))
932 /* Everything matches, keep going until the full size is matched */
933 tmp
= (immediate_storage
*)tmp
->next
;
936 /* The full value matched */
943 for (i
= 0; i
* 4 < size32
; i
++) {
944 int slot_size
= MIN2(size32
- (i
* 4), 4);
945 /* Add this immediate to the list. */
946 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4],
947 slot_size
, datatype
);
948 this->immediates
.push_tail(entry
);
949 this->num_immediates
++;
955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
957 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
958 union gl_constant_value uval
;
961 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
969 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
970 union gl_constant_value uval
[2];
972 memcpy(uval
, &val
, sizeof(uval
));
973 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
974 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
981 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
982 union gl_constant_value uval
;
984 assert(native_integers
);
987 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
995 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
996 union gl_constant_value uval
[2];
998 memcpy(uval
, &val
, sizeof(uval
));
999 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1000 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1008 if (native_integers
)
1009 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1010 st_src_reg_for_int(val
);
1012 return st_src_reg_for_float(val
);
1016 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1018 return type
->count_attribute_slots(is_vs_input
);
1022 type_size(const struct glsl_type
*type
)
1024 return type
->count_attribute_slots(false);
1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
1029 exec_list
*instructions
, ir_constant
*access
)
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1035 enum tgsi_opcode op
= inst
->op
;
1037 inst
->resource
= *buf
;
1039 inst
->buffer_access
= access
->value
.u
[0];
1041 if (inst
== instructions
->get_head_raw())
1043 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1045 if (inst
->op
== TGSI_OPCODE_UADD
) {
1046 if (inst
== instructions
->get_head_raw())
1048 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1050 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1063 type_has_array_or_matrix(const glsl_type
*type
)
1065 if (type
->is_array() || type
->is_matrix())
1068 if (type
->is_struct()) {
1069 for (unsigned i
= 0; i
< type
->length
; i
++) {
1070 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1086 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1090 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1095 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1096 if (next_array
>= max_num_arrays
) {
1097 max_num_arrays
+= 32;
1098 array_sizes
= (unsigned*)
1099 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1102 src
.file
= PROGRAM_ARRAY
;
1104 src
.array_id
= next_array
+ 1;
1105 array_sizes
[next_array
] = type_size(type
);
1109 src
.file
= PROGRAM_TEMPORARY
;
1110 src
.index
= next_temp
;
1111 next_temp
+= type_size(type
);
1114 if (type
->is_array() || type
->is_struct()) {
1115 src
.swizzle
= SWIZZLE_NOOP
;
1117 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1126 struct hash_entry
*entry
;
1128 entry
= _mesa_hash_table_search(this->variables
, var
);
1132 return (variable_storage
*)entry
->data
;
1136 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1138 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1140 const ir_state_slot
*const slots
= ir
->get_state_slots();
1141 assert(slots
!= NULL
);
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1149 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1150 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1155 variable_storage
*storage
;
1157 if (i
== ir
->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1161 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1169 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1171 dst
= st_dst_reg(get_temp(ir
->type
));
1173 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1176 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1180 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1181 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1184 if (storage
->file
== PROGRAM_STATE_VAR
) {
1185 if (storage
->index
== -1) {
1186 storage
->index
= index
;
1188 assert(index
== storage
->index
+ (int)i
);
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1196 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1197 src
.swizzle
= slots
[i
].swizzle
;
1198 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1204 if (storage
->file
== PROGRAM_TEMPORARY
&&
1205 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1206 fail_link(this->shader_program
,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir
->name
, dst
.index
- storage
->index
,
1209 type_size(ir
->type
));
1215 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1217 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1219 visit_exec_list(&ir
->body_instructions
, this);
1221 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1228 case ir_loop_jump::jump_break
:
1229 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1231 case ir_loop_jump::jump_continue
:
1232 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1239 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1246 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1251 if (strcmp(ir
->name
, "main") == 0) {
1252 const ir_function_signature
*sig
;
1255 sig
= ir
->matching_signature(NULL
, &empty
, false);
1259 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1268 int nonmul_operand
= 1 - mul_operand
;
1270 st_dst_reg result_dst
;
1272 // there is no TGSI opcode for this
1273 if (ir
->type
->is_integer_64())
1276 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1277 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1280 expr
->operands
[0]->accept(this);
1282 expr
->operands
[1]->accept(this);
1284 ir
->operands
[nonmul_operand
]->accept(this);
1287 this->result
= get_temp(ir
->type
);
1288 result_dst
= st_dst_reg(this->result
);
1289 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1290 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1305 * - (a * 1) - (a * b)
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
,
1316 const int other_operand
= 1 - try_operand
;
1319 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1320 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1323 ir
->operands
[other_operand
]->accept(this);
1325 expr
->operands
[0]->accept(this);
1328 b
.negate
= ~b
.negate
;
1330 this->result
= get_temp(ir
->type
);
1331 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1338 st_src_reg
*reg
, int *num_reladdr
)
1340 if (!reg
->reladdr
&& !reg
->reladdr2
)
1344 emit_arl(ir
, address_reg
, *reg
->reladdr
);
1346 emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1348 if (*num_reladdr
!= 1) {
1349 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1351 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1359 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1361 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1365 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1366 if (try_emit_mad(ir
, 1))
1368 if (try_emit_mad(ir
, 0))
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1374 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1375 if (try_emit_mad_for_and_not(ir
, 1))
1377 if (try_emit_mad_for_and_not(ir
, 0))
1381 if (ir
->operation
== ir_quadop_vector
)
1382 assert(!"ir_quadop_vector should have been lowered");
1384 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1385 this->result
.file
= PROGRAM_UNDEFINED
;
1386 ir
->operands
[operand
]->accept(this);
1387 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir
->operands
[operand
]->print();
1393 op
[operand
] = this->result
;
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1398 assert(!ir
->operands
[operand
]->type
->is_matrix());
1401 visit_expression(ir
, op
);
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1411 st_src_reg result_src
;
1412 st_dst_reg result_dst
;
1414 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1415 if (ir
->operands
[1] &&
1416 ir
->operation
!= ir_binop_interpolate_at_offset
&&
1417 ir
->operation
!= ir_binop_interpolate_at_sample
) {
1418 st_src_reg
*swz_op
= NULL
;
1419 if (vector_elements
> ir
->operands
[1]->type
->vector_elements
) {
1420 assert(ir
->operands
[1]->type
->vector_elements
== 1);
1422 } else if (vector_elements
< ir
->operands
[1]->type
->vector_elements
) {
1423 assert(ir
->operands
[0]->type
->vector_elements
== 1);
1427 uint16_t swizzle_x
= GET_SWZ(swz_op
->swizzle
, 0);
1428 swz_op
->swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1429 swizzle_x
, swizzle_x
);
1431 vector_elements
= MAX2(vector_elements
,
1432 ir
->operands
[1]->type
->vector_elements
);
1434 if (ir
->operands
[2] &&
1435 ir
->operands
[2]->type
->vector_elements
!= vector_elements
) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir
->operands
[2]->type
->vector_elements
== 1);
1438 uint16_t swizzle_x
= GET_SWZ(op
[2].swizzle
, 0);
1439 op
[2].swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1440 swizzle_x
, swizzle_x
);
1443 this->result
.file
= PROGRAM_UNDEFINED
;
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1448 result_src
= get_temp(ir
->type
);
1449 /* convenience for the emit functions below. */
1450 result_dst
= st_dst_reg(result_src
);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1455 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1457 switch (ir
->operation
) {
1458 case ir_unop_logic_not
:
1459 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1460 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1467 op
[0].negate
= ~op
[0].negate
;
1468 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0],
1469 st_src_reg_for_float(1.0));
1473 if (result_dst
.type
== GLSL_TYPE_INT64
||
1474 result_dst
.type
== GLSL_TYPE_UINT64
)
1475 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1476 else if (result_dst
.type
== GLSL_TYPE_INT
||
1477 result_dst
.type
== GLSL_TYPE_UINT
)
1478 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1479 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1480 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1482 op
[0].negate
= ~op
[0].negate
;
1486 case ir_unop_subroutine_to_int
:
1487 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1490 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1491 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1492 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1493 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1494 else if (result_dst
.type
== GLSL_TYPE_INT64
||
1495 result_dst
.type
== GLSL_TYPE_UINT64
)
1496 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1498 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1501 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1504 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1508 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1511 assert(!"not reached: should be handled by exp_to_exp2");
1514 assert(!"not reached: should be handled by log_to_log2");
1517 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1520 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1523 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1525 case ir_unop_saturate
: {
1526 glsl_to_tgsi_instruction
*inst
;
1527 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1528 inst
->saturate
= true;
1533 case ir_unop_dFdx_coarse
:
1534 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1536 case ir_unop_dFdx_fine
:
1537 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1540 case ir_unop_dFdy_coarse
:
1541 case ir_unop_dFdy_fine
:
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1547 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
1548 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1550 unsigned transform_y_index
=
1551 _mesa_add_state_reference(this->prog
->Parameters
,
1554 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1556 glsl_type::vec4_type
);
1557 transform_y
.swizzle
= SWIZZLE_XXXX
;
1559 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1561 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1562 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1563 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1567 case ir_unop_frexp_sig
:
1568 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1571 case ir_unop_frexp_exp
:
1572 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1575 case ir_unop_noise
: {
1576 /* At some point, a motivated person could add a better
1577 * implementation of noise. Currently not even the nvidia
1578 * binary drivers do anything more than this. In any case, the
1579 * place to do this is in the GL state tracker, not the poor
1582 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1587 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1590 op
[1].negate
= ~op
[1].negate
;
1591 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1595 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1598 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1601 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1602 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1604 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1608 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1610 case ir_binop_gequal
:
1611 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1613 case ir_binop_equal
:
1614 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1616 case ir_binop_nequal
:
1617 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1619 case ir_binop_all_equal
:
1620 /* "==" operator producing a scalar boolean. */
1621 if (ir
->operands
[0]->type
->is_vector() ||
1622 ir
->operands
[1]->type
->is_vector()) {
1623 st_src_reg temp
= get_temp(native_integers
?
1624 glsl_type::uvec4_type
:
1625 glsl_type::vec4_type
);
1627 if (native_integers
) {
1628 st_dst_reg temp_dst
= st_dst_reg(temp
);
1629 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1631 if (ir
->operands
[0]->type
->is_boolean() &&
1632 ir
->operands
[1]->as_constant() &&
1633 ir
->operands
[1]->as_constant()->is_one()) {
1634 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1636 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1639 /* Emit 1-3 AND operations to combine the SEQ results. */
1640 switch (ir
->operands
[0]->type
->vector_elements
) {
1644 temp_dst
.writemask
= WRITEMASK_Y
;
1645 temp1
.swizzle
= SWIZZLE_YYYY
;
1646 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1647 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1650 temp_dst
.writemask
= WRITEMASK_X
;
1651 temp1
.swizzle
= SWIZZLE_XXXX
;
1652 temp2
.swizzle
= SWIZZLE_YYYY
;
1653 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1654 temp_dst
.writemask
= WRITEMASK_Y
;
1655 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1656 temp2
.swizzle
= SWIZZLE_WWWW
;
1657 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1660 temp1
.swizzle
= SWIZZLE_XXXX
;
1661 temp2
.swizzle
= SWIZZLE_YYYY
;
1662 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1664 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1666 /* After the dot-product, the value will be an integer on the
1667 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1669 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1671 /* Negating the result of the dot-product gives values on the range
1672 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1673 * This is achieved using SGE.
1675 st_src_reg sge_src
= result_src
;
1676 sge_src
.negate
= ~sge_src
.negate
;
1677 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
,
1678 st_src_reg_for_float(0.0));
1681 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1684 case ir_binop_any_nequal
:
1685 /* "!=" operator producing a scalar boolean. */
1686 if (ir
->operands
[0]->type
->is_vector() ||
1687 ir
->operands
[1]->type
->is_vector()) {
1688 st_src_reg temp
= get_temp(native_integers
?
1689 glsl_type::uvec4_type
:
1690 glsl_type::vec4_type
);
1691 if (ir
->operands
[0]->type
->is_boolean() &&
1692 ir
->operands
[1]->as_constant() &&
1693 ir
->operands
[1]->as_constant()->is_zero()) {
1694 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1696 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1699 if (native_integers
) {
1700 st_dst_reg temp_dst
= st_dst_reg(temp
);
1701 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1703 /* Emit 1-3 OR operations to combine the SNE results. */
1704 switch (ir
->operands
[0]->type
->vector_elements
) {
1708 temp_dst
.writemask
= WRITEMASK_Y
;
1709 temp1
.swizzle
= SWIZZLE_YYYY
;
1710 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1711 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1714 temp_dst
.writemask
= WRITEMASK_X
;
1715 temp1
.swizzle
= SWIZZLE_XXXX
;
1716 temp2
.swizzle
= SWIZZLE_YYYY
;
1717 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1718 temp_dst
.writemask
= WRITEMASK_Y
;
1719 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1720 temp2
.swizzle
= SWIZZLE_WWWW
;
1721 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1724 temp1
.swizzle
= SWIZZLE_XXXX
;
1725 temp2
.swizzle
= SWIZZLE_YYYY
;
1726 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1728 /* After the dot-product, the value will be an integer on the
1729 * range [0,4]. Zero stays zero, and positive values become 1.0.
1731 glsl_to_tgsi_instruction
*const dp
=
1732 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1733 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1734 /* The clamping to [0,1] can be done for free in the fragment
1735 * shader with a saturate.
1737 dp
->saturate
= true;
1739 /* Negating the result of the dot-product gives values on the
1740 * range [-4, 0]. Zero stays zero, and negative values become
1741 * 1.0. This achieved using SLT.
1743 st_src_reg slt_src
= result_src
;
1744 slt_src
.negate
= ~slt_src
.negate
;
1745 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1746 st_src_reg_for_float(0.0));
1750 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1754 case ir_binop_logic_xor
:
1755 if (native_integers
)
1756 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1758 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1761 case ir_binop_logic_or
: {
1762 if (native_integers
) {
1763 /* If integers are used as booleans, we can use an actual "or"
1766 assert(native_integers
);
1767 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1769 /* After the addition, the value will be an integer on the
1770 * range [0,2]. Zero stays zero, and positive values become 1.0.
1772 glsl_to_tgsi_instruction
*add
=
1773 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1774 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1775 /* The clamping to [0,1] can be done for free in the fragment
1776 * shader with a saturate if floats are being used as boolean
1779 add
->saturate
= true;
1781 /* Negating the result of the addition gives values on the range
1782 * [-2, 0]. Zero stays zero, and negative values become 1.0
1783 * This is achieved using SLT.
1785 st_src_reg slt_src
= result_src
;
1786 slt_src
.negate
= ~slt_src
.negate
;
1787 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1788 st_src_reg_for_float(0.0));
1794 case ir_binop_logic_and
:
1795 /* If native integers are disabled, the bool args are stored as float 0.0
1796 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1797 * actual AND opcode.
1799 if (native_integers
)
1800 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1802 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1806 assert(ir
->operands
[0]->type
->is_vector());
1807 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1808 emit_dp(ir
, result_dst
, op
[0], op
[1],
1809 ir
->operands
[0]->type
->vector_elements
);
1814 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1816 /* This is the only instruction sequence that makes the game "Risen"
1817 * render correctly. ABS is not required for the game, but since GLSL
1818 * declares negative values as "undefined", allowing us to do whatever
1819 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1822 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1823 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1827 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1830 if (native_integers
) {
1831 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1834 /* fallthrough to next case otherwise */
1836 if (native_integers
) {
1837 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1838 st_src_reg_for_float(1.0));
1841 /* fallthrough to next case otherwise */
1844 case ir_unop_i642u64
:
1845 case ir_unop_u642i64
:
1846 /* Converting between signed and unsigned integers is a no-op. */
1848 result_src
.type
= result_dst
.type
;
1851 if (native_integers
) {
1852 /* Booleans are stored as integers using ~0 for true and 0 for false.
1853 * GLSL requires that int(bool) return 1 for true and 0 for false.
1854 * This conversion is done with AND, but it could be done with NEG.
1856 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1857 st_src_reg_for_int(1));
1859 /* Booleans and integers are both stored as floats when native
1860 * integers are disabled.
1866 if (native_integers
)
1867 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1869 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1872 if (native_integers
)
1873 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1875 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1877 case ir_unop_bitcast_f2i
:
1878 case ir_unop_bitcast_f2u
:
1879 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1880 if (op
[0].negate
|| op
[0].abs
)
1881 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1884 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1887 case ir_unop_bitcast_i2f
:
1888 case ir_unop_bitcast_u2f
:
1890 result_src
.type
= GLSL_TYPE_FLOAT
;
1893 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1894 st_src_reg_for_float(0.0));
1897 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1898 st_src_reg_for_double(0.0));
1901 if (native_integers
)
1902 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0],
1903 st_src_reg_for_int(0));
1905 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1906 st_src_reg_for_float(0.0));
1908 case ir_unop_bitcast_u642d
:
1909 case ir_unop_bitcast_i642d
:
1911 result_src
.type
= GLSL_TYPE_DOUBLE
;
1913 case ir_unop_bitcast_d2i64
:
1915 result_src
.type
= GLSL_TYPE_INT64
;
1917 case ir_unop_bitcast_d2u64
:
1919 result_src
.type
= GLSL_TYPE_UINT64
;
1922 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1925 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1928 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1930 case ir_unop_round_even
:
1931 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1934 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1938 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1941 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1944 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1947 case ir_unop_bit_not
:
1948 if (native_integers
) {
1949 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1953 if (native_integers
) {
1954 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1957 case ir_binop_lshift
:
1958 case ir_binop_rshift
:
1959 if (native_integers
) {
1960 enum tgsi_opcode opcode
= ir
->operation
== ir_binop_lshift
1961 ? TGSI_OPCODE_SHL
: TGSI_OPCODE_ISHR
;
1964 if (glsl_base_type_is_64bit(op
[0].type
)) {
1965 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1968 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]
1969 ->type
->components()));
1970 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1975 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1978 case ir_binop_bit_and
:
1979 if (native_integers
) {
1980 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1983 case ir_binop_bit_xor
:
1984 if (native_integers
) {
1985 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1988 case ir_binop_bit_or
:
1989 if (native_integers
) {
1990 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1994 assert(!"GLSL 1.30 features unsupported");
1997 case ir_binop_ubo_load
: {
1998 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1999 ir_rvalue
*block
= ir
->operands
[0];
2000 ir_rvalue
*offset
= ir
->operands
[1];
2001 ir_constant
*const_block
= block
->as_constant();
2003 st_src_reg
cbuf(PROGRAM_CONSTANT
,
2004 (const_block
? const_block
->value
.u
[0] + 1 : 1),
2005 ir
->type
->base_type
);
2007 cbuf
.has_index2
= true;
2010 block
->accept(this);
2011 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2012 *cbuf
.reladdr
= this->result
;
2013 emit_arl(ir
, sampler_reladdr
, this->result
);
2016 /* Calculate the surface offset */
2017 offset
->accept(this);
2018 st_src_reg off
= this->result
;
2020 glsl_to_tgsi_instruction
*inst
=
2021 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
2023 if (result_dst
.type
== GLSL_TYPE_BOOL
)
2024 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
2025 st_src_reg_for_int(0));
2027 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
2030 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2031 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2032 unsigned const_offset
= const_offset_ir
?
2033 const_offset_ir
->value
.u
[0] : 0;
2034 unsigned const_block
= const_uniform_block
?
2035 const_uniform_block
->value
.u
[0] + 1 : 1;
2036 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2039 cbuf
.type
= ir
->type
->base_type
;
2040 cbuf
.file
= PROGRAM_CONSTANT
;
2042 cbuf
.reladdr
= NULL
;
2045 cbuf
.index2D
= const_block
;
2047 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2049 if (const_offset_ir
) {
2050 /* Constant index into constant buffer */
2051 cbuf
.reladdr
= NULL
;
2052 cbuf
.index
= const_offset
/ 16;
2054 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2055 st_src_reg offset
= op
[1];
2057 /* The OpenGL spec is written in such a way that accesses with
2058 * non-constant offset are almost always vec4-aligned. The only
2059 * exception to this are members of structs in arrays of structs:
2060 * each struct in an array of structs is at least vec4-aligned,
2061 * but single-element and [ui]vec2 members of the struct may be at
2062 * an offset that is not a multiple of 16 bytes.
2064 * Here, we extract that offset, relying on previous passes to
2065 * always generate offset expressions of the form
2066 * (+ expr constant_offset).
2068 * Note that the std430 layout, which allows more cases of
2069 * alignment less than vec4 in arrays, is not supported for
2070 * uniform blocks, so we do not have to deal with it here.
2072 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2073 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2074 if (const_offset_ir
) {
2075 const_offset
= const_offset_ir
->value
.u
[0];
2076 cbuf
.index
= const_offset
/ 16;
2077 offset_expr
->operands
[0]->accept(this);
2078 offset
= this->result
;
2082 /* Relative/variable index into constant buffer */
2083 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2084 st_src_reg_for_int(4));
2085 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2086 *cbuf
.reladdr
= index_reg
;
2089 if (const_uniform_block
) {
2090 /* Constant constant buffer */
2091 cbuf
.reladdr2
= NULL
;
2093 /* Relative/variable constant buffer */
2094 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2095 *cbuf
.reladdr2
= op
[0];
2097 cbuf
.has_index2
= true;
2099 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2100 if (glsl_base_type_is_64bit(cbuf
.type
))
2101 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2102 const_offset
% 16 / 8,
2103 const_offset
% 16 / 8,
2104 const_offset
% 16 / 8);
2106 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2107 const_offset
% 16 / 4,
2108 const_offset
% 16 / 4,
2109 const_offset
% 16 / 4);
2111 if (ir
->type
->is_boolean()) {
2112 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2113 st_src_reg_for_int(0));
2115 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2121 /* note: we have to reorder the three args here */
2122 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2125 if (this->ctx
->Const
.NativeIntegers
)
2126 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2128 op
[0].negate
= ~op
[0].negate
;
2129 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2132 case ir_triop_bitfield_extract
:
2133 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2135 case ir_quadop_bitfield_insert
:
2136 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2138 case ir_unop_bitfield_reverse
:
2139 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2141 case ir_unop_bit_count
:
2142 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2144 case ir_unop_find_msb
:
2145 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2147 case ir_unop_find_lsb
:
2148 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2150 case ir_binop_imul_high
:
2151 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2154 /* In theory, MAD is incorrect here. */
2156 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2158 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2160 case ir_unop_interpolate_at_centroid
:
2161 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2163 case ir_binop_interpolate_at_offset
: {
2164 /* The y coordinate needs to be flipped for the default fb */
2165 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
2166 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2168 unsigned transform_y_index
=
2169 _mesa_add_state_reference(this->prog
->Parameters
,
2172 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2174 glsl_type::vec4_type
);
2175 transform_y
.swizzle
= SWIZZLE_XXXX
;
2177 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2178 st_dst_reg temp_dst
= st_dst_reg(temp
);
2180 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2181 temp_dst
.writemask
= WRITEMASK_Y
;
2182 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2183 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2186 case ir_binop_interpolate_at_sample
:
2187 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2191 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2194 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2197 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2200 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2203 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2206 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2208 case ir_unop_unpack_double_2x32
:
2209 case ir_unop_pack_double_2x32
:
2210 case ir_unop_unpack_int_2x32
:
2211 case ir_unop_pack_int_2x32
:
2212 case ir_unop_unpack_uint_2x32
:
2213 case ir_unop_pack_uint_2x32
:
2214 case ir_unop_unpack_sampler_2x32
:
2215 case ir_unop_pack_sampler_2x32
:
2216 case ir_unop_unpack_image_2x32
:
2217 case ir_unop_pack_image_2x32
:
2218 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2221 case ir_binop_ldexp
:
2222 if (ir
->operands
[0]->type
->is_double()) {
2223 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2224 } else if (ir
->operands
[0]->type
->is_float()) {
2225 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2227 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2231 case ir_unop_pack_half_2x16
:
2232 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2234 case ir_unop_unpack_half_2x16
:
2235 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2238 case ir_unop_get_buffer_size
: {
2239 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2242 const_offset
? const_offset
->value
.u
[0] : 0,
2244 if (!const_offset
) {
2245 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2246 *buffer
.reladdr
= op
[0];
2247 emit_arl(ir
, sampler_reladdr
, op
[0]);
2249 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2255 case ir_unop_b2i64
: {
2256 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2257 st_dst_reg temp_dst
= st_dst_reg(temp
);
2258 unsigned orig_swz
= op
[0].swizzle
;
2260 * To convert unsigned to 64-bit:
2261 * zero Y channel, copy X channel.
2263 temp_dst
.writemask
= WRITEMASK_Y
;
2264 if (vector_elements
> 1)
2265 temp_dst
.writemask
|= WRITEMASK_W
;
2266 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2267 temp_dst
.writemask
= WRITEMASK_X
;
2268 if (vector_elements
> 1)
2269 temp_dst
.writemask
|= WRITEMASK_Z
;
2270 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2271 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2272 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2273 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2275 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2277 result_src
.type
= GLSL_TYPE_UINT64
;
2278 if (vector_elements
> 2) {
2279 /* Subtle: We rely on the fact that get_temp here returns the next
2280 * TGSI temporary register directly after the temp register used for
2281 * the first two components, so that the result gets picked up
2284 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2285 st_dst_reg temp_dst
= st_dst_reg(temp
);
2286 temp_dst
.writemask
= WRITEMASK_Y
;
2287 if (vector_elements
> 3)
2288 temp_dst
.writemask
|= WRITEMASK_W
;
2289 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2291 temp_dst
.writemask
= WRITEMASK_X
;
2292 if (vector_elements
> 3)
2293 temp_dst
.writemask
|= WRITEMASK_Z
;
2294 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2),
2295 GET_SWZ(orig_swz
, 2),
2296 GET_SWZ(orig_swz
, 3),
2297 GET_SWZ(orig_swz
, 3));
2298 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2299 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2301 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0],
2302 st_src_reg_for_int(1));
2309 case ir_unop_i642u
: {
2310 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2311 st_dst_reg temp_dst
= st_dst_reg(temp
);
2312 unsigned orig_swz
= op
[0].swizzle
;
2313 unsigned orig_idx
= op
[0].index
;
2315 temp_dst
.writemask
= WRITEMASK_X
;
2317 for (el
= 0; el
< vector_elements
; el
++) {
2318 unsigned swz
= GET_SWZ(orig_swz
, el
);
2320 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
,
2321 SWIZZLE_Z
, SWIZZLE_Z
);
2323 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
2324 SWIZZLE_X
, SWIZZLE_X
);
2326 op
[0].index
= orig_idx
+ 1;
2327 op
[0].type
= GLSL_TYPE_UINT
;
2328 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2329 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2332 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2333 result_src
.type
= GLSL_TYPE_UINT
;
2335 result_src
.type
= GLSL_TYPE_INT
;
2339 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0],
2340 st_src_reg_for_int64(0));
2343 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2346 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2349 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2352 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2355 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2358 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2361 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2364 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2367 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2370 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2372 /* these might be needed */
2373 case ir_unop_pack_snorm_2x16
:
2374 case ir_unop_pack_unorm_2x16
:
2375 case ir_unop_pack_snorm_4x8
:
2376 case ir_unop_pack_unorm_4x8
:
2378 case ir_unop_unpack_snorm_2x16
:
2379 case ir_unop_unpack_unorm_2x16
:
2380 case ir_unop_unpack_snorm_4x8
:
2381 case ir_unop_unpack_unorm_4x8
:
2383 case ir_quadop_vector
:
2384 case ir_binop_vector_extract
:
2385 case ir_triop_vector_insert
:
2386 case ir_binop_carry
:
2387 case ir_binop_borrow
:
2388 case ir_unop_ssbo_unsized_array_length
:
2390 case ir_binop_atan2
:
2392 case ir_binop_add_sat
:
2393 case ir_binop_sub_sat
:
2394 case ir_binop_abs_sub
:
2396 case ir_binop_avg_round
:
2397 case ir_binop_mul_32x16
:
2398 /* This operation is not supported, or should have already been handled.
2400 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2404 this->result
= result_src
;
2409 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2415 /* Note that this is only swizzles in expressions, not those on the left
2416 * hand side of an assignment, which do write masking. See ir_assignment
2420 ir
->val
->accept(this);
2422 assert(src
.file
!= PROGRAM_UNDEFINED
);
2423 assert(ir
->type
->vector_elements
> 0);
2425 for (i
= 0; i
< 4; i
++) {
2426 if (i
< ir
->type
->vector_elements
) {
2429 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2432 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2435 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2438 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2442 /* If the type is smaller than a vec4, replicate the last
2445 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2449 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2454 /* Test if the variable is an array. Note that geometry and
2455 * tessellation shader inputs are outputs are always arrays (except
2456 * for patch inputs), so only the array element type is considered.
2459 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2461 const glsl_type
*type
= var
->type
;
2463 *remove_array
= false;
2465 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2466 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2469 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2470 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2471 stage
== MESA_SHADER_TESS_CTRL
) &&
2473 if (!var
->type
->is_array())
2474 return false; /* a system value probably */
2476 type
= var
->type
->fields
.array
;
2477 *remove_array
= true;
2480 return type
->is_array() || type
->is_matrix();
2484 st_translate_interp_loc(ir_variable
*var
)
2486 if (var
->data
.centroid
)
2487 return TGSI_INTERPOLATE_LOC_CENTROID
;
2488 else if (var
->data
.sample
)
2489 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2491 return TGSI_INTERPOLATE_LOC_CENTER
;
2495 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2497 variable_storage
*entry
;
2498 ir_variable
*var
= ir
->var
;
2501 if (handle_bound_deref(ir
->as_dereference()))
2504 entry
= find_variable_storage(ir
->var
);
2507 switch (var
->data
.mode
) {
2508 case ir_var_uniform
:
2509 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2510 var
->data
.param_index
);
2511 _mesa_hash_table_insert(this->variables
, var
, entry
);
2513 case ir_var_shader_in
: {
2514 /* The linker assigns locations for varyings and attributes,
2515 * including deprecated builtins (like gl_Color), user-assign
2516 * generic attributes (glBindVertexLocation), and
2517 * user-defined varyings.
2519 assert(var
->data
.location
!= -1);
2521 const glsl_type
*type_without_array
= var
->type
->without_array();
2522 struct inout_decl
*decl
= &inputs
[num_inputs
];
2523 unsigned component
= var
->data
.location_frac
;
2524 unsigned num_components
;
2527 if (type_without_array
->is_64bit())
2528 component
= component
/ 2;
2529 if (type_without_array
->vector_elements
)
2530 num_components
= type_without_array
->vector_elements
;
2534 decl
->mesa_index
= var
->data
.location
;
2535 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2536 decl
->interp_loc
= st_translate_interp_loc(var
);
2537 decl
->base_type
= type_without_array
->base_type
;
2538 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2540 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2541 decl
->array_id
= num_input_arrays
+ 1;
2548 decl
->size
= type_size(var
->type
->fields
.array
);
2550 decl
->size
= type_size(var
->type
);
2552 entry
= new(mem_ctx
) variable_storage(var
,
2556 entry
->component
= component
;
2558 _mesa_hash_table_insert(this->variables
, var
, entry
);
2562 case ir_var_shader_out
: {
2563 assert(var
->data
.location
!= -1);
2565 const glsl_type
*type_without_array
= var
->type
->without_array();
2566 struct inout_decl
*decl
= &outputs
[num_outputs
];
2567 unsigned component
= var
->data
.location_frac
;
2568 unsigned num_components
;
2571 decl
->invariant
= var
->data
.invariant
;
2573 if (type_without_array
->is_64bit())
2574 component
= component
/ 2;
2575 if (type_without_array
->vector_elements
)
2576 num_components
= type_without_array
->vector_elements
;
2580 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2581 decl
->base_type
= type_without_array
->base_type
;
2582 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2583 if (var
->data
.stream
& (1u << 31)) {
2584 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2586 assert(var
->data
.stream
< 4);
2587 decl
->gs_out_streams
= 0;
2588 for (unsigned i
= 0; i
< num_components
; ++i
)
2589 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2592 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2593 decl
->array_id
= num_output_arrays
+ 1;
2594 num_output_arrays
++;
2600 decl
->size
= type_size(var
->type
->fields
.array
);
2602 decl
->size
= type_size(var
->type
);
2604 if (var
->data
.fb_fetch_output
) {
2605 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2606 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2607 var
->type
, component
, decl
->array_id
);
2608 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2609 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2612 entry
= new(mem_ctx
) variable_storage(var
,
2617 entry
->component
= component
;
2619 _mesa_hash_table_insert(this->variables
, var
, entry
);
2623 case ir_var_system_value
:
2624 entry
= new(mem_ctx
) variable_storage(var
,
2625 PROGRAM_SYSTEM_VALUE
,
2626 var
->data
.location
);
2629 case ir_var_temporary
:
2630 st_src_reg src
= get_temp(var
->type
);
2632 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2634 _mesa_hash_table_insert(this->variables
, var
, entry
);
2640 printf("Failed to make storage for %s\n", var
->name
);
2645 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2646 entry
->component
, entry
->array_id
);
2647 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2648 var
->data
.mode
== ir_var_shader_in
&&
2649 var
->type
->without_array()->is_double())
2650 this->result
.is_double_vertex_input
= true;
2651 if (!native_integers
)
2652 this->result
.type
= GLSL_TYPE_FLOAT
;
2656 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2657 GLbitfield64
* usage_mask
,
2658 GLbitfield64 double_usage_mask
,
2659 GLbitfield
* patch_usage_mask
)
2664 /* Fix array declarations by removing unused array elements at both ends
2665 * of the arrays. For example, mat4[3] where only mat[1] is used.
2667 for (i
= 0; i
< count
; i
++) {
2668 struct inout_decl
*decl
= &decls
[i
];
2669 if (!decl
->array_id
)
2672 /* Shrink the beginning. */
2673 for (j
= 0; j
< (int)decl
->size
; j
++) {
2674 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2675 if (*patch_usage_mask
&
2676 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2680 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2682 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2691 /* Shrink the end. */
2692 for (j
= decl
->size
-1; j
>= 0; j
--) {
2693 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2694 if (*patch_usage_mask
&
2695 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2699 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2701 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2708 /* When not all entries of an array are accessed, we mark them as used
2709 * here anyway, to ensure that the input/output mapping logic doesn't get
2712 * TODO This happens when an array isn't used via indirect access, which
2713 * some game ports do (at least eON-based). There is an optimization
2714 * opportunity here by replacing the array declaration with non-array
2715 * declarations of those slots that are actually used.
2717 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2718 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2719 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2721 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2728 mark_array_io(struct inout_decl
*decls
, unsigned count
,
2729 GLbitfield64
* usage_mask
,
2730 GLbitfield64 double_usage_mask
,
2731 GLbitfield
* patch_usage_mask
)
2736 /* Fix array declarations by removing unused array elements at both ends
2737 * of the arrays. For example, mat4[3] where only mat[1] is used.
2739 for (i
= 0; i
< count
; i
++) {
2740 struct inout_decl
*decl
= &decls
[i
];
2741 if (!decl
->array_id
)
2744 /* When not all entries of an array are accessed, we mark them as used
2745 * here anyway, to ensure that the input/output mapping logic doesn't get
2748 * TODO This happens when an array isn't used via indirect access, which
2749 * some game ports do (at least eON-based). There is an optimization
2750 * opportunity here by replacing the array declaration with non-array
2751 * declarations of those slots that are actually used.
2753 for (j
= 0; j
< (int)decl
->size
; ++j
) {
2754 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2755 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2757 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2763 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2768 ir_variable
*var
= ir
->variable_referenced();
2770 if (handle_bound_deref(ir
->as_dereference()))
2773 /* We only need the logic provided by count_vec4_slots()
2774 * for arrays of structs. Indirect sampler and image indexing is handled
2777 int element_size
= ir
->type
->without_array()->is_struct() ?
2778 ir
->type
->count_vec4_slots(false, var
->data
.bindless
) :
2779 type_size(ir
->type
);
2781 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2783 ir
->array
->accept(this);
2786 if (!src
.has_index2
) {
2787 switch (this->prog
->Target
) {
2788 case GL_TESS_CONTROL_PROGRAM_NV
:
2789 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2790 !ir
->variable_referenced()->data
.patch
;
2792 case GL_TESS_EVALUATION_PROGRAM_NV
:
2793 is_2D
= src
.file
== PROGRAM_INPUT
&&
2794 !ir
->variable_referenced()->data
.patch
;
2796 case GL_GEOMETRY_PROGRAM_NV
:
2797 is_2D
= src
.file
== PROGRAM_INPUT
;
2807 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2808 src
.file
== PROGRAM_INPUT
)
2809 element_size
= attrib_type_size(ir
->type
, true);
2811 src
.index2D
= index
->value
.i
[0];
2812 src
.has_index2
= true;
2814 src
.index
+= index
->value
.i
[0] * element_size
;
2816 /* Variable index array dereference. It eats the "vec4" of the
2817 * base of the array and an index that offsets the TGSI register
2820 ir
->array_index
->accept(this);
2822 st_src_reg index_reg
;
2824 if (element_size
== 1) {
2825 index_reg
= this->result
;
2827 index_reg
= get_temp(native_integers
?
2828 glsl_type::int_type
: glsl_type::float_type
);
2830 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2831 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2834 /* If there was already a relative address register involved, add the
2835 * new and the old together to get the new offset.
2837 if (!is_2D
&& src
.reladdr
!= NULL
) {
2838 st_src_reg accum_reg
= get_temp(native_integers
?
2839 glsl_type::int_type
: glsl_type::float_type
);
2841 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2842 index_reg
, *src
.reladdr
);
2844 index_reg
= accum_reg
;
2848 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2849 *src
.reladdr2
= index_reg
;
2851 src
.has_index2
= true;
2853 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2854 *src
.reladdr
= index_reg
;
2858 /* Change the register type to the element type of the array. */
2859 src
.type
= ir
->type
->base_type
;
2865 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2868 const glsl_type
*struct_type
= ir
->record
->type
;
2869 ir_variable
*var
= ir
->record
->variable_referenced();
2872 if (handle_bound_deref(ir
->as_dereference()))
2875 ir
->record
->accept(this);
2877 assert(ir
->field_idx
>= 0);
2879 for (i
= 0; i
< struct_type
->length
; i
++) {
2880 if (i
== (unsigned) ir
->field_idx
)
2882 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2883 offset
+= member_type
->count_vec4_slots(false, var
->data
.bindless
);
2886 /* If the type is smaller than a vec4, replicate the last channel out. */
2887 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2888 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2890 this->result
.swizzle
= SWIZZLE_NOOP
;
2892 this->result
.index
+= offset
;
2893 this->result
.type
= ir
->type
->base_type
;
2897 * We want to be careful in assignment setup to hit the actual storage
2898 * instead of potentially using a temporary like we might with the
2899 * ir_dereference handler.
2902 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2904 /* The LHS must be a dereference. If the LHS is a variable indexed array
2905 * access of a vector, it must be separated into a series conditional moves
2906 * before reaching this point (see ir_vec_index_to_cond_assign).
2908 assert(ir
->as_dereference());
2909 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2911 assert(!deref_array
->array
->type
->is_vector());
2914 /* Use the rvalue deref handler for the most part. We write swizzles using
2915 * the writemask, but we do extract the base component for enhanced layouts
2916 * from the source swizzle.
2919 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2920 return st_dst_reg(v
->result
);
2924 * Process the condition of a conditional assignment
2926 * Examines the condition of a conditional assignment to generate the optimal
2927 * first operand of a \c CMP instruction. If the condition is a relational
2928 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2929 * used as the source for the \c CMP instruction. Otherwise the comparison
2930 * is processed to a boolean result, and the boolean result is used as the
2931 * operand to the CMP instruction.
2934 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2936 ir_rvalue
*src_ir
= ir
;
2938 bool switch_order
= false;
2940 ir_expression
*const expr
= ir
->as_expression();
2942 if (native_integers
) {
2943 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2944 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2945 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2946 type
== GLSL_TYPE_BOOL
) {
2947 if (expr
->operation
== ir_binop_equal
) {
2948 if (expr
->operands
[0]->is_zero()) {
2949 src_ir
= expr
->operands
[1];
2950 switch_order
= true;
2952 else if (expr
->operands
[1]->is_zero()) {
2953 src_ir
= expr
->operands
[0];
2954 switch_order
= true;
2957 else if (expr
->operation
== ir_binop_nequal
) {
2958 if (expr
->operands
[0]->is_zero()) {
2959 src_ir
= expr
->operands
[1];
2961 else if (expr
->operands
[1]->is_zero()) {
2962 src_ir
= expr
->operands
[0];
2968 src_ir
->accept(this);
2969 return switch_order
;
2972 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2973 bool zero_on_left
= false;
2975 if (expr
->operands
[0]->is_zero()) {
2976 src_ir
= expr
->operands
[1];
2977 zero_on_left
= true;
2978 } else if (expr
->operands
[1]->is_zero()) {
2979 src_ir
= expr
->operands
[0];
2980 zero_on_left
= false;
2984 * (a < 0) T F F ( a < 0) T F F
2985 * (0 < a) F F T (-a < 0) F F T
2986 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2987 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2989 * Note that exchanging the order of 0 and 'a' in the comparison simply
2990 * means that the value of 'a' should be negated.
2993 switch (expr
->operation
) {
2995 switch_order
= false;
2996 negate
= zero_on_left
;
2999 case ir_binop_gequal
:
3000 switch_order
= true;
3001 negate
= zero_on_left
;
3005 /* This isn't the right kind of comparison afterall, so make sure
3006 * the whole condition is visited.
3014 src_ir
->accept(this);
3016 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3017 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3018 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3019 * computing the condition.
3022 this->result
.negate
= ~this->result
.negate
;
3024 return switch_order
;
3028 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3029 st_dst_reg
*l
, st_src_reg
*r
,
3030 st_src_reg
*cond
, bool cond_swap
)
3032 if (type
->is_struct()) {
3033 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3034 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3040 if (type
->is_array()) {
3041 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3042 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3047 if (type
->is_matrix()) {
3048 const struct glsl_type
*vec_type
;
3050 vec_type
= glsl_type::get_instance(type
->is_double()
3051 ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3052 type
->vector_elements
, 1);
3054 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3055 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3060 assert(type
->is_scalar() || type
->is_vector());
3062 l
->type
= type
->base_type
;
3063 r
->type
= type
->base_type
;
3065 st_src_reg l_src
= st_src_reg(*l
);
3067 if (l_src
.file
== PROGRAM_OUTPUT
&&
3068 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
3069 (l_src
.index
== FRAG_RESULT_DEPTH
||
3070 l_src
.index
== FRAG_RESULT_STENCIL
)) {
3071 /* This is a special case because the source swizzles will be shifted
3072 * later to account for the difference between GLSL (where they're
3073 * plain floats) and TGSI (where they're Z and Y components). */
3074 l_src
.swizzle
= SWIZZLE_XXXX
;
3077 if (native_integers
) {
3078 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3079 cond_swap
? l_src
: *r
,
3080 cond_swap
? *r
: l_src
);
3082 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3083 cond_swap
? l_src
: *r
,
3084 cond_swap
? *r
: l_src
);
3087 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3091 if (type
->is_dual_slot()) {
3093 if (r
->is_double_vertex_input
== false)
3099 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3105 /* all generated instructions need to be flaged as precise */
3106 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3107 ir
->rhs
->accept(this);
3110 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3114 int first_enabled_chan
= 0;
3116 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3118 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3119 variable
->data
.mode
== ir_var_shader_out
&&
3120 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3121 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3122 assert(ir
->lhs
->type
->is_scalar());
3123 assert(ir
->write_mask
== WRITEMASK_X
);
3125 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3126 l
.writemask
= WRITEMASK_Z
;
3128 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3129 l
.writemask
= WRITEMASK_Y
;
3131 } else if (ir
->write_mask
== 0) {
3132 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3134 unsigned num_elements
=
3135 ir
->lhs
->type
->without_array()->vector_elements
;
3138 l
.writemask
= u_bit_consecutive(0, num_elements
);
3140 /* The type is a struct or an array of (array of) structs. */
3141 l
.writemask
= WRITEMASK_XYZW
;
3144 l
.writemask
= ir
->write_mask
;
3147 for (int i
= 0; i
< 4; i
++) {
3148 if (l
.writemask
& (1 << i
)) {
3149 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3154 l
.writemask
= l
.writemask
<< dst_component
;
3156 /* Swizzle a small RHS vector into the channels being written.
3158 * glsl ir treats write_mask as dictating how many channels are
3159 * present on the RHS while TGSI treats write_mask as just
3160 * showing which channels of the vec4 RHS get written.
3162 for (int i
= 0; i
< 4; i
++) {
3163 if (l
.writemask
& (1 << i
))
3164 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3166 swizzles
[i
] = first_enabled_chan
;
3168 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3169 swizzles
[2], swizzles
[3]);
3172 assert(l
.file
!= PROGRAM_UNDEFINED
);
3173 assert(r
.file
!= PROGRAM_UNDEFINED
);
3175 if (ir
->condition
) {
3176 const bool switch_order
= this->process_move_condition(ir
->condition
);
3177 st_src_reg condition
= this->result
;
3179 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3180 } else if (ir
->rhs
->as_expression() &&
3181 this->instructions
.get_tail() &&
3182 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3183 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3184 type_size(ir
->lhs
->type
) == 1 &&
3185 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3186 /* To avoid emitting an extra MOV when assigning an expression to a
3187 * variable, emit the last instruction of the expression again, but
3188 * replace the destination register with the target of the assignment.
3189 * Dead code elimination will remove the original instruction.
3191 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3192 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3193 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3194 new_inst
->saturate
= inst
->saturate
;
3195 new_inst
->resource
= inst
->resource
;
3196 inst
->dead_mask
= inst
->dst
[0].writemask
;
3198 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3205 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3208 GLdouble stack_vals
[4] = { 0 };
3209 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3210 GLenum gl_type
= GL_NONE
;
3211 unsigned int i
, elements
;
3212 static int in_array
= 0;
3213 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3215 /* Unfortunately, 4 floats is all we can get into
3216 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3217 * aggregate constant and move each constant value into it. If we
3218 * get lucky, copy propagation will eliminate the extra moves.
3220 if (ir
->type
->is_struct()) {
3221 st_src_reg temp_base
= get_temp(ir
->type
);
3222 st_dst_reg temp
= st_dst_reg(temp_base
);
3224 for (i
= 0; i
< ir
->type
->length
; i
++) {
3225 ir_constant
*const field_value
= ir
->get_record_field(i
);
3226 int size
= type_size(field_value
->type
);
3230 field_value
->accept(this);
3233 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3234 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3240 this->result
= temp_base
;
3244 if (ir
->type
->is_array()) {
3245 st_src_reg temp_base
= get_temp(ir
->type
);
3246 st_dst_reg temp
= st_dst_reg(temp_base
);
3247 int size
= type_size(ir
->type
->fields
.array
);
3252 for (i
= 0; i
< ir
->type
->length
; i
++) {
3253 ir
->const_elements
[i
]->accept(this);
3255 for (int j
= 0; j
< size
; j
++) {
3256 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3262 this->result
= temp_base
;
3267 if (ir
->type
->is_matrix()) {
3268 st_src_reg mat
= get_temp(ir
->type
);
3269 st_dst_reg mat_column
= st_dst_reg(mat
);
3271 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3272 switch (ir
->type
->base_type
) {
3273 case GLSL_TYPE_FLOAT
:
3274 values
= (gl_constant_value
*)
3275 &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3277 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3278 src
.index
= add_constant(file
,
3280 ir
->type
->vector_elements
,
3283 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3285 case GLSL_TYPE_DOUBLE
:
3286 values
= (gl_constant_value
*)
3287 &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3288 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3289 src
.index
= add_constant(file
,
3291 ir
->type
->vector_elements
,
3294 if (ir
->type
->vector_elements
>= 2) {
3295 mat_column
.writemask
= WRITEMASK_XY
;
3296 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3297 SWIZZLE_X
, SWIZZLE_Y
);
3298 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3300 mat_column
.writemask
= WRITEMASK_X
;
3301 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
3302 SWIZZLE_X
, SWIZZLE_X
);
3303 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3306 if (ir
->type
->vector_elements
> 2) {
3307 if (ir
->type
->vector_elements
== 4) {
3308 mat_column
.writemask
= WRITEMASK_ZW
;
3309 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3310 SWIZZLE_X
, SWIZZLE_Y
);
3311 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3313 mat_column
.writemask
= WRITEMASK_Z
;
3314 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
,
3315 SWIZZLE_Y
, SWIZZLE_Y
);
3316 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3317 mat_column
.writemask
= WRITEMASK_XYZW
;
3318 src
.swizzle
= SWIZZLE_XYZW
;
3324 unreachable("Illegal matrix constant type.\n");
3333 elements
= ir
->type
->vector_elements
;
3334 switch (ir
->type
->base_type
) {
3335 case GLSL_TYPE_FLOAT
:
3337 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3338 values
[i
].f
= ir
->value
.f
[i
];
3341 case GLSL_TYPE_DOUBLE
:
3342 gl_type
= GL_DOUBLE
;
3343 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3344 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3347 case GLSL_TYPE_INT64
:
3348 gl_type
= GL_INT64_ARB
;
3349 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3350 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3353 case GLSL_TYPE_UINT64
:
3354 gl_type
= GL_UNSIGNED_INT64_ARB
;
3355 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3356 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3359 case GLSL_TYPE_UINT
:
3360 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3361 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3362 if (native_integers
)
3363 values
[i
].u
= ir
->value
.u
[i
];
3365 values
[i
].f
= ir
->value
.u
[i
];
3369 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3370 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3371 if (native_integers
)
3372 values
[i
].i
= ir
->value
.i
[i
];
3374 values
[i
].f
= ir
->value
.i
[i
];
3377 case GLSL_TYPE_BOOL
:
3378 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3379 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3380 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3383 case GLSL_TYPE_SAMPLER
:
3384 case GLSL_TYPE_IMAGE
:
3385 gl_type
= GL_UNSIGNED_INT
;
3387 values
[0].u
= ir
->value
.u64
[0] & 0xffffffff;
3388 values
[1].u
= ir
->value
.u64
[0] >> 32;
3391 assert(!"Non-float/uint/int/bool/sampler/image constant");
3394 this->result
= st_src_reg(file
, -1, ir
->type
);
3395 this->result
.index
= add_constant(file
,
3399 &this->result
.swizzle
);
3403 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3405 exec_node
*param
= ir
->actual_parameters
.get_head();
3406 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3407 ir_variable
*location
= deref
->variable_referenced();
3408 bool has_hw_atomics
= st_context(ctx
)->has_hw_atomics
;
3409 /* Calculate the surface offset */
3411 unsigned array_size
= 0, base
= 0;
3413 st_src_reg resource
;
3415 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3417 if (has_hw_atomics
) {
3418 variable_storage
*entry
= find_variable_storage(location
);
3419 st_src_reg
buffer(PROGRAM_HW_ATOMIC
, 0, GLSL_TYPE_ATOMIC_UINT
,
3420 location
->data
.binding
);
3423 entry
= new(mem_ctx
) variable_storage(location
, PROGRAM_HW_ATOMIC
,
3425 _mesa_hash_table_insert(this->variables
, location
, entry
);
3427 atomic_info
[num_atomics
].location
= location
->data
.location
;
3428 atomic_info
[num_atomics
].binding
= location
->data
.binding
;
3429 atomic_info
[num_atomics
].size
= location
->type
->arrays_of_arrays_size();
3430 if (atomic_info
[num_atomics
].size
== 0)
3431 atomic_info
[num_atomics
].size
= 1;
3432 atomic_info
[num_atomics
].array_id
= 0;
3436 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3437 if (atomic_info
[entry
->index
].array_id
== 0) {
3438 num_atomic_arrays
++;
3439 atomic_info
[entry
->index
].array_id
= num_atomic_arrays
;
3441 buffer
.array_id
= atomic_info
[entry
->index
].array_id
;
3444 buffer
.index
= index
;
3445 buffer
.index
+= location
->data
.offset
/ ATOMIC_COUNTER_SIZE
;
3446 buffer
.has_index2
= true;
3448 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3449 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3450 *buffer
.reladdr
= offset
;
3451 emit_arl(ir
, sampler_reladdr
, offset
);
3453 offset
= st_src_reg_for_int(0);
3457 st_src_reg
buffer(PROGRAM_BUFFER
,
3458 prog
->info
.num_ssbos
+
3459 location
->data
.binding
,
3460 GLSL_TYPE_ATOMIC_UINT
);
3462 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3463 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3464 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3465 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3466 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3468 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3473 ir
->return_deref
->accept(this);
3474 st_dst_reg
dst(this->result
);
3475 dst
.writemask
= WRITEMASK_X
;
3477 glsl_to_tgsi_instruction
*inst
;
3479 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3480 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3481 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3482 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3483 st_src_reg_for_int(1));
3484 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3485 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3486 st_src_reg_for_int(-1));
3487 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3489 param
= param
->get_next();
3490 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3493 st_src_reg data
= this->result
, data2
= undef_src
;
3494 enum tgsi_opcode opcode
;
3495 switch (ir
->callee
->intrinsic_id
) {
3496 case ir_intrinsic_atomic_counter_add
:
3497 opcode
= TGSI_OPCODE_ATOMUADD
;
3499 case ir_intrinsic_atomic_counter_min
:
3500 opcode
= TGSI_OPCODE_ATOMIMIN
;
3502 case ir_intrinsic_atomic_counter_max
:
3503 opcode
= TGSI_OPCODE_ATOMIMAX
;
3505 case ir_intrinsic_atomic_counter_and
:
3506 opcode
= TGSI_OPCODE_ATOMAND
;
3508 case ir_intrinsic_atomic_counter_or
:
3509 opcode
= TGSI_OPCODE_ATOMOR
;
3511 case ir_intrinsic_atomic_counter_xor
:
3512 opcode
= TGSI_OPCODE_ATOMXOR
;
3514 case ir_intrinsic_atomic_counter_exchange
:
3515 opcode
= TGSI_OPCODE_ATOMXCHG
;
3517 case ir_intrinsic_atomic_counter_comp_swap
: {
3518 opcode
= TGSI_OPCODE_ATOMCAS
;
3519 param
= param
->get_next();
3520 val
= ((ir_instruction
*)param
)->as_rvalue();
3522 data2
= this->result
;
3526 assert(!"Unexpected intrinsic");
3530 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3533 inst
->resource
= resource
;
3537 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3539 exec_node
*param
= ir
->actual_parameters
.get_head();
3541 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3543 param
= param
->get_next();
3544 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3546 ir_constant
*const_block
= block
->as_constant();
3549 const_block
? const_block
->value
.u
[0] : 0,
3553 block
->accept(this);
3554 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3555 *buffer
.reladdr
= this->result
;
3556 emit_arl(ir
, sampler_reladdr
, this->result
);
3559 /* Calculate the surface offset */
3560 offset
->accept(this);
3561 st_src_reg off
= this->result
;
3563 st_dst_reg dst
= undef_dst
;
3564 if (ir
->return_deref
) {
3565 ir
->return_deref
->accept(this);
3566 dst
= st_dst_reg(this->result
);
3567 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3570 glsl_to_tgsi_instruction
*inst
;
3572 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3573 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3574 if (dst
.type
== GLSL_TYPE_BOOL
)
3575 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
),
3576 st_src_reg_for_int(0));
3577 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3578 param
= param
->get_next();
3579 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3582 param
= param
->get_next();
3583 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3585 dst
.writemask
= write_mask
->value
.u
[0];
3587 dst
.type
= this->result
.type
;
3588 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3590 param
= param
->get_next();
3591 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3594 st_src_reg data
= this->result
, data2
= undef_src
;
3595 enum tgsi_opcode opcode
;
3596 switch (ir
->callee
->intrinsic_id
) {
3597 case ir_intrinsic_ssbo_atomic_add
:
3598 opcode
= TGSI_OPCODE_ATOMUADD
;
3600 case ir_intrinsic_ssbo_atomic_min
:
3601 opcode
= TGSI_OPCODE_ATOMIMIN
;
3603 case ir_intrinsic_ssbo_atomic_max
:
3604 opcode
= TGSI_OPCODE_ATOMIMAX
;
3606 case ir_intrinsic_ssbo_atomic_and
:
3607 opcode
= TGSI_OPCODE_ATOMAND
;
3609 case ir_intrinsic_ssbo_atomic_or
:
3610 opcode
= TGSI_OPCODE_ATOMOR
;
3612 case ir_intrinsic_ssbo_atomic_xor
:
3613 opcode
= TGSI_OPCODE_ATOMXOR
;
3615 case ir_intrinsic_ssbo_atomic_exchange
:
3616 opcode
= TGSI_OPCODE_ATOMXCHG
;
3618 case ir_intrinsic_ssbo_atomic_comp_swap
:
3619 opcode
= TGSI_OPCODE_ATOMCAS
;
3620 param
= param
->get_next();
3621 val
= ((ir_instruction
*)param
)->as_rvalue();
3623 data2
= this->result
;
3626 assert(!"Unexpected intrinsic");
3630 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3633 param
= param
->get_next();
3634 ir_constant
*access
= NULL
;
3635 if (!param
->is_tail_sentinel()) {
3636 access
= ((ir_instruction
*)param
)->as_constant();
3640 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3644 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3646 switch (ir
->callee
->intrinsic_id
) {
3647 case ir_intrinsic_memory_barrier
:
3648 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3649 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3650 TGSI_MEMBAR_ATOMIC_BUFFER
|
3651 TGSI_MEMBAR_SHADER_IMAGE
|
3652 TGSI_MEMBAR_SHARED
));
3654 case ir_intrinsic_memory_barrier_atomic_counter
:
3655 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3656 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3658 case ir_intrinsic_memory_barrier_buffer
:
3659 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3660 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3662 case ir_intrinsic_memory_barrier_image
:
3663 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3664 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3666 case ir_intrinsic_memory_barrier_shared
:
3667 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3668 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3670 case ir_intrinsic_group_memory_barrier
:
3671 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3672 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3673 TGSI_MEMBAR_ATOMIC_BUFFER
|
3674 TGSI_MEMBAR_SHADER_IMAGE
|
3675 TGSI_MEMBAR_SHARED
|
3676 TGSI_MEMBAR_THREAD_GROUP
));
3679 assert(!"Unexpected memory barrier intrinsic");
3684 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3686 exec_node
*param
= ir
->actual_parameters
.get_head();
3688 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3690 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3692 /* Calculate the surface offset */
3693 offset
->accept(this);
3694 st_src_reg off
= this->result
;
3696 st_dst_reg dst
= undef_dst
;
3697 if (ir
->return_deref
) {
3698 ir
->return_deref
->accept(this);
3699 dst
= st_dst_reg(this->result
);
3700 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3703 glsl_to_tgsi_instruction
*inst
;
3705 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3706 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3707 inst
->resource
= buffer
;
3708 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3709 param
= param
->get_next();
3710 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3713 param
= param
->get_next();
3714 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3716 dst
.writemask
= write_mask
->value
.u
[0];
3718 dst
.type
= this->result
.type
;
3719 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3720 inst
->resource
= buffer
;
3722 param
= param
->get_next();
3723 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3726 st_src_reg data
= this->result
, data2
= undef_src
;
3727 enum tgsi_opcode opcode
;
3728 switch (ir
->callee
->intrinsic_id
) {
3729 case ir_intrinsic_shared_atomic_add
:
3730 opcode
= TGSI_OPCODE_ATOMUADD
;
3732 case ir_intrinsic_shared_atomic_min
:
3733 opcode
= TGSI_OPCODE_ATOMIMIN
;
3735 case ir_intrinsic_shared_atomic_max
:
3736 opcode
= TGSI_OPCODE_ATOMIMAX
;
3738 case ir_intrinsic_shared_atomic_and
:
3739 opcode
= TGSI_OPCODE_ATOMAND
;
3741 case ir_intrinsic_shared_atomic_or
:
3742 opcode
= TGSI_OPCODE_ATOMOR
;
3744 case ir_intrinsic_shared_atomic_xor
:
3745 opcode
= TGSI_OPCODE_ATOMXOR
;
3747 case ir_intrinsic_shared_atomic_exchange
:
3748 opcode
= TGSI_OPCODE_ATOMXCHG
;
3750 case ir_intrinsic_shared_atomic_comp_swap
:
3751 opcode
= TGSI_OPCODE_ATOMCAS
;
3752 param
= param
->get_next();
3753 val
= ((ir_instruction
*)param
)->as_rvalue();
3755 data2
= this->result
;
3758 assert(!"Unexpected intrinsic");
3762 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3763 inst
->resource
= buffer
;
3768 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3769 bool *memory_coherent
, bool *memory_volatile
,
3770 bool *memory_restrict
, bool *memory_read_only
,
3771 unsigned *image_format
)
3774 switch (ir
->ir_type
) {
3775 case ir_type_dereference_record
: {
3776 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3777 const glsl_type
*struct_type
= deref_record
->record
->type
;
3778 int fild_idx
= deref_record
->field_idx
;
3780 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3782 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3784 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3786 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3788 struct_type
->fields
.structure
[fild_idx
].memory_read_only
;
3790 struct_type
->fields
.structure
[fild_idx
].image_format
;
3794 case ir_type_dereference_array
: {
3795 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3796 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3797 memory_coherent
, memory_volatile
, memory_restrict
,
3798 memory_read_only
, image_format
);
3802 case ir_type_dereference_variable
: {
3803 ir_variable
*var
= ir
->variable_referenced();
3805 *type
= var
->type
->without_array();
3806 *memory_coherent
= var
->data
.memory_coherent
;
3807 *memory_volatile
= var
->data
.memory_volatile
;
3808 *memory_restrict
= var
->data
.memory_restrict
;
3809 *memory_read_only
= var
->data
.memory_read_only
;
3810 *image_format
= var
->data
.image_format
;
3820 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3822 exec_node
*param
= ir
->actual_parameters
.get_head();
3824 ir_dereference
*img
= (ir_dereference
*)param
;
3825 const ir_variable
*imgvar
= img
->variable_referenced();
3826 unsigned sampler_array_size
= 1, sampler_base
= 0;
3827 bool memory_coherent
= false, memory_volatile
= false,
3828 memory_restrict
= false, memory_read_only
= false;
3829 unsigned image_format
= 0;
3830 const glsl_type
*type
= NULL
;
3832 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3833 &memory_restrict
, &memory_read_only
, &image_format
);
3836 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3838 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3839 &index
, &reladdr
, !imgvar
->contains_bindless());
3841 image
.index
= index
;
3842 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3843 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3844 *image
.reladdr
= reladdr
;
3845 emit_arl(ir
, sampler_reladdr
, reladdr
);
3848 st_dst_reg dst
= undef_dst
;
3849 if (ir
->return_deref
) {
3850 ir
->return_deref
->accept(this);
3851 dst
= st_dst_reg(this->result
);
3852 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3855 glsl_to_tgsi_instruction
*inst
;
3857 st_src_reg bindless
;
3858 if (imgvar
->contains_bindless()) {
3860 bindless
= this->result
;
3863 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3864 dst
.writemask
= WRITEMASK_XYZ
;
3865 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3866 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3867 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3868 st_dst_reg dstres
= st_dst_reg(res
);
3869 dstres
.writemask
= WRITEMASK_W
;
3870 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3871 res
.swizzle
= SWIZZLE_WWWW
;
3872 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3874 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3876 st_dst_reg coord_dst
;
3877 coord
= get_temp(glsl_type::ivec4_type
);
3878 coord_dst
= st_dst_reg(coord
);
3879 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3880 param
= param
->get_next();
3881 ((ir_dereference
*)param
)->accept(this);
3882 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3883 coord
.swizzle
= SWIZZLE_XXXX
;
3884 switch (type
->coordinate_components()) {
3885 case 4: assert(!"unexpected coord count");
3887 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3889 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3892 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3893 param
= param
->get_next();
3894 ((ir_dereference
*)param
)->accept(this);
3895 st_src_reg sample
= this->result
;
3896 sample
.swizzle
= SWIZZLE_XXXX
;
3897 coord_dst
.writemask
= WRITEMASK_W
;
3898 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3899 coord
.swizzle
|= SWIZZLE_W
<< 9;
3902 param
= param
->get_next();
3903 if (!param
->is_tail_sentinel()) {
3904 ((ir_dereference
*)param
)->accept(this);
3905 arg1
= this->result
;
3906 param
= param
->get_next();
3909 if (!param
->is_tail_sentinel()) {
3910 ((ir_dereference
*)param
)->accept(this);
3911 arg2
= this->result
;
3912 param
= param
->get_next();
3915 assert(param
->is_tail_sentinel());
3917 enum tgsi_opcode opcode
;
3918 switch (ir
->callee
->intrinsic_id
) {
3919 case ir_intrinsic_image_load
:
3920 opcode
= TGSI_OPCODE_LOAD
;
3922 case ir_intrinsic_image_store
:
3923 opcode
= TGSI_OPCODE_STORE
;
3925 case ir_intrinsic_image_atomic_add
:
3926 opcode
= TGSI_OPCODE_ATOMUADD
;
3928 case ir_intrinsic_image_atomic_min
:
3929 opcode
= TGSI_OPCODE_ATOMIMIN
;
3931 case ir_intrinsic_image_atomic_max
:
3932 opcode
= TGSI_OPCODE_ATOMIMAX
;
3934 case ir_intrinsic_image_atomic_and
:
3935 opcode
= TGSI_OPCODE_ATOMAND
;
3937 case ir_intrinsic_image_atomic_or
:
3938 opcode
= TGSI_OPCODE_ATOMOR
;
3940 case ir_intrinsic_image_atomic_xor
:
3941 opcode
= TGSI_OPCODE_ATOMXOR
;
3943 case ir_intrinsic_image_atomic_exchange
:
3944 opcode
= TGSI_OPCODE_ATOMXCHG
;
3946 case ir_intrinsic_image_atomic_comp_swap
:
3947 opcode
= TGSI_OPCODE_ATOMCAS
;
3949 case ir_intrinsic_image_atomic_inc_wrap
: {
3950 /* There's a bit of disagreement between GLSL and the hardware. The
3951 * hardware wants to wrap after the given wrap value, while GLSL
3952 * wants to wrap at the value. Subtract 1 to make up the difference.
3954 st_src_reg wrap
= get_temp(glsl_type::uint_type
);
3955 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(wrap
),
3956 arg1
, st_src_reg_for_int(-1));
3958 opcode
= TGSI_OPCODE_ATOMINC_WRAP
;
3961 case ir_intrinsic_image_atomic_dec_wrap
:
3962 opcode
= TGSI_OPCODE_ATOMDEC_WRAP
;
3965 assert(!"Unexpected intrinsic");
3969 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3970 if (opcode
== TGSI_OPCODE_STORE
)
3971 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3974 if (imgvar
->contains_bindless()) {
3975 inst
->resource
= bindless
;
3976 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3977 SWIZZLE_X
, SWIZZLE_Y
);
3979 inst
->resource
= image
;
3980 inst
->sampler_array_size
= sampler_array_size
;
3981 inst
->sampler_base
= sampler_base
;
3984 inst
->tex_target
= type
->sampler_index();
3985 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3986 _mesa_get_shader_image_format(image_format
));
3987 inst
->read_only
= memory_read_only
;
3989 if (memory_coherent
)
3990 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3991 if (memory_restrict
)
3992 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3993 if (memory_volatile
)
3994 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3998 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, enum tgsi_opcode op
)
4000 ir
->return_deref
->accept(this);
4001 st_dst_reg dst
= st_dst_reg(this->result
);
4003 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
4005 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
4006 unsigned num_src
= 0;
4007 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
4008 assert(num_src
< ARRAY_SIZE(src
));
4010 this->result
.file
= PROGRAM_UNDEFINED
;
4011 param
->accept(this);
4012 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4014 src
[num_src
] = this->result
;
4018 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
4022 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
4024 ir_function_signature
*sig
= ir
->callee
;
4026 /* Filter out intrinsics */
4027 switch (sig
->intrinsic_id
) {
4028 case ir_intrinsic_atomic_counter_read
:
4029 case ir_intrinsic_atomic_counter_increment
:
4030 case ir_intrinsic_atomic_counter_predecrement
:
4031 case ir_intrinsic_atomic_counter_add
:
4032 case ir_intrinsic_atomic_counter_min
:
4033 case ir_intrinsic_atomic_counter_max
:
4034 case ir_intrinsic_atomic_counter_and
:
4035 case ir_intrinsic_atomic_counter_or
:
4036 case ir_intrinsic_atomic_counter_xor
:
4037 case ir_intrinsic_atomic_counter_exchange
:
4038 case ir_intrinsic_atomic_counter_comp_swap
:
4039 visit_atomic_counter_intrinsic(ir
);
4042 case ir_intrinsic_ssbo_load
:
4043 case ir_intrinsic_ssbo_store
:
4044 case ir_intrinsic_ssbo_atomic_add
:
4045 case ir_intrinsic_ssbo_atomic_min
:
4046 case ir_intrinsic_ssbo_atomic_max
:
4047 case ir_intrinsic_ssbo_atomic_and
:
4048 case ir_intrinsic_ssbo_atomic_or
:
4049 case ir_intrinsic_ssbo_atomic_xor
:
4050 case ir_intrinsic_ssbo_atomic_exchange
:
4051 case ir_intrinsic_ssbo_atomic_comp_swap
:
4052 visit_ssbo_intrinsic(ir
);
4055 case ir_intrinsic_memory_barrier
:
4056 case ir_intrinsic_memory_barrier_atomic_counter
:
4057 case ir_intrinsic_memory_barrier_buffer
:
4058 case ir_intrinsic_memory_barrier_image
:
4059 case ir_intrinsic_memory_barrier_shared
:
4060 case ir_intrinsic_group_memory_barrier
:
4061 visit_membar_intrinsic(ir
);
4064 case ir_intrinsic_shared_load
:
4065 case ir_intrinsic_shared_store
:
4066 case ir_intrinsic_shared_atomic_add
:
4067 case ir_intrinsic_shared_atomic_min
:
4068 case ir_intrinsic_shared_atomic_max
:
4069 case ir_intrinsic_shared_atomic_and
:
4070 case ir_intrinsic_shared_atomic_or
:
4071 case ir_intrinsic_shared_atomic_xor
:
4072 case ir_intrinsic_shared_atomic_exchange
:
4073 case ir_intrinsic_shared_atomic_comp_swap
:
4074 visit_shared_intrinsic(ir
);
4077 case ir_intrinsic_image_load
:
4078 case ir_intrinsic_image_store
:
4079 case ir_intrinsic_image_atomic_add
:
4080 case ir_intrinsic_image_atomic_min
:
4081 case ir_intrinsic_image_atomic_max
:
4082 case ir_intrinsic_image_atomic_and
:
4083 case ir_intrinsic_image_atomic_or
:
4084 case ir_intrinsic_image_atomic_xor
:
4085 case ir_intrinsic_image_atomic_exchange
:
4086 case ir_intrinsic_image_atomic_comp_swap
:
4087 case ir_intrinsic_image_size
:
4088 case ir_intrinsic_image_samples
:
4089 case ir_intrinsic_image_atomic_inc_wrap
:
4090 case ir_intrinsic_image_atomic_dec_wrap
:
4091 visit_image_intrinsic(ir
);
4094 case ir_intrinsic_shader_clock
:
4095 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4098 case ir_intrinsic_vote_all
:
4099 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4101 case ir_intrinsic_vote_any
:
4102 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4104 case ir_intrinsic_vote_eq
:
4105 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4107 case ir_intrinsic_ballot
:
4108 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4110 case ir_intrinsic_read_first_invocation
:
4111 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4113 case ir_intrinsic_read_invocation
:
4114 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4117 case ir_intrinsic_helper_invocation
:
4118 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_HELPER
);
4121 case ir_intrinsic_invalid
:
4122 case ir_intrinsic_generic_load
:
4123 case ir_intrinsic_generic_store
:
4124 case ir_intrinsic_generic_atomic_add
:
4125 case ir_intrinsic_generic_atomic_and
:
4126 case ir_intrinsic_generic_atomic_or
:
4127 case ir_intrinsic_generic_atomic_xor
:
4128 case ir_intrinsic_generic_atomic_min
:
4129 case ir_intrinsic_generic_atomic_max
:
4130 case ir_intrinsic_generic_atomic_exchange
:
4131 case ir_intrinsic_generic_atomic_comp_swap
:
4132 case ir_intrinsic_begin_invocation_interlock
:
4133 case ir_intrinsic_end_invocation_interlock
:
4134 unreachable("Invalid intrinsic");
4139 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4140 unsigned *array_elements
,
4142 st_src_reg
*indirect
,
4145 switch (tail
->ir_type
) {
4146 case ir_type_dereference_record
: {
4147 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4148 const glsl_type
*struct_type
= deref_record
->record
->type
;
4149 int field_index
= deref_record
->field_idx
;
4151 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4153 assert(field_index
>= 0);
4154 *location
+= struct_type
->struct_location_offset(field_index
);
4158 case ir_type_dereference_array
: {
4159 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4161 void *mem_ctx
= ralloc_parent(deref_arr
);
4162 ir_constant
*array_index
=
4163 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
4166 st_src_reg temp_reg
;
4167 st_dst_reg temp_dst
;
4169 temp_reg
= get_temp(glsl_type::uint_type
);
4170 temp_dst
= st_dst_reg(temp_reg
);
4171 temp_dst
.writemask
= 1;
4173 deref_arr
->array_index
->accept(this);
4174 if (*array_elements
!= 1)
4175 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4177 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4179 if (indirect
->file
== PROGRAM_UNDEFINED
)
4180 *indirect
= temp_reg
;
4182 temp_dst
= st_dst_reg(*indirect
);
4183 temp_dst
.writemask
= 1;
4184 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4187 *index
+= array_index
->value
.u
[0] * *array_elements
;
4189 *array_elements
*= deref_arr
->array
->type
->length
;
4191 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4200 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4201 unsigned *array_size
,
4204 st_src_reg
*reladdr
,
4207 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4208 unsigned location
= 0;
4209 ir_variable
*var
= ir
->variable_referenced();
4217 location
= var
->data
.location
;
4218 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4221 * If we end up with no indirect then adjust the base to the index,
4222 * and set the array size to 1.
4224 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4230 assert(location
!= 0xffffffff);
4231 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4232 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4237 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4239 if (offset
.reladdr
|| offset
.reladdr2
||
4240 offset
.has_index2
||
4241 offset
.file
== PROGRAM_UNIFORM
||
4242 offset
.file
== PROGRAM_CONSTANT
||
4243 offset
.file
== PROGRAM_STATE_VAR
) {
4244 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4245 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4246 tmp_dst
.writemask
= WRITEMASK_XY
;
4247 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4255 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference
*ir
)
4257 ir_variable
*var
= ir
->variable_referenced();
4259 if (!var
|| var
->data
.mode
!= ir_var_uniform
|| var
->data
.bindless
||
4260 !(ir
->type
->is_image() || ir
->type
->is_sampler()))
4263 /* Convert from bound sampler/image to bindless handle. */
4264 bool is_image
= ir
->type
->is_image();
4265 st_src_reg
resource(is_image
? PROGRAM_IMAGE
: PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4267 unsigned array_size
= 1, base
= 0;
4269 get_deref_offsets(ir
, &array_size
, &base
, &index
, &reladdr
, true);
4271 resource
.index
= index
;
4272 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4273 resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4274 *resource
.reladdr
= reladdr
;
4275 emit_arl(ir
, sampler_reladdr
, reladdr
);
4278 this->result
= get_temp(glsl_type::uvec2_type
);
4279 st_dst_reg
dst(this->result
);
4280 dst
.writemask
= WRITEMASK_XY
;
4282 glsl_to_tgsi_instruction
*inst
= emit_asm(
4283 ir
, is_image
? TGSI_OPCODE_IMG2HND
: TGSI_OPCODE_SAMP2HND
, dst
);
4285 inst
->tex_target
= ir
->type
->sampler_index();
4286 inst
->resource
= resource
;
4287 inst
->sampler_array_size
= array_size
;
4288 inst
->sampler_base
= base
;
4294 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4296 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4297 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4298 st_src_reg levels_src
, reladdr
;
4299 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4300 glsl_to_tgsi_instruction
*inst
= NULL
;
4301 enum tgsi_opcode opcode
= TGSI_OPCODE_NOP
;
4302 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4303 unsigned sampler_array_size
= 1, sampler_base
= 0;
4304 bool is_cube_array
= false, is_cube_shadow
= false;
4305 ir_variable
*var
= ir
->sampler
->variable_referenced();
4308 /* if we are a cube array sampler or a cube shadow */
4309 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4310 is_cube_array
= sampler_type
->sampler_array
;
4311 is_cube_shadow
= sampler_type
->sampler_shadow
;
4314 if (ir
->coordinate
) {
4315 ir
->coordinate
->accept(this);
4317 /* Put our coords in a temp. We'll need to modify them for shadow,
4318 * projection, or LOD, so the only case we'd use it as-is is if
4319 * we're doing plain old texturing. The optimization passes on
4320 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4322 coord
= get_temp(glsl_type::vec4_type
);
4323 coord_dst
= st_dst_reg(coord
);
4324 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4325 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4328 if (ir
->projector
) {
4329 ir
->projector
->accept(this);
4330 projector
= this->result
;
4333 /* Storage for our result. Ideally for an assignment we'd be using
4334 * the actual storage for the result here, instead.
4336 result_src
= get_temp(ir
->type
);
4337 result_dst
= st_dst_reg(result_src
);
4338 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4342 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4344 ir
->offset
->accept(this);
4345 offset
[0] = this->result
;
4349 if (is_cube_array
|| is_cube_shadow
) {
4350 opcode
= TGSI_OPCODE_TXB2
;
4353 opcode
= TGSI_OPCODE_TXB
;
4355 ir
->lod_info
.bias
->accept(this);
4356 lod_info
= this->result
;
4358 ir
->offset
->accept(this);
4359 offset
[0] = this->result
;
4363 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4364 opcode
= TGSI_OPCODE_TEX_LZ
;
4366 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4367 ir
->lod_info
.lod
->accept(this);
4368 lod_info
= this->result
;
4371 ir
->offset
->accept(this);
4372 offset
[0] = this->result
;
4376 opcode
= TGSI_OPCODE_TXD
;
4377 ir
->lod_info
.grad
.dPdx
->accept(this);
4379 ir
->lod_info
.grad
.dPdy
->accept(this);
4382 ir
->offset
->accept(this);
4383 offset
[0] = this->result
;
4387 opcode
= TGSI_OPCODE_TXQ
;
4388 ir
->lod_info
.lod
->accept(this);
4389 lod_info
= this->result
;
4391 case ir_query_levels
:
4392 opcode
= TGSI_OPCODE_TXQ
;
4393 lod_info
= undef_src
;
4394 levels_src
= get_temp(ir
->type
);
4397 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4398 opcode
= TGSI_OPCODE_TXF_LZ
;
4400 opcode
= TGSI_OPCODE_TXF
;
4401 ir
->lod_info
.lod
->accept(this);
4402 lod_info
= this->result
;
4405 ir
->offset
->accept(this);
4406 offset
[0] = this->result
;
4410 opcode
= TGSI_OPCODE_TXF
;
4411 ir
->lod_info
.sample_index
->accept(this);
4412 sample_index
= this->result
;
4415 opcode
= TGSI_OPCODE_TG4
;
4416 ir
->lod_info
.component
->accept(this);
4417 component
= this->result
;
4419 ir
->offset
->accept(this);
4420 if (ir
->offset
->type
->is_array()) {
4421 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4422 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4423 offset
[i
] = this->result
;
4424 offset
[i
].index
+= i
* type_size(elt_type
);
4425 offset
[i
].type
= elt_type
->base_type
;
4426 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4427 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4430 offset
[0] = canonicalize_gather_offset(this->result
);
4435 opcode
= TGSI_OPCODE_LODQ
;
4437 case ir_texture_samples
:
4438 opcode
= TGSI_OPCODE_TXQS
;
4440 case ir_samples_identical
:
4441 unreachable("Unexpected ir_samples_identical opcode");
4444 if (ir
->projector
) {
4445 if (opcode
== TGSI_OPCODE_TEX
) {
4446 /* Slot the projector in as the last component of the coord. */
4447 coord_dst
.writemask
= WRITEMASK_W
;
4448 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4449 coord_dst
.writemask
= WRITEMASK_XYZW
;
4450 opcode
= TGSI_OPCODE_TXP
;
4452 st_src_reg coord_w
= coord
;
4453 coord_w
.swizzle
= SWIZZLE_WWWW
;
4455 /* For the other TEX opcodes there's no projective version
4456 * since the last slot is taken up by LOD info. Do the
4457 * projective divide now.
4459 coord_dst
.writemask
= WRITEMASK_W
;
4460 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4462 /* In the case where we have to project the coordinates "by hand,"
4463 * the shadow comparator value must also be projected.
4465 st_src_reg tmp_src
= coord
;
4466 if (ir
->shadow_comparator
) {
4467 /* Slot the shadow value in as the second to last component of the
4470 ir
->shadow_comparator
->accept(this);
4472 tmp_src
= get_temp(glsl_type::vec4_type
);
4473 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4475 /* Projective division not allowed for array samplers. */
4476 assert(!sampler_type
->sampler_array
);
4478 tmp_dst
.writemask
= WRITEMASK_Z
;
4479 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4481 tmp_dst
.writemask
= WRITEMASK_XY
;
4482 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4485 coord_dst
.writemask
= WRITEMASK_XYZ
;
4486 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4488 coord_dst
.writemask
= WRITEMASK_XYZW
;
4489 coord
.swizzle
= SWIZZLE_XYZW
;
4493 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4494 * shadow comparator was put in the correct place (and projected) by the
4495 * code, above, that handles by-hand projection.
4497 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4498 /* Slot the shadow value in as the second to last component of the
4501 ir
->shadow_comparator
->accept(this);
4503 if (is_cube_array
) {
4504 cube_sc
= get_temp(glsl_type::float_type
);
4505 cube_sc_dst
= st_dst_reg(cube_sc
);
4506 cube_sc_dst
.writemask
= WRITEMASK_X
;
4507 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4508 cube_sc_dst
.writemask
= WRITEMASK_X
;
4511 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4512 sampler_type
->sampler_array
) ||
4513 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4514 coord_dst
.writemask
= WRITEMASK_W
;
4516 coord_dst
.writemask
= WRITEMASK_Z
;
4518 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4519 coord_dst
.writemask
= WRITEMASK_XYZW
;
4523 if (ir
->op
== ir_txf_ms
) {
4524 coord_dst
.writemask
= WRITEMASK_W
;
4525 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4526 coord_dst
.writemask
= WRITEMASK_XYZW
;
4527 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4528 opcode
== TGSI_OPCODE_TXF
) {
4529 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4530 coord_dst
.writemask
= WRITEMASK_W
;
4531 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4532 coord_dst
.writemask
= WRITEMASK_XYZW
;
4535 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4538 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4539 &index
, &reladdr
, !var
->contains_bindless());
4541 sampler
.index
= index
;
4542 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4543 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4544 *sampler
.reladdr
= reladdr
;
4545 emit_arl(ir
, sampler_reladdr
, reladdr
);
4548 st_src_reg bindless
;
4549 if (var
->contains_bindless()) {
4550 ir
->sampler
->accept(this);
4551 bindless
= this->result
;
4554 if (opcode
== TGSI_OPCODE_TXD
)
4555 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4556 else if (opcode
== TGSI_OPCODE_TXQ
) {
4557 if (ir
->op
== ir_query_levels
) {
4558 /* the level is stored in W */
4559 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4560 result_dst
.writemask
= WRITEMASK_X
;
4561 levels_src
.swizzle
= SWIZZLE_WWWW
;
4562 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4564 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4565 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4566 inst
= emit_asm(ir
, opcode
, result_dst
);
4567 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4568 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4569 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4570 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4571 } else if (opcode
== TGSI_OPCODE_TG4
) {
4572 if (is_cube_array
&& ir
->shadow_comparator
) {
4573 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4575 if (this->tg4_component_in_swizzle
) {
4576 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4578 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
4579 if (component
.index
== idx
) {
4580 gl_constant_value value
= entry
->values
[component
.swizzle
];
4581 inst
->gather_component
= value
.i
;
4587 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4591 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4593 if (ir
->shadow_comparator
)
4594 inst
->tex_shadow
= GL_TRUE
;
4596 if (var
->contains_bindless()) {
4597 inst
->resource
= bindless
;
4598 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4599 SWIZZLE_X
, SWIZZLE_Y
);
4601 inst
->resource
= sampler
;
4602 inst
->sampler_array_size
= sampler_array_size
;
4603 inst
->sampler_base
= sampler_base
;
4607 if (!inst
->tex_offsets
)
4608 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
,
4609 MAX_GLSL_TEXTURE_OFFSET
);
4611 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&&
4612 offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4613 inst
->tex_offsets
[i
] = offset
[i
];
4614 inst
->tex_offset_num_offset
= i
;
4617 inst
->tex_target
= sampler_type
->sampler_index();
4618 inst
->tex_type
= ir
->type
->base_type
;
4620 this->result
= result_src
;
4624 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4626 assert(!ir
->get_value());
4628 emit_asm(ir
, TGSI_OPCODE_RET
);
4632 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4634 if (ir
->condition
) {
4635 ir
->condition
->accept(this);
4636 st_src_reg condition
= this->result
;
4638 /* Convert the bool condition to a float so we can negate. */
4639 if (native_integers
) {
4640 st_src_reg temp
= get_temp(ir
->condition
->type
);
4641 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4642 condition
, st_src_reg_for_float(1.0));
4646 condition
.negate
= ~condition
.negate
;
4647 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4649 /* unconditional kil */
4650 emit_asm(ir
, TGSI_OPCODE_KILL
);
4655 glsl_to_tgsi_visitor::visit(ir_demote
*ir
)
4657 emit_asm(ir
, TGSI_OPCODE_DEMOTE
);
4661 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4663 enum tgsi_opcode if_opcode
;
4664 glsl_to_tgsi_instruction
*if_inst
;
4666 ir
->condition
->accept(this);
4667 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4669 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4671 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4673 this->instructions
.push_tail(if_inst
);
4675 visit_exec_list(&ir
->then_instructions
, this);
4677 if (!ir
->else_instructions
.is_empty()) {
4678 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4679 visit_exec_list(&ir
->else_instructions
, this);
4682 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4687 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4689 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4691 ir
->stream
->accept(this);
4692 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4696 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4698 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4700 ir
->stream
->accept(this);
4701 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4705 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4707 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4708 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4710 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4713 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4715 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4717 result
.file
= PROGRAM_UNDEFINED
;
4724 num_input_arrays
= 0;
4725 num_output_arrays
= 0;
4727 num_atomic_arrays
= 0;
4729 num_address_regs
= 0;
4732 indirect_addr_consts
= false;
4733 wpos_transform_const
= -1;
4734 native_integers
= false;
4735 mem_ctx
= ralloc_context(NULL
);
4740 tg4_component_in_swizzle
= false;
4741 shader_program
= NULL
;
4746 use_shared_memory
= false;
4747 has_tex_txf_lz
= false;
4751 static void var_destroy(struct hash_entry
*entry
)
4753 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4758 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4760 _mesa_hash_table_destroy(variables
, var_destroy
);
4762 ralloc_free(mem_ctx
);
4765 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4772 * Count resources used by the given gpu program (number of texture
4776 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4778 v
->samplers_used
= 0;
4780 prog
->info
.textures_used_by_txf
= 0;
4782 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4783 if (inst
->info
->is_tex
) {
4784 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4785 unsigned idx
= inst
->sampler_base
+ i
;
4786 v
->samplers_used
|= 1u << idx
;
4788 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4789 v
->sampler_types
[idx
] = inst
->tex_type
;
4790 v
->sampler_targets
[idx
] =
4791 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4793 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4794 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4799 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4800 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4802 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4803 is_resource_instruction(inst
->op
) ||
4804 inst
->op
== TGSI_OPCODE_STORE
)) {
4805 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4806 v
->use_shared_memory
= true;
4807 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4808 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4809 unsigned idx
= inst
->sampler_base
+ i
;
4810 v
->images_used
|= 1 << idx
;
4811 v
->image_targets
[idx
] =
4812 st_translate_texture_target(inst
->tex_target
, false);
4813 v
->image_formats
[idx
] = inst
->image_format
;
4814 v
->image_wr
[idx
] = !inst
->read_only
;
4819 prog
->SamplersUsed
= v
->samplers_used
;
4821 if (v
->shader_program
!= NULL
)
4822 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4826 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4827 * are read from the given src in this instruction
4830 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4832 int read_mask
= 0, comp
;
4834 /* Now, given the src swizzle and the written channels, find which
4835 * components are actually read
4837 for (comp
= 0; comp
< 4; ++comp
) {
4838 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4840 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4841 read_mask
|= 1 << coord
;
4848 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4849 * instruction is the first instruction to write to register T0. There are
4850 * several lowering passes done in GLSL IR (e.g. branches and
4851 * relative addressing) that create a large number of conditional assignments
4852 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4854 * Here is why this conversion is safe:
4855 * CMP T0, T1 T2 T0 can be expanded to:
4861 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4862 * as the original program. If (T1 < 0.0) evaluates to false, executing
4863 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4864 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4865 * because any instruction that was going to read from T0 after this was going
4866 * to read a garbage value anyway.
4869 glsl_to_tgsi_visitor::simplify_cmp(void)
4871 int tempWritesSize
= 0;
4872 unsigned *tempWrites
= NULL
;
4873 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4875 memset(outputWrites
, 0, sizeof(outputWrites
));
4877 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4878 unsigned prevWriteMask
= 0;
4880 /* Give up if we encounter relative addressing or flow control. */
4881 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4882 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4883 inst
->info
->is_branch
||
4884 inst
->op
== TGSI_OPCODE_CONT
||
4885 inst
->op
== TGSI_OPCODE_END
||
4886 inst
->op
== TGSI_OPCODE_RET
) {
4890 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4891 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4892 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4893 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4894 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4895 if (inst
->dst
[0].index
>= tempWritesSize
) {
4896 const int inc
= 4096;
4898 tempWrites
= (unsigned*)
4900 (tempWritesSize
+ inc
) * sizeof(unsigned));
4904 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4905 tempWritesSize
+= inc
;
4908 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4909 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4913 /* For a CMP to be considered a conditional write, the destination
4914 * register and source register two must be the same. */
4915 if (inst
->op
== TGSI_OPCODE_CMP
4916 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4917 && inst
->src
[2].file
== inst
->dst
[0].file
4918 && inst
->src
[2].index
== inst
->dst
[0].index
4919 && inst
->dst
[0].writemask
==
4920 get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4922 inst
->op
= TGSI_OPCODE_MOV
;
4923 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4924 inst
->src
[0] = inst
->src
[1];
4932 rename_temp_handle_src(struct rename_reg_pair
*renames
, st_src_reg
*src
)
4934 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4935 int old_idx
= src
->index
;
4936 if (renames
[old_idx
].valid
)
4937 src
->index
= renames
[old_idx
].new_reg
;
4941 /* Replaces all references to a temporary register index with another index. */
4943 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4945 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4947 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4948 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4949 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4950 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4953 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4954 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4955 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4956 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4959 rename_temp_handle_src(renames
, &inst
->resource
);
4960 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4961 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4963 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4964 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4965 int old_idx
= inst
->dst
[j
].index
;
4966 if (renames
[old_idx
].valid
)
4967 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4969 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4970 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4976 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4978 int depth
= 0; /* loop depth */
4979 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4982 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4983 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4984 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4985 if (first_writes
[inst
->dst
[j
].index
] == -1)
4986 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4990 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4993 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
5003 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
5005 int depth
= 0; /* loop depth */
5006 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
5009 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5010 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
5011 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
5012 if (first_reads
[inst
->src
[j
].index
] == -1)
5013 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5016 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
5017 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
5018 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
5019 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5022 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
5025 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
5035 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
5037 int depth
= 0; /* loop depth */
5038 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
5041 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5042 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
5043 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
5044 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
5046 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5047 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
5048 if (first_writes
[inst
->dst
[j
].index
] == -1)
5049 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5050 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5053 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
5054 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
5055 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
5057 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
5060 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
5063 for (k
= 0; k
< this->next_temp
; k
++) {
5064 if (last_reads
[k
] == -2) {
5076 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
5078 int depth
= 0; /* loop depth */
5082 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5083 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5084 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
5085 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5088 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
5090 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
5092 for (k
= 0; k
< this->next_temp
; k
++) {
5093 if (last_writes
[k
] == -2) {
5104 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5105 * channels for copy propagation and updates following instructions to
5106 * use the original versions.
5108 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5109 * will occur. As an example, a TXP production before this pass:
5111 * 0: MOV TEMP[1], INPUT[4].xyyy;
5112 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5113 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5117 * 0: MOV TEMP[1], INPUT[4].xyyy;
5118 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5119 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5121 * which allows for dead code elimination on TEMP[1]'s writes.
5124 glsl_to_tgsi_visitor::copy_propagate(void)
5126 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5127 glsl_to_tgsi_instruction
*,
5128 this->next_temp
* 4);
5129 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5132 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5133 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5134 || inst
->dst
[0].index
< this->next_temp
);
5136 /* First, do any copy propagation possible into the src regs. */
5137 for (int r
= 0; r
< 3; r
++) {
5138 glsl_to_tgsi_instruction
*first
= NULL
;
5140 int acp_base
= inst
->src
[r
].index
* 4;
5142 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5143 inst
->src
[r
].reladdr
||
5144 inst
->src
[r
].reladdr2
)
5147 /* See if we can find entries in the ACP consisting of MOVs
5148 * from the same src register for all the swizzled channels
5149 * of this src register reference.
5151 for (int i
= 0; i
< 4; i
++) {
5152 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5153 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5160 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5165 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5166 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5167 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5168 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5176 /* We've now validated that we can copy-propagate to
5177 * replace this src register reference. Do it.
5179 inst
->src
[r
].file
= first
->src
[0].file
;
5180 inst
->src
[r
].index
= first
->src
[0].index
;
5181 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5182 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5183 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5184 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5187 for (int i
= 0; i
< 4; i
++) {
5188 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5189 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5190 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5192 inst
->src
[r
].swizzle
= swizzle
;
5197 case TGSI_OPCODE_BGNLOOP
:
5198 case TGSI_OPCODE_ENDLOOP
:
5199 /* End of a basic block, clear the ACP entirely. */
5200 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5203 case TGSI_OPCODE_IF
:
5204 case TGSI_OPCODE_UIF
:
5208 case TGSI_OPCODE_ENDIF
:
5209 case TGSI_OPCODE_ELSE
:
5210 /* Clear all channels written inside the block from the ACP, but
5211 * leaving those that were not touched.
5213 for (int r
= 0; r
< this->next_temp
; r
++) {
5214 for (int c
= 0; c
< 4; c
++) {
5215 if (!acp
[4 * r
+ c
])
5218 if (acp_level
[4 * r
+ c
] >= level
)
5219 acp
[4 * r
+ c
] = NULL
;
5222 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5227 /* Continuing the block, clear any written channels from
5230 for (int d
= 0; d
< 2; d
++) {
5231 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5232 /* Any temporary might be written, so no copy propagation
5233 * across this instruction.
5235 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5236 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5237 inst
->dst
[d
].reladdr
) {
5238 /* Any output might be written, so no copy propagation
5239 * from outputs across this instruction.
5241 for (int r
= 0; r
< this->next_temp
; r
++) {
5242 for (int c
= 0; c
< 4; c
++) {
5243 if (!acp
[4 * r
+ c
])
5246 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5247 acp
[4 * r
+ c
] = NULL
;
5250 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5251 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5252 /* Clear where it's used as dst. */
5253 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5254 for (int c
= 0; c
< 4; c
++) {
5255 if (inst
->dst
[d
].writemask
& (1 << c
))
5256 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5260 /* Clear where it's used as src. */
5261 for (int r
= 0; r
< this->next_temp
; r
++) {
5262 for (int c
= 0; c
< 4; c
++) {
5263 if (!acp
[4 * r
+ c
])
5266 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5268 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5269 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5270 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5271 acp
[4 * r
+ c
] = NULL
;
5280 /* If this is a copy, add it to the ACP. */
5281 if (inst
->op
== TGSI_OPCODE_MOV
&&
5282 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5283 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5284 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5285 !inst
->dst
[0].reladdr
&&
5286 !inst
->dst
[0].reladdr2
&&
5288 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5289 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
5290 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
5291 !inst
->src
[0].reladdr
&&
5292 !inst
->src
[0].reladdr2
&&
5293 !inst
->src
[0].negate
&&
5294 !inst
->src
[0].abs
) {
5295 for (int i
= 0; i
< 4; i
++) {
5296 if (inst
->dst
[0].writemask
& (1 << i
)) {
5297 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5298 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5304 ralloc_free(acp_level
);
5309 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
5311 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
5312 /* Clear where it's used as src. */
5313 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
5314 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5319 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5322 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5323 * will occur. As an example, a TXP production after copy propagation but
5326 * 0: MOV TEMP[1], INPUT[4].xyyy;
5327 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5328 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5330 * and after this pass:
5332 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5335 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5337 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5338 glsl_to_tgsi_instruction
*,
5339 this->next_temp
* 4);
5340 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5344 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5345 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5346 || inst
->dst
[0].index
< this->next_temp
);
5349 case TGSI_OPCODE_BGNLOOP
:
5350 case TGSI_OPCODE_ENDLOOP
:
5351 case TGSI_OPCODE_CONT
:
5352 case TGSI_OPCODE_BRK
:
5353 /* End of a basic block, clear the write array entirely.
5355 * This keeps us from killing dead code when the writes are
5356 * on either side of a loop, even when the register isn't touched
5357 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5358 * dead code of this type, so it shouldn't make a difference as long as
5359 * the dead code elimination pass in the GLSL compiler does its job.
5361 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5364 case TGSI_OPCODE_ENDIF
:
5365 case TGSI_OPCODE_ELSE
:
5366 /* Promote the recorded level of all channels written inside the
5367 * preceding if or else block to the level above the if/else block.
5369 for (int r
= 0; r
< this->next_temp
; r
++) {
5370 for (int c
= 0; c
< 4; c
++) {
5371 if (!writes
[4 * r
+ c
])
5374 if (write_level
[4 * r
+ c
] == level
)
5375 write_level
[4 * r
+ c
] = level
-1;
5378 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5382 case TGSI_OPCODE_IF
:
5383 case TGSI_OPCODE_UIF
:
5385 /* fallthrough to default case to mark the condition as read */
5387 /* Continuing the block, clear any channels from the write array that
5388 * are read by this instruction.
5390 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5391 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5392 /* Any temporary might be read, so no dead code elimination
5393 * across this instruction.
5395 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5396 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5397 /* Clear where it's used as src. */
5398 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5399 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5400 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5401 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5403 for (int c
= 0; c
< 4; c
++) {
5404 if (src_chans
& (1 << c
))
5405 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5408 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5409 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5411 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5412 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5413 /* Any temporary might be read, so no dead code elimination
5414 * across this instruction.
5416 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5417 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5418 /* Clear where it's used as src. */
5419 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5420 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5421 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5422 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5424 for (int c
= 0; c
< 4; c
++) {
5425 if (src_chans
& (1 << c
))
5426 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5429 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5430 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5433 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5436 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5437 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5438 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5439 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5441 for (int c
= 0; c
< 4; c
++) {
5442 if (src_chans
& (1 << c
))
5443 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5446 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5447 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5449 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5450 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5451 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5456 /* If this instruction writes to a temporary, add it to the write array.
5457 * If there is already an instruction in the write array for one or more
5458 * of the channels, flag that channel write as dead.
5460 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5461 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5462 !inst
->dst
[i
].reladdr
) {
5463 for (int c
= 0; c
< 4; c
++) {
5464 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5465 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5466 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5469 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5471 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5472 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5479 /* Anything still in the write array at this point is dead code. */
5480 for (int r
= 0; r
< this->next_temp
; r
++) {
5481 for (int c
= 0; c
< 4; c
++) {
5482 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5484 inst
->dead_mask
|= (1 << c
);
5488 /* Now actually remove the instructions that are completely dead and update
5489 * the writemask of other instructions with dead channels.
5491 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5492 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5494 /* No amount of dead masks should remove memory stores */
5495 if (inst
->info
->is_store
)
5498 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5503 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5504 if (inst
->dead_mask
== WRITEMASK_XY
||
5505 inst
->dead_mask
== WRITEMASK_ZW
)
5506 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5508 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5512 ralloc_free(write_level
);
5513 ralloc_free(writes
);
5518 /* merge DFRACEXP instructions into one. */
5520 glsl_to_tgsi_visitor::merge_two_dsts(void)
5522 /* We never delete inst, but we may delete its successor. */
5523 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5524 glsl_to_tgsi_instruction
*inst2
;
5527 if (num_inst_dst_regs(inst
) != 2)
5530 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5531 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5534 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5535 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5537 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5542 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5543 while (!inst2
->is_tail_sentinel()) {
5544 if (inst
->op
== inst2
->op
&&
5545 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5546 inst
->src
[0].file
== inst2
->src
[0].file
&&
5547 inst
->src
[0].index
== inst2
->src
[0].index
&&
5548 inst
->src
[0].type
== inst2
->src
[0].type
&&
5549 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5551 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5554 if (inst2
->is_tail_sentinel()) {
5555 /* Undefined destinations are not allowed, substitute with an unused
5556 * temporary register.
5558 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5559 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5560 inst
->dst
[defined
^ 1].writemask
= 0;
5564 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5570 template <typename st_reg
>
5571 void test_indirect_access(const st_reg
& reg
, bool *has_indirect_access
)
5573 if (reg
.file
== PROGRAM_ARRAY
) {
5574 if (reg
.reladdr
|| reg
.reladdr2
|| reg
.has_index2
) {
5575 has_indirect_access
[reg
.array_id
] = true;
5577 test_indirect_access(*reg
.reladdr
, has_indirect_access
);
5579 test_indirect_access(*reg
.reladdr2
, has_indirect_access
);
5584 template <typename st_reg
>
5585 void remap_array(st_reg
& reg
, const int *array_remap_info
,
5586 const bool *has_indirect_access
)
5588 if (reg
.file
== PROGRAM_ARRAY
) {
5589 if (!has_indirect_access
[reg
.array_id
]) {
5590 reg
.file
= PROGRAM_TEMPORARY
;
5591 reg
.index
= reg
.index
+ array_remap_info
[reg
.array_id
];
5594 reg
.array_id
= array_remap_info
[reg
.array_id
];
5598 remap_array(*reg
.reladdr
, array_remap_info
, has_indirect_access
);
5601 remap_array(*reg
.reladdr2
, array_remap_info
, has_indirect_access
);
5605 /* One-dimensional arrays whose elements are only accessed directly are
5606 * replaced by an according set of temporary registers that then can become
5607 * subject to further optimization steps like copy propagation and
5611 glsl_to_tgsi_visitor::split_arrays(void)
5616 bool *has_indirect_access
= rzalloc_array(mem_ctx
, bool, next_array
+ 1);
5618 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5619 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5620 test_indirect_access(inst
->src
[j
], has_indirect_access
);
5622 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5623 test_indirect_access(inst
->tex_offsets
[j
], has_indirect_access
);
5625 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++)
5626 test_indirect_access(inst
->dst
[j
], has_indirect_access
);
5628 test_indirect_access(inst
->resource
, has_indirect_access
);
5631 unsigned array_offset
= 0;
5632 unsigned n_remaining_arrays
= 0;
5634 /* Double use: For arrays that get split this value will contain
5635 * the base index of the temporary registers this array is replaced
5636 * with. For arrays that remain it contains the new array ID.
5638 int *array_remap_info
= rzalloc_array(has_indirect_access
, int,
5641 for (unsigned i
= 1; i
<= next_array
; ++i
) {
5642 if (!has_indirect_access
[i
]) {
5643 array_remap_info
[i
] = this->next_temp
+ array_offset
;
5644 array_offset
+= array_sizes
[i
- 1];
5646 array_sizes
[n_remaining_arrays
] = array_sizes
[i
-1];
5647 array_remap_info
[i
] = ++n_remaining_arrays
;
5651 if (next_array
!= n_remaining_arrays
) {
5652 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5653 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5654 remap_array(inst
->src
[j
], array_remap_info
, has_indirect_access
);
5656 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5657 remap_array(inst
->tex_offsets
[j
], array_remap_info
, has_indirect_access
);
5659 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5660 remap_array(inst
->dst
[j
], array_remap_info
, has_indirect_access
);
5662 remap_array(inst
->resource
, array_remap_info
, has_indirect_access
);
5666 ralloc_free(has_indirect_access
);
5667 this->next_temp
+= array_offset
;
5668 next_array
= n_remaining_arrays
;
5671 /* Merges temporary registers together where possible to reduce the number of
5672 * registers needed to run a program.
5674 * Produces optimal code only after copy propagation and dead code elimination
5677 glsl_to_tgsi_visitor::merge_registers(void)
5679 class array_live_range
*arr_live_ranges
= NULL
;
5681 struct register_live_range
*reg_live_ranges
=
5682 rzalloc_array(mem_ctx
, struct register_live_range
, this->next_temp
);
5684 if (this->next_array
> 0) {
5685 arr_live_ranges
= new array_live_range
[this->next_array
];
5686 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5687 arr_live_ranges
[i
] = array_live_range(i
+1, this->array_sizes
[i
]);
5691 if (get_temp_registers_required_live_ranges(reg_live_ranges
, &this->instructions
,
5692 this->next_temp
, reg_live_ranges
,
5693 this->next_array
, arr_live_ranges
)) {
5694 struct rename_reg_pair
*renames
=
5695 rzalloc_array(reg_live_ranges
, struct rename_reg_pair
, this->next_temp
);
5696 get_temp_registers_remapping(reg_live_ranges
, this->next_temp
,
5697 reg_live_ranges
, renames
);
5698 rename_temp_registers(renames
);
5700 this->next_array
= merge_arrays(this->next_array
, this->array_sizes
,
5701 &this->instructions
, arr_live_ranges
);
5704 if (arr_live_ranges
)
5705 delete[] arr_live_ranges
;
5707 ralloc_free(reg_live_ranges
);
5710 /* Reassign indices to temporary registers by reusing unused indices created
5711 * by optimization passes. */
5713 glsl_to_tgsi_visitor::renumber_registers(void)
5717 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5718 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5720 for (i
= 0; i
< this->next_temp
; i
++) {
5721 first_writes
[i
] = -1;
5723 get_first_temp_write(first_writes
);
5725 for (i
= 0; i
< this->next_temp
; i
++) {
5726 if (first_writes
[i
] < 0) continue;
5727 if (i
!= new_index
) {
5728 renames
[i
].new_reg
= new_index
;
5729 renames
[i
].valid
= true;
5734 rename_temp_registers(renames
);
5735 this->next_temp
= new_index
;
5736 ralloc_free(renames
);
5737 ralloc_free(first_writes
);
5741 void glsl_to_tgsi_visitor::print_stats()
5743 int narray_registers
= 0;
5744 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5745 narray_registers
+= this->array_sizes
[i
];
5747 int ninstructions
= 0;
5748 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &instructions
) {
5752 simple_mtx_lock(&print_stats_mutex
);
5753 stats_log
<< next_array
<< ", "
5754 << next_temp
<< ", "
5755 << narray_registers
<< ", "
5756 << next_temp
+ narray_registers
<< ", "
5757 << ninstructions
<< "\n";
5758 simple_mtx_unlock(&print_stats_mutex
);
5761 /* ------------------------- TGSI conversion stuff -------------------------- */
5764 * Intermediate state used during shader translation.
5766 struct st_translate
{
5767 struct ureg_program
*ureg
;
5769 unsigned temps_size
;
5770 struct ureg_dst
*temps
;
5772 struct ureg_dst
*arrays
;
5773 unsigned num_temp_arrays
;
5774 struct ureg_src
*constants
;
5776 struct ureg_src
*immediates
;
5778 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5779 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5780 struct ureg_dst address
[3];
5781 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5782 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5783 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5784 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5785 struct ureg_src hw_atomics
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
5786 struct ureg_src shared_memory
;
5787 unsigned *array_sizes
;
5788 struct inout_decl
*input_decls
;
5789 unsigned num_input_decls
;
5790 struct inout_decl
*output_decls
;
5791 unsigned num_output_decls
;
5793 const ubyte
*inputMapping
;
5794 const ubyte
*outputMapping
;
5796 enum pipe_shader_type procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5798 bool tg4_component_in_swizzle
;
5801 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5803 _mesa_sysval_to_semantic(unsigned sysval
)
5807 case SYSTEM_VALUE_VERTEX_ID
:
5808 return TGSI_SEMANTIC_VERTEXID
;
5809 case SYSTEM_VALUE_INSTANCE_ID
:
5810 return TGSI_SEMANTIC_INSTANCEID
;
5811 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5812 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5813 case SYSTEM_VALUE_BASE_VERTEX
:
5814 return TGSI_SEMANTIC_BASEVERTEX
;
5815 case SYSTEM_VALUE_BASE_INSTANCE
:
5816 return TGSI_SEMANTIC_BASEINSTANCE
;
5817 case SYSTEM_VALUE_DRAW_ID
:
5818 return TGSI_SEMANTIC_DRAWID
;
5820 /* Geometry shader */
5821 case SYSTEM_VALUE_INVOCATION_ID
:
5822 return TGSI_SEMANTIC_INVOCATIONID
;
5824 /* Fragment shader */
5825 case SYSTEM_VALUE_FRAG_COORD
:
5826 return TGSI_SEMANTIC_POSITION
;
5827 case SYSTEM_VALUE_POINT_COORD
:
5828 return TGSI_SEMANTIC_PCOORD
;
5829 case SYSTEM_VALUE_FRONT_FACE
:
5830 return TGSI_SEMANTIC_FACE
;
5831 case SYSTEM_VALUE_SAMPLE_ID
:
5832 return TGSI_SEMANTIC_SAMPLEID
;
5833 case SYSTEM_VALUE_SAMPLE_POS
:
5834 return TGSI_SEMANTIC_SAMPLEPOS
;
5835 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5836 return TGSI_SEMANTIC_SAMPLEMASK
;
5837 case SYSTEM_VALUE_HELPER_INVOCATION
:
5838 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5840 /* Tessellation shader */
5841 case SYSTEM_VALUE_TESS_COORD
:
5842 return TGSI_SEMANTIC_TESSCOORD
;
5843 case SYSTEM_VALUE_VERTICES_IN
:
5844 return TGSI_SEMANTIC_VERTICESIN
;
5845 case SYSTEM_VALUE_PRIMITIVE_ID
:
5846 return TGSI_SEMANTIC_PRIMID
;
5847 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5848 return TGSI_SEMANTIC_TESSOUTER
;
5849 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5850 return TGSI_SEMANTIC_TESSINNER
;
5852 /* Compute shader */
5853 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5854 return TGSI_SEMANTIC_THREAD_ID
;
5855 case SYSTEM_VALUE_WORK_GROUP_ID
:
5856 return TGSI_SEMANTIC_BLOCK_ID
;
5857 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5858 return TGSI_SEMANTIC_GRID_SIZE
;
5859 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5860 return TGSI_SEMANTIC_BLOCK_SIZE
;
5862 /* ARB_shader_ballot */
5863 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5864 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5865 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5866 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5867 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5868 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5869 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5870 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5871 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5872 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5873 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5874 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5875 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5876 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5879 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5880 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5881 case SYSTEM_VALUE_VERTEX_CNT
:
5882 case SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
:
5883 case SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
:
5884 case SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
:
5885 case SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
:
5887 assert(!"Unexpected SYSTEM_VALUE_ enum");
5888 return TGSI_SEMANTIC_COUNT
;
5893 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5895 static struct ureg_src
5896 emit_immediate(struct st_translate
*t
,
5897 gl_constant_value values
[4],
5898 GLenum type
, int size
)
5900 struct ureg_program
*ureg
= t
->ureg
;
5904 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5906 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5908 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5909 case GL_UNSIGNED_INT64_ARB
:
5910 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5912 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5913 case GL_UNSIGNED_INT
:
5915 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5917 assert(!"should not get here - type must be float, int, uint, or bool");
5918 return ureg_src_undef();
5923 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5925 static struct ureg_dst
5926 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5932 case PROGRAM_UNDEFINED
:
5933 return ureg_dst_undef();
5935 case PROGRAM_TEMPORARY
:
5936 /* Allocate space for temporaries on demand. */
5937 if (index
>= t
->temps_size
) {
5938 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5940 t
->temps
= (struct ureg_dst
*)
5942 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5944 return ureg_dst_undef();
5946 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5947 t
->temps_size
+= inc
;
5950 if (ureg_dst_is_undef(t
->temps
[index
]))
5951 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5953 return t
->temps
[index
];
5956 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5957 array
= array_id
- 1;
5959 if (ureg_dst_is_undef(t
->arrays
[array
]))
5960 t
->arrays
[array
] = ureg_DECL_array_temporary(
5961 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5963 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5965 case PROGRAM_OUTPUT
:
5967 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5968 assert(index
< 2 * FRAG_RESULT_MAX
);
5969 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5970 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5971 assert(index
< VARYING_SLOT_TESS_MAX
);
5973 assert(index
< VARYING_SLOT_MAX
);
5975 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5976 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5977 return t
->outputs
[t
->outputMapping
[index
]];
5980 struct inout_decl
*decl
=
5981 find_inout_array(t
->output_decls
,
5982 t
->num_output_decls
, array_id
);
5983 unsigned mesa_index
= decl
->mesa_index
;
5984 int slot
= t
->outputMapping
[mesa_index
];
5986 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5988 struct ureg_dst dst
= t
->outputs
[slot
];
5989 dst
.ArrayID
= array_id
;
5990 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5993 case PROGRAM_ADDRESS
:
5994 return t
->address
[index
];
5997 assert(!"unknown dst register file");
5998 return ureg_dst_undef();
6002 static struct ureg_src
6003 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
6005 static struct ureg_src
6006 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
6007 unsigned addr_index
)
6009 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
6010 return ureg_src(t
->address
[addr_index
]);
6012 return translate_src(t
, reladdr
);
6016 * Create a TGSI ureg_dst register from an st_dst_reg.
6018 static struct ureg_dst
6019 translate_dst(struct st_translate
*t
,
6020 const st_dst_reg
*dst_reg
,
6023 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
6026 if (dst
.File
== TGSI_FILE_NULL
)
6029 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
6032 dst
= ureg_saturate(dst
);
6034 if (dst_reg
->reladdr
!= NULL
) {
6035 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
6036 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
6039 if (dst_reg
->has_index2
) {
6040 if (dst_reg
->reladdr2
)
6041 dst
= ureg_dst_dimension_indirect(dst
,
6042 translate_addr(t
, dst_reg
->reladdr2
, 1),
6045 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
6052 * Create a TGSI ureg_src register from an st_src_reg.
6054 static struct ureg_src
6055 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
6057 struct ureg_src src
;
6058 int index
= src_reg
->index
;
6059 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
6061 switch (src_reg
->file
) {
6062 case PROGRAM_UNDEFINED
:
6063 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6066 case PROGRAM_TEMPORARY
:
6068 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
,
6069 src_reg
->array_id
));
6072 case PROGRAM_OUTPUT
: {
6073 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
,
6075 assert(dst
.WriteMask
!= 0);
6076 unsigned shift
= ffs(dst
.WriteMask
) - 1;
6077 src
= ureg_swizzle(ureg_src(dst
),
6081 MIN2(shift
+ 3, 3));
6085 case PROGRAM_UNIFORM
:
6086 assert(src_reg
->index
>= 0);
6087 src
= src_reg
->index
< t
->num_constants
?
6088 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6090 case PROGRAM_STATE_VAR
:
6091 case PROGRAM_CONSTANT
: /* ie, immediate */
6092 if (src_reg
->has_index2
)
6093 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
6095 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
6096 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6099 case PROGRAM_IMMEDIATE
:
6100 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
6101 src
= t
->immediates
[src_reg
->index
];
6105 /* GLSL inputs are 64-bit containers, so we have to
6106 * map back to the original index and add the offset after
6108 index
-= double_reg2
;
6109 if (!src_reg
->array_id
) {
6110 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
6111 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
6112 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
6115 struct inout_decl
*decl
= find_inout_array(t
->input_decls
,
6118 unsigned mesa_index
= decl
->mesa_index
;
6119 int slot
= t
->inputMapping
[mesa_index
];
6121 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
6123 src
= t
->inputs
[slot
];
6124 src
.ArrayID
= src_reg
->array_id
;
6125 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
6129 case PROGRAM_ADDRESS
:
6130 src
= ureg_src(t
->address
[src_reg
->index
]);
6133 case PROGRAM_SYSTEM_VALUE
:
6134 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
6135 src
= t
->systemValues
[src_reg
->index
];
6138 case PROGRAM_HW_ATOMIC
:
6139 src
= ureg_src_array_register(TGSI_FILE_HW_ATOMIC
, src_reg
->index
,
6144 assert(!"unknown src register file");
6145 return ureg_src_undef();
6148 if (src_reg
->has_index2
) {
6149 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6150 * and UBO constant buffers (buffer, position).
6152 if (src_reg
->reladdr2
)
6153 src
= ureg_src_dimension_indirect(src
,
6154 translate_addr(t
, src_reg
->reladdr2
, 1),
6157 src
= ureg_src_dimension(src
, src_reg
->index2D
);
6160 src
= ureg_swizzle(src
,
6161 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
6162 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
6163 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
6164 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
6167 src
= ureg_abs(src
);
6169 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
6170 src
= ureg_negate(src
);
6172 if (src_reg
->reladdr
!= NULL
) {
6173 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
6174 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
6180 static struct tgsi_texture_offset
6181 translate_tex_offset(struct st_translate
*t
,
6182 const st_src_reg
*in_offset
)
6184 struct tgsi_texture_offset offset
;
6185 struct ureg_src src
= translate_src(t
, in_offset
);
6187 offset
.File
= src
.File
;
6188 offset
.Index
= src
.Index
;
6189 offset
.SwizzleX
= src
.SwizzleX
;
6190 offset
.SwizzleY
= src
.SwizzleY
;
6191 offset
.SwizzleZ
= src
.SwizzleZ
;
6194 assert(!src
.Indirect
);
6195 assert(!src
.DimIndirect
);
6196 assert(!src
.Dimension
);
6197 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
6198 assert(!src
.Negate
);
6204 compile_tgsi_instruction(struct st_translate
*t
,
6205 const glsl_to_tgsi_instruction
*inst
)
6207 struct ureg_program
*ureg
= t
->ureg
;
6209 struct ureg_dst dst
[2];
6210 struct ureg_src src
[4];
6211 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
6215 enum tgsi_texture_type tex_target
= TGSI_TEXTURE_BUFFER
;
6217 num_dst
= num_inst_dst_regs(inst
);
6218 num_src
= num_inst_src_regs(inst
);
6220 for (i
= 0; i
< num_dst
; i
++)
6221 dst
[i
] = translate_dst(t
,
6225 for (i
= 0; i
< num_src
; i
++)
6226 src
[i
] = translate_src(t
, &inst
->src
[i
]);
6229 case TGSI_OPCODE_BGNLOOP
:
6230 case TGSI_OPCODE_ELSE
:
6231 case TGSI_OPCODE_ENDLOOP
:
6232 case TGSI_OPCODE_IF
:
6233 case TGSI_OPCODE_UIF
:
6234 assert(num_dst
== 0);
6235 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
6238 case TGSI_OPCODE_TEX
:
6239 case TGSI_OPCODE_TEX_LZ
:
6240 case TGSI_OPCODE_TXB
:
6241 case TGSI_OPCODE_TXD
:
6242 case TGSI_OPCODE_TXL
:
6243 case TGSI_OPCODE_TXP
:
6244 case TGSI_OPCODE_TXQ
:
6245 case TGSI_OPCODE_TXQS
:
6246 case TGSI_OPCODE_TXF
:
6247 case TGSI_OPCODE_TXF_LZ
:
6248 case TGSI_OPCODE_TEX2
:
6249 case TGSI_OPCODE_TXB2
:
6250 case TGSI_OPCODE_TXL2
:
6251 case TGSI_OPCODE_TG4
:
6252 case TGSI_OPCODE_LODQ
:
6253 case TGSI_OPCODE_SAMP2HND
:
6254 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
6255 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
6256 if (t
->tg4_component_in_swizzle
&& inst
->op
== TGSI_OPCODE_TG4
)
6257 src
[num_src
].SwizzleX
= inst
->gather_component
;
6259 /* Bindless samplers. */
6260 src
[num_src
] = translate_src(t
, &inst
->resource
);
6262 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
6263 if (inst
->resource
.reladdr
)
6265 ureg_src_indirect(src
[num_src
],
6266 translate_addr(t
, inst
->resource
.reladdr
, 2));
6268 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
6269 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
6271 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6277 st_translate_texture_type(inst
->tex_type
),
6278 texoffsets
, inst
->tex_offset_num_offset
,
6282 case TGSI_OPCODE_RESQ
:
6283 case TGSI_OPCODE_LOAD
:
6284 case TGSI_OPCODE_ATOMUADD
:
6285 case TGSI_OPCODE_ATOMXCHG
:
6286 case TGSI_OPCODE_ATOMCAS
:
6287 case TGSI_OPCODE_ATOMAND
:
6288 case TGSI_OPCODE_ATOMOR
:
6289 case TGSI_OPCODE_ATOMXOR
:
6290 case TGSI_OPCODE_ATOMUMIN
:
6291 case TGSI_OPCODE_ATOMUMAX
:
6292 case TGSI_OPCODE_ATOMIMIN
:
6293 case TGSI_OPCODE_ATOMIMAX
:
6294 case TGSI_OPCODE_ATOMFADD
:
6295 case TGSI_OPCODE_IMG2HND
:
6296 case TGSI_OPCODE_ATOMINC_WRAP
:
6297 case TGSI_OPCODE_ATOMDEC_WRAP
:
6298 for (i
= num_src
- 1; i
>= 0; i
--)
6299 src
[i
+ 1] = src
[i
];
6301 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6302 src
[0] = t
->shared_memory
;
6303 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6304 src
[0] = t
->buffers
[inst
->resource
.index
];
6305 } else if (inst
->resource
.file
== PROGRAM_HW_ATOMIC
) {
6306 src
[0] = translate_src(t
, &inst
->resource
);
6307 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
6308 assert(inst
->resource
.has_index2
);
6309 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
6311 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
6312 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6313 src
[0] = t
->images
[inst
->resource
.index
];
6315 /* Bindless images. */
6316 src
[0] = translate_src(t
, &inst
->resource
);
6318 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6320 if (inst
->resource
.reladdr
)
6321 src
[0] = ureg_src_indirect(src
[0],
6322 translate_addr(t
, inst
->resource
.reladdr
, 2));
6323 assert(src
[0].File
!= TGSI_FILE_NULL
);
6324 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6325 inst
->buffer_access
,
6326 tex_target
, inst
->image_format
);
6329 case TGSI_OPCODE_STORE
:
6330 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6331 dst
[0] = ureg_dst(t
->shared_memory
);
6332 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6333 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6335 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6336 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6338 /* Bindless images. */
6339 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6341 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6343 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6344 if (inst
->resource
.reladdr
)
6345 dst
[0] = ureg_dst_indirect(dst
[0],
6346 translate_addr(t
, inst
->resource
.reladdr
, 2));
6347 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6348 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6349 inst
->buffer_access
,
6350 tex_target
, inst
->image_format
);
6357 src
, num_src
, inst
->precise
);
6362 /* Invert SamplePos.y when rendering to the default framebuffer. */
6364 emit_samplepos_adjustment(struct st_translate
*t
, int wpos_y_transform
)
6366 struct ureg_program
*ureg
= t
->ureg
;
6368 assert(wpos_y_transform
>= 0);
6369 struct ureg_src trans_const
= ureg_DECL_constant(ureg
, wpos_y_transform
);
6370 struct ureg_src samplepos_sysval
= t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
];
6371 struct ureg_dst samplepos_flipped
= ureg_DECL_temporary(ureg
);
6372 struct ureg_dst is_fbo
= ureg_DECL_temporary(ureg
);
6374 ureg_ADD(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6375 ureg_imm1f(ureg
, 1), ureg_negate(samplepos_sysval
));
6377 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6378 ureg_FSEQ(ureg
, ureg_writemask(is_fbo
, TGSI_WRITEMASK_Y
),
6379 ureg_scalar(trans_const
, TGSI_SWIZZLE_X
), ureg_imm1f(ureg
, 1));
6380 ureg_UCMP(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6381 ureg_src(is_fbo
), samplepos_sysval
, ureg_src(samplepos_flipped
));
6382 ureg_MOV(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_X
),
6385 /* Use the result in place of the system value. */
6386 t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
] = ureg_src(samplepos_flipped
);
6391 * Emit the TGSI instructions for inverting and adjusting WPOS.
6392 * This code is unavoidable because it also depends on whether
6393 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6396 emit_wpos_adjustment(struct gl_context
*ctx
,
6397 struct st_translate
*t
,
6398 int wpos_transform_const
,
6400 GLfloat adjX
, GLfloat adjY
[2])
6402 struct ureg_program
*ureg
= t
->ureg
;
6404 assert(wpos_transform_const
>= 0);
6406 /* Fragment program uses fragment position input.
6407 * Need to replace instances of INPUT[WPOS] with temp T
6408 * where T = INPUT[WPOS] is inverted by Y.
6410 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6411 struct ureg_dst wpos_temp
= ureg_DECL_temporary(ureg
);
6412 struct ureg_src
*wpos
=
6413 ctx
->Const
.GLSLFragCoordIsSysVal
?
6414 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6415 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6416 struct ureg_src wpos_input
= *wpos
;
6418 /* First, apply the coordinate shift: */
6419 if (adjX
|| adjY
[0] || adjY
[1]) {
6420 if (adjY
[0] != adjY
[1]) {
6421 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6422 * depending on whether inversion is actually going to be applied
6423 * or not, which is determined by testing against the inversion
6424 * state variable used below, which will be either +1 or -1.
6426 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6428 ureg_CMP(ureg
, adj_temp
,
6429 ureg_scalar(wpostrans
, invert
? 2 : 0),
6430 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6431 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6432 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6434 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6435 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6437 wpos_input
= ureg_src(wpos_temp
);
6439 /* MOV wpos_temp, input[wpos]
6441 ureg_MOV(ureg
, wpos_temp
, wpos_input
);
6444 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6445 * inversion/identity, or the other way around if we're drawing to an FBO.
6448 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6451 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6453 ureg_scalar(wpostrans
, 0),
6454 ureg_scalar(wpostrans
, 1));
6456 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6459 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6461 ureg_scalar(wpostrans
, 2),
6462 ureg_scalar(wpostrans
, 3));
6465 /* Use wpos_temp as position input from here on:
6467 *wpos
= ureg_src(wpos_temp
);
6472 * Emit fragment position/ooordinate code.
6475 emit_wpos(struct st_context
*st
,
6476 struct st_translate
*t
,
6477 const struct gl_program
*program
,
6478 struct ureg_program
*ureg
,
6479 int wpos_transform_const
)
6481 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6482 GLfloat adjX
= 0.0f
;
6483 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6484 boolean invert
= FALSE
;
6486 /* Query the pixel center conventions supported by the pipe driver and set
6487 * adjX, adjY to help out if it cannot handle the requested one internally.
6489 * The bias of the y-coordinate depends on whether y-inversion takes place
6490 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6491 * drawing to an FBO (causes additional inversion), and whether the pipe
6492 * driver origin and the requested origin differ (the latter condition is
6493 * stored in the 'invert' variable).
6495 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6497 * center shift only:
6502 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6503 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6504 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6505 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6507 * inversion and center shift:
6508 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6509 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6510 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6511 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6513 if (program
->info
.fs
.origin_upper_left
) {
6514 /* Fragment shader wants origin in upper-left */
6515 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6516 /* the driver supports upper-left origin */
6518 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6519 /* the driver supports lower-left origin, need to invert Y */
6520 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6521 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6528 /* Fragment shader wants origin in lower-left */
6529 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6530 /* the driver supports lower-left origin */
6531 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6532 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6533 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6534 /* the driver supports upper-left origin, need to invert Y */
6540 if (program
->info
.fs
.pixel_center_integer
) {
6541 /* Fragment shader wants pixel center integer */
6542 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6543 /* the driver supports pixel center integer */
6545 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6546 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6548 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6549 /* the driver supports pixel center half integer, need to bias X,Y */
6558 /* Fragment shader wants pixel center half integer */
6559 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6560 /* the driver supports pixel center half integer */
6562 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6563 /* the driver supports pixel center integer, need to bias X,Y */
6564 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6565 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6566 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6572 /* we invert after adjustment so that we avoid the MOV to temporary,
6573 * and reuse the adjustment ADD instead */
6574 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6578 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6579 * TGSI uses +1 for front, -1 for back.
6580 * This function converts the TGSI value to the GL value. Simply clamping/
6581 * saturating the value to [0,1] does the job.
6584 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6586 struct ureg_program
*ureg
= t
->ureg
;
6587 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6588 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6590 if (ctx
->Const
.NativeIntegers
) {
6591 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6594 /* MOV_SAT face_temp, input[face] */
6595 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6598 /* Use face_temp as face input from here on: */
6599 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6603 emit_compute_block_size(const struct gl_program
*prog
,
6604 struct ureg_program
*ureg
) {
6605 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6606 prog
->info
.cs
.local_size
[0]);
6607 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6608 prog
->info
.cs
.local_size
[1]);
6609 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6610 prog
->info
.cs
.local_size
[2]);
6613 struct sort_inout_decls
{
6614 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6615 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6618 const ubyte
*mapping
;
6621 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6623 * This is for the benefit of older drivers which are broken when the
6624 * declarations aren't sorted in this way.
6627 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6629 const ubyte mapping
[])
6631 sort_inout_decls sorter
;
6632 sorter
.mapping
= mapping
;
6633 std::sort(decls
, decls
+ count
, sorter
);
6636 static enum tgsi_interpolate_mode
6637 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6639 switch (glsl_qual
) {
6640 case INTERP_MODE_NONE
:
6641 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6642 return TGSI_INTERPOLATE_COLOR
;
6643 return TGSI_INTERPOLATE_PERSPECTIVE
;
6644 case INTERP_MODE_SMOOTH
:
6645 return TGSI_INTERPOLATE_PERSPECTIVE
;
6646 case INTERP_MODE_FLAT
:
6647 return TGSI_INTERPOLATE_CONSTANT
;
6648 case INTERP_MODE_NOPERSPECTIVE
:
6649 return TGSI_INTERPOLATE_LINEAR
;
6651 assert(0 && "unexpected interp mode in st_translate_interp()");
6652 return TGSI_INTERPOLATE_PERSPECTIVE
;
6657 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6658 * \param program the program to translate
6659 * \param numInputs number of input registers used
6660 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6662 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6663 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6665 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6666 * \param numOutputs number of output registers used
6667 * \param outputMapping maps Mesa fragment program outputs to TGSI
6669 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6670 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6673 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6675 extern "C" enum pipe_error
6676 st_translate_program(
6677 struct gl_context
*ctx
,
6678 enum pipe_shader_type procType
,
6679 struct ureg_program
*ureg
,
6680 glsl_to_tgsi_visitor
*program
,
6681 const struct gl_program
*proginfo
,
6683 const ubyte inputMapping
[],
6684 const ubyte inputSlotToAttr
[],
6685 const ubyte inputSemanticName
[],
6686 const ubyte inputSemanticIndex
[],
6687 const ubyte interpMode
[],
6689 const ubyte outputMapping
[],
6690 const ubyte outputSemanticName
[],
6691 const ubyte outputSemanticIndex
[])
6693 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6694 struct st_translate
*t
;
6696 struct gl_program_constants
*frag_const
=
6697 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6698 enum pipe_error ret
= PIPE_OK
;
6700 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6701 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6703 ASSERT_BITFIELD_SIZE(st_src_reg
, type
, GLSL_TYPE_ERROR
);
6704 ASSERT_BITFIELD_SIZE(st_dst_reg
, type
, GLSL_TYPE_ERROR
);
6705 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_type
, GLSL_TYPE_ERROR
);
6706 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
, PIPE_FORMAT_COUNT
);
6707 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_target
,
6708 (gl_texture_index
) (NUM_TEXTURE_TARGETS
- 1));
6709 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
,
6710 (enum pipe_format
) (PIPE_FORMAT_COUNT
- 1));
6711 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, op
,
6712 (enum tgsi_opcode
) (TGSI_OPCODE_LAST
- 1));
6714 t
= CALLOC_STRUCT(st_translate
);
6716 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6720 t
->procType
= procType
;
6721 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6722 t
->tg4_component_in_swizzle
= screen
->get_param(screen
, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
);
6723 t
->inputMapping
= inputMapping
;
6724 t
->outputMapping
= outputMapping
;
6726 t
->num_temp_arrays
= program
->next_array
;
6727 if (t
->num_temp_arrays
)
6728 t
->arrays
= (struct ureg_dst
*)
6729 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6732 * Declare input attributes.
6735 case PIPE_SHADER_FRAGMENT
:
6736 case PIPE_SHADER_GEOMETRY
:
6737 case PIPE_SHADER_TESS_EVAL
:
6738 case PIPE_SHADER_TESS_CTRL
:
6739 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6741 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6742 struct inout_decl
*decl
= &program
->inputs
[i
];
6743 unsigned slot
= inputMapping
[decl
->mesa_index
];
6744 struct ureg_src src
;
6745 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6747 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6748 if (tgsi_usage_mask
== 1)
6749 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6750 else if (tgsi_usage_mask
== 2)
6751 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6753 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6756 enum tgsi_interpolate_mode interp_mode
= TGSI_INTERPOLATE_CONSTANT
;
6757 enum tgsi_interpolate_loc interp_location
= TGSI_INTERPOLATE_LOC_CENTER
;
6758 if (procType
== PIPE_SHADER_FRAGMENT
) {
6760 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6761 (enum tgsi_interpolate_mode
) interpMode
[slot
] :
6762 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6764 interp_location
= (enum tgsi_interpolate_loc
) decl
->interp_loc
;
6767 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6768 (enum tgsi_semantic
) inputSemanticName
[slot
],
6769 inputSemanticIndex
[slot
],
6770 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6771 decl
->array_id
, decl
->size
);
6773 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6774 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6775 /* The ArrayID is set up in dst_register */
6776 t
->inputs
[slot
+ j
] = src
;
6777 t
->inputs
[slot
+ j
].ArrayID
= 0;
6778 t
->inputs
[slot
+ j
].Index
+= j
;
6783 case PIPE_SHADER_VERTEX
:
6784 for (i
= 0; i
< numInputs
; i
++) {
6785 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6788 case PIPE_SHADER_COMPUTE
:
6795 * Declare output attributes.
6798 case PIPE_SHADER_FRAGMENT
:
6799 case PIPE_SHADER_COMPUTE
:
6801 case PIPE_SHADER_GEOMETRY
:
6802 case PIPE_SHADER_TESS_EVAL
:
6803 case PIPE_SHADER_TESS_CTRL
:
6804 case PIPE_SHADER_VERTEX
:
6805 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6807 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6808 struct inout_decl
*decl
= &program
->outputs
[i
];
6809 unsigned slot
= outputMapping
[decl
->mesa_index
];
6810 struct ureg_dst dst
;
6811 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6813 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6814 if (tgsi_usage_mask
== 1)
6815 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6816 else if (tgsi_usage_mask
== 2)
6817 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6819 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6822 dst
= ureg_DECL_output_layout(ureg
,
6823 (enum tgsi_semantic
) outputSemanticName
[slot
],
6824 outputSemanticIndex
[slot
],
6825 decl
->gs_out_streams
,
6826 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
, decl
->invariant
);
6827 dst
.Invariant
= decl
->invariant
;
6828 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6829 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6830 /* The ArrayID is set up in dst_register */
6831 t
->outputs
[slot
+ j
] = dst
;
6832 t
->outputs
[slot
+ j
].ArrayID
= 0;
6833 t
->outputs
[slot
+ j
].Index
+= j
;
6834 t
->outputs
[slot
+ j
].Invariant
= decl
->invariant
;
6843 if (procType
== PIPE_SHADER_FRAGMENT
) {
6844 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6845 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6846 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6848 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6849 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6852 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6853 /* Must do this after setting up t->inputs. */
6854 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6855 program
->wpos_transform_const
);
6858 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6859 emit_face_var(ctx
, t
);
6861 for (i
= 0; i
< numOutputs
; i
++) {
6862 switch (outputSemanticName
[i
]) {
6863 case TGSI_SEMANTIC_POSITION
:
6864 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6865 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6866 outputSemanticIndex
[i
]);
6867 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6869 case TGSI_SEMANTIC_STENCIL
:
6870 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6871 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6872 outputSemanticIndex
[i
]);
6873 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6875 case TGSI_SEMANTIC_COLOR
:
6876 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6877 TGSI_SEMANTIC_COLOR
,
6878 outputSemanticIndex
[i
]);
6880 case TGSI_SEMANTIC_SAMPLEMASK
:
6881 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6882 TGSI_SEMANTIC_SAMPLEMASK
,
6883 outputSemanticIndex
[i
]);
6884 /* TODO: If we ever support more than 32 samples, this will have
6885 * to become an array.
6887 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6890 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6891 ret
= PIPE_ERROR_BAD_INPUT
;
6896 else if (procType
== PIPE_SHADER_VERTEX
) {
6897 for (i
= 0; i
< numOutputs
; i
++) {
6898 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6899 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6901 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6902 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6903 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6908 if (procType
== PIPE_SHADER_COMPUTE
) {
6909 emit_compute_block_size(proginfo
, ureg
);
6912 /* Declare address register.
6914 if (program
->num_address_regs
> 0) {
6915 assert(program
->num_address_regs
<= 3);
6916 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6917 t
->address
[i
] = ureg_DECL_address(ureg
);
6920 /* Declare misc input registers
6923 GLbitfield64 sysInputs
= proginfo
->info
.system_values_read
;
6925 for (i
= 0; sysInputs
; i
++) {
6926 if (sysInputs
& (1ull << i
)) {
6927 enum tgsi_semantic semName
= _mesa_sysval_to_semantic(i
);
6929 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6931 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6932 semName
== TGSI_SEMANTIC_VERTEXID
) {
6933 /* From Gallium perspective, these system values are always
6934 * integer, and require native integer support. However, if
6935 * native integer is supported on the vertex stage but not the
6936 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6937 * assumes these system values are floats. To resolve the
6938 * inconsistency, we insert a U2F.
6940 struct st_context
*st
= st_context(ctx
);
6941 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6942 assert(procType
== PIPE_SHADER_VERTEX
);
6943 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6945 if (!ctx
->Const
.NativeIntegers
) {
6946 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6947 ureg_U2F(t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
),
6948 t
->systemValues
[i
]);
6949 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6953 if (procType
== PIPE_SHADER_FRAGMENT
&&
6954 semName
== TGSI_SEMANTIC_POSITION
)
6955 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6956 program
->wpos_transform_const
);
6958 if (procType
== PIPE_SHADER_FRAGMENT
&&
6959 semName
== TGSI_SEMANTIC_SAMPLEPOS
)
6960 emit_samplepos_adjustment(t
, program
->wpos_transform_const
);
6962 sysInputs
&= ~(1ull << i
);
6967 t
->array_sizes
= program
->array_sizes
;
6968 t
->input_decls
= program
->inputs
;
6969 t
->num_input_decls
= program
->num_inputs
;
6970 t
->output_decls
= program
->outputs
;
6971 t
->num_output_decls
= program
->num_outputs
;
6973 /* Emit constants and uniforms. TGSI uses a single index space for these,
6974 * so we put all the translated regs in t->constants.
6976 if (proginfo
->Parameters
) {
6977 t
->constants
= (struct ureg_src
*)
6978 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6979 if (t
->constants
== NULL
) {
6980 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6983 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6985 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6986 unsigned pvo
= proginfo
->Parameters
->ParameterValueOffset
[i
];
6988 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6989 case PROGRAM_STATE_VAR
:
6990 case PROGRAM_UNIFORM
:
6991 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6994 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6995 * addressing of the const buffer.
6996 * FIXME: Be smarter and recognize param arrays:
6997 * indirect addressing is only valid within the referenced
7000 case PROGRAM_CONSTANT
:
7001 if (program
->indirect_addr_consts
)
7002 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
7004 t
->constants
[i
] = emit_immediate(t
,
7005 proginfo
->Parameters
->ParameterValues
+ pvo
,
7006 proginfo
->Parameters
->Parameters
[i
].DataType
,
7015 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
7016 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
7017 unsigned num_const_vecs
= (size
+ 15) / 16;
7018 unsigned first
, last
;
7019 assert(num_const_vecs
> 0);
7021 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
7022 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
7025 /* Emit immediate values.
7027 t
->immediates
= (struct ureg_src
*)
7028 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
7029 if (t
->immediates
== NULL
) {
7030 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
7033 t
->num_immediates
= program
->num_immediates
;
7036 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
7037 assert(i
< program
->num_immediates
);
7038 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
7040 assert(i
== program
->num_immediates
);
7042 /* texture samplers */
7043 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
7044 if (program
->samplers_used
& (1u << i
)) {
7045 enum tgsi_return_type type
=
7046 st_translate_texture_type(program
->sampler_types
[i
]);
7048 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
7050 ureg_DECL_sampler_view(ureg
, i
, program
->sampler_targets
[i
],
7051 type
, type
, type
, type
);
7055 /* Declare atomic and shader storage buffers. */
7057 struct gl_program
*prog
= program
->prog
;
7059 if (!st_context(ctx
)->has_hw_atomics
) {
7060 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
7061 unsigned index
= (prog
->info
.num_ssbos
+
7062 prog
->sh
.AtomicBuffers
[i
]->Binding
);
7063 assert(prog
->sh
.AtomicBuffers
[i
]->Binding
<
7064 frag_const
->MaxAtomicBuffers
);
7065 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
7068 for (i
= 0; i
< program
->num_atomics
; i
++) {
7069 struct hwatomic_decl
*ainfo
= &program
->atomic_info
[i
];
7070 gl_uniform_storage
*uni_storage
= &prog
->sh
.data
->UniformStorage
[ainfo
->location
];
7071 int base
= uni_storage
->offset
/ ATOMIC_COUNTER_SIZE
;
7072 ureg_DECL_hw_atomic(ureg
, base
, base
+ ainfo
->size
- 1, ainfo
->binding
,
7077 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
7078 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
7079 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
7083 if (program
->use_shared_memory
)
7084 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
7086 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
7087 if (program
->images_used
& (1 << i
)) {
7088 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
7089 program
->image_targets
[i
],
7090 program
->image_formats
[i
],
7091 program
->image_wr
[i
],
7096 /* Emit each instruction in turn:
7098 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
7099 compile_tgsi_instruction(t
, inst
);
7101 /* Set the next shader stage hint for VS and TES. */
7103 case PIPE_SHADER_VERTEX
:
7104 case PIPE_SHADER_TESS_EVAL
:
7105 if (program
->shader_program
->SeparateShader
)
7108 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
7109 if (program
->shader_program
->_LinkedShaders
[i
]) {
7110 ureg_set_next_shader_processor(
7111 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
7117 ; /* nothing - silence compiler warning */
7125 t
->num_constants
= 0;
7126 free(t
->immediates
);
7127 t
->num_immediates
= 0;
7133 /* ----------------------------- End TGSI code ------------------------------ */
7137 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7138 * generating Mesa IR.
7140 static struct gl_program
*
7141 get_mesa_program_tgsi(struct gl_context
*ctx
,
7142 struct gl_shader_program
*shader_program
,
7143 struct gl_linked_shader
*shader
)
7145 glsl_to_tgsi_visitor
* v
;
7146 struct gl_program
*prog
;
7147 struct gl_shader_compiler_options
*options
=
7148 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
7149 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7150 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
7151 unsigned skip_merge_registers
;
7153 validate_ir_tree(shader
->ir
);
7155 prog
= shader
->Program
;
7157 prog
->Parameters
= _mesa_new_parameter_list();
7158 v
= new glsl_to_tgsi_visitor();
7161 v
->shader_program
= shader_program
;
7163 v
->options
= options
;
7164 v
->native_integers
= ctx
->Const
.NativeIntegers
;
7166 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
7167 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
7168 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
7169 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
7170 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
7171 PIPE_CAP_TGSI_TEX_TXF_LZ
);
7172 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
7174 v
->tg4_component_in_swizzle
= pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
);
7175 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
7176 _mesa_key_pointer_equal
);
7177 skip_merge_registers
=
7178 pscreen
->get_shader_param(pscreen
, ptarget
,
7179 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
7181 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
7184 /* Remove reads from output registers. */
7185 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
7186 lower_output_reads(shader
->Stage
, shader
->ir
);
7188 /* Emit intermediate IR for main(). */
7189 visit_exec_list(shader
->ir
, v
);
7192 /* Print out some information (for debugging purposes) used by the
7193 * optimization passes. */
7196 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7197 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7198 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7199 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7201 for (i
= 0; i
< v
->next_temp
; i
++) {
7202 first_writes
[i
] = -1;
7203 first_reads
[i
] = -1;
7204 last_writes
[i
] = -1;
7207 v
->get_first_temp_read(first_reads
);
7208 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
7209 v
->get_last_temp_write(last_writes
);
7210 for (i
= 0; i
< v
->next_temp
; i
++)
7211 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
7215 ralloc_free(first_writes
);
7216 ralloc_free(first_reads
);
7217 ralloc_free(last_writes
);
7218 ralloc_free(last_reads
);
7222 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7224 v
->copy_propagate();
7226 while (v
->eliminate_dead_code());
7228 v
->merge_two_dsts();
7230 if (!skip_merge_registers
) {
7232 v
->copy_propagate();
7233 while (v
->eliminate_dead_code());
7235 v
->merge_registers();
7236 v
->copy_propagate();
7237 while (v
->eliminate_dead_code());
7240 v
->renumber_registers();
7242 /* Write the END instruction. */
7243 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
7245 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
7247 _mesa_log("GLSL IR for linked %s program %d:\n",
7248 _mesa_shader_stage_to_string(shader
->Stage
),
7249 shader_program
->Name
);
7250 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
7254 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
7256 _mesa_copy_linked_program_data(shader_program
, shader
);
7258 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS
)) {
7259 mark_array_io(v
->inputs
, v
->num_inputs
,
7260 &prog
->info
.inputs_read
,
7261 prog
->DualSlotInputs
,
7262 &prog
->info
.patch_inputs_read
);
7264 mark_array_io(v
->outputs
, v
->num_outputs
,
7265 &prog
->info
.outputs_written
, 0ULL,
7266 &prog
->info
.patch_outputs_written
);
7268 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
7269 &prog
->info
.inputs_read
,
7270 prog
->DualSlotInputs
,
7271 &prog
->info
.patch_inputs_read
);
7272 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
7273 &prog
->info
.outputs_written
, 0ULL,
7274 &prog
->info
.patch_outputs_written
);
7277 count_resources(v
, prog
);
7279 /* The GLSL IR won't be needed anymore. */
7280 ralloc_free(shader
->ir
);
7283 /* This must be done before the uniform storage is associated. */
7284 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
7285 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
7286 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
) ||
7287 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_SAMPLE_POS
))) {
7288 static const gl_state_index16 wposTransformState
[STATE_LENGTH
] = {
7289 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
7292 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
7293 wposTransformState
);
7296 /* Avoid reallocation of the program parameter list, because the uniform
7297 * storage is only associated with the original parameter list.
7298 * This should be enough for Bitmap and DrawPixels constants.
7300 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
7302 /* This has to be done last. Any operation the can cause
7303 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7304 * program constant) has to happen before creating this linkage.
7306 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
);
7307 if (!shader_program
->data
->LinkStatus
) {
7308 free_glsl_to_tgsi_visitor(v
);
7309 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7313 st_program(prog
)->glsl_to_tgsi
= v
;
7315 PRINT_STATS(v
->print_stats());
7320 /* See if there are unsupported control flow statements. */
7321 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
7323 const struct gl_shader_compiler_options
*options
;
7325 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
7331 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
7333 /* Other functions are skipped (same as glsl_to_tgsi). */
7334 if (strcmp(ir
->name
, "main") == 0)
7335 return visit_continue
;
7337 return visit_continue_with_parent
;
7340 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
7342 if (!ir
->callee
->is_intrinsic()) {
7343 unsupported
= true; /* it's a function call */
7346 return visit_continue
;
7349 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7351 if (options
->EmitNoMainReturn
) {
7355 return visit_continue
;
7362 has_unsupported_control_flow(exec_list
*ir
,
7363 const struct gl_shader_compiler_options
*options
)
7365 ir_control_flow_info_visitor
visitor(options
);
7366 visit_list_elements(&visitor
, ir
);
7367 return visitor
.unsupported
;
7372 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7373 * with code lowering and other optimizations.
7376 st_link_tgsi(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7378 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7380 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7381 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7385 exec_list
*ir
= shader
->ir
;
7386 gl_shader_stage stage
= shader
->Stage
;
7387 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
7388 const struct gl_shader_compiler_options
*options
=
7389 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7391 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7392 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7393 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7394 /* Do it once and repeat only if there's unsupported control flow. */
7396 do_common_optimization(ir
, true, true, options
,
7397 ctx
->Const
.NativeIntegers
);
7398 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7399 options
->MaxIfDepth
, if_threshold
);
7400 } while (has_unsupported_control_flow(ir
, options
));
7402 /* Repeat it until it stops making changes. */
7405 progress
= do_common_optimization(ir
, true, true, options
,
7406 ctx
->Const
.NativeIntegers
);
7407 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7408 options
->MaxIfDepth
, if_threshold
);
7412 /* Do this again to lower ir_binop_vector_extract introduced
7413 * by optimization passes.
7415 do_vec_index_to_cond_assign(ir
);
7417 validate_ir_tree(ir
);
7419 struct gl_program
*linked_prog
=
7420 get_mesa_program_tgsi(ctx
, prog
, shader
);
7421 st_set_prog_affected_state_flags(linked_prog
);
7424 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7425 _mesa_shader_stage_to_program(i
),
7427 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);