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glsl: Add ir_unop_f2fmp
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_to_tgsi_temprename.h"
56
57 #include "util/hash_table.h"
58 #include <algorithm>
59
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
63
64 #define MAX_GLSL_TEXTURE_OFFSET 4
65
66 #ifndef NDEBUG
67 #include "util/u_atomic.h"
68 #include "util/simple_mtx.h"
69 #include <fstream>
70 #include <ios>
71
72 /* Prepare to make it possible to specify log file */
73 static std::ofstream stats_log;
74
75 /* Helper function to check whether we want to write some statistics
76 * of the shader conversion.
77 */
78
79 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
80
81 static inline bool print_stats_enabled ()
82 {
83 static int stats_enabled = 0;
84
85 if (!stats_enabled) {
86 simple_mtx_lock(&print_stats_mutex);
87 if (!stats_enabled) {
88 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
89 if (stats_filename) {
90 bool write_header = std::ifstream(stats_filename).fail();
91 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
92 stats_enabled = stats_log.good() ? 1 : -1;
93 if (write_header)
94 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
95 } else {
96 stats_enabled = -1;
97 }
98 }
99 simple_mtx_unlock(&print_stats_mutex);
100 }
101 return stats_enabled > 0;
102 }
103 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
104 #else
105 #define PRINT_STATS(X)
106 #endif
107
108
109 static unsigned is_precise(const ir_variable *ir)
110 {
111 if (!ir)
112 return 0;
113 return ir->data.precise || ir->data.invariant;
114 }
115
116 class variable_storage {
117 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
118
119 public:
120 variable_storage(ir_variable *var, gl_register_file file, int index,
121 unsigned array_id = 0)
122 : file(file), index(index), component(0), var(var), array_id(array_id)
123 {
124 assert(file != PROGRAM_ARRAY || array_id != 0);
125 }
126
127 gl_register_file file;
128 int index;
129
130 /* Explicit component location. This is given in terms of the GLSL-style
131 * swizzles where each double is a single component, i.e. for 64-bit types
132 * it can only be 0 or 1.
133 */
134 int component;
135 ir_variable *var; /* variable that maps to this, if any */
136 unsigned array_id;
137 };
138
139 class immediate_storage : public exec_node {
140 public:
141 immediate_storage(gl_constant_value *values, int size32, GLenum type)
142 {
143 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
144 this->size32 = size32;
145 this->type = type;
146 }
147
148 /* doubles are stored across 2 gl_constant_values */
149 gl_constant_value values[4];
150 int size32; /**< Number of 32-bit components (1-4) */
151 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
152 };
153
154 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
155 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
156
157 struct inout_decl {
158 unsigned mesa_index;
159 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
160 unsigned size;
161 unsigned interp_loc;
162 unsigned gs_out_streams;
163 enum glsl_interp_mode interp;
164 enum glsl_base_type base_type;
165 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
166 bool invariant;
167 };
168
169 static struct inout_decl *
170 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
171 {
172 assert(array_id != 0);
173
174 for (unsigned i = 0; i < count; i++) {
175 struct inout_decl *decl = &decls[i];
176
177 if (array_id == decl->array_id) {
178 return decl;
179 }
180 }
181
182 return NULL;
183 }
184
185 static enum glsl_base_type
186 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
187 {
188 if (!array_id)
189 return GLSL_TYPE_ERROR;
190 struct inout_decl *decl = find_inout_array(decls, count, array_id);
191 if (decl)
192 return decl->base_type;
193 return GLSL_TYPE_ERROR;
194 }
195
196 struct hwatomic_decl {
197 unsigned location;
198 unsigned binding;
199 unsigned size;
200 unsigned array_id;
201 };
202
203 struct glsl_to_tgsi_visitor : public ir_visitor {
204 public:
205 glsl_to_tgsi_visitor();
206 ~glsl_to_tgsi_visitor();
207
208 struct gl_context *ctx;
209 struct gl_program *prog;
210 struct gl_shader_program *shader_program;
211 struct gl_linked_shader *shader;
212 struct gl_shader_compiler_options *options;
213
214 int next_temp;
215
216 unsigned *array_sizes;
217 unsigned max_num_arrays;
218 unsigned next_array;
219
220 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
221 unsigned num_inputs;
222 unsigned num_input_arrays;
223 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
224 unsigned num_outputs;
225 unsigned num_output_arrays;
226
227 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
228 unsigned num_atomics;
229 unsigned num_atomic_arrays;
230 int num_address_regs;
231 uint32_t samplers_used;
232 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
233 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
234 int images_used;
235 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
236 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
237 bool image_wr[PIPE_MAX_SHADER_IMAGES];
238 bool indirect_addr_consts;
239 int wpos_transform_const;
240
241 bool native_integers;
242 bool have_sqrt;
243 bool have_fma;
244 bool use_shared_memory;
245 bool has_tex_txf_lz;
246 bool precise;
247 bool need_uarl;
248 bool tg4_component_in_swizzle;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_demote *);
288 virtual void visit(ir_texture *);
289 virtual void visit(ir_if *);
290 virtual void visit(ir_emit_vertex *);
291 virtual void visit(ir_end_primitive *);
292 virtual void visit(ir_barrier *);
293 /*@}*/
294
295 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
296
297 void visit_atomic_counter_intrinsic(ir_call *);
298 void visit_ssbo_intrinsic(ir_call *);
299 void visit_membar_intrinsic(ir_call *);
300 void visit_shared_intrinsic(ir_call *);
301 void visit_image_intrinsic(ir_call *);
302 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
303
304 st_src_reg result;
305
306 /** List of variable_storage */
307 struct hash_table *variables;
308
309 /** List of immediate_storage */
310 exec_list immediates;
311 unsigned num_immediates;
312
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions;
315
316 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
317 st_dst_reg dst = undef_dst,
318 st_src_reg src0 = undef_src,
319 st_src_reg src1 = undef_src,
320 st_src_reg src2 = undef_src,
321 st_src_reg src3 = undef_src);
322
323 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
324 st_dst_reg dst, st_dst_reg dst1,
325 st_src_reg src0 = undef_src,
326 st_src_reg src1 = undef_src,
327 st_src_reg src2 = undef_src,
328 st_src_reg src3 = undef_src);
329
330 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
331 st_dst_reg dst,
332 st_src_reg src0, st_src_reg src1);
333
334 /**
335 * Emit the correct dot-product instruction for the type of arguments
336 */
337 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
338 st_dst_reg dst,
339 st_src_reg src0,
340 st_src_reg src1,
341 unsigned elements);
342
343 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
344 st_dst_reg dst, st_src_reg src0);
345
346 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
347 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
348
349 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
350
351 void get_deref_offsets(ir_dereference *ir,
352 unsigned *array_size,
353 unsigned *base,
354 uint16_t *index,
355 st_src_reg *reladdr,
356 bool opaque);
357 void calc_deref_offsets(ir_dereference *tail,
358 unsigned *array_elements,
359 uint16_t *index,
360 st_src_reg *indirect,
361 unsigned *location);
362 st_src_reg canonicalize_gather_offset(st_src_reg offset);
363 bool handle_bound_deref(ir_dereference *ir);
364
365 bool try_emit_mad(ir_expression *ir,
366 int mul_operand);
367 bool try_emit_mad_for_and_not(ir_expression *ir,
368 int mul_operand);
369
370 void emit_swz(ir_expression *ir);
371
372 bool process_move_condition(ir_rvalue *ir);
373
374 void simplify_cmp(void);
375
376 void rename_temp_registers(struct rename_reg_pair *renames);
377 void get_first_temp_read(int *first_reads);
378 void get_first_temp_write(int *first_writes);
379 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
380 void get_last_temp_write(int *last_writes);
381
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
384
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
389
390 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
391 st_dst_reg *l, st_src_reg *r,
392 st_src_reg *cond, bool cond_swap);
393
394 void print_stats();
395
396 void *mem_ctx;
397 };
398
399 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
400 GLSL_TYPE_FLOAT, 0);
401 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
402 GLSL_TYPE_FLOAT, 1);
403 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
404 GLSL_TYPE_FLOAT, 2);
405
406 static void
407 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
408 PRINTFLIKE(2, 3);
409
410 static void
411 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
412 {
413 va_list args;
414 va_start(args, fmt);
415 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
416 va_end(args);
417
418 prog->data->LinkStatus = LINKING_FAILURE;
419 }
420
421 int
422 swizzle_for_size(int size)
423 {
424 static const int size_swizzles[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
428 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
429 };
430
431 assert((size >= 1) && (size <= 4));
432 return size_swizzles[size - 1];
433 }
434
435
436 glsl_to_tgsi_instruction *
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
438 st_dst_reg dst, st_dst_reg dst1,
439 st_src_reg src0, st_src_reg src1,
440 st_src_reg src2, st_src_reg src3)
441 {
442 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
443 int num_reladdr = 0, i, j;
444 bool dst_is_64bit[2];
445
446 op = get_opcode(op, dst, src0, src1);
447
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
451 */
452 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
453 assert(!dst1.reladdr); /* should be lowered in earlier passes */
454 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
455 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
456 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
457 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
458
459 reladdr_to_temp(ir, &src3, &num_reladdr);
460 reladdr_to_temp(ir, &src2, &num_reladdr);
461 reladdr_to_temp(ir, &src1, &num_reladdr);
462 reladdr_to_temp(ir, &src0, &num_reladdr);
463
464 if (dst.reladdr || dst.reladdr2) {
465 if (dst.reladdr)
466 emit_arl(ir, address_reg, *dst.reladdr);
467 if (dst.reladdr2)
468 emit_arl(ir, address_reg2, *dst.reladdr2);
469 num_reladdr--;
470 }
471
472 assert(num_reladdr == 0);
473
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
476
477 inst->op = op;
478 inst->precise = this->precise;
479 inst->info = tgsi_get_opcode_info(op);
480 inst->dst[0] = dst;
481 inst->dst[1] = dst1;
482 inst->src[0] = src0;
483 inst->src[1] = src1;
484 inst->src[2] = src2;
485 inst->src[3] = src3;
486 inst->is_64bit_expanded = false;
487 inst->ir = ir;
488 inst->dead_mask = 0;
489 inst->tex_offsets = NULL;
490 inst->tex_offset_num_offset = 0;
491 inst->saturate = 0;
492 inst->tex_shadow = 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
495 */
496 inst->tex_type = GLSL_TYPE_FLOAT;
497
498 /* Update indirect addressing status used by TGSI */
499 if (dst.reladdr || dst.reladdr2) {
500 switch (dst.file) {
501 case PROGRAM_STATE_VAR:
502 case PROGRAM_CONSTANT:
503 case PROGRAM_UNIFORM:
504 this->indirect_addr_consts = true;
505 break;
506 case PROGRAM_IMMEDIATE:
507 assert(!"immediates should not have indirect addressing");
508 break;
509 default:
510 break;
511 }
512 }
513 else {
514 for (i = 0; i < 4; i++) {
515 if (inst->src[i].reladdr) {
516 switch (inst->src[i].file) {
517 case PROGRAM_STATE_VAR:
518 case PROGRAM_CONSTANT:
519 case PROGRAM_UNIFORM:
520 this->indirect_addr_consts = true;
521 break;
522 case PROGRAM_IMMEDIATE:
523 assert(!"immediates should not have indirect addressing");
524 break;
525 default:
526 break;
527 }
528 }
529 }
530 }
531
532 /*
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
536 *
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
541 *
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
544 *
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
549 */
550 for (j = 0; j < 2; j++) {
551 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
552 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
553 inst->dst[j].type == GLSL_TYPE_ARRAY) {
554 enum glsl_base_type type = find_array_type(this->outputs,
555 this->num_outputs,
556 inst->dst[j].array_id);
557 if (glsl_base_type_is_64bit(type))
558 dst_is_64bit[j] = true;
559 }
560 }
561
562 if (dst_is_64bit[0] || dst_is_64bit[1] ||
563 glsl_base_type_is_64bit(inst->src[0].type)) {
564 glsl_to_tgsi_instruction *dinst = NULL;
565 int initial_src_swz[4], initial_src_idx[4];
566 int initial_dst_idx[2], initial_dst_writemask[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
569 ? inst->dst[0].writemask : inst->dst[1].writemask;
570
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j = 0; j < 2; j++) {
573 initial_dst_writemask[j] = inst->dst[j].writemask;
574 initial_dst_idx[j] = inst->dst[j].index;
575 }
576
577 for (j = 0; j < 4; j++) {
578 initial_src_swz[j] = inst->src[j].swizzle;
579 initial_src_idx[j] = inst->src[j].index;
580 }
581
582 /*
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
585 */
586 st_src_reg addr;
587 while (writemask) {
588
589 int i = u_bit_scan(&writemask);
590
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
594 inst->op == TGSI_OPCODE_STORE) &&
595 addr.file == PROGRAM_UNDEFINED) {
596 /* We have to advance the buffer address by 16 */
597 addr = get_temp(glsl_type::uint_type);
598 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
599 inst->src[0], st_src_reg_for_int(16));
600 }
601
602 /* first time use previous instruction */
603 if (dinst == NULL) {
604 dinst = inst;
605 } else {
606 /* create a new instructions for subsequent attempts */
607 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
608 *dinst = *inst;
609 dinst->next = NULL;
610 dinst->prev = NULL;
611 }
612 this->instructions.push_tail(dinst);
613 dinst->is_64bit_expanded = true;
614
615 /* modify the destination if we are splitting */
616 for (j = 0; j < 2; j++) {
617 if (dst_is_64bit[j]) {
618 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
619 dinst->dst[j].index = initial_dst_idx[j];
620 if (i > 1) {
621 if (dinst->op == TGSI_OPCODE_LOAD ||
622 dinst->op == TGSI_OPCODE_STORE)
623 dinst->src[0] = addr;
624 if (dinst->op != TGSI_OPCODE_STORE)
625 dinst->dst[j].index++;
626 }
627 } else {
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
630 */
631 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
632 }
633 }
634
635 /* modify the src registers */
636 for (j = 0; j < 4; j++) {
637 int swz = GET_SWZ(initial_src_swz[j], i);
638
639 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
640 dinst->src[j].index = initial_src_idx[j];
641 if (swz > 1) {
642 dinst->src[j].double_reg2 = true;
643 dinst->src[j].index++;
644 }
645
646 if (swz & 1)
647 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
648 SWIZZLE_Z, SWIZZLE_W);
649 else
650 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
651 SWIZZLE_X, SWIZZLE_Y);
652
653 } else {
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
656 * integer src1
657 */
658 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
659 op == TGSI_OPCODE_I2D ||
660 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
661 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
662 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
663 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
664 }
665 }
666 }
667 }
668 inst = dinst;
669 } else {
670 this->instructions.push_tail(inst);
671 }
672
673
674 return inst;
675 }
676
677 glsl_to_tgsi_instruction *
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
679 st_dst_reg dst,
680 st_src_reg src0, st_src_reg src1,
681 st_src_reg src2, st_src_reg src3)
682 {
683 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
684 }
685
686 /**
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
689 */
690 enum tgsi_opcode
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
692 st_dst_reg dst,
693 st_src_reg src0, st_src_reg src1)
694 {
695 enum glsl_base_type type = GLSL_TYPE_FLOAT;
696
697 if (op == TGSI_OPCODE_MOV)
698 return op;
699
700 assert(src0.type != GLSL_TYPE_ARRAY);
701 assert(src0.type != GLSL_TYPE_STRUCT);
702 assert(src1.type != GLSL_TYPE_ARRAY);
703 assert(src1.type != GLSL_TYPE_STRUCT);
704
705 if (is_resource_instruction(op))
706 type = src1.type;
707 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
708 type = GLSL_TYPE_INT64;
709 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
710 type = GLSL_TYPE_UINT64;
711 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
712 type = GLSL_TYPE_DOUBLE;
713 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
714 type = GLSL_TYPE_FLOAT;
715 else if (native_integers)
716 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
717
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
730 else \
731 op = TGSI_OPCODE_##f; \
732 break;
733
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
748 else \
749 op = TGSI_OPCODE_##c; \
750 break;
751
752 switch (op) {
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
755 *
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
757 */
758 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
759 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
760 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
761 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
762 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
763 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
764 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
765 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
766 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
767 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
768 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
769 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
770 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
771 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
772 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
773 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
774
775 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
776 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
777 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
778 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
779 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
780 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
781 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
782 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
783 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
784
785 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
786 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
787 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
788 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
789
790 default:
791 break;
792 }
793
794 assert(op != TGSI_OPCODE_LAST);
795 return op;
796 }
797
798 glsl_to_tgsi_instruction *
799 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
800 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
801 unsigned elements)
802 {
803 static const enum tgsi_opcode dot_opcodes[] = {
804 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
805 };
806
807 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
808 }
809
810 /**
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
812 *
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
817 */
818 void
819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
820 st_dst_reg dst,
821 st_src_reg orig_src0, st_src_reg orig_src1)
822 {
823 int i, j;
824 int done_mask = ~dst.writemask;
825
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
828 * dst channels.
829 */
830 for (i = 0; i < 4; i++) {
831 GLuint this_mask = (1 << i);
832 st_src_reg src0 = orig_src0;
833 st_src_reg src1 = orig_src1;
834
835 if (done_mask & this_mask)
836 continue;
837
838 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
839 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
840 for (j = i + 1; j < 4; j++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
843 * well.
844 */
845 if (!(done_mask & (1 << j)) &&
846 GET_SWZ(src0.swizzle, j) == src0_swiz &&
847 GET_SWZ(src1.swizzle, j) == src1_swiz) {
848 this_mask |= (1 << j);
849 }
850 }
851 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
852 src0_swiz, src0_swiz);
853 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
854 src1_swiz, src1_swiz);
855
856 dst.writemask = this_mask;
857 emit_asm(ir, op, dst, src0, src1);
858 done_mask |= this_mask;
859 }
860 }
861
862 void
863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
864 st_dst_reg dst, st_src_reg src0)
865 {
866 st_src_reg undef = undef_src;
867
868 undef.swizzle = SWIZZLE_XXXX;
869
870 emit_scalar(ir, op, dst, src0, undef);
871 }
872
873 void
874 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
875 st_dst_reg dst, st_src_reg src0)
876 {
877 enum tgsi_opcode op = TGSI_OPCODE_ARL;
878
879 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
880 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
881 return;
882
883 op = TGSI_OPCODE_UARL;
884 }
885
886 assert(dst.file == PROGRAM_ADDRESS);
887 if (dst.index >= this->num_address_regs)
888 this->num_address_regs = dst.index + 1;
889
890 emit_asm(NULL, op, dst, src0);
891 }
892
893 int
894 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
895 gl_constant_value values[8], int size,
896 GLenum datatype,
897 uint16_t *swizzle_out)
898 {
899 if (file == PROGRAM_CONSTANT) {
900 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
901 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
902 values, size, datatype,
903 &swizzle);
904 if (swizzle_out)
905 *swizzle_out = swizzle;
906 return result;
907 }
908
909 assert(file == PROGRAM_IMMEDIATE);
910
911 int index = 0;
912 immediate_storage *entry;
913 int size32 = size * ((datatype == GL_DOUBLE ||
914 datatype == GL_INT64_ARB ||
915 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
916 int i;
917
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
920 */
921 foreach_in_list(immediate_storage, entry, &this->immediates) {
922 immediate_storage *tmp = entry;
923
924 for (i = 0; i * 4 < size32; i++) {
925 int slot_size = MIN2(size32 - (i * 4), 4);
926 if (tmp->type != datatype || tmp->size32 != slot_size)
927 break;
928 if (memcmp(tmp->values, &values[i * 4],
929 slot_size * sizeof(gl_constant_value)))
930 break;
931
932 /* Everything matches, keep going until the full size is matched */
933 tmp = (immediate_storage *)tmp->next;
934 }
935
936 /* The full value matched */
937 if (i * 4 >= size32)
938 return index;
939
940 index++;
941 }
942
943 for (i = 0; i * 4 < size32; i++) {
944 int slot_size = MIN2(size32 - (i * 4), 4);
945 /* Add this immediate to the list. */
946 entry = new(mem_ctx) immediate_storage(&values[i * 4],
947 slot_size, datatype);
948 this->immediates.push_tail(entry);
949 this->num_immediates++;
950 }
951 return index;
952 }
953
954 st_src_reg
955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
956 {
957 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
958 union gl_constant_value uval;
959
960 uval.f = val;
961 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
962
963 return src;
964 }
965
966 st_src_reg
967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
968 {
969 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
970 union gl_constant_value uval[2];
971
972 memcpy(uval, &val, sizeof(uval));
973 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
974 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
975 return src;
976 }
977
978 st_src_reg
979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
980 {
981 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
982 union gl_constant_value uval;
983
984 assert(native_integers);
985
986 uval.i = val;
987 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
988
989 return src;
990 }
991
992 st_src_reg
993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
994 {
995 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
996 union gl_constant_value uval[2];
997
998 memcpy(uval, &val, sizeof(uval));
999 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
1000 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1001
1002 return src;
1003 }
1004
1005 st_src_reg
1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1007 {
1008 if (native_integers)
1009 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1010 st_src_reg_for_int(val);
1011 else
1012 return st_src_reg_for_float(val);
1013 }
1014
1015 static int
1016 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1017 {
1018 return type->count_attribute_slots(is_vs_input);
1019 }
1020
1021 static int
1022 type_size(const struct glsl_type *type)
1023 {
1024 return type->count_attribute_slots(false);
1025 }
1026
1027 static void
1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1029 exec_list *instructions, ir_constant *access)
1030 {
1031 /**
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1034 */
1035 enum tgsi_opcode op = inst->op;
1036 do {
1037 inst->resource = *buf;
1038 if (access)
1039 inst->buffer_access = access->value.u[0];
1040
1041 if (inst == instructions->get_head_raw())
1042 break;
1043 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1044
1045 if (inst->op == TGSI_OPCODE_UADD) {
1046 if (inst == instructions->get_head_raw())
1047 break;
1048 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1049 }
1050 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1051 }
1052
1053 /**
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1056 *
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1061 */
1062 static bool
1063 type_has_array_or_matrix(const glsl_type *type)
1064 {
1065 if (type->is_array() || type->is_matrix())
1066 return true;
1067
1068 if (type->is_struct()) {
1069 for (unsigned i = 0; i < type->length; i++) {
1070 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1071 return true;
1072 }
1073 }
1074 }
1075
1076 return false;
1077 }
1078
1079
1080 /**
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1083 * storage).
1084 */
1085 st_src_reg
1086 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1087 {
1088 st_src_reg src;
1089
1090 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1091 src.reladdr = NULL;
1092 src.negate = 0;
1093 src.abs = 0;
1094
1095 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1096 if (next_array >= max_num_arrays) {
1097 max_num_arrays += 32;
1098 array_sizes = (unsigned*)
1099 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1100 }
1101
1102 src.file = PROGRAM_ARRAY;
1103 src.index = 0;
1104 src.array_id = next_array + 1;
1105 array_sizes[next_array] = type_size(type);
1106 ++next_array;
1107
1108 } else {
1109 src.file = PROGRAM_TEMPORARY;
1110 src.index = next_temp;
1111 next_temp += type_size(type);
1112 }
1113
1114 if (type->is_array() || type->is_struct()) {
1115 src.swizzle = SWIZZLE_NOOP;
1116 } else {
1117 src.swizzle = swizzle_for_size(type->vector_elements);
1118 }
1119
1120 return src;
1121 }
1122
1123 variable_storage *
1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1125 {
1126 struct hash_entry *entry;
1127
1128 entry = _mesa_hash_table_search(this->variables, var);
1129 if (!entry)
1130 return NULL;
1131
1132 return (variable_storage *)entry->data;
1133 }
1134
1135 void
1136 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1137 {
1138 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1139 unsigned int i;
1140 const ir_state_slot *const slots = ir->get_state_slots();
1141 assert(slots != NULL);
1142
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1147 * out.
1148 */
1149 for (i = 0; i < ir->get_num_state_slots(); i++) {
1150 if (slots[i].swizzle != SWIZZLE_XYZW) {
1151 break;
1152 }
1153 }
1154
1155 variable_storage *storage;
1156 st_dst_reg dst;
1157 if (i == ir->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1160
1161 _mesa_hash_table_insert(this->variables, ir, storage);
1162
1163 dst = undef_dst;
1164 } else {
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1168 */
1169 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1170
1171 dst = st_dst_reg(get_temp(ir->type));
1172
1173 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1174 dst.array_id);
1175
1176 _mesa_hash_table_insert(this->variables, ir, storage);
1177 }
1178
1179
1180 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1181 int index = _mesa_add_state_reference(this->prog->Parameters,
1182 slots[i].tokens);
1183
1184 if (storage->file == PROGRAM_STATE_VAR) {
1185 if (storage->index == -1) {
1186 storage->index = index;
1187 } else {
1188 assert(index == storage->index + (int)i);
1189 }
1190 } else {
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1195 */
1196 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1197 src.swizzle = slots[i].swizzle;
1198 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1200 dst.index++;
1201 }
1202 }
1203
1204 if (storage->file == PROGRAM_TEMPORARY &&
1205 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1206 fail_link(this->shader_program,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir->name, dst.index - storage->index,
1209 type_size(ir->type));
1210 }
1211 }
1212 }
1213
1214 void
1215 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1216 {
1217 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1218
1219 visit_exec_list(&ir->body_instructions, this);
1220
1221 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1222 }
1223
1224 void
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1226 {
1227 switch (ir->mode) {
1228 case ir_loop_jump::jump_break:
1229 emit_asm(NULL, TGSI_OPCODE_BRK);
1230 break;
1231 case ir_loop_jump::jump_continue:
1232 emit_asm(NULL, TGSI_OPCODE_CONT);
1233 break;
1234 }
1235 }
1236
1237
1238 void
1239 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1240 {
1241 assert(0);
1242 (void)ir;
1243 }
1244
1245 void
1246 glsl_to_tgsi_visitor::visit(ir_function *ir)
1247 {
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1250 */
1251 if (strcmp(ir->name, "main") == 0) {
1252 const ir_function_signature *sig;
1253 exec_list empty;
1254
1255 sig = ir->matching_signature(NULL, &empty, false);
1256
1257 assert(sig);
1258
1259 foreach_in_list(ir_instruction, ir, &sig->body) {
1260 ir->accept(this);
1261 }
1262 }
1263 }
1264
1265 bool
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1267 {
1268 int nonmul_operand = 1 - mul_operand;
1269 st_src_reg a, b, c;
1270 st_dst_reg result_dst;
1271
1272 // there is no TGSI opcode for this
1273 if (ir->type->is_integer_64())
1274 return false;
1275
1276 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1277 if (!expr || expr->operation != ir_binop_mul)
1278 return false;
1279
1280 expr->operands[0]->accept(this);
1281 a = this->result;
1282 expr->operands[1]->accept(this);
1283 b = this->result;
1284 ir->operands[nonmul_operand]->accept(this);
1285 c = this->result;
1286
1287 this->result = get_temp(ir->type);
1288 result_dst = st_dst_reg(this->result);
1289 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1290 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1291
1292 return true;
1293 }
1294
1295 /**
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1297 *
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1302 *
1303 * - a * !b
1304 * - a * (1 - b)
1305 * - (a * 1) - (a * b)
1306 * - a + -(a * b)
1307 * - a + (a * -b)
1308 *
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1310 * instruction.
1311 */
1312 bool
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1314 int try_operand)
1315 {
1316 const int other_operand = 1 - try_operand;
1317 st_src_reg a, b;
1318
1319 ir_expression *expr = ir->operands[try_operand]->as_expression();
1320 if (!expr || expr->operation != ir_unop_logic_not)
1321 return false;
1322
1323 ir->operands[other_operand]->accept(this);
1324 a = this->result;
1325 expr->operands[0]->accept(this);
1326 b = this->result;
1327
1328 b.negate = ~b.negate;
1329
1330 this->result = get_temp(ir->type);
1331 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1332
1333 return true;
1334 }
1335
1336 void
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1338 st_src_reg *reg, int *num_reladdr)
1339 {
1340 if (!reg->reladdr && !reg->reladdr2)
1341 return;
1342
1343 if (reg->reladdr)
1344 emit_arl(ir, address_reg, *reg->reladdr);
1345 if (reg->reladdr2)
1346 emit_arl(ir, address_reg2, *reg->reladdr2);
1347
1348 if (*num_reladdr != 1) {
1349 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1350
1351 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1352 *reg = temp;
1353 }
1354
1355 (*num_reladdr)--;
1356 }
1357
1358 void
1359 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1360 {
1361 st_src_reg op[ARRAY_SIZE(ir->operands)];
1362
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1364 */
1365 if (!this->precise && ir->operation == ir_binop_add) {
1366 if (try_emit_mad(ir, 1))
1367 return;
1368 if (try_emit_mad(ir, 0))
1369 return;
1370 }
1371
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1373 */
1374 if (!native_integers && ir->operation == ir_binop_logic_and) {
1375 if (try_emit_mad_for_and_not(ir, 1))
1376 return;
1377 if (try_emit_mad_for_and_not(ir, 0))
1378 return;
1379 }
1380
1381 if (ir->operation == ir_quadop_vector)
1382 assert(!"ir_quadop_vector should have been lowered");
1383
1384 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1385 this->result.file = PROGRAM_UNDEFINED;
1386 ir->operands[operand]->accept(this);
1387 if (this->result.file == PROGRAM_UNDEFINED) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir->operands[operand]->print();
1390 printf("\n");
1391 exit(1);
1392 }
1393 op[operand] = this->result;
1394
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1397 */
1398 assert(!ir->operands[operand]->type->is_matrix());
1399 }
1400
1401 visit_expression(ir, op);
1402 }
1403
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1407 */
1408 void
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1410 {
1411 st_src_reg result_src;
1412 st_dst_reg result_dst;
1413
1414 int vector_elements = ir->operands[0]->type->vector_elements;
1415 if (ir->operands[1] &&
1416 ir->operation != ir_binop_interpolate_at_offset &&
1417 ir->operation != ir_binop_interpolate_at_sample) {
1418 st_src_reg *swz_op = NULL;
1419 if (vector_elements > ir->operands[1]->type->vector_elements) {
1420 assert(ir->operands[1]->type->vector_elements == 1);
1421 swz_op = &op[1];
1422 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1423 assert(ir->operands[0]->type->vector_elements == 1);
1424 swz_op = &op[0];
1425 }
1426 if (swz_op) {
1427 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1428 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1429 swizzle_x, swizzle_x);
1430 }
1431 vector_elements = MAX2(vector_elements,
1432 ir->operands[1]->type->vector_elements);
1433 }
1434 if (ir->operands[2] &&
1435 ir->operands[2]->type->vector_elements != vector_elements) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir->operands[2]->type->vector_elements == 1);
1438 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1439 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1440 swizzle_x, swizzle_x);
1441 }
1442
1443 this->result.file = PROGRAM_UNDEFINED;
1444
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1447 */
1448 result_src = get_temp(ir->type);
1449 /* convenience for the emit functions below. */
1450 result_dst = st_dst_reg(result_src);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1453 * sequences.
1454 */
1455 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1456
1457 switch (ir->operation) {
1458 case ir_unop_logic_not:
1459 if (result_dst.type != GLSL_TYPE_FLOAT)
1460 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1461 else {
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1466 */
1467 op[0].negate = ~op[0].negate;
1468 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1469 st_src_reg_for_float(1.0));
1470 }
1471 break;
1472 case ir_unop_neg:
1473 if (result_dst.type == GLSL_TYPE_INT64 ||
1474 result_dst.type == GLSL_TYPE_UINT64)
1475 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1476 else if (result_dst.type == GLSL_TYPE_INT ||
1477 result_dst.type == GLSL_TYPE_UINT)
1478 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1479 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1480 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1481 else {
1482 op[0].negate = ~op[0].negate;
1483 result_src = op[0];
1484 }
1485 break;
1486 case ir_unop_subroutine_to_int:
1487 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1488 break;
1489 case ir_unop_abs:
1490 if (result_dst.type == GLSL_TYPE_FLOAT)
1491 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1492 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1493 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1494 else if (result_dst.type == GLSL_TYPE_INT64 ||
1495 result_dst.type == GLSL_TYPE_UINT64)
1496 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1497 else
1498 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1499 break;
1500 case ir_unop_sign:
1501 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1502 break;
1503 case ir_unop_rcp:
1504 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1505 break;
1506
1507 case ir_unop_exp2:
1508 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1509 break;
1510 case ir_unop_exp:
1511 assert(!"not reached: should be handled by exp_to_exp2");
1512 break;
1513 case ir_unop_log:
1514 assert(!"not reached: should be handled by log_to_log2");
1515 break;
1516 case ir_unop_log2:
1517 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1518 break;
1519 case ir_unop_sin:
1520 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1521 break;
1522 case ir_unop_cos:
1523 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1524 break;
1525 case ir_unop_saturate: {
1526 glsl_to_tgsi_instruction *inst;
1527 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1528 inst->saturate = true;
1529 break;
1530 }
1531
1532 case ir_unop_dFdx:
1533 case ir_unop_dFdx_coarse:
1534 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1535 break;
1536 case ir_unop_dFdx_fine:
1537 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1538 break;
1539 case ir_unop_dFdy:
1540 case ir_unop_dFdy_coarse:
1541 case ir_unop_dFdy_fine:
1542 {
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1546 */
1547 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1548 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1549
1550 unsigned transform_y_index =
1551 _mesa_add_state_reference(this->prog->Parameters,
1552 transform_y_state);
1553
1554 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1555 transform_y_index,
1556 glsl_type::vec4_type);
1557 transform_y.swizzle = SWIZZLE_XXXX;
1558
1559 st_src_reg temp = get_temp(glsl_type::vec4_type);
1560
1561 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1562 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1563 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1564 break;
1565 }
1566
1567 case ir_unop_frexp_sig:
1568 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1569 break;
1570
1571 case ir_unop_frexp_exp:
1572 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1573 break;
1574
1575 case ir_unop_noise: {
1576 /* At some point, a motivated person could add a better
1577 * implementation of noise. Currently not even the nvidia
1578 * binary drivers do anything more than this. In any case, the
1579 * place to do this is in the GL state tracker, not the poor
1580 * driver.
1581 */
1582 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1583 break;
1584 }
1585
1586 case ir_binop_add:
1587 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1588 break;
1589 case ir_binop_sub:
1590 op[1].negate = ~op[1].negate;
1591 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1592 break;
1593
1594 case ir_binop_mul:
1595 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1596 break;
1597 case ir_binop_div:
1598 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1599 break;
1600 case ir_binop_mod:
1601 if (result_dst.type == GLSL_TYPE_FLOAT)
1602 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1603 else
1604 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1605 break;
1606
1607 case ir_binop_less:
1608 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1609 break;
1610 case ir_binop_gequal:
1611 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1612 break;
1613 case ir_binop_equal:
1614 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1615 break;
1616 case ir_binop_nequal:
1617 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1618 break;
1619 case ir_binop_all_equal:
1620 /* "==" operator producing a scalar boolean. */
1621 if (ir->operands[0]->type->is_vector() ||
1622 ir->operands[1]->type->is_vector()) {
1623 st_src_reg temp = get_temp(native_integers ?
1624 glsl_type::uvec4_type :
1625 glsl_type::vec4_type);
1626
1627 if (native_integers) {
1628 st_dst_reg temp_dst = st_dst_reg(temp);
1629 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1630
1631 if (ir->operands[0]->type->is_boolean() &&
1632 ir->operands[1]->as_constant() &&
1633 ir->operands[1]->as_constant()->is_one()) {
1634 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1635 } else {
1636 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1637 }
1638
1639 /* Emit 1-3 AND operations to combine the SEQ results. */
1640 switch (ir->operands[0]->type->vector_elements) {
1641 case 2:
1642 break;
1643 case 3:
1644 temp_dst.writemask = WRITEMASK_Y;
1645 temp1.swizzle = SWIZZLE_YYYY;
1646 temp2.swizzle = SWIZZLE_ZZZZ;
1647 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1648 break;
1649 case 4:
1650 temp_dst.writemask = WRITEMASK_X;
1651 temp1.swizzle = SWIZZLE_XXXX;
1652 temp2.swizzle = SWIZZLE_YYYY;
1653 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1654 temp_dst.writemask = WRITEMASK_Y;
1655 temp1.swizzle = SWIZZLE_ZZZZ;
1656 temp2.swizzle = SWIZZLE_WWWW;
1657 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1658 }
1659
1660 temp1.swizzle = SWIZZLE_XXXX;
1661 temp2.swizzle = SWIZZLE_YYYY;
1662 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1663 } else {
1664 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1665
1666 /* After the dot-product, the value will be an integer on the
1667 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1668 */
1669 emit_dp(ir, result_dst, temp, temp, vector_elements);
1670
1671 /* Negating the result of the dot-product gives values on the range
1672 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1673 * This is achieved using SGE.
1674 */
1675 st_src_reg sge_src = result_src;
1676 sge_src.negate = ~sge_src.negate;
1677 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1678 st_src_reg_for_float(0.0));
1679 }
1680 } else {
1681 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1682 }
1683 break;
1684 case ir_binop_any_nequal:
1685 /* "!=" operator producing a scalar boolean. */
1686 if (ir->operands[0]->type->is_vector() ||
1687 ir->operands[1]->type->is_vector()) {
1688 st_src_reg temp = get_temp(native_integers ?
1689 glsl_type::uvec4_type :
1690 glsl_type::vec4_type);
1691 if (ir->operands[0]->type->is_boolean() &&
1692 ir->operands[1]->as_constant() &&
1693 ir->operands[1]->as_constant()->is_zero()) {
1694 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1695 } else {
1696 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1697 }
1698
1699 if (native_integers) {
1700 st_dst_reg temp_dst = st_dst_reg(temp);
1701 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1702
1703 /* Emit 1-3 OR operations to combine the SNE results. */
1704 switch (ir->operands[0]->type->vector_elements) {
1705 case 2:
1706 break;
1707 case 3:
1708 temp_dst.writemask = WRITEMASK_Y;
1709 temp1.swizzle = SWIZZLE_YYYY;
1710 temp2.swizzle = SWIZZLE_ZZZZ;
1711 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1712 break;
1713 case 4:
1714 temp_dst.writemask = WRITEMASK_X;
1715 temp1.swizzle = SWIZZLE_XXXX;
1716 temp2.swizzle = SWIZZLE_YYYY;
1717 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1718 temp_dst.writemask = WRITEMASK_Y;
1719 temp1.swizzle = SWIZZLE_ZZZZ;
1720 temp2.swizzle = SWIZZLE_WWWW;
1721 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1722 }
1723
1724 temp1.swizzle = SWIZZLE_XXXX;
1725 temp2.swizzle = SWIZZLE_YYYY;
1726 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1727 } else {
1728 /* After the dot-product, the value will be an integer on the
1729 * range [0,4]. Zero stays zero, and positive values become 1.0.
1730 */
1731 glsl_to_tgsi_instruction *const dp =
1732 emit_dp(ir, result_dst, temp, temp, vector_elements);
1733 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1734 /* The clamping to [0,1] can be done for free in the fragment
1735 * shader with a saturate.
1736 */
1737 dp->saturate = true;
1738 } else {
1739 /* Negating the result of the dot-product gives values on the
1740 * range [-4, 0]. Zero stays zero, and negative values become
1741 * 1.0. This achieved using SLT.
1742 */
1743 st_src_reg slt_src = result_src;
1744 slt_src.negate = ~slt_src.negate;
1745 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1746 st_src_reg_for_float(0.0));
1747 }
1748 }
1749 } else {
1750 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1751 }
1752 break;
1753
1754 case ir_binop_logic_xor:
1755 if (native_integers)
1756 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1757 else
1758 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1759 break;
1760
1761 case ir_binop_logic_or: {
1762 if (native_integers) {
1763 /* If integers are used as booleans, we can use an actual "or"
1764 * instruction.
1765 */
1766 assert(native_integers);
1767 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1768 } else {
1769 /* After the addition, the value will be an integer on the
1770 * range [0,2]. Zero stays zero, and positive values become 1.0.
1771 */
1772 glsl_to_tgsi_instruction *add =
1773 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1774 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1775 /* The clamping to [0,1] can be done for free in the fragment
1776 * shader with a saturate if floats are being used as boolean
1777 * values.
1778 */
1779 add->saturate = true;
1780 } else {
1781 /* Negating the result of the addition gives values on the range
1782 * [-2, 0]. Zero stays zero, and negative values become 1.0
1783 * This is achieved using SLT.
1784 */
1785 st_src_reg slt_src = result_src;
1786 slt_src.negate = ~slt_src.negate;
1787 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1788 st_src_reg_for_float(0.0));
1789 }
1790 }
1791 break;
1792 }
1793
1794 case ir_binop_logic_and:
1795 /* If native integers are disabled, the bool args are stored as float 0.0
1796 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1797 * actual AND opcode.
1798 */
1799 if (native_integers)
1800 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1801 else
1802 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1803 break;
1804
1805 case ir_binop_dot:
1806 assert(ir->operands[0]->type->is_vector());
1807 assert(ir->operands[0]->type == ir->operands[1]->type);
1808 emit_dp(ir, result_dst, op[0], op[1],
1809 ir->operands[0]->type->vector_elements);
1810 break;
1811
1812 case ir_unop_sqrt:
1813 if (have_sqrt) {
1814 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1815 } else {
1816 /* This is the only instruction sequence that makes the game "Risen"
1817 * render correctly. ABS is not required for the game, but since GLSL
1818 * declares negative values as "undefined", allowing us to do whatever
1819 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1820 * behavior.
1821 */
1822 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1823 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1824 }
1825 break;
1826 case ir_unop_rsq:
1827 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1828 break;
1829 case ir_unop_i2f:
1830 if (native_integers) {
1831 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1832 break;
1833 }
1834 /* fallthrough to next case otherwise */
1835 case ir_unop_b2f:
1836 if (native_integers) {
1837 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1838 st_src_reg_for_float(1.0));
1839 break;
1840 }
1841 /* fallthrough to next case otherwise */
1842 case ir_unop_i2u:
1843 case ir_unop_u2i:
1844 case ir_unop_i642u64:
1845 case ir_unop_u642i64:
1846 /* Converting between signed and unsigned integers is a no-op. */
1847 result_src = op[0];
1848 result_src.type = result_dst.type;
1849 break;
1850 case ir_unop_b2i:
1851 if (native_integers) {
1852 /* Booleans are stored as integers using ~0 for true and 0 for false.
1853 * GLSL requires that int(bool) return 1 for true and 0 for false.
1854 * This conversion is done with AND, but it could be done with NEG.
1855 */
1856 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1857 st_src_reg_for_int(1));
1858 } else {
1859 /* Booleans and integers are both stored as floats when native
1860 * integers are disabled.
1861 */
1862 result_src = op[0];
1863 }
1864 break;
1865 case ir_unop_f2i:
1866 if (native_integers)
1867 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1868 else
1869 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1870 break;
1871 case ir_unop_f2u:
1872 if (native_integers)
1873 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1874 else
1875 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1876 break;
1877 case ir_unop_bitcast_f2i:
1878 case ir_unop_bitcast_f2u:
1879 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1880 if (op[0].negate || op[0].abs)
1881 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1882 else
1883 result_src = op[0];
1884 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1885 GLSL_TYPE_UINT;
1886 break;
1887 case ir_unop_bitcast_i2f:
1888 case ir_unop_bitcast_u2f:
1889 result_src = op[0];
1890 result_src.type = GLSL_TYPE_FLOAT;
1891 break;
1892 case ir_unop_f2b:
1893 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1894 st_src_reg_for_float(0.0));
1895 break;
1896 case ir_unop_d2b:
1897 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1898 st_src_reg_for_double(0.0));
1899 break;
1900 case ir_unop_i2b:
1901 if (native_integers)
1902 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1903 st_src_reg_for_int(0));
1904 else
1905 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1906 st_src_reg_for_float(0.0));
1907 break;
1908 case ir_unop_bitcast_u642d:
1909 case ir_unop_bitcast_i642d:
1910 result_src = op[0];
1911 result_src.type = GLSL_TYPE_DOUBLE;
1912 break;
1913 case ir_unop_bitcast_d2i64:
1914 result_src = op[0];
1915 result_src.type = GLSL_TYPE_INT64;
1916 break;
1917 case ir_unop_bitcast_d2u64:
1918 result_src = op[0];
1919 result_src.type = GLSL_TYPE_UINT64;
1920 break;
1921 case ir_unop_trunc:
1922 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1923 break;
1924 case ir_unop_ceil:
1925 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1926 break;
1927 case ir_unop_floor:
1928 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1929 break;
1930 case ir_unop_round_even:
1931 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1932 break;
1933 case ir_unop_fract:
1934 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1935 break;
1936
1937 case ir_binop_min:
1938 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1939 break;
1940 case ir_binop_max:
1941 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1942 break;
1943 case ir_binop_pow:
1944 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1945 break;
1946
1947 case ir_unop_bit_not:
1948 if (native_integers) {
1949 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1950 break;
1951 }
1952 case ir_unop_u2f:
1953 if (native_integers) {
1954 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1955 break;
1956 }
1957 case ir_binop_lshift:
1958 case ir_binop_rshift:
1959 if (native_integers) {
1960 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1961 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1962 st_src_reg count;
1963
1964 if (glsl_base_type_is_64bit(op[0].type)) {
1965 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1966 * 64 bits.
1967 */
1968 count = get_temp(glsl_type::u64vec(ir->operands[1]
1969 ->type->components()));
1970 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1971 } else {
1972 count = op[1];
1973 }
1974
1975 emit_asm(ir, opcode, result_dst, op[0], count);
1976 break;
1977 }
1978 case ir_binop_bit_and:
1979 if (native_integers) {
1980 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1981 break;
1982 }
1983 case ir_binop_bit_xor:
1984 if (native_integers) {
1985 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1986 break;
1987 }
1988 case ir_binop_bit_or:
1989 if (native_integers) {
1990 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1991 break;
1992 }
1993
1994 assert(!"GLSL 1.30 features unsupported");
1995 break;
1996
1997 case ir_binop_ubo_load: {
1998 if (ctx->Const.UseSTD430AsDefaultPacking) {
1999 ir_rvalue *block = ir->operands[0];
2000 ir_rvalue *offset = ir->operands[1];
2001 ir_constant *const_block = block->as_constant();
2002
2003 st_src_reg cbuf(PROGRAM_CONSTANT,
2004 (const_block ? const_block->value.u[0] + 1 : 1),
2005 ir->type->base_type);
2006
2007 cbuf.has_index2 = true;
2008
2009 if (!const_block) {
2010 block->accept(this);
2011 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2012 *cbuf.reladdr = this->result;
2013 emit_arl(ir, sampler_reladdr, this->result);
2014 }
2015
2016 /* Calculate the surface offset */
2017 offset->accept(this);
2018 st_src_reg off = this->result;
2019
2020 glsl_to_tgsi_instruction *inst =
2021 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2022
2023 if (result_dst.type == GLSL_TYPE_BOOL)
2024 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2025 st_src_reg_for_int(0));
2026
2027 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2028 NULL);
2029 } else {
2030 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2031 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2032 unsigned const_offset = const_offset_ir ?
2033 const_offset_ir->value.u[0] : 0;
2034 unsigned const_block = const_uniform_block ?
2035 const_uniform_block->value.u[0] + 1 : 1;
2036 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2037 st_src_reg cbuf;
2038
2039 cbuf.type = ir->type->base_type;
2040 cbuf.file = PROGRAM_CONSTANT;
2041 cbuf.index = 0;
2042 cbuf.reladdr = NULL;
2043 cbuf.negate = 0;
2044 cbuf.abs = 0;
2045 cbuf.index2D = const_block;
2046
2047 assert(ir->type->is_vector() || ir->type->is_scalar());
2048
2049 if (const_offset_ir) {
2050 /* Constant index into constant buffer */
2051 cbuf.reladdr = NULL;
2052 cbuf.index = const_offset / 16;
2053 } else {
2054 ir_expression *offset_expr = ir->operands[1]->as_expression();
2055 st_src_reg offset = op[1];
2056
2057 /* The OpenGL spec is written in such a way that accesses with
2058 * non-constant offset are almost always vec4-aligned. The only
2059 * exception to this are members of structs in arrays of structs:
2060 * each struct in an array of structs is at least vec4-aligned,
2061 * but single-element and [ui]vec2 members of the struct may be at
2062 * an offset that is not a multiple of 16 bytes.
2063 *
2064 * Here, we extract that offset, relying on previous passes to
2065 * always generate offset expressions of the form
2066 * (+ expr constant_offset).
2067 *
2068 * Note that the std430 layout, which allows more cases of
2069 * alignment less than vec4 in arrays, is not supported for
2070 * uniform blocks, so we do not have to deal with it here.
2071 */
2072 if (offset_expr && offset_expr->operation == ir_binop_add) {
2073 const_offset_ir = offset_expr->operands[1]->as_constant();
2074 if (const_offset_ir) {
2075 const_offset = const_offset_ir->value.u[0];
2076 cbuf.index = const_offset / 16;
2077 offset_expr->operands[0]->accept(this);
2078 offset = this->result;
2079 }
2080 }
2081
2082 /* Relative/variable index into constant buffer */
2083 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2084 st_src_reg_for_int(4));
2085 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2086 *cbuf.reladdr = index_reg;
2087 }
2088
2089 if (const_uniform_block) {
2090 /* Constant constant buffer */
2091 cbuf.reladdr2 = NULL;
2092 } else {
2093 /* Relative/variable constant buffer */
2094 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2095 *cbuf.reladdr2 = op[0];
2096 }
2097 cbuf.has_index2 = true;
2098
2099 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2100 if (glsl_base_type_is_64bit(cbuf.type))
2101 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2102 const_offset % 16 / 8,
2103 const_offset % 16 / 8,
2104 const_offset % 16 / 8);
2105 else
2106 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2107 const_offset % 16 / 4,
2108 const_offset % 16 / 4,
2109 const_offset % 16 / 4);
2110
2111 if (ir->type->is_boolean()) {
2112 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2113 st_src_reg_for_int(0));
2114 } else {
2115 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2116 }
2117 }
2118 break;
2119 }
2120 case ir_triop_lrp:
2121 /* note: we have to reorder the three args here */
2122 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2123 break;
2124 case ir_triop_csel:
2125 if (this->ctx->Const.NativeIntegers)
2126 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2127 else {
2128 op[0].negate = ~op[0].negate;
2129 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2130 }
2131 break;
2132 case ir_triop_bitfield_extract:
2133 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2134 break;
2135 case ir_quadop_bitfield_insert:
2136 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2137 break;
2138 case ir_unop_bitfield_reverse:
2139 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2140 break;
2141 case ir_unop_bit_count:
2142 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2143 break;
2144 case ir_unop_find_msb:
2145 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2146 break;
2147 case ir_unop_find_lsb:
2148 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2149 break;
2150 case ir_binop_imul_high:
2151 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2152 break;
2153 case ir_triop_fma:
2154 /* In theory, MAD is incorrect here. */
2155 if (have_fma)
2156 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2157 else
2158 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2159 break;
2160 case ir_unop_interpolate_at_centroid:
2161 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2162 break;
2163 case ir_binop_interpolate_at_offset: {
2164 /* The y coordinate needs to be flipped for the default fb */
2165 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2166 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2167
2168 unsigned transform_y_index =
2169 _mesa_add_state_reference(this->prog->Parameters,
2170 transform_y_state);
2171
2172 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2173 transform_y_index,
2174 glsl_type::vec4_type);
2175 transform_y.swizzle = SWIZZLE_XXXX;
2176
2177 st_src_reg temp = get_temp(glsl_type::vec2_type);
2178 st_dst_reg temp_dst = st_dst_reg(temp);
2179
2180 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2181 temp_dst.writemask = WRITEMASK_Y;
2182 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2183 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2184 break;
2185 }
2186 case ir_binop_interpolate_at_sample:
2187 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2188 break;
2189
2190 case ir_unop_d2f:
2191 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2192 break;
2193 case ir_unop_f2d:
2194 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2195 break;
2196 case ir_unop_d2i:
2197 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2198 break;
2199 case ir_unop_i2d:
2200 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2201 break;
2202 case ir_unop_d2u:
2203 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2204 break;
2205 case ir_unop_u2d:
2206 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2207 break;
2208 case ir_unop_unpack_double_2x32:
2209 case ir_unop_pack_double_2x32:
2210 case ir_unop_unpack_int_2x32:
2211 case ir_unop_pack_int_2x32:
2212 case ir_unop_unpack_uint_2x32:
2213 case ir_unop_pack_uint_2x32:
2214 case ir_unop_unpack_sampler_2x32:
2215 case ir_unop_pack_sampler_2x32:
2216 case ir_unop_unpack_image_2x32:
2217 case ir_unop_pack_image_2x32:
2218 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2219 break;
2220
2221 case ir_binop_ldexp:
2222 if (ir->operands[0]->type->is_double()) {
2223 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2224 } else if (ir->operands[0]->type->is_float()) {
2225 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2226 } else {
2227 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2228 }
2229 break;
2230
2231 case ir_unop_pack_half_2x16:
2232 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2233 break;
2234 case ir_unop_unpack_half_2x16:
2235 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2236 break;
2237
2238 case ir_unop_get_buffer_size: {
2239 ir_constant *const_offset = ir->operands[0]->as_constant();
2240 st_src_reg buffer(
2241 PROGRAM_BUFFER,
2242 const_offset ? const_offset->value.u[0] : 0,
2243 GLSL_TYPE_UINT);
2244 if (!const_offset) {
2245 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2246 *buffer.reladdr = op[0];
2247 emit_arl(ir, sampler_reladdr, op[0]);
2248 }
2249 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2250 break;
2251 }
2252
2253 case ir_unop_u2i64:
2254 case ir_unop_u2u64:
2255 case ir_unop_b2i64: {
2256 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2257 st_dst_reg temp_dst = st_dst_reg(temp);
2258 unsigned orig_swz = op[0].swizzle;
2259 /*
2260 * To convert unsigned to 64-bit:
2261 * zero Y channel, copy X channel.
2262 */
2263 temp_dst.writemask = WRITEMASK_Y;
2264 if (vector_elements > 1)
2265 temp_dst.writemask |= WRITEMASK_W;
2266 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2267 temp_dst.writemask = WRITEMASK_X;
2268 if (vector_elements > 1)
2269 temp_dst.writemask |= WRITEMASK_Z;
2270 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2271 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2272 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2273 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2274 else
2275 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2276 result_src = temp;
2277 result_src.type = GLSL_TYPE_UINT64;
2278 if (vector_elements > 2) {
2279 /* Subtle: We rely on the fact that get_temp here returns the next
2280 * TGSI temporary register directly after the temp register used for
2281 * the first two components, so that the result gets picked up
2282 * automatically.
2283 */
2284 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2285 st_dst_reg temp_dst = st_dst_reg(temp);
2286 temp_dst.writemask = WRITEMASK_Y;
2287 if (vector_elements > 3)
2288 temp_dst.writemask |= WRITEMASK_W;
2289 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2290
2291 temp_dst.writemask = WRITEMASK_X;
2292 if (vector_elements > 3)
2293 temp_dst.writemask |= WRITEMASK_Z;
2294 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2295 GET_SWZ(orig_swz, 2),
2296 GET_SWZ(orig_swz, 3),
2297 GET_SWZ(orig_swz, 3));
2298 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2299 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2300 else
2301 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2302 st_src_reg_for_int(1));
2303 }
2304 break;
2305 }
2306 case ir_unop_i642i:
2307 case ir_unop_u642i:
2308 case ir_unop_u642u:
2309 case ir_unop_i642u: {
2310 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2311 st_dst_reg temp_dst = st_dst_reg(temp);
2312 unsigned orig_swz = op[0].swizzle;
2313 unsigned orig_idx = op[0].index;
2314 int el;
2315 temp_dst.writemask = WRITEMASK_X;
2316
2317 for (el = 0; el < vector_elements; el++) {
2318 unsigned swz = GET_SWZ(orig_swz, el);
2319 if (swz & 1)
2320 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2321 SWIZZLE_Z, SWIZZLE_Z);
2322 else
2323 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2324 SWIZZLE_X, SWIZZLE_X);
2325 if (swz > 2)
2326 op[0].index = orig_idx + 1;
2327 op[0].type = GLSL_TYPE_UINT;
2328 temp_dst.writemask = WRITEMASK_X << el;
2329 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2330 }
2331 result_src = temp;
2332 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2333 result_src.type = GLSL_TYPE_UINT;
2334 else
2335 result_src.type = GLSL_TYPE_INT;
2336 break;
2337 }
2338 case ir_unop_i642b:
2339 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2340 st_src_reg_for_int64(0));
2341 break;
2342 case ir_unop_i642f:
2343 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2344 break;
2345 case ir_unop_u642f:
2346 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2347 break;
2348 case ir_unop_i642d:
2349 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2350 break;
2351 case ir_unop_u642d:
2352 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2353 break;
2354 case ir_unop_i2i64:
2355 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2356 break;
2357 case ir_unop_f2i64:
2358 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2359 break;
2360 case ir_unop_d2i64:
2361 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2362 break;
2363 case ir_unop_i2u64:
2364 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2365 break;
2366 case ir_unop_f2u64:
2367 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2368 break;
2369 case ir_unop_d2u64:
2370 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2371 break;
2372 /* these might be needed */
2373 case ir_unop_pack_snorm_2x16:
2374 case ir_unop_pack_unorm_2x16:
2375 case ir_unop_pack_snorm_4x8:
2376 case ir_unop_pack_unorm_4x8:
2377
2378 case ir_unop_unpack_snorm_2x16:
2379 case ir_unop_unpack_unorm_2x16:
2380 case ir_unop_unpack_snorm_4x8:
2381 case ir_unop_unpack_unorm_4x8:
2382
2383 case ir_quadop_vector:
2384 case ir_binop_vector_extract:
2385 case ir_triop_vector_insert:
2386 case ir_binop_carry:
2387 case ir_binop_borrow:
2388 case ir_unop_ssbo_unsized_array_length:
2389 case ir_unop_atan:
2390 case ir_binop_atan2:
2391 case ir_unop_clz:
2392 case ir_binop_add_sat:
2393 case ir_binop_sub_sat:
2394 case ir_binop_abs_sub:
2395 case ir_binop_avg:
2396 case ir_binop_avg_round:
2397 case ir_binop_mul_32x16:
2398 case ir_unop_f162f:
2399 case ir_unop_f2f16:
2400 case ir_unop_f2fmp:
2401 case ir_unop_f162b:
2402 case ir_unop_b2f16:
2403 /* This operation is not supported, or should have already been handled.
2404 */
2405 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2406 break;
2407 }
2408
2409 this->result = result_src;
2410 }
2411
2412
2413 void
2414 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2415 {
2416 st_src_reg src;
2417 int i;
2418 int swizzle[4] = {0};
2419
2420 /* Note that this is only swizzles in expressions, not those on the left
2421 * hand side of an assignment, which do write masking. See ir_assignment
2422 * for that.
2423 */
2424
2425 ir->val->accept(this);
2426 src = this->result;
2427 assert(src.file != PROGRAM_UNDEFINED);
2428 assert(ir->type->vector_elements > 0);
2429
2430 for (i = 0; i < 4; i++) {
2431 if (i < ir->type->vector_elements) {
2432 switch (i) {
2433 case 0:
2434 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2435 break;
2436 case 1:
2437 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2438 break;
2439 case 2:
2440 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2441 break;
2442 case 3:
2443 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2444 break;
2445 }
2446 } else {
2447 /* If the type is smaller than a vec4, replicate the last
2448 * channel out.
2449 */
2450 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2451 }
2452 }
2453
2454 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2455
2456 this->result = src;
2457 }
2458
2459 /* Test if the variable is an array. Note that geometry and
2460 * tessellation shader inputs are outputs are always arrays (except
2461 * for patch inputs), so only the array element type is considered.
2462 */
2463 static bool
2464 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2465 {
2466 const glsl_type *type = var->type;
2467
2468 *remove_array = false;
2469
2470 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2471 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2472 return false;
2473
2474 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2475 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2476 stage == MESA_SHADER_TESS_CTRL) &&
2477 !var->data.patch) {
2478 if (!var->type->is_array())
2479 return false; /* a system value probably */
2480
2481 type = var->type->fields.array;
2482 *remove_array = true;
2483 }
2484
2485 return type->is_array() || type->is_matrix();
2486 }
2487
2488 static unsigned
2489 st_translate_interp_loc(ir_variable *var)
2490 {
2491 if (var->data.centroid)
2492 return TGSI_INTERPOLATE_LOC_CENTROID;
2493 else if (var->data.sample)
2494 return TGSI_INTERPOLATE_LOC_SAMPLE;
2495 else
2496 return TGSI_INTERPOLATE_LOC_CENTER;
2497 }
2498
2499 void
2500 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2501 {
2502 variable_storage *entry;
2503 ir_variable *var = ir->var;
2504 bool remove_array;
2505
2506 if (handle_bound_deref(ir->as_dereference()))
2507 return;
2508
2509 entry = find_variable_storage(ir->var);
2510
2511 if (!entry) {
2512 switch (var->data.mode) {
2513 case ir_var_uniform:
2514 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2515 var->data.param_index);
2516 _mesa_hash_table_insert(this->variables, var, entry);
2517 break;
2518 case ir_var_shader_in: {
2519 /* The linker assigns locations for varyings and attributes,
2520 * including deprecated builtins (like gl_Color), user-assign
2521 * generic attributes (glBindVertexLocation), and
2522 * user-defined varyings.
2523 */
2524 assert(var->data.location != -1);
2525
2526 const glsl_type *type_without_array = var->type->without_array();
2527 struct inout_decl *decl = &inputs[num_inputs];
2528 unsigned component = var->data.location_frac;
2529 unsigned num_components;
2530 num_inputs++;
2531
2532 if (type_without_array->is_64bit())
2533 component = component / 2;
2534 if (type_without_array->vector_elements)
2535 num_components = type_without_array->vector_elements;
2536 else
2537 num_components = 4;
2538
2539 decl->mesa_index = var->data.location;
2540 decl->interp = (glsl_interp_mode) var->data.interpolation;
2541 decl->interp_loc = st_translate_interp_loc(var);
2542 decl->base_type = type_without_array->base_type;
2543 decl->usage_mask = u_bit_consecutive(component, num_components);
2544
2545 if (is_inout_array(shader->Stage, var, &remove_array)) {
2546 decl->array_id = num_input_arrays + 1;
2547 num_input_arrays++;
2548 } else {
2549 decl->array_id = 0;
2550 }
2551
2552 if (remove_array)
2553 decl->size = type_size(var->type->fields.array);
2554 else
2555 decl->size = type_size(var->type);
2556
2557 entry = new(mem_ctx) variable_storage(var,
2558 PROGRAM_INPUT,
2559 decl->mesa_index,
2560 decl->array_id);
2561 entry->component = component;
2562
2563 _mesa_hash_table_insert(this->variables, var, entry);
2564
2565 break;
2566 }
2567 case ir_var_shader_out: {
2568 assert(var->data.location != -1);
2569
2570 const glsl_type *type_without_array = var->type->without_array();
2571 struct inout_decl *decl = &outputs[num_outputs];
2572 unsigned component = var->data.location_frac;
2573 unsigned num_components;
2574 num_outputs++;
2575
2576 decl->invariant = var->data.invariant;
2577
2578 if (type_without_array->is_64bit())
2579 component = component / 2;
2580 if (type_without_array->vector_elements)
2581 num_components = type_without_array->vector_elements;
2582 else
2583 num_components = 4;
2584
2585 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2586 decl->base_type = type_without_array->base_type;
2587 decl->usage_mask = u_bit_consecutive(component, num_components);
2588 if (var->data.stream & (1u << 31)) {
2589 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2590 } else {
2591 assert(var->data.stream < 4);
2592 decl->gs_out_streams = 0;
2593 for (unsigned i = 0; i < num_components; ++i)
2594 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2595 }
2596
2597 if (is_inout_array(shader->Stage, var, &remove_array)) {
2598 decl->array_id = num_output_arrays + 1;
2599 num_output_arrays++;
2600 } else {
2601 decl->array_id = 0;
2602 }
2603
2604 if (remove_array)
2605 decl->size = type_size(var->type->fields.array);
2606 else
2607 decl->size = type_size(var->type);
2608
2609 if (var->data.fb_fetch_output) {
2610 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2611 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2612 var->type, component, decl->array_id);
2613 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2614 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2615 dst.array_id);
2616 } else {
2617 entry = new(mem_ctx) variable_storage(var,
2618 PROGRAM_OUTPUT,
2619 decl->mesa_index,
2620 decl->array_id);
2621 }
2622 entry->component = component;
2623
2624 _mesa_hash_table_insert(this->variables, var, entry);
2625
2626 break;
2627 }
2628 case ir_var_system_value:
2629 entry = new(mem_ctx) variable_storage(var,
2630 PROGRAM_SYSTEM_VALUE,
2631 var->data.location);
2632 break;
2633 case ir_var_auto:
2634 case ir_var_temporary:
2635 st_src_reg src = get_temp(var->type);
2636
2637 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2638 src.array_id);
2639 _mesa_hash_table_insert(this->variables, var, entry);
2640
2641 break;
2642 }
2643
2644 if (!entry) {
2645 printf("Failed to make storage for %s\n", var->name);
2646 exit(1);
2647 }
2648 }
2649
2650 this->result = st_src_reg(entry->file, entry->index, var->type,
2651 entry->component, entry->array_id);
2652 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2653 var->data.mode == ir_var_shader_in &&
2654 var->type->without_array()->is_double())
2655 this->result.is_double_vertex_input = true;
2656 if (!native_integers)
2657 this->result.type = GLSL_TYPE_FLOAT;
2658 }
2659
2660 static void
2661 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2662 GLbitfield64* usage_mask,
2663 GLbitfield64 double_usage_mask,
2664 GLbitfield* patch_usage_mask)
2665 {
2666 unsigned i;
2667 int j;
2668
2669 /* Fix array declarations by removing unused array elements at both ends
2670 * of the arrays. For example, mat4[3] where only mat[1] is used.
2671 */
2672 for (i = 0; i < count; i++) {
2673 struct inout_decl *decl = &decls[i];
2674 if (!decl->array_id)
2675 continue;
2676
2677 /* Shrink the beginning. */
2678 for (j = 0; j < (int)decl->size; j++) {
2679 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2680 if (*patch_usage_mask &
2681 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2682 break;
2683 }
2684 else {
2685 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2686 break;
2687 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2688 break;
2689 }
2690
2691 decl->mesa_index++;
2692 decl->size--;
2693 j--;
2694 }
2695
2696 /* Shrink the end. */
2697 for (j = decl->size-1; j >= 0; j--) {
2698 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2699 if (*patch_usage_mask &
2700 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2701 break;
2702 }
2703 else {
2704 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2705 break;
2706 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2707 break;
2708 }
2709
2710 decl->size--;
2711 }
2712
2713 /* When not all entries of an array are accessed, we mark them as used
2714 * here anyway, to ensure that the input/output mapping logic doesn't get
2715 * confused.
2716 *
2717 * TODO This happens when an array isn't used via indirect access, which
2718 * some game ports do (at least eON-based). There is an optimization
2719 * opportunity here by replacing the array declaration with non-array
2720 * declarations of those slots that are actually used.
2721 */
2722 for (j = 1; j < (int)decl->size; ++j) {
2723 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2724 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2725 else
2726 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2727 }
2728 }
2729 }
2730
2731
2732 static void
2733 mark_array_io(struct inout_decl *decls, unsigned count,
2734 GLbitfield64* usage_mask,
2735 GLbitfield64 double_usage_mask,
2736 GLbitfield* patch_usage_mask)
2737 {
2738 unsigned i;
2739 int j;
2740
2741 /* Fix array declarations by removing unused array elements at both ends
2742 * of the arrays. For example, mat4[3] where only mat[1] is used.
2743 */
2744 for (i = 0; i < count; i++) {
2745 struct inout_decl *decl = &decls[i];
2746 if (!decl->array_id)
2747 continue;
2748
2749 /* When not all entries of an array are accessed, we mark them as used
2750 * here anyway, to ensure that the input/output mapping logic doesn't get
2751 * confused.
2752 *
2753 * TODO This happens when an array isn't used via indirect access, which
2754 * some game ports do (at least eON-based). There is an optimization
2755 * opportunity here by replacing the array declaration with non-array
2756 * declarations of those slots that are actually used.
2757 */
2758 for (j = 0; j < (int)decl->size; ++j) {
2759 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2760 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2761 else
2762 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2763 }
2764 }
2765 }
2766
2767 void
2768 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2769 {
2770 ir_constant *index;
2771 st_src_reg src;
2772 bool is_2D = false;
2773 ir_variable *var = ir->variable_referenced();
2774
2775 if (handle_bound_deref(ir->as_dereference()))
2776 return;
2777
2778 /* We only need the logic provided by count_vec4_slots()
2779 * for arrays of structs. Indirect sampler and image indexing is handled
2780 * elsewhere.
2781 */
2782 int element_size = ir->type->without_array()->is_struct() ?
2783 ir->type->count_vec4_slots(false, var->data.bindless) :
2784 type_size(ir->type);
2785
2786 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2787
2788 ir->array->accept(this);
2789 src = this->result;
2790
2791 if (!src.has_index2) {
2792 switch (this->prog->Target) {
2793 case GL_TESS_CONTROL_PROGRAM_NV:
2794 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2795 !ir->variable_referenced()->data.patch;
2796 break;
2797 case GL_TESS_EVALUATION_PROGRAM_NV:
2798 is_2D = src.file == PROGRAM_INPUT &&
2799 !ir->variable_referenced()->data.patch;
2800 break;
2801 case GL_GEOMETRY_PROGRAM_NV:
2802 is_2D = src.file == PROGRAM_INPUT;
2803 break;
2804 }
2805 }
2806
2807 if (is_2D)
2808 element_size = 1;
2809
2810 if (index) {
2811
2812 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2813 src.file == PROGRAM_INPUT)
2814 element_size = attrib_type_size(ir->type, true);
2815 if (is_2D) {
2816 src.index2D = index->value.i[0];
2817 src.has_index2 = true;
2818 } else
2819 src.index += index->value.i[0] * element_size;
2820 } else {
2821 /* Variable index array dereference. It eats the "vec4" of the
2822 * base of the array and an index that offsets the TGSI register
2823 * index.
2824 */
2825 ir->array_index->accept(this);
2826
2827 st_src_reg index_reg;
2828
2829 if (element_size == 1) {
2830 index_reg = this->result;
2831 } else {
2832 index_reg = get_temp(native_integers ?
2833 glsl_type::int_type : glsl_type::float_type);
2834
2835 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2836 this->result, st_src_reg_for_type(index_reg.type, element_size));
2837 }
2838
2839 /* If there was already a relative address register involved, add the
2840 * new and the old together to get the new offset.
2841 */
2842 if (!is_2D && src.reladdr != NULL) {
2843 st_src_reg accum_reg = get_temp(native_integers ?
2844 glsl_type::int_type : glsl_type::float_type);
2845
2846 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2847 index_reg, *src.reladdr);
2848
2849 index_reg = accum_reg;
2850 }
2851
2852 if (is_2D) {
2853 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2854 *src.reladdr2 = index_reg;
2855 src.index2D = 0;
2856 src.has_index2 = true;
2857 } else {
2858 src.reladdr = ralloc(mem_ctx, st_src_reg);
2859 *src.reladdr = index_reg;
2860 }
2861 }
2862
2863 /* Change the register type to the element type of the array. */
2864 src.type = ir->type->base_type;
2865
2866 this->result = src;
2867 }
2868
2869 void
2870 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2871 {
2872 unsigned int i;
2873 const glsl_type *struct_type = ir->record->type;
2874 ir_variable *var = ir->record->variable_referenced();
2875 int offset = 0;
2876
2877 if (handle_bound_deref(ir->as_dereference()))
2878 return;
2879
2880 ir->record->accept(this);
2881
2882 assert(ir->field_idx >= 0);
2883 assert(var);
2884 for (i = 0; i < struct_type->length; i++) {
2885 if (i == (unsigned) ir->field_idx)
2886 break;
2887 const glsl_type *member_type = struct_type->fields.structure[i].type;
2888 offset += member_type->count_vec4_slots(false, var->data.bindless);
2889 }
2890
2891 /* If the type is smaller than a vec4, replicate the last channel out. */
2892 if (ir->type->is_scalar() || ir->type->is_vector())
2893 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2894 else
2895 this->result.swizzle = SWIZZLE_NOOP;
2896
2897 this->result.index += offset;
2898 this->result.type = ir->type->base_type;
2899 }
2900
2901 /**
2902 * We want to be careful in assignment setup to hit the actual storage
2903 * instead of potentially using a temporary like we might with the
2904 * ir_dereference handler.
2905 */
2906 static st_dst_reg
2907 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2908 {
2909 /* The LHS must be a dereference. If the LHS is a variable indexed array
2910 * access of a vector, it must be separated into a series conditional moves
2911 * before reaching this point (see ir_vec_index_to_cond_assign).
2912 */
2913 assert(ir->as_dereference());
2914 ir_dereference_array *deref_array = ir->as_dereference_array();
2915 if (deref_array) {
2916 assert(!deref_array->array->type->is_vector());
2917 }
2918
2919 /* Use the rvalue deref handler for the most part. We write swizzles using
2920 * the writemask, but we do extract the base component for enhanced layouts
2921 * from the source swizzle.
2922 */
2923 ir->accept(v);
2924 *component = GET_SWZ(v->result.swizzle, 0);
2925 return st_dst_reg(v->result);
2926 }
2927
2928 /**
2929 * Process the condition of a conditional assignment
2930 *
2931 * Examines the condition of a conditional assignment to generate the optimal
2932 * first operand of a \c CMP instruction. If the condition is a relational
2933 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2934 * used as the source for the \c CMP instruction. Otherwise the comparison
2935 * is processed to a boolean result, and the boolean result is used as the
2936 * operand to the CMP instruction.
2937 */
2938 bool
2939 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2940 {
2941 ir_rvalue *src_ir = ir;
2942 bool negate = true;
2943 bool switch_order = false;
2944
2945 ir_expression *const expr = ir->as_expression();
2946
2947 if (native_integers) {
2948 if ((expr != NULL) && (expr->num_operands == 2)) {
2949 enum glsl_base_type type = expr->operands[0]->type->base_type;
2950 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2951 type == GLSL_TYPE_BOOL) {
2952 if (expr->operation == ir_binop_equal) {
2953 if (expr->operands[0]->is_zero()) {
2954 src_ir = expr->operands[1];
2955 switch_order = true;
2956 }
2957 else if (expr->operands[1]->is_zero()) {
2958 src_ir = expr->operands[0];
2959 switch_order = true;
2960 }
2961 }
2962 else if (expr->operation == ir_binop_nequal) {
2963 if (expr->operands[0]->is_zero()) {
2964 src_ir = expr->operands[1];
2965 }
2966 else if (expr->operands[1]->is_zero()) {
2967 src_ir = expr->operands[0];
2968 }
2969 }
2970 }
2971 }
2972
2973 src_ir->accept(this);
2974 return switch_order;
2975 }
2976
2977 if ((expr != NULL) && (expr->num_operands == 2)) {
2978 bool zero_on_left = false;
2979
2980 if (expr->operands[0]->is_zero()) {
2981 src_ir = expr->operands[1];
2982 zero_on_left = true;
2983 } else if (expr->operands[1]->is_zero()) {
2984 src_ir = expr->operands[0];
2985 zero_on_left = false;
2986 }
2987
2988 /* a is - 0 + - 0 +
2989 * (a < 0) T F F ( a < 0) T F F
2990 * (0 < a) F F T (-a < 0) F F T
2991 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2992 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2993 *
2994 * Note that exchanging the order of 0 and 'a' in the comparison simply
2995 * means that the value of 'a' should be negated.
2996 */
2997 if (src_ir != ir) {
2998 switch (expr->operation) {
2999 case ir_binop_less:
3000 switch_order = false;
3001 negate = zero_on_left;
3002 break;
3003
3004 case ir_binop_gequal:
3005 switch_order = true;
3006 negate = zero_on_left;
3007 break;
3008
3009 default:
3010 /* This isn't the right kind of comparison afterall, so make sure
3011 * the whole condition is visited.
3012 */
3013 src_ir = ir;
3014 break;
3015 }
3016 }
3017 }
3018
3019 src_ir->accept(this);
3020
3021 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3022 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3023 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3024 * computing the condition.
3025 */
3026 if (negate)
3027 this->result.negate = ~this->result.negate;
3028
3029 return switch_order;
3030 }
3031
3032 void
3033 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
3034 st_dst_reg *l, st_src_reg *r,
3035 st_src_reg *cond, bool cond_swap)
3036 {
3037 if (type->is_struct()) {
3038 for (unsigned int i = 0; i < type->length; i++) {
3039 emit_block_mov(ir, type->fields.structure[i].type, l, r,
3040 cond, cond_swap);
3041 }
3042 return;
3043 }
3044
3045 if (type->is_array()) {
3046 for (unsigned int i = 0; i < type->length; i++) {
3047 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
3048 }
3049 return;
3050 }
3051
3052 if (type->is_matrix()) {
3053 const struct glsl_type *vec_type;
3054
3055 vec_type = glsl_type::get_instance(type->is_double()
3056 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3057 type->vector_elements, 1);
3058
3059 for (int i = 0; i < type->matrix_columns; i++) {
3060 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3061 }
3062 return;
3063 }
3064
3065 assert(type->is_scalar() || type->is_vector());
3066
3067 l->type = type->base_type;
3068 r->type = type->base_type;
3069 if (cond) {
3070 st_src_reg l_src = st_src_reg(*l);
3071
3072 if (l_src.file == PROGRAM_OUTPUT &&
3073 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3074 (l_src.index == FRAG_RESULT_DEPTH ||
3075 l_src.index == FRAG_RESULT_STENCIL)) {
3076 /* This is a special case because the source swizzles will be shifted
3077 * later to account for the difference between GLSL (where they're
3078 * plain floats) and TGSI (where they're Z and Y components). */
3079 l_src.swizzle = SWIZZLE_XXXX;
3080 }
3081
3082 if (native_integers) {
3083 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3084 cond_swap ? l_src : *r,
3085 cond_swap ? *r : l_src);
3086 } else {
3087 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3088 cond_swap ? l_src : *r,
3089 cond_swap ? *r : l_src);
3090 }
3091 } else {
3092 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3093 }
3094 l->index++;
3095 r->index++;
3096 if (type->is_dual_slot()) {
3097 l->index++;
3098 if (r->is_double_vertex_input == false)
3099 r->index++;
3100 }
3101 }
3102
3103 void
3104 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3105 {
3106 int dst_component;
3107 st_dst_reg l;
3108 st_src_reg r;
3109
3110 /* all generated instructions need to be flaged as precise */
3111 this->precise = is_precise(ir->lhs->variable_referenced());
3112 ir->rhs->accept(this);
3113 r = this->result;
3114
3115 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3116
3117 {
3118 int swizzles[4];
3119 int first_enabled_chan = 0;
3120 int rhs_chan = 0;
3121 ir_variable *variable = ir->lhs->variable_referenced();
3122
3123 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3124 variable->data.mode == ir_var_shader_out &&
3125 (variable->data.location == FRAG_RESULT_DEPTH ||
3126 variable->data.location == FRAG_RESULT_STENCIL)) {
3127 assert(ir->lhs->type->is_scalar());
3128 assert(ir->write_mask == WRITEMASK_X);
3129
3130 if (variable->data.location == FRAG_RESULT_DEPTH)
3131 l.writemask = WRITEMASK_Z;
3132 else {
3133 assert(variable->data.location == FRAG_RESULT_STENCIL);
3134 l.writemask = WRITEMASK_Y;
3135 }
3136 } else if (ir->write_mask == 0) {
3137 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3138
3139 unsigned num_elements =
3140 ir->lhs->type->without_array()->vector_elements;
3141
3142 if (num_elements) {
3143 l.writemask = u_bit_consecutive(0, num_elements);
3144 } else {
3145 /* The type is a struct or an array of (array of) structs. */
3146 l.writemask = WRITEMASK_XYZW;
3147 }
3148 } else {
3149 l.writemask = ir->write_mask;
3150 }
3151
3152 for (int i = 0; i < 4; i++) {
3153 if (l.writemask & (1 << i)) {
3154 first_enabled_chan = GET_SWZ(r.swizzle, i);
3155 break;
3156 }
3157 }
3158
3159 l.writemask = l.writemask << dst_component;
3160
3161 /* Swizzle a small RHS vector into the channels being written.
3162 *
3163 * glsl ir treats write_mask as dictating how many channels are
3164 * present on the RHS while TGSI treats write_mask as just
3165 * showing which channels of the vec4 RHS get written.
3166 */
3167 for (int i = 0; i < 4; i++) {
3168 if (l.writemask & (1 << i))
3169 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3170 else
3171 swizzles[i] = first_enabled_chan;
3172 }
3173 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3174 swizzles[2], swizzles[3]);
3175 }
3176
3177 assert(l.file != PROGRAM_UNDEFINED);
3178 assert(r.file != PROGRAM_UNDEFINED);
3179
3180 if (ir->condition) {
3181 const bool switch_order = this->process_move_condition(ir->condition);
3182 st_src_reg condition = this->result;
3183
3184 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3185 } else if (ir->rhs->as_expression() &&
3186 this->instructions.get_tail() &&
3187 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3188 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3189 type_size(ir->lhs->type) == 1 &&
3190 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3191 /* To avoid emitting an extra MOV when assigning an expression to a
3192 * variable, emit the last instruction of the expression again, but
3193 * replace the destination register with the target of the assignment.
3194 * Dead code elimination will remove the original instruction.
3195 */
3196 glsl_to_tgsi_instruction *inst, *new_inst;
3197 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3198 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3199 new_inst->saturate = inst->saturate;
3200 new_inst->resource = inst->resource;
3201 inst->dead_mask = inst->dst[0].writemask;
3202 } else {
3203 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3204 }
3205 this->precise = 0;
3206 }
3207
3208
3209 void
3210 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3211 {
3212 st_src_reg src;
3213 GLdouble stack_vals[4] = { 0 };
3214 gl_constant_value *values = (gl_constant_value *) stack_vals;
3215 GLenum gl_type = GL_NONE;
3216 unsigned int i, elements;
3217 static int in_array = 0;
3218 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3219
3220 /* Unfortunately, 4 floats is all we can get into
3221 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3222 * aggregate constant and move each constant value into it. If we
3223 * get lucky, copy propagation will eliminate the extra moves.
3224 */
3225 if (ir->type->is_struct()) {
3226 st_src_reg temp_base = get_temp(ir->type);
3227 st_dst_reg temp = st_dst_reg(temp_base);
3228
3229 for (i = 0; i < ir->type->length; i++) {
3230 ir_constant *const field_value = ir->get_record_field(i);
3231 int size = type_size(field_value->type);
3232
3233 assert(size > 0);
3234
3235 field_value->accept(this);
3236 src = this->result;
3237
3238 for (unsigned j = 0; j < (unsigned int)size; j++) {
3239 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3240
3241 src.index++;
3242 temp.index++;
3243 }
3244 }
3245 this->result = temp_base;
3246 return;
3247 }
3248
3249 if (ir->type->is_array()) {
3250 st_src_reg temp_base = get_temp(ir->type);
3251 st_dst_reg temp = st_dst_reg(temp_base);
3252 int size = type_size(ir->type->fields.array);
3253
3254 assert(size > 0);
3255 in_array++;
3256
3257 for (i = 0; i < ir->type->length; i++) {
3258 ir->const_elements[i]->accept(this);
3259 src = this->result;
3260 for (int j = 0; j < size; j++) {
3261 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3262
3263 src.index++;
3264 temp.index++;
3265 }
3266 }
3267 this->result = temp_base;
3268 in_array--;
3269 return;
3270 }
3271
3272 if (ir->type->is_matrix()) {
3273 st_src_reg mat = get_temp(ir->type);
3274 st_dst_reg mat_column = st_dst_reg(mat);
3275
3276 for (i = 0; i < ir->type->matrix_columns; i++) {
3277 switch (ir->type->base_type) {
3278 case GLSL_TYPE_FLOAT:
3279 values = (gl_constant_value *)
3280 &ir->value.f[i * ir->type->vector_elements];
3281
3282 src = st_src_reg(file, -1, ir->type->base_type);
3283 src.index = add_constant(file,
3284 values,
3285 ir->type->vector_elements,
3286 GL_FLOAT,
3287 &src.swizzle);
3288 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3289 break;
3290 case GLSL_TYPE_DOUBLE:
3291 values = (gl_constant_value *)
3292 &ir->value.d[i * ir->type->vector_elements];
3293 src = st_src_reg(file, -1, ir->type->base_type);
3294 src.index = add_constant(file,
3295 values,
3296 ir->type->vector_elements,
3297 GL_DOUBLE,
3298 &src.swizzle);
3299 if (ir->type->vector_elements >= 2) {
3300 mat_column.writemask = WRITEMASK_XY;
3301 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3302 SWIZZLE_X, SWIZZLE_Y);
3303 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3304 } else {
3305 mat_column.writemask = WRITEMASK_X;
3306 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3307 SWIZZLE_X, SWIZZLE_X);
3308 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3309 }
3310 src.index++;
3311 if (ir->type->vector_elements > 2) {
3312 if (ir->type->vector_elements == 4) {
3313 mat_column.writemask = WRITEMASK_ZW;
3314 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3315 SWIZZLE_X, SWIZZLE_Y);
3316 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3317 } else {
3318 mat_column.writemask = WRITEMASK_Z;
3319 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3320 SWIZZLE_Y, SWIZZLE_Y);
3321 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3322 mat_column.writemask = WRITEMASK_XYZW;
3323 src.swizzle = SWIZZLE_XYZW;
3324 }
3325 mat_column.index++;
3326 }
3327 break;
3328 default:
3329 unreachable("Illegal matrix constant type.\n");
3330 break;
3331 }
3332 mat_column.index++;
3333 }
3334 this->result = mat;
3335 return;
3336 }
3337
3338 elements = ir->type->vector_elements;
3339 switch (ir->type->base_type) {
3340 case GLSL_TYPE_FLOAT:
3341 gl_type = GL_FLOAT;
3342 for (i = 0; i < ir->type->vector_elements; i++) {
3343 values[i].f = ir->value.f[i];
3344 }
3345 break;
3346 case GLSL_TYPE_DOUBLE:
3347 gl_type = GL_DOUBLE;
3348 for (i = 0; i < ir->type->vector_elements; i++) {
3349 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3350 }
3351 break;
3352 case GLSL_TYPE_INT64:
3353 gl_type = GL_INT64_ARB;
3354 for (i = 0; i < ir->type->vector_elements; i++) {
3355 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3356 }
3357 break;
3358 case GLSL_TYPE_UINT64:
3359 gl_type = GL_UNSIGNED_INT64_ARB;
3360 for (i = 0; i < ir->type->vector_elements; i++) {
3361 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3362 }
3363 break;
3364 case GLSL_TYPE_UINT:
3365 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3366 for (i = 0; i < ir->type->vector_elements; i++) {
3367 if (native_integers)
3368 values[i].u = ir->value.u[i];
3369 else
3370 values[i].f = ir->value.u[i];
3371 }
3372 break;
3373 case GLSL_TYPE_INT:
3374 gl_type = native_integers ? GL_INT : GL_FLOAT;
3375 for (i = 0; i < ir->type->vector_elements; i++) {
3376 if (native_integers)
3377 values[i].i = ir->value.i[i];
3378 else
3379 values[i].f = ir->value.i[i];
3380 }
3381 break;
3382 case GLSL_TYPE_BOOL:
3383 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3384 for (i = 0; i < ir->type->vector_elements; i++) {
3385 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3386 }
3387 break;
3388 case GLSL_TYPE_SAMPLER:
3389 case GLSL_TYPE_IMAGE:
3390 gl_type = GL_UNSIGNED_INT;
3391 elements = 2;
3392 values[0].u = ir->value.u64[0] & 0xffffffff;
3393 values[1].u = ir->value.u64[0] >> 32;
3394 break;
3395 default:
3396 assert(!"Non-float/uint/int/bool/sampler/image constant");
3397 }
3398
3399 this->result = st_src_reg(file, -1, ir->type);
3400 this->result.index = add_constant(file,
3401 values,
3402 elements,
3403 gl_type,
3404 &this->result.swizzle);
3405 }
3406
3407 void
3408 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3409 {
3410 exec_node *param = ir->actual_parameters.get_head();
3411 ir_dereference *deref = static_cast<ir_dereference *>(param);
3412 ir_variable *location = deref->variable_referenced();
3413 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3414 /* Calculate the surface offset */
3415 st_src_reg offset;
3416 unsigned array_size = 0, base = 0;
3417 uint16_t index = 0;
3418 st_src_reg resource;
3419
3420 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3421
3422 if (has_hw_atomics) {
3423 variable_storage *entry = find_variable_storage(location);
3424 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3425 location->data.binding);
3426
3427 if (!entry) {
3428 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3429 num_atomics);
3430 _mesa_hash_table_insert(this->variables, location, entry);
3431
3432 atomic_info[num_atomics].location = location->data.location;
3433 atomic_info[num_atomics].binding = location->data.binding;
3434 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3435 if (atomic_info[num_atomics].size == 0)
3436 atomic_info[num_atomics].size = 1;
3437 atomic_info[num_atomics].array_id = 0;
3438 num_atomics++;
3439 }
3440
3441 if (offset.file != PROGRAM_UNDEFINED) {
3442 if (atomic_info[entry->index].array_id == 0) {
3443 num_atomic_arrays++;
3444 atomic_info[entry->index].array_id = num_atomic_arrays;
3445 }
3446 buffer.array_id = atomic_info[entry->index].array_id;
3447 }
3448
3449 buffer.index = index;
3450 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3451 buffer.has_index2 = true;
3452
3453 if (offset.file != PROGRAM_UNDEFINED) {
3454 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3455 *buffer.reladdr = offset;
3456 emit_arl(ir, sampler_reladdr, offset);
3457 }
3458 offset = st_src_reg_for_int(0);
3459
3460 resource = buffer;
3461 } else {
3462 st_src_reg buffer(PROGRAM_BUFFER,
3463 prog->info.num_ssbos +
3464 location->data.binding,
3465 GLSL_TYPE_ATOMIC_UINT);
3466
3467 if (offset.file != PROGRAM_UNDEFINED) {
3468 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3469 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3470 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3471 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3472 } else {
3473 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3474 }
3475 resource = buffer;
3476 }
3477
3478 ir->return_deref->accept(this);
3479 st_dst_reg dst(this->result);
3480 dst.writemask = WRITEMASK_X;
3481
3482 glsl_to_tgsi_instruction *inst;
3483
3484 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3485 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3486 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3487 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3488 st_src_reg_for_int(1));
3489 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3490 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3491 st_src_reg_for_int(-1));
3492 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3493 } else {
3494 param = param->get_next();
3495 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3496 val->accept(this);
3497
3498 st_src_reg data = this->result, data2 = undef_src;
3499 enum tgsi_opcode opcode;
3500 switch (ir->callee->intrinsic_id) {
3501 case ir_intrinsic_atomic_counter_add:
3502 opcode = TGSI_OPCODE_ATOMUADD;
3503 break;
3504 case ir_intrinsic_atomic_counter_min:
3505 opcode = TGSI_OPCODE_ATOMIMIN;
3506 break;
3507 case ir_intrinsic_atomic_counter_max:
3508 opcode = TGSI_OPCODE_ATOMIMAX;
3509 break;
3510 case ir_intrinsic_atomic_counter_and:
3511 opcode = TGSI_OPCODE_ATOMAND;
3512 break;
3513 case ir_intrinsic_atomic_counter_or:
3514 opcode = TGSI_OPCODE_ATOMOR;
3515 break;
3516 case ir_intrinsic_atomic_counter_xor:
3517 opcode = TGSI_OPCODE_ATOMXOR;
3518 break;
3519 case ir_intrinsic_atomic_counter_exchange:
3520 opcode = TGSI_OPCODE_ATOMXCHG;
3521 break;
3522 case ir_intrinsic_atomic_counter_comp_swap: {
3523 opcode = TGSI_OPCODE_ATOMCAS;
3524 param = param->get_next();
3525 val = ((ir_instruction *)param)->as_rvalue();
3526 val->accept(this);
3527 data2 = this->result;
3528 break;
3529 }
3530 default:
3531 assert(!"Unexpected intrinsic");
3532 return;
3533 }
3534
3535 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3536 }
3537
3538 inst->resource = resource;
3539 }
3540
3541 void
3542 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3543 {
3544 exec_node *param = ir->actual_parameters.get_head();
3545
3546 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3547
3548 param = param->get_next();
3549 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3550
3551 ir_constant *const_block = block->as_constant();
3552 st_src_reg buffer(
3553 PROGRAM_BUFFER,
3554 const_block ? const_block->value.u[0] : 0,
3555 GLSL_TYPE_UINT);
3556
3557 if (!const_block) {
3558 block->accept(this);
3559 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3560 *buffer.reladdr = this->result;
3561 emit_arl(ir, sampler_reladdr, this->result);
3562 }
3563
3564 /* Calculate the surface offset */
3565 offset->accept(this);
3566 st_src_reg off = this->result;
3567
3568 st_dst_reg dst = undef_dst;
3569 if (ir->return_deref) {
3570 ir->return_deref->accept(this);
3571 dst = st_dst_reg(this->result);
3572 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3573 }
3574
3575 glsl_to_tgsi_instruction *inst;
3576
3577 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3578 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3579 if (dst.type == GLSL_TYPE_BOOL)
3580 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3581 st_src_reg_for_int(0));
3582 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3583 param = param->get_next();
3584 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3585 val->accept(this);
3586
3587 param = param->get_next();
3588 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3589 assert(write_mask);
3590 dst.writemask = write_mask->value.u[0];
3591
3592 dst.type = this->result.type;
3593 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3594 } else {
3595 param = param->get_next();
3596 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3597 val->accept(this);
3598
3599 st_src_reg data = this->result, data2 = undef_src;
3600 enum tgsi_opcode opcode;
3601 switch (ir->callee->intrinsic_id) {
3602 case ir_intrinsic_ssbo_atomic_add:
3603 opcode = TGSI_OPCODE_ATOMUADD;
3604 break;
3605 case ir_intrinsic_ssbo_atomic_min:
3606 opcode = TGSI_OPCODE_ATOMIMIN;
3607 break;
3608 case ir_intrinsic_ssbo_atomic_max:
3609 opcode = TGSI_OPCODE_ATOMIMAX;
3610 break;
3611 case ir_intrinsic_ssbo_atomic_and:
3612 opcode = TGSI_OPCODE_ATOMAND;
3613 break;
3614 case ir_intrinsic_ssbo_atomic_or:
3615 opcode = TGSI_OPCODE_ATOMOR;
3616 break;
3617 case ir_intrinsic_ssbo_atomic_xor:
3618 opcode = TGSI_OPCODE_ATOMXOR;
3619 break;
3620 case ir_intrinsic_ssbo_atomic_exchange:
3621 opcode = TGSI_OPCODE_ATOMXCHG;
3622 break;
3623 case ir_intrinsic_ssbo_atomic_comp_swap:
3624 opcode = TGSI_OPCODE_ATOMCAS;
3625 param = param->get_next();
3626 val = ((ir_instruction *)param)->as_rvalue();
3627 val->accept(this);
3628 data2 = this->result;
3629 break;
3630 default:
3631 assert(!"Unexpected intrinsic");
3632 return;
3633 }
3634
3635 inst = emit_asm(ir, opcode, dst, off, data, data2);
3636 }
3637
3638 param = param->get_next();
3639 ir_constant *access = NULL;
3640 if (!param->is_tail_sentinel()) {
3641 access = ((ir_instruction *)param)->as_constant();
3642 assert(access);
3643 }
3644
3645 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3646 }
3647
3648 void
3649 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3650 {
3651 switch (ir->callee->intrinsic_id) {
3652 case ir_intrinsic_memory_barrier:
3653 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3654 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3655 TGSI_MEMBAR_ATOMIC_BUFFER |
3656 TGSI_MEMBAR_SHADER_IMAGE |
3657 TGSI_MEMBAR_SHARED));
3658 break;
3659 case ir_intrinsic_memory_barrier_atomic_counter:
3660 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3661 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3662 break;
3663 case ir_intrinsic_memory_barrier_buffer:
3664 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3665 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3666 break;
3667 case ir_intrinsic_memory_barrier_image:
3668 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3669 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3670 break;
3671 case ir_intrinsic_memory_barrier_shared:
3672 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3673 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3674 break;
3675 case ir_intrinsic_group_memory_barrier:
3676 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3677 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3678 TGSI_MEMBAR_ATOMIC_BUFFER |
3679 TGSI_MEMBAR_SHADER_IMAGE |
3680 TGSI_MEMBAR_SHARED |
3681 TGSI_MEMBAR_THREAD_GROUP));
3682 break;
3683 default:
3684 assert(!"Unexpected memory barrier intrinsic");
3685 }
3686 }
3687
3688 void
3689 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3690 {
3691 exec_node *param = ir->actual_parameters.get_head();
3692
3693 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3694
3695 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3696
3697 /* Calculate the surface offset */
3698 offset->accept(this);
3699 st_src_reg off = this->result;
3700
3701 st_dst_reg dst = undef_dst;
3702 if (ir->return_deref) {
3703 ir->return_deref->accept(this);
3704 dst = st_dst_reg(this->result);
3705 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3706 }
3707
3708 glsl_to_tgsi_instruction *inst;
3709
3710 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3711 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3712 inst->resource = buffer;
3713 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3714 param = param->get_next();
3715 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3716 val->accept(this);
3717
3718 param = param->get_next();
3719 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3720 assert(write_mask);
3721 dst.writemask = write_mask->value.u[0];
3722
3723 dst.type = this->result.type;
3724 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3725 inst->resource = buffer;
3726 } else {
3727 param = param->get_next();
3728 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3729 val->accept(this);
3730
3731 st_src_reg data = this->result, data2 = undef_src;
3732 enum tgsi_opcode opcode;
3733 switch (ir->callee->intrinsic_id) {
3734 case ir_intrinsic_shared_atomic_add:
3735 opcode = TGSI_OPCODE_ATOMUADD;
3736 break;
3737 case ir_intrinsic_shared_atomic_min:
3738 opcode = TGSI_OPCODE_ATOMIMIN;
3739 break;
3740 case ir_intrinsic_shared_atomic_max:
3741 opcode = TGSI_OPCODE_ATOMIMAX;
3742 break;
3743 case ir_intrinsic_shared_atomic_and:
3744 opcode = TGSI_OPCODE_ATOMAND;
3745 break;
3746 case ir_intrinsic_shared_atomic_or:
3747 opcode = TGSI_OPCODE_ATOMOR;
3748 break;
3749 case ir_intrinsic_shared_atomic_xor:
3750 opcode = TGSI_OPCODE_ATOMXOR;
3751 break;
3752 case ir_intrinsic_shared_atomic_exchange:
3753 opcode = TGSI_OPCODE_ATOMXCHG;
3754 break;
3755 case ir_intrinsic_shared_atomic_comp_swap:
3756 opcode = TGSI_OPCODE_ATOMCAS;
3757 param = param->get_next();
3758 val = ((ir_instruction *)param)->as_rvalue();
3759 val->accept(this);
3760 data2 = this->result;
3761 break;
3762 default:
3763 assert(!"Unexpected intrinsic");
3764 return;
3765 }
3766
3767 inst = emit_asm(ir, opcode, dst, off, data, data2);
3768 inst->resource = buffer;
3769 }
3770 }
3771
3772 static void
3773 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3774 bool *memory_coherent, bool *memory_volatile,
3775 bool *memory_restrict, bool *memory_read_only,
3776 enum pipe_format *image_format)
3777 {
3778
3779 switch (ir->ir_type) {
3780 case ir_type_dereference_record: {
3781 ir_dereference_record *deref_record = ir->as_dereference_record();
3782 const glsl_type *struct_type = deref_record->record->type;
3783 int fild_idx = deref_record->field_idx;
3784
3785 *type = struct_type->fields.structure[fild_idx].type->without_array();
3786 *memory_coherent =
3787 struct_type->fields.structure[fild_idx].memory_coherent;
3788 *memory_volatile =
3789 struct_type->fields.structure[fild_idx].memory_volatile;
3790 *memory_restrict =
3791 struct_type->fields.structure[fild_idx].memory_restrict;
3792 *memory_read_only =
3793 struct_type->fields.structure[fild_idx].memory_read_only;
3794 *image_format =
3795 struct_type->fields.structure[fild_idx].image_format;
3796 break;
3797 }
3798
3799 case ir_type_dereference_array: {
3800 ir_dereference_array *deref_arr = ir->as_dereference_array();
3801 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3802 memory_coherent, memory_volatile, memory_restrict,
3803 memory_read_only, image_format);
3804 break;
3805 }
3806
3807 case ir_type_dereference_variable: {
3808 ir_variable *var = ir->variable_referenced();
3809
3810 *type = var->type->without_array();
3811 *memory_coherent = var->data.memory_coherent;
3812 *memory_volatile = var->data.memory_volatile;
3813 *memory_restrict = var->data.memory_restrict;
3814 *memory_read_only = var->data.memory_read_only;
3815 *image_format = var->data.image_format;
3816 break;
3817 }
3818
3819 default:
3820 break;
3821 }
3822 }
3823
3824 void
3825 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3826 {
3827 exec_node *param = ir->actual_parameters.get_head();
3828
3829 ir_dereference *img = (ir_dereference *)param;
3830 const ir_variable *imgvar = img->variable_referenced();
3831 unsigned sampler_array_size = 1, sampler_base = 0;
3832 bool memory_coherent = false, memory_volatile = false,
3833 memory_restrict = false, memory_read_only = false;
3834 enum pipe_format image_format = PIPE_FORMAT_NONE;
3835 const glsl_type *type = NULL;
3836
3837 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3838 &memory_restrict, &memory_read_only, &image_format);
3839
3840 st_src_reg reladdr;
3841 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3842 uint16_t index = 0;
3843 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3844 &index, &reladdr, !imgvar->contains_bindless());
3845
3846 image.index = index;
3847 if (reladdr.file != PROGRAM_UNDEFINED) {
3848 image.reladdr = ralloc(mem_ctx, st_src_reg);
3849 *image.reladdr = reladdr;
3850 emit_arl(ir, sampler_reladdr, reladdr);
3851 }
3852
3853 st_dst_reg dst = undef_dst;
3854 if (ir->return_deref) {
3855 ir->return_deref->accept(this);
3856 dst = st_dst_reg(this->result);
3857 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3858 }
3859
3860 glsl_to_tgsi_instruction *inst;
3861
3862 st_src_reg bindless;
3863 if (imgvar->contains_bindless()) {
3864 img->accept(this);
3865 bindless = this->result;
3866 }
3867
3868 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3869 dst.writemask = WRITEMASK_XYZ;
3870 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3871 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3872 st_src_reg res = get_temp(glsl_type::ivec4_type);
3873 st_dst_reg dstres = st_dst_reg(res);
3874 dstres.writemask = WRITEMASK_W;
3875 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3876 res.swizzle = SWIZZLE_WWWW;
3877 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3878 } else {
3879 st_src_reg arg1 = undef_src, arg2 = undef_src;
3880 st_src_reg coord;
3881 st_dst_reg coord_dst;
3882 coord = get_temp(glsl_type::ivec4_type);
3883 coord_dst = st_dst_reg(coord);
3884 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3885 param = param->get_next();
3886 ((ir_dereference *)param)->accept(this);
3887 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3888 coord.swizzle = SWIZZLE_XXXX;
3889 switch (type->coordinate_components()) {
3890 case 4: assert(!"unexpected coord count");
3891 /* fallthrough */
3892 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3893 /* fallthrough */
3894 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3895 }
3896
3897 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3898 param = param->get_next();
3899 ((ir_dereference *)param)->accept(this);
3900 st_src_reg sample = this->result;
3901 sample.swizzle = SWIZZLE_XXXX;
3902 coord_dst.writemask = WRITEMASK_W;
3903 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3904 coord.swizzle |= SWIZZLE_W << 9;
3905 }
3906
3907 param = param->get_next();
3908 if (!param->is_tail_sentinel()) {
3909 ((ir_dereference *)param)->accept(this);
3910 arg1 = this->result;
3911 param = param->get_next();
3912 }
3913
3914 if (!param->is_tail_sentinel()) {
3915 ((ir_dereference *)param)->accept(this);
3916 arg2 = this->result;
3917 param = param->get_next();
3918 }
3919
3920 assert(param->is_tail_sentinel());
3921
3922 enum tgsi_opcode opcode;
3923 switch (ir->callee->intrinsic_id) {
3924 case ir_intrinsic_image_load:
3925 opcode = TGSI_OPCODE_LOAD;
3926 break;
3927 case ir_intrinsic_image_store:
3928 opcode = TGSI_OPCODE_STORE;
3929 break;
3930 case ir_intrinsic_image_atomic_add:
3931 opcode = TGSI_OPCODE_ATOMUADD;
3932 break;
3933 case ir_intrinsic_image_atomic_min:
3934 opcode = TGSI_OPCODE_ATOMIMIN;
3935 break;
3936 case ir_intrinsic_image_atomic_max:
3937 opcode = TGSI_OPCODE_ATOMIMAX;
3938 break;
3939 case ir_intrinsic_image_atomic_and:
3940 opcode = TGSI_OPCODE_ATOMAND;
3941 break;
3942 case ir_intrinsic_image_atomic_or:
3943 opcode = TGSI_OPCODE_ATOMOR;
3944 break;
3945 case ir_intrinsic_image_atomic_xor:
3946 opcode = TGSI_OPCODE_ATOMXOR;
3947 break;
3948 case ir_intrinsic_image_atomic_exchange:
3949 opcode = TGSI_OPCODE_ATOMXCHG;
3950 break;
3951 case ir_intrinsic_image_atomic_comp_swap:
3952 opcode = TGSI_OPCODE_ATOMCAS;
3953 break;
3954 case ir_intrinsic_image_atomic_inc_wrap: {
3955 /* There's a bit of disagreement between GLSL and the hardware. The
3956 * hardware wants to wrap after the given wrap value, while GLSL
3957 * wants to wrap at the value. Subtract 1 to make up the difference.
3958 */
3959 st_src_reg wrap = get_temp(glsl_type::uint_type);
3960 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(wrap),
3961 arg1, st_src_reg_for_int(-1));
3962 arg1 = wrap;
3963 opcode = TGSI_OPCODE_ATOMINC_WRAP;
3964 break;
3965 }
3966 case ir_intrinsic_image_atomic_dec_wrap:
3967 opcode = TGSI_OPCODE_ATOMDEC_WRAP;
3968 break;
3969 default:
3970 assert(!"Unexpected intrinsic");
3971 return;
3972 }
3973
3974 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3975 if (opcode == TGSI_OPCODE_STORE)
3976 inst->dst[0].writemask = WRITEMASK_XYZW;
3977 }
3978
3979 if (imgvar->contains_bindless()) {
3980 inst->resource = bindless;
3981 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3982 SWIZZLE_X, SWIZZLE_Y);
3983 } else {
3984 inst->resource = image;
3985 inst->sampler_array_size = sampler_array_size;
3986 inst->sampler_base = sampler_base;
3987 }
3988
3989 inst->tex_target = type->sampler_index();
3990 inst->image_format = image_format;
3991 inst->read_only = memory_read_only;
3992
3993 if (memory_coherent)
3994 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3995 if (memory_restrict)
3996 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3997 if (memory_volatile)
3998 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3999 }
4000
4001 void
4002 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
4003 {
4004 ir->return_deref->accept(this);
4005 st_dst_reg dst = st_dst_reg(this->result);
4006
4007 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
4008
4009 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
4010 unsigned num_src = 0;
4011 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
4012 assert(num_src < ARRAY_SIZE(src));
4013
4014 this->result.file = PROGRAM_UNDEFINED;
4015 param->accept(this);
4016 assert(this->result.file != PROGRAM_UNDEFINED);
4017
4018 src[num_src] = this->result;
4019 num_src++;
4020 }
4021
4022 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
4023 }
4024
4025 void
4026 glsl_to_tgsi_visitor::visit(ir_call *ir)
4027 {
4028 ir_function_signature *sig = ir->callee;
4029
4030 /* Filter out intrinsics */
4031 switch (sig->intrinsic_id) {
4032 case ir_intrinsic_atomic_counter_read:
4033 case ir_intrinsic_atomic_counter_increment:
4034 case ir_intrinsic_atomic_counter_predecrement:
4035 case ir_intrinsic_atomic_counter_add:
4036 case ir_intrinsic_atomic_counter_min:
4037 case ir_intrinsic_atomic_counter_max:
4038 case ir_intrinsic_atomic_counter_and:
4039 case ir_intrinsic_atomic_counter_or:
4040 case ir_intrinsic_atomic_counter_xor:
4041 case ir_intrinsic_atomic_counter_exchange:
4042 case ir_intrinsic_atomic_counter_comp_swap:
4043 visit_atomic_counter_intrinsic(ir);
4044 return;
4045
4046 case ir_intrinsic_ssbo_load:
4047 case ir_intrinsic_ssbo_store:
4048 case ir_intrinsic_ssbo_atomic_add:
4049 case ir_intrinsic_ssbo_atomic_min:
4050 case ir_intrinsic_ssbo_atomic_max:
4051 case ir_intrinsic_ssbo_atomic_and:
4052 case ir_intrinsic_ssbo_atomic_or:
4053 case ir_intrinsic_ssbo_atomic_xor:
4054 case ir_intrinsic_ssbo_atomic_exchange:
4055 case ir_intrinsic_ssbo_atomic_comp_swap:
4056 visit_ssbo_intrinsic(ir);
4057 return;
4058
4059 case ir_intrinsic_memory_barrier:
4060 case ir_intrinsic_memory_barrier_atomic_counter:
4061 case ir_intrinsic_memory_barrier_buffer:
4062 case ir_intrinsic_memory_barrier_image:
4063 case ir_intrinsic_memory_barrier_shared:
4064 case ir_intrinsic_group_memory_barrier:
4065 visit_membar_intrinsic(ir);
4066 return;
4067
4068 case ir_intrinsic_shared_load:
4069 case ir_intrinsic_shared_store:
4070 case ir_intrinsic_shared_atomic_add:
4071 case ir_intrinsic_shared_atomic_min:
4072 case ir_intrinsic_shared_atomic_max:
4073 case ir_intrinsic_shared_atomic_and:
4074 case ir_intrinsic_shared_atomic_or:
4075 case ir_intrinsic_shared_atomic_xor:
4076 case ir_intrinsic_shared_atomic_exchange:
4077 case ir_intrinsic_shared_atomic_comp_swap:
4078 visit_shared_intrinsic(ir);
4079 return;
4080
4081 case ir_intrinsic_image_load:
4082 case ir_intrinsic_image_store:
4083 case ir_intrinsic_image_atomic_add:
4084 case ir_intrinsic_image_atomic_min:
4085 case ir_intrinsic_image_atomic_max:
4086 case ir_intrinsic_image_atomic_and:
4087 case ir_intrinsic_image_atomic_or:
4088 case ir_intrinsic_image_atomic_xor:
4089 case ir_intrinsic_image_atomic_exchange:
4090 case ir_intrinsic_image_atomic_comp_swap:
4091 case ir_intrinsic_image_size:
4092 case ir_intrinsic_image_samples:
4093 case ir_intrinsic_image_atomic_inc_wrap:
4094 case ir_intrinsic_image_atomic_dec_wrap:
4095 visit_image_intrinsic(ir);
4096 return;
4097
4098 case ir_intrinsic_shader_clock:
4099 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4100 return;
4101
4102 case ir_intrinsic_vote_all:
4103 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4104 return;
4105 case ir_intrinsic_vote_any:
4106 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4107 return;
4108 case ir_intrinsic_vote_eq:
4109 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4110 return;
4111 case ir_intrinsic_ballot:
4112 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4113 return;
4114 case ir_intrinsic_read_first_invocation:
4115 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4116 return;
4117 case ir_intrinsic_read_invocation:
4118 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4119 return;
4120
4121 case ir_intrinsic_helper_invocation:
4122 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_HELPER);
4123 return;
4124
4125 case ir_intrinsic_invalid:
4126 case ir_intrinsic_generic_load:
4127 case ir_intrinsic_generic_store:
4128 case ir_intrinsic_generic_atomic_add:
4129 case ir_intrinsic_generic_atomic_and:
4130 case ir_intrinsic_generic_atomic_or:
4131 case ir_intrinsic_generic_atomic_xor:
4132 case ir_intrinsic_generic_atomic_min:
4133 case ir_intrinsic_generic_atomic_max:
4134 case ir_intrinsic_generic_atomic_exchange:
4135 case ir_intrinsic_generic_atomic_comp_swap:
4136 case ir_intrinsic_begin_invocation_interlock:
4137 case ir_intrinsic_end_invocation_interlock:
4138 unreachable("Invalid intrinsic");
4139 }
4140 }
4141
4142 void
4143 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4144 unsigned *array_elements,
4145 uint16_t *index,
4146 st_src_reg *indirect,
4147 unsigned *location)
4148 {
4149 switch (tail->ir_type) {
4150 case ir_type_dereference_record: {
4151 ir_dereference_record *deref_record = tail->as_dereference_record();
4152 const glsl_type *struct_type = deref_record->record->type;
4153 int field_index = deref_record->field_idx;
4154
4155 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4156
4157 assert(field_index >= 0);
4158 *location += struct_type->struct_location_offset(field_index);
4159 break;
4160 }
4161
4162 case ir_type_dereference_array: {
4163 ir_dereference_array *deref_arr = tail->as_dereference_array();
4164
4165 void *mem_ctx = ralloc_parent(deref_arr);
4166 ir_constant *array_index =
4167 deref_arr->array_index->constant_expression_value(mem_ctx);
4168
4169 if (!array_index) {
4170 st_src_reg temp_reg;
4171 st_dst_reg temp_dst;
4172
4173 temp_reg = get_temp(glsl_type::uint_type);
4174 temp_dst = st_dst_reg(temp_reg);
4175 temp_dst.writemask = 1;
4176
4177 deref_arr->array_index->accept(this);
4178 if (*array_elements != 1)
4179 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4180 else
4181 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4182
4183 if (indirect->file == PROGRAM_UNDEFINED)
4184 *indirect = temp_reg;
4185 else {
4186 temp_dst = st_dst_reg(*indirect);
4187 temp_dst.writemask = 1;
4188 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4189 }
4190 } else
4191 *index += array_index->value.u[0] * *array_elements;
4192
4193 *array_elements *= deref_arr->array->type->length;
4194
4195 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4196 break;
4197 }
4198 default:
4199 break;
4200 }
4201 }
4202
4203 void
4204 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4205 unsigned *array_size,
4206 unsigned *base,
4207 uint16_t *index,
4208 st_src_reg *reladdr,
4209 bool opaque)
4210 {
4211 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4212 unsigned location = 0;
4213 ir_variable *var = ir->variable_referenced();
4214
4215 reladdr->reset();
4216
4217 *base = 0;
4218 *array_size = 1;
4219
4220 assert(var);
4221 location = var->data.location;
4222 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4223
4224 /*
4225 * If we end up with no indirect then adjust the base to the index,
4226 * and set the array size to 1.
4227 */
4228 if (reladdr->file == PROGRAM_UNDEFINED) {
4229 *base = *index;
4230 *array_size = 1;
4231 }
4232
4233 if (opaque) {
4234 assert(location != 0xffffffff);
4235 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4236 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4237 }
4238 }
4239
4240 st_src_reg
4241 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4242 {
4243 if (offset.reladdr || offset.reladdr2 ||
4244 offset.has_index2 ||
4245 offset.file == PROGRAM_UNIFORM ||
4246 offset.file == PROGRAM_CONSTANT ||
4247 offset.file == PROGRAM_STATE_VAR) {
4248 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4249 st_dst_reg tmp_dst = st_dst_reg(tmp);
4250 tmp_dst.writemask = WRITEMASK_XY;
4251 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4252 return tmp;
4253 }
4254
4255 return offset;
4256 }
4257
4258 bool
4259 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4260 {
4261 ir_variable *var = ir->variable_referenced();
4262
4263 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4264 !(ir->type->is_image() || ir->type->is_sampler()))
4265 return false;
4266
4267 /* Convert from bound sampler/image to bindless handle. */
4268 bool is_image = ir->type->is_image();
4269 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4270 uint16_t index = 0;
4271 unsigned array_size = 1, base = 0;
4272 st_src_reg reladdr;
4273 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4274
4275 resource.index = index;
4276 if (reladdr.file != PROGRAM_UNDEFINED) {
4277 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4278 *resource.reladdr = reladdr;
4279 emit_arl(ir, sampler_reladdr, reladdr);
4280 }
4281
4282 this->result = get_temp(glsl_type::uvec2_type);
4283 st_dst_reg dst(this->result);
4284 dst.writemask = WRITEMASK_XY;
4285
4286 glsl_to_tgsi_instruction *inst = emit_asm(
4287 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4288
4289 inst->tex_target = ir->type->sampler_index();
4290 inst->resource = resource;
4291 inst->sampler_array_size = array_size;
4292 inst->sampler_base = base;
4293
4294 return true;
4295 }
4296
4297 void
4298 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4299 {
4300 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4301 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4302 st_src_reg levels_src, reladdr;
4303 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4304 glsl_to_tgsi_instruction *inst = NULL;
4305 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4306 const glsl_type *sampler_type = ir->sampler->type;
4307 unsigned sampler_array_size = 1, sampler_base = 0;
4308 bool is_cube_array = false;
4309 ir_variable *var = ir->sampler->variable_referenced();
4310 unsigned i;
4311
4312 /* if we are a cube array sampler or a cube shadow */
4313 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4314 is_cube_array = sampler_type->sampler_array;
4315 }
4316
4317 if (ir->coordinate) {
4318 ir->coordinate->accept(this);
4319
4320 /* Put our coords in a temp. We'll need to modify them for shadow,
4321 * projection, or LOD, so the only case we'd use it as-is is if
4322 * we're doing plain old texturing. The optimization passes on
4323 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4324 */
4325 coord = get_temp(glsl_type::vec4_type);
4326 coord_dst = st_dst_reg(coord);
4327 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4328 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4329 }
4330
4331 if (ir->projector) {
4332 ir->projector->accept(this);
4333 projector = this->result;
4334 }
4335
4336 /* Storage for our result. Ideally for an assignment we'd be using
4337 * the actual storage for the result here, instead.
4338 */
4339 result_src = get_temp(ir->type);
4340 result_dst = st_dst_reg(result_src);
4341 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4342
4343 switch (ir->op) {
4344 case ir_tex:
4345 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4346 if (ir->offset) {
4347 ir->offset->accept(this);
4348 offset[0] = this->result;
4349 }
4350 break;
4351 case ir_txb:
4352 if (is_cube_array ||
4353 (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) {
4354 opcode = TGSI_OPCODE_TXB2;
4355 }
4356 else {
4357 opcode = TGSI_OPCODE_TXB;
4358 }
4359 ir->lod_info.bias->accept(this);
4360 lod_info = this->result;
4361 if (ir->offset) {
4362 ir->offset->accept(this);
4363 offset[0] = this->result;
4364 }
4365 break;
4366 case ir_txl:
4367 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4368 opcode = TGSI_OPCODE_TEX_LZ;
4369 } else {
4370 opcode = (is_cube_array || (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4371 ir->lod_info.lod->accept(this);
4372 lod_info = this->result;
4373 }
4374 if (ir->offset) {
4375 ir->offset->accept(this);
4376 offset[0] = this->result;
4377 }
4378 break;
4379 case ir_txd:
4380 opcode = TGSI_OPCODE_TXD;
4381 ir->lod_info.grad.dPdx->accept(this);
4382 dx = this->result;
4383 ir->lod_info.grad.dPdy->accept(this);
4384 dy = this->result;
4385 if (ir->offset) {
4386 ir->offset->accept(this);
4387 offset[0] = this->result;
4388 }
4389 break;
4390 case ir_txs:
4391 opcode = TGSI_OPCODE_TXQ;
4392 ir->lod_info.lod->accept(this);
4393 lod_info = this->result;
4394 break;
4395 case ir_query_levels:
4396 opcode = TGSI_OPCODE_TXQ;
4397 lod_info = undef_src;
4398 levels_src = get_temp(ir->type);
4399 break;
4400 case ir_txf:
4401 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4402 opcode = TGSI_OPCODE_TXF_LZ;
4403 } else {
4404 opcode = TGSI_OPCODE_TXF;
4405 ir->lod_info.lod->accept(this);
4406 lod_info = this->result;
4407 }
4408 if (ir->offset) {
4409 ir->offset->accept(this);
4410 offset[0] = this->result;
4411 }
4412 break;
4413 case ir_txf_ms:
4414 opcode = TGSI_OPCODE_TXF;
4415 ir->lod_info.sample_index->accept(this);
4416 sample_index = this->result;
4417 break;
4418 case ir_tg4:
4419 opcode = TGSI_OPCODE_TG4;
4420 ir->lod_info.component->accept(this);
4421 component = this->result;
4422 if (ir->offset) {
4423 ir->offset->accept(this);
4424 if (ir->offset->type->is_array()) {
4425 const glsl_type *elt_type = ir->offset->type->fields.array;
4426 for (i = 0; i < ir->offset->type->length; i++) {
4427 offset[i] = this->result;
4428 offset[i].index += i * type_size(elt_type);
4429 offset[i].type = elt_type->base_type;
4430 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4431 offset[i] = canonicalize_gather_offset(offset[i]);
4432 }
4433 } else {
4434 offset[0] = canonicalize_gather_offset(this->result);
4435 }
4436 }
4437 break;
4438 case ir_lod:
4439 opcode = TGSI_OPCODE_LODQ;
4440 break;
4441 case ir_texture_samples:
4442 opcode = TGSI_OPCODE_TXQS;
4443 break;
4444 case ir_samples_identical:
4445 unreachable("Unexpected ir_samples_identical opcode");
4446 }
4447
4448 if (ir->projector) {
4449 if (opcode == TGSI_OPCODE_TEX) {
4450 /* Slot the projector in as the last component of the coord. */
4451 coord_dst.writemask = WRITEMASK_W;
4452 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4453 coord_dst.writemask = WRITEMASK_XYZW;
4454 opcode = TGSI_OPCODE_TXP;
4455 } else {
4456 st_src_reg coord_w = coord;
4457 coord_w.swizzle = SWIZZLE_WWWW;
4458
4459 /* For the other TEX opcodes there's no projective version
4460 * since the last slot is taken up by LOD info. Do the
4461 * projective divide now.
4462 */
4463 coord_dst.writemask = WRITEMASK_W;
4464 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4465
4466 /* In the case where we have to project the coordinates "by hand,"
4467 * the shadow comparator value must also be projected.
4468 */
4469 st_src_reg tmp_src = coord;
4470 if (ir->shadow_comparator) {
4471 /* Slot the shadow value in as the second to last component of the
4472 * coord.
4473 */
4474 ir->shadow_comparator->accept(this);
4475
4476 tmp_src = get_temp(glsl_type::vec4_type);
4477 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4478
4479 /* Projective division not allowed for array samplers. */
4480 assert(!sampler_type->sampler_array);
4481
4482 tmp_dst.writemask = WRITEMASK_Z;
4483 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4484
4485 tmp_dst.writemask = WRITEMASK_XY;
4486 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4487 }
4488
4489 coord_dst.writemask = WRITEMASK_XYZ;
4490 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4491
4492 coord_dst.writemask = WRITEMASK_XYZW;
4493 coord.swizzle = SWIZZLE_XYZW;
4494 }
4495 }
4496
4497 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4498 * shadow comparator was put in the correct place (and projected) by the
4499 * code, above, that handles by-hand projection.
4500 */
4501 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4502 /* Slot the shadow value in as the second to last component of the
4503 * coord.
4504 */
4505 ir->shadow_comparator->accept(this);
4506
4507 if (is_cube_array) {
4508 if (lod_info.file != PROGRAM_UNDEFINED) {
4509 // If we have both a cube array *and* a bias/lod, stick the
4510 // comparator into the .Y of the second argument.
4511 st_src_reg tmp = get_temp(glsl_type::vec2_type);
4512 cube_sc_dst = st_dst_reg(tmp);
4513 cube_sc_dst.writemask = WRITEMASK_X;
4514 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, lod_info);
4515 lod_info = tmp;
4516 cube_sc_dst.writemask = WRITEMASK_Y;
4517 } else {
4518 cube_sc = get_temp(glsl_type::float_type);
4519 cube_sc_dst = st_dst_reg(cube_sc);
4520 cube_sc_dst.writemask = WRITEMASK_X;
4521 }
4522 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4523 }
4524 else {
4525 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4526 sampler_type->sampler_array) ||
4527 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4528 coord_dst.writemask = WRITEMASK_W;
4529 } else {
4530 coord_dst.writemask = WRITEMASK_Z;
4531 }
4532 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4533 coord_dst.writemask = WRITEMASK_XYZW;
4534 }
4535 }
4536
4537 if (ir->op == ir_txf_ms) {
4538 coord_dst.writemask = WRITEMASK_W;
4539 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4540 coord_dst.writemask = WRITEMASK_XYZW;
4541 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4542 opcode == TGSI_OPCODE_TXF) {
4543 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4544 coord_dst.writemask = WRITEMASK_W;
4545 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4546 coord_dst.writemask = WRITEMASK_XYZW;
4547 }
4548
4549 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4550
4551 uint16_t index = 0;
4552 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4553 &index, &reladdr, !var->contains_bindless());
4554
4555 sampler.index = index;
4556 if (reladdr.file != PROGRAM_UNDEFINED) {
4557 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4558 *sampler.reladdr = reladdr;
4559 emit_arl(ir, sampler_reladdr, reladdr);
4560 }
4561
4562 st_src_reg bindless;
4563 if (var->contains_bindless()) {
4564 ir->sampler->accept(this);
4565 bindless = this->result;
4566 }
4567
4568 if (opcode == TGSI_OPCODE_TXD)
4569 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4570 else if (opcode == TGSI_OPCODE_TXQ) {
4571 if (ir->op == ir_query_levels) {
4572 /* the level is stored in W */
4573 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4574 result_dst.writemask = WRITEMASK_X;
4575 levels_src.swizzle = SWIZZLE_WWWW;
4576 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4577 } else
4578 inst = emit_asm(ir, opcode, result_dst, lod_info);
4579 } else if (opcode == TGSI_OPCODE_TXQS) {
4580 inst = emit_asm(ir, opcode, result_dst);
4581 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4582 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4583 } else if (opcode == TGSI_OPCODE_TEX2) {
4584 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4585 } else if (opcode == TGSI_OPCODE_TG4) {
4586 if (is_cube_array && ir->shadow_comparator) {
4587 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4588 } else {
4589 if (this->tg4_component_in_swizzle) {
4590 inst = emit_asm(ir, opcode, result_dst, coord);
4591 int idx = 0;
4592 foreach_in_list(immediate_storage, entry, &this->immediates) {
4593 if (component.index == idx) {
4594 gl_constant_value value = entry->values[component.swizzle];
4595 inst->gather_component = value.i;
4596 break;
4597 }
4598 idx++;
4599 }
4600 } else {
4601 inst = emit_asm(ir, opcode, result_dst, coord, component);
4602 }
4603 }
4604 } else
4605 inst = emit_asm(ir, opcode, result_dst, coord);
4606
4607 if (ir->shadow_comparator)
4608 inst->tex_shadow = GL_TRUE;
4609
4610 if (var->contains_bindless()) {
4611 inst->resource = bindless;
4612 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4613 SWIZZLE_X, SWIZZLE_Y);
4614 } else {
4615 inst->resource = sampler;
4616 inst->sampler_array_size = sampler_array_size;
4617 inst->sampler_base = sampler_base;
4618 }
4619
4620 if (ir->offset) {
4621 if (!inst->tex_offsets)
4622 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4623 MAX_GLSL_TEXTURE_OFFSET);
4624
4625 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4626 offset[i].file != PROGRAM_UNDEFINED; i++)
4627 inst->tex_offsets[i] = offset[i];
4628 inst->tex_offset_num_offset = i;
4629 }
4630
4631 inst->tex_target = sampler_type->sampler_index();
4632 inst->tex_type = ir->type->base_type;
4633
4634 this->result = result_src;
4635 }
4636
4637 void
4638 glsl_to_tgsi_visitor::visit(ir_return *ir)
4639 {
4640 assert(!ir->get_value());
4641
4642 emit_asm(ir, TGSI_OPCODE_RET);
4643 }
4644
4645 void
4646 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4647 {
4648 if (ir->condition) {
4649 ir->condition->accept(this);
4650 st_src_reg condition = this->result;
4651
4652 /* Convert the bool condition to a float so we can negate. */
4653 if (native_integers) {
4654 st_src_reg temp = get_temp(ir->condition->type);
4655 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4656 condition, st_src_reg_for_float(1.0));
4657 condition = temp;
4658 }
4659
4660 condition.negate = ~condition.negate;
4661 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4662 } else {
4663 /* unconditional kil */
4664 emit_asm(ir, TGSI_OPCODE_KILL);
4665 }
4666 }
4667
4668 void
4669 glsl_to_tgsi_visitor::visit(ir_demote *ir)
4670 {
4671 emit_asm(ir, TGSI_OPCODE_DEMOTE);
4672 }
4673
4674 void
4675 glsl_to_tgsi_visitor::visit(ir_if *ir)
4676 {
4677 enum tgsi_opcode if_opcode;
4678 glsl_to_tgsi_instruction *if_inst;
4679
4680 ir->condition->accept(this);
4681 assert(this->result.file != PROGRAM_UNDEFINED);
4682
4683 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4684
4685 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4686
4687 this->instructions.push_tail(if_inst);
4688
4689 visit_exec_list(&ir->then_instructions, this);
4690
4691 if (!ir->else_instructions.is_empty()) {
4692 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4693 visit_exec_list(&ir->else_instructions, this);
4694 }
4695
4696 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4697 }
4698
4699
4700 void
4701 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4702 {
4703 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4704
4705 ir->stream->accept(this);
4706 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4707 }
4708
4709 void
4710 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4711 {
4712 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4713
4714 ir->stream->accept(this);
4715 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4716 }
4717
4718 void
4719 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4720 {
4721 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4722 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4723
4724 emit_asm(ir, TGSI_OPCODE_BARRIER);
4725 }
4726
4727 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4728 {
4729 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4730
4731 result.file = PROGRAM_UNDEFINED;
4732 next_temp = 1;
4733 array_sizes = NULL;
4734 max_num_arrays = 0;
4735 next_array = 0;
4736 num_inputs = 0;
4737 num_outputs = 0;
4738 num_input_arrays = 0;
4739 num_output_arrays = 0;
4740 num_atomics = 0;
4741 num_atomic_arrays = 0;
4742 num_immediates = 0;
4743 num_address_regs = 0;
4744 samplers_used = 0;
4745 images_used = 0;
4746 indirect_addr_consts = false;
4747 wpos_transform_const = -1;
4748 native_integers = false;
4749 mem_ctx = ralloc_context(NULL);
4750 ctx = NULL;
4751 prog = NULL;
4752 precise = 0;
4753 need_uarl = false;
4754 tg4_component_in_swizzle = false;
4755 shader_program = NULL;
4756 shader = NULL;
4757 options = NULL;
4758 have_sqrt = false;
4759 have_fma = false;
4760 use_shared_memory = false;
4761 has_tex_txf_lz = false;
4762 variables = NULL;
4763 }
4764
4765 static void var_destroy(struct hash_entry *entry)
4766 {
4767 variable_storage *storage = (variable_storage *)entry->data;
4768
4769 delete storage;
4770 }
4771
4772 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4773 {
4774 _mesa_hash_table_destroy(variables, var_destroy);
4775 free(array_sizes);
4776 ralloc_free(mem_ctx);
4777 }
4778
4779 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4780 {
4781 delete v;
4782 }
4783
4784
4785 /**
4786 * Count resources used by the given gpu program (number of texture
4787 * samplers, etc).
4788 */
4789 static void
4790 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4791 {
4792 v->samplers_used = 0;
4793 v->images_used = 0;
4794 prog->info.textures_used_by_txf = 0;
4795
4796 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4797 if (inst->info->is_tex) {
4798 for (int i = 0; i < inst->sampler_array_size; i++) {
4799 unsigned idx = inst->sampler_base + i;
4800 v->samplers_used |= 1u << idx;
4801
4802 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4803 v->sampler_types[idx] = inst->tex_type;
4804 v->sampler_targets[idx] =
4805 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4806
4807 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4808 prog->info.textures_used_by_txf |= 1u << idx;
4809 }
4810 }
4811 }
4812
4813 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4814 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4815
4816 if (inst->resource.file != PROGRAM_UNDEFINED && (
4817 is_resource_instruction(inst->op) ||
4818 inst->op == TGSI_OPCODE_STORE)) {
4819 if (inst->resource.file == PROGRAM_MEMORY) {
4820 v->use_shared_memory = true;
4821 } else if (inst->resource.file == PROGRAM_IMAGE) {
4822 for (int i = 0; i < inst->sampler_array_size; i++) {
4823 unsigned idx = inst->sampler_base + i;
4824 v->images_used |= 1 << idx;
4825 v->image_targets[idx] =
4826 st_translate_texture_target(inst->tex_target, false);
4827 v->image_formats[idx] = inst->image_format;
4828 v->image_wr[idx] = !inst->read_only;
4829 }
4830 }
4831 }
4832 }
4833 prog->SamplersUsed = v->samplers_used;
4834
4835 if (v->shader_program != NULL)
4836 _mesa_update_shader_textures_used(v->shader_program, prog);
4837 }
4838
4839 /**
4840 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4841 * are read from the given src in this instruction
4842 */
4843 static int
4844 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4845 {
4846 int read_mask = 0, comp;
4847
4848 /* Now, given the src swizzle and the written channels, find which
4849 * components are actually read
4850 */
4851 for (comp = 0; comp < 4; ++comp) {
4852 const unsigned coord = GET_SWZ(src.swizzle, comp);
4853 assert(coord < 4);
4854 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4855 read_mask |= 1 << coord;
4856 }
4857
4858 return read_mask;
4859 }
4860
4861 /**
4862 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4863 * instruction is the first instruction to write to register T0. There are
4864 * several lowering passes done in GLSL IR (e.g. branches and
4865 * relative addressing) that create a large number of conditional assignments
4866 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4867 *
4868 * Here is why this conversion is safe:
4869 * CMP T0, T1 T2 T0 can be expanded to:
4870 * if (T1 < 0.0)
4871 * MOV T0, T2;
4872 * else
4873 * MOV T0, T0;
4874 *
4875 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4876 * as the original program. If (T1 < 0.0) evaluates to false, executing
4877 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4878 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4879 * because any instruction that was going to read from T0 after this was going
4880 * to read a garbage value anyway.
4881 */
4882 void
4883 glsl_to_tgsi_visitor::simplify_cmp(void)
4884 {
4885 int tempWritesSize = 0;
4886 unsigned *tempWrites = NULL;
4887 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4888
4889 memset(outputWrites, 0, sizeof(outputWrites));
4890
4891 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4892 unsigned prevWriteMask = 0;
4893
4894 /* Give up if we encounter relative addressing or flow control. */
4895 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4896 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4897 inst->info->is_branch ||
4898 inst->op == TGSI_OPCODE_CONT ||
4899 inst->op == TGSI_OPCODE_END ||
4900 inst->op == TGSI_OPCODE_RET) {
4901 break;
4902 }
4903
4904 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4905 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4906 prevWriteMask = outputWrites[inst->dst[0].index];
4907 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4908 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4909 if (inst->dst[0].index >= tempWritesSize) {
4910 const int inc = 4096;
4911
4912 tempWrites = (unsigned*)
4913 realloc(tempWrites,
4914 (tempWritesSize + inc) * sizeof(unsigned));
4915 if (!tempWrites)
4916 return;
4917
4918 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4919 tempWritesSize += inc;
4920 }
4921
4922 prevWriteMask = tempWrites[inst->dst[0].index];
4923 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4924 } else
4925 continue;
4926
4927 /* For a CMP to be considered a conditional write, the destination
4928 * register and source register two must be the same. */
4929 if (inst->op == TGSI_OPCODE_CMP
4930 && !(inst->dst[0].writemask & prevWriteMask)
4931 && inst->src[2].file == inst->dst[0].file
4932 && inst->src[2].index == inst->dst[0].index
4933 && inst->dst[0].writemask ==
4934 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4935
4936 inst->op = TGSI_OPCODE_MOV;
4937 inst->info = tgsi_get_opcode_info(inst->op);
4938 inst->src[0] = inst->src[1];
4939 }
4940 }
4941
4942 free(tempWrites);
4943 }
4944
4945 static void
4946 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4947 {
4948 if (src && src->file == PROGRAM_TEMPORARY) {
4949 int old_idx = src->index;
4950 if (renames[old_idx].valid)
4951 src->index = renames[old_idx].new_reg;
4952 }
4953 }
4954
4955 /* Replaces all references to a temporary register index with another index. */
4956 void
4957 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4958 {
4959 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4960 unsigned j;
4961 for (j = 0; j < num_inst_src_regs(inst); j++) {
4962 rename_temp_handle_src(renames, &inst->src[j]);
4963 rename_temp_handle_src(renames, inst->src[j].reladdr);
4964 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4965 }
4966
4967 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4968 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4969 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4970 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4971 }
4972
4973 rename_temp_handle_src(renames, &inst->resource);
4974 rename_temp_handle_src(renames, inst->resource.reladdr);
4975 rename_temp_handle_src(renames, inst->resource.reladdr2);
4976
4977 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4978 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4979 int old_idx = inst->dst[j].index;
4980 if (renames[old_idx].valid)
4981 inst->dst[j].index = renames[old_idx].new_reg;
4982 }
4983 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4984 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4985 }
4986 }
4987 }
4988
4989 void
4990 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4991 {
4992 int depth = 0; /* loop depth */
4993 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4994 unsigned i = 0, j;
4995
4996 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4997 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4998 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4999 if (first_writes[inst->dst[j].index] == -1)
5000 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5001 }
5002 }
5003
5004 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5005 if (depth++ == 0)
5006 loop_start = i;
5007 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5008 if (--depth == 0)
5009 loop_start = -1;
5010 }
5011 assert(depth >= 0);
5012 i++;
5013 }
5014 }
5015
5016 void
5017 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
5018 {
5019 int depth = 0; /* loop depth */
5020 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5021 unsigned i = 0, j;
5022
5023 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5024 for (j = 0; j < num_inst_src_regs(inst); j++) {
5025 if (inst->src[j].file == PROGRAM_TEMPORARY) {
5026 if (first_reads[inst->src[j].index] == -1)
5027 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
5028 }
5029 }
5030 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5031 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
5032 if (first_reads[inst->tex_offsets[j].index] == -1)
5033 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
5034 }
5035 }
5036 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5037 if (depth++ == 0)
5038 loop_start = i;
5039 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5040 if (--depth == 0)
5041 loop_start = -1;
5042 }
5043 assert(depth >= 0);
5044 i++;
5045 }
5046 }
5047
5048 void
5049 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
5050 {
5051 int depth = 0; /* loop depth */
5052 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5053 unsigned i = 0, j;
5054 int k;
5055 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5056 for (j = 0; j < num_inst_src_regs(inst); j++) {
5057 if (inst->src[j].file == PROGRAM_TEMPORARY)
5058 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
5059 }
5060 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5061 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
5062 if (first_writes[inst->dst[j].index] == -1)
5063 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5064 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
5065 }
5066 }
5067 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5068 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
5069 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
5070 }
5071 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5072 if (depth++ == 0)
5073 loop_start = i;
5074 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5075 if (--depth == 0) {
5076 loop_start = -1;
5077 for (k = 0; k < this->next_temp; k++) {
5078 if (last_reads[k] == -2) {
5079 last_reads[k] = i;
5080 }
5081 }
5082 }
5083 }
5084 assert(depth >= 0);
5085 i++;
5086 }
5087 }
5088
5089 void
5090 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
5091 {
5092 int depth = 0; /* loop depth */
5093 int i = 0, k;
5094 unsigned j;
5095
5096 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5097 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5098 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5099 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5100 }
5101
5102 if (inst->op == TGSI_OPCODE_BGNLOOP)
5103 depth++;
5104 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5105 if (--depth == 0) {
5106 for (k = 0; k < this->next_temp; k++) {
5107 if (last_writes[k] == -2) {
5108 last_writes[k] = i;
5109 }
5110 }
5111 }
5112 assert(depth >= 0);
5113 i++;
5114 }
5115 }
5116
5117 /*
5118 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5119 * channels for copy propagation and updates following instructions to
5120 * use the original versions.
5121 *
5122 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5123 * will occur. As an example, a TXP production before this pass:
5124 *
5125 * 0: MOV TEMP[1], INPUT[4].xyyy;
5126 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5127 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5128 *
5129 * and after:
5130 *
5131 * 0: MOV TEMP[1], INPUT[4].xyyy;
5132 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5133 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5134 *
5135 * which allows for dead code elimination on TEMP[1]'s writes.
5136 */
5137 void
5138 glsl_to_tgsi_visitor::copy_propagate(void)
5139 {
5140 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5141 glsl_to_tgsi_instruction *,
5142 this->next_temp * 4);
5143 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5144 int level = 0;
5145
5146 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5147 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5148 || inst->dst[0].index < this->next_temp);
5149
5150 /* First, do any copy propagation possible into the src regs. */
5151 for (int r = 0; r < 3; r++) {
5152 glsl_to_tgsi_instruction *first = NULL;
5153 bool good = true;
5154 int acp_base = inst->src[r].index * 4;
5155
5156 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5157 inst->src[r].reladdr ||
5158 inst->src[r].reladdr2)
5159 continue;
5160
5161 /* See if we can find entries in the ACP consisting of MOVs
5162 * from the same src register for all the swizzled channels
5163 * of this src register reference.
5164 */
5165 for (int i = 0; i < 4; i++) {
5166 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5167 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5168
5169 if (!copy_chan) {
5170 good = false;
5171 break;
5172 }
5173
5174 assert(acp_level[acp_base + src_chan] <= level);
5175
5176 if (!first) {
5177 first = copy_chan;
5178 } else {
5179 if (first->src[0].file != copy_chan->src[0].file ||
5180 first->src[0].index != copy_chan->src[0].index ||
5181 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5182 first->src[0].index2D != copy_chan->src[0].index2D) {
5183 good = false;
5184 break;
5185 }
5186 }
5187 }
5188
5189 if (good) {
5190 /* We've now validated that we can copy-propagate to
5191 * replace this src register reference. Do it.
5192 */
5193 inst->src[r].file = first->src[0].file;
5194 inst->src[r].index = first->src[0].index;
5195 inst->src[r].index2D = first->src[0].index2D;
5196 inst->src[r].has_index2 = first->src[0].has_index2;
5197 inst->src[r].double_reg2 = first->src[0].double_reg2;
5198 inst->src[r].array_id = first->src[0].array_id;
5199
5200 int swizzle = 0;
5201 for (int i = 0; i < 4; i++) {
5202 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5203 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5204 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5205 }
5206 inst->src[r].swizzle = swizzle;
5207 }
5208 }
5209
5210 switch (inst->op) {
5211 case TGSI_OPCODE_BGNLOOP:
5212 case TGSI_OPCODE_ENDLOOP:
5213 /* End of a basic block, clear the ACP entirely. */
5214 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5215 break;
5216
5217 case TGSI_OPCODE_IF:
5218 case TGSI_OPCODE_UIF:
5219 ++level;
5220 break;
5221
5222 case TGSI_OPCODE_ENDIF:
5223 case TGSI_OPCODE_ELSE:
5224 /* Clear all channels written inside the block from the ACP, but
5225 * leaving those that were not touched.
5226 */
5227 for (int r = 0; r < this->next_temp; r++) {
5228 for (int c = 0; c < 4; c++) {
5229 if (!acp[4 * r + c])
5230 continue;
5231
5232 if (acp_level[4 * r + c] >= level)
5233 acp[4 * r + c] = NULL;
5234 }
5235 }
5236 if (inst->op == TGSI_OPCODE_ENDIF)
5237 --level;
5238 break;
5239
5240 default:
5241 /* Continuing the block, clear any written channels from
5242 * the ACP.
5243 */
5244 for (int d = 0; d < 2; d++) {
5245 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5246 /* Any temporary might be written, so no copy propagation
5247 * across this instruction.
5248 */
5249 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5250 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5251 inst->dst[d].reladdr) {
5252 /* Any output might be written, so no copy propagation
5253 * from outputs across this instruction.
5254 */
5255 for (int r = 0; r < this->next_temp; r++) {
5256 for (int c = 0; c < 4; c++) {
5257 if (!acp[4 * r + c])
5258 continue;
5259
5260 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5261 acp[4 * r + c] = NULL;
5262 }
5263 }
5264 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5265 inst->dst[d].file == PROGRAM_OUTPUT) {
5266 /* Clear where it's used as dst. */
5267 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5268 for (int c = 0; c < 4; c++) {
5269 if (inst->dst[d].writemask & (1 << c))
5270 acp[4 * inst->dst[d].index + c] = NULL;
5271 }
5272 }
5273
5274 /* Clear where it's used as src. */
5275 for (int r = 0; r < this->next_temp; r++) {
5276 for (int c = 0; c < 4; c++) {
5277 if (!acp[4 * r + c])
5278 continue;
5279
5280 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5281
5282 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5283 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5284 inst->dst[d].writemask & (1 << src_chan)) {
5285 acp[4 * r + c] = NULL;
5286 }
5287 }
5288 }
5289 }
5290 }
5291 break;
5292 }
5293
5294 /* If this is a copy, add it to the ACP. */
5295 if (inst->op == TGSI_OPCODE_MOV &&
5296 inst->dst[0].file == PROGRAM_TEMPORARY &&
5297 !(inst->dst[0].file == inst->src[0].file &&
5298 inst->dst[0].index == inst->src[0].index) &&
5299 !inst->dst[0].reladdr &&
5300 !inst->dst[0].reladdr2 &&
5301 !inst->saturate &&
5302 inst->src[0].file != PROGRAM_ARRAY &&
5303 (inst->src[0].file != PROGRAM_OUTPUT ||
5304 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5305 !inst->src[0].reladdr &&
5306 !inst->src[0].reladdr2 &&
5307 !inst->src[0].negate &&
5308 !inst->src[0].abs) {
5309 for (int i = 0; i < 4; i++) {
5310 if (inst->dst[0].writemask & (1 << i)) {
5311 acp[4 * inst->dst[0].index + i] = inst;
5312 acp_level[4 * inst->dst[0].index + i] = level;
5313 }
5314 }
5315 }
5316 }
5317
5318 ralloc_free(acp_level);
5319 ralloc_free(acp);
5320 }
5321
5322 static void
5323 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5324 {
5325 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5326 /* Clear where it's used as src. */
5327 int swz = GET_SWZ(reladdr->swizzle, 0);
5328 writes[4 * reladdr->index + swz] = NULL;
5329 }
5330 }
5331
5332 /*
5333 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5334 * code elimination.
5335 *
5336 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5337 * will occur. As an example, a TXP production after copy propagation but
5338 * before this pass:
5339 *
5340 * 0: MOV TEMP[1], INPUT[4].xyyy;
5341 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5342 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5343 *
5344 * and after this pass:
5345 *
5346 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5347 */
5348 int
5349 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5350 {
5351 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5352 glsl_to_tgsi_instruction *,
5353 this->next_temp * 4);
5354 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5355 int level = 0;
5356 int removed = 0;
5357
5358 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5359 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5360 || inst->dst[0].index < this->next_temp);
5361
5362 switch (inst->op) {
5363 case TGSI_OPCODE_BGNLOOP:
5364 case TGSI_OPCODE_ENDLOOP:
5365 case TGSI_OPCODE_CONT:
5366 case TGSI_OPCODE_BRK:
5367 /* End of a basic block, clear the write array entirely.
5368 *
5369 * This keeps us from killing dead code when the writes are
5370 * on either side of a loop, even when the register isn't touched
5371 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5372 * dead code of this type, so it shouldn't make a difference as long as
5373 * the dead code elimination pass in the GLSL compiler does its job.
5374 */
5375 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5376 break;
5377
5378 case TGSI_OPCODE_ENDIF:
5379 case TGSI_OPCODE_ELSE:
5380 /* Promote the recorded level of all channels written inside the
5381 * preceding if or else block to the level above the if/else block.
5382 */
5383 for (int r = 0; r < this->next_temp; r++) {
5384 for (int c = 0; c < 4; c++) {
5385 if (!writes[4 * r + c])
5386 continue;
5387
5388 if (write_level[4 * r + c] == level)
5389 write_level[4 * r + c] = level-1;
5390 }
5391 }
5392 if (inst->op == TGSI_OPCODE_ENDIF)
5393 --level;
5394 break;
5395
5396 case TGSI_OPCODE_IF:
5397 case TGSI_OPCODE_UIF:
5398 ++level;
5399 /* fallthrough to default case to mark the condition as read */
5400 default:
5401 /* Continuing the block, clear any channels from the write array that
5402 * are read by this instruction.
5403 */
5404 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5405 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5406 /* Any temporary might be read, so no dead code elimination
5407 * across this instruction.
5408 */
5409 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5410 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5411 /* Clear where it's used as src. */
5412 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5413 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5414 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5415 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5416
5417 for (int c = 0; c < 4; c++) {
5418 if (src_chans & (1 << c))
5419 writes[4 * inst->src[i].index + c] = NULL;
5420 }
5421 }
5422 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5423 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5424 }
5425 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5426 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5427 /* Any temporary might be read, so no dead code elimination
5428 * across this instruction.
5429 */
5430 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5431 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5432 /* Clear where it's used as src. */
5433 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5434 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5435 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5436 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5437
5438 for (int c = 0; c < 4; c++) {
5439 if (src_chans & (1 << c))
5440 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5441 }
5442 }
5443 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5444 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5445 }
5446
5447 if (inst->resource.file == PROGRAM_TEMPORARY) {
5448 int src_chans;
5449
5450 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5451 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5452 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5453 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5454
5455 for (int c = 0; c < 4; c++) {
5456 if (src_chans & (1 << c))
5457 writes[4 * inst->resource.index + c] = NULL;
5458 }
5459 }
5460 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5461 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5462
5463 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5464 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5465 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5466 }
5467 break;
5468 }
5469
5470 /* If this instruction writes to a temporary, add it to the write array.
5471 * If there is already an instruction in the write array for one or more
5472 * of the channels, flag that channel write as dead.
5473 */
5474 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5475 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5476 !inst->dst[i].reladdr) {
5477 for (int c = 0; c < 4; c++) {
5478 if (inst->dst[i].writemask & (1 << c)) {
5479 if (writes[4 * inst->dst[i].index + c]) {
5480 if (write_level[4 * inst->dst[i].index + c] < level)
5481 continue;
5482 else
5483 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5484 }
5485 writes[4 * inst->dst[i].index + c] = inst;
5486 write_level[4 * inst->dst[i].index + c] = level;
5487 }
5488 }
5489 }
5490 }
5491 }
5492
5493 /* Anything still in the write array at this point is dead code. */
5494 for (int r = 0; r < this->next_temp; r++) {
5495 for (int c = 0; c < 4; c++) {
5496 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5497 if (inst)
5498 inst->dead_mask |= (1 << c);
5499 }
5500 }
5501
5502 /* Now actually remove the instructions that are completely dead and update
5503 * the writemask of other instructions with dead channels.
5504 */
5505 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5506 if (!inst->dead_mask || !inst->dst[0].writemask)
5507 continue;
5508 /* No amount of dead masks should remove memory stores */
5509 if (inst->info->is_store)
5510 continue;
5511
5512 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5513 inst->remove();
5514 delete inst;
5515 removed++;
5516 } else {
5517 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5518 if (inst->dead_mask == WRITEMASK_XY ||
5519 inst->dead_mask == WRITEMASK_ZW)
5520 inst->dst[0].writemask &= ~(inst->dead_mask);
5521 } else
5522 inst->dst[0].writemask &= ~(inst->dead_mask);
5523 }
5524 }
5525
5526 ralloc_free(write_level);
5527 ralloc_free(writes);
5528
5529 return removed;
5530 }
5531
5532 /* merge DFRACEXP instructions into one. */
5533 void
5534 glsl_to_tgsi_visitor::merge_two_dsts(void)
5535 {
5536 /* We never delete inst, but we may delete its successor. */
5537 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5538 glsl_to_tgsi_instruction *inst2;
5539 unsigned defined;
5540
5541 if (num_inst_dst_regs(inst) != 2)
5542 continue;
5543
5544 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5545 inst->dst[1].file != PROGRAM_UNDEFINED)
5546 continue;
5547
5548 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5549 inst->dst[1].file != PROGRAM_UNDEFINED);
5550
5551 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5552 defined = 1;
5553 else
5554 defined = 0;
5555
5556 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5557 while (!inst2->is_tail_sentinel()) {
5558 if (inst->op == inst2->op &&
5559 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5560 inst->src[0].file == inst2->src[0].file &&
5561 inst->src[0].index == inst2->src[0].index &&
5562 inst->src[0].type == inst2->src[0].type &&
5563 inst->src[0].swizzle == inst2->src[0].swizzle)
5564 break;
5565 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5566 }
5567
5568 if (inst2->is_tail_sentinel()) {
5569 /* Undefined destinations are not allowed, substitute with an unused
5570 * temporary register.
5571 */
5572 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5573 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5574 inst->dst[defined ^ 1].writemask = 0;
5575 continue;
5576 }
5577
5578 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5579 inst2->remove();
5580 delete inst2;
5581 }
5582 }
5583
5584 template <typename st_reg>
5585 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5586 {
5587 if (reg.file == PROGRAM_ARRAY) {
5588 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5589 has_indirect_access[reg.array_id] = true;
5590 if (reg.reladdr)
5591 test_indirect_access(*reg.reladdr, has_indirect_access);
5592 if (reg.reladdr2)
5593 test_indirect_access(*reg.reladdr2, has_indirect_access);
5594 }
5595 }
5596 }
5597
5598 template <typename st_reg>
5599 void remap_array(st_reg& reg, const int *array_remap_info,
5600 const bool *has_indirect_access)
5601 {
5602 if (reg.file == PROGRAM_ARRAY) {
5603 if (!has_indirect_access[reg.array_id]) {
5604 reg.file = PROGRAM_TEMPORARY;
5605 reg.index = reg.index + array_remap_info[reg.array_id];
5606 reg.array_id = 0;
5607 } else {
5608 reg.array_id = array_remap_info[reg.array_id];
5609 }
5610
5611 if (reg.reladdr)
5612 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5613
5614 if (reg.reladdr2)
5615 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5616 }
5617 }
5618
5619 /* One-dimensional arrays whose elements are only accessed directly are
5620 * replaced by an according set of temporary registers that then can become
5621 * subject to further optimization steps like copy propagation and
5622 * register merging.
5623 */
5624 void
5625 glsl_to_tgsi_visitor::split_arrays(void)
5626 {
5627 if (!next_array)
5628 return;
5629
5630 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5631
5632 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5633 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5634 test_indirect_access(inst->src[j], has_indirect_access);
5635
5636 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5637 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5638
5639 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5640 test_indirect_access(inst->dst[j], has_indirect_access);
5641
5642 test_indirect_access(inst->resource, has_indirect_access);
5643 }
5644
5645 unsigned array_offset = 0;
5646 unsigned n_remaining_arrays = 0;
5647
5648 /* Double use: For arrays that get split this value will contain
5649 * the base index of the temporary registers this array is replaced
5650 * with. For arrays that remain it contains the new array ID.
5651 */
5652 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5653 next_array + 1);
5654
5655 for (unsigned i = 1; i <= next_array; ++i) {
5656 if (!has_indirect_access[i]) {
5657 array_remap_info[i] = this->next_temp + array_offset;
5658 array_offset += array_sizes[i - 1];
5659 } else {
5660 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5661 array_remap_info[i] = ++n_remaining_arrays;
5662 }
5663 }
5664
5665 if (next_array != n_remaining_arrays) {
5666 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5667 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5668 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5669
5670 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5671 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5672
5673 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5674 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5675 }
5676 remap_array(inst->resource, array_remap_info, has_indirect_access);
5677 }
5678 }
5679
5680 ralloc_free(has_indirect_access);
5681 this->next_temp += array_offset;
5682 next_array = n_remaining_arrays;
5683 }
5684
5685 /* Merges temporary registers together where possible to reduce the number of
5686 * registers needed to run a program.
5687 *
5688 * Produces optimal code only after copy propagation and dead code elimination
5689 * have been run. */
5690 void
5691 glsl_to_tgsi_visitor::merge_registers(void)
5692 {
5693 class array_live_range *arr_live_ranges = NULL;
5694
5695 struct register_live_range *reg_live_ranges =
5696 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5697
5698 if (this->next_array > 0) {
5699 arr_live_ranges = new array_live_range[this->next_array];
5700 for (unsigned i = 0; i < this->next_array; ++i)
5701 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5702 }
5703
5704
5705 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5706 this->next_temp, reg_live_ranges,
5707 this->next_array, arr_live_ranges)) {
5708 struct rename_reg_pair *renames =
5709 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5710 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5711 reg_live_ranges, renames);
5712 rename_temp_registers(renames);
5713
5714 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5715 &this->instructions, arr_live_ranges);
5716 }
5717
5718 if (arr_live_ranges)
5719 delete[] arr_live_ranges;
5720
5721 ralloc_free(reg_live_ranges);
5722 }
5723
5724 /* Reassign indices to temporary registers by reusing unused indices created
5725 * by optimization passes. */
5726 void
5727 glsl_to_tgsi_visitor::renumber_registers(void)
5728 {
5729 int i = 0;
5730 int new_index = 0;
5731 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5732 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5733
5734 for (i = 0; i < this->next_temp; i++) {
5735 first_writes[i] = -1;
5736 }
5737 get_first_temp_write(first_writes);
5738
5739 for (i = 0; i < this->next_temp; i++) {
5740 if (first_writes[i] < 0) continue;
5741 if (i != new_index) {
5742 renames[i].new_reg = new_index;
5743 renames[i].valid = true;
5744 }
5745 new_index++;
5746 }
5747
5748 rename_temp_registers(renames);
5749 this->next_temp = new_index;
5750 ralloc_free(renames);
5751 ralloc_free(first_writes);
5752 }
5753
5754 #ifndef NDEBUG
5755 void glsl_to_tgsi_visitor::print_stats()
5756 {
5757 int narray_registers = 0;
5758 for (unsigned i = 0; i < this->next_array; ++i)
5759 narray_registers += this->array_sizes[i];
5760
5761 int ninstructions = 0;
5762 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5763 ++ninstructions;
5764 }
5765
5766 simple_mtx_lock(&print_stats_mutex);
5767 stats_log << next_array << ", "
5768 << next_temp << ", "
5769 << narray_registers << ", "
5770 << next_temp + narray_registers << ", "
5771 << ninstructions << "\n";
5772 simple_mtx_unlock(&print_stats_mutex);
5773 }
5774 #endif
5775 /* ------------------------- TGSI conversion stuff -------------------------- */
5776
5777 /**
5778 * Intermediate state used during shader translation.
5779 */
5780 struct st_translate {
5781 struct ureg_program *ureg;
5782
5783 unsigned temps_size;
5784 struct ureg_dst *temps;
5785
5786 struct ureg_dst *arrays;
5787 unsigned num_temp_arrays;
5788 struct ureg_src *constants;
5789 int num_constants;
5790 struct ureg_src *immediates;
5791 int num_immediates;
5792 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5793 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5794 struct ureg_dst address[3];
5795 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5796 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5797 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5798 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5799 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5800 struct ureg_src shared_memory;
5801 unsigned *array_sizes;
5802 struct inout_decl *input_decls;
5803 unsigned num_input_decls;
5804 struct inout_decl *output_decls;
5805 unsigned num_output_decls;
5806
5807 const ubyte *inputMapping;
5808 const ubyte *outputMapping;
5809
5810 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5811 bool need_uarl;
5812 bool tg4_component_in_swizzle;
5813 };
5814
5815 /**
5816 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5817 */
5818 static struct ureg_src
5819 emit_immediate(struct st_translate *t,
5820 gl_constant_value values[4],
5821 GLenum type, int size)
5822 {
5823 struct ureg_program *ureg = t->ureg;
5824
5825 switch (type) {
5826 case GL_FLOAT:
5827 return ureg_DECL_immediate(ureg, &values[0].f, size);
5828 case GL_DOUBLE:
5829 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5830 case GL_INT64_ARB:
5831 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5832 case GL_UNSIGNED_INT64_ARB:
5833 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5834 case GL_INT:
5835 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5836 case GL_UNSIGNED_INT:
5837 case GL_BOOL:
5838 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5839 default:
5840 assert(!"should not get here - type must be float, int, uint, or bool");
5841 return ureg_src_undef();
5842 }
5843 }
5844
5845 /**
5846 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5847 */
5848 static struct ureg_dst
5849 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5850 unsigned array_id)
5851 {
5852 unsigned array;
5853
5854 switch (file) {
5855 case PROGRAM_UNDEFINED:
5856 return ureg_dst_undef();
5857
5858 case PROGRAM_TEMPORARY:
5859 /* Allocate space for temporaries on demand. */
5860 if (index >= t->temps_size) {
5861 const int inc = align(index - t->temps_size + 1, 4096);
5862
5863 t->temps = (struct ureg_dst*)
5864 realloc(t->temps,
5865 (t->temps_size + inc) * sizeof(struct ureg_dst));
5866 if (!t->temps)
5867 return ureg_dst_undef();
5868
5869 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5870 t->temps_size += inc;
5871 }
5872
5873 if (ureg_dst_is_undef(t->temps[index]))
5874 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5875
5876 return t->temps[index];
5877
5878 case PROGRAM_ARRAY:
5879 assert(array_id && array_id <= t->num_temp_arrays);
5880 array = array_id - 1;
5881
5882 if (ureg_dst_is_undef(t->arrays[array]))
5883 t->arrays[array] = ureg_DECL_array_temporary(
5884 t->ureg, t->array_sizes[array], TRUE);
5885
5886 return ureg_dst_array_offset(t->arrays[array], index);
5887
5888 case PROGRAM_OUTPUT:
5889 if (!array_id) {
5890 if (t->procType == PIPE_SHADER_FRAGMENT)
5891 assert(index < 2 * FRAG_RESULT_MAX);
5892 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5893 t->procType == PIPE_SHADER_TESS_EVAL)
5894 assert(index < VARYING_SLOT_TESS_MAX);
5895 else
5896 assert(index < VARYING_SLOT_MAX);
5897
5898 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5899 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5900 return t->outputs[t->outputMapping[index]];
5901 }
5902 else {
5903 struct inout_decl *decl =
5904 find_inout_array(t->output_decls,
5905 t->num_output_decls, array_id);
5906 unsigned mesa_index = decl->mesa_index;
5907 int slot = t->outputMapping[mesa_index];
5908
5909 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5910
5911 struct ureg_dst dst = t->outputs[slot];
5912 dst.ArrayID = array_id;
5913 return ureg_dst_array_offset(dst, index - mesa_index);
5914 }
5915
5916 case PROGRAM_ADDRESS:
5917 return t->address[index];
5918
5919 default:
5920 assert(!"unknown dst register file");
5921 return ureg_dst_undef();
5922 }
5923 }
5924
5925 static struct ureg_src
5926 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5927
5928 static struct ureg_src
5929 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5930 unsigned addr_index)
5931 {
5932 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5933 return ureg_src(t->address[addr_index]);
5934
5935 return translate_src(t, reladdr);
5936 }
5937
5938 /**
5939 * Create a TGSI ureg_dst register from an st_dst_reg.
5940 */
5941 static struct ureg_dst
5942 translate_dst(struct st_translate *t,
5943 const st_dst_reg *dst_reg,
5944 bool saturate)
5945 {
5946 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5947 dst_reg->array_id);
5948
5949 if (dst.File == TGSI_FILE_NULL)
5950 return dst;
5951
5952 dst = ureg_writemask(dst, dst_reg->writemask);
5953
5954 if (saturate)
5955 dst = ureg_saturate(dst);
5956
5957 if (dst_reg->reladdr != NULL) {
5958 assert(dst_reg->file != PROGRAM_TEMPORARY);
5959 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5960 }
5961
5962 if (dst_reg->has_index2) {
5963 if (dst_reg->reladdr2)
5964 dst = ureg_dst_dimension_indirect(dst,
5965 translate_addr(t, dst_reg->reladdr2, 1),
5966 dst_reg->index2D);
5967 else
5968 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5969 }
5970
5971 return dst;
5972 }
5973
5974 /**
5975 * Create a TGSI ureg_src register from an st_src_reg.
5976 */
5977 static struct ureg_src
5978 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5979 {
5980 struct ureg_src src;
5981 int index = src_reg->index;
5982 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5983
5984 switch (src_reg->file) {
5985 case PROGRAM_UNDEFINED:
5986 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5987 break;
5988
5989 case PROGRAM_TEMPORARY:
5990 case PROGRAM_ARRAY:
5991 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5992 src_reg->array_id));
5993 break;
5994
5995 case PROGRAM_OUTPUT: {
5996 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5997 src_reg->array_id);
5998 assert(dst.WriteMask != 0);
5999 unsigned shift = ffs(dst.WriteMask) - 1;
6000 src = ureg_swizzle(ureg_src(dst),
6001 shift,
6002 MIN2(shift + 1, 3),
6003 MIN2(shift + 2, 3),
6004 MIN2(shift + 3, 3));
6005 break;
6006 }
6007
6008 case PROGRAM_UNIFORM:
6009 assert(src_reg->index >= 0);
6010 src = src_reg->index < t->num_constants ?
6011 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6012 break;
6013 case PROGRAM_STATE_VAR:
6014 case PROGRAM_CONSTANT: /* ie, immediate */
6015 if (src_reg->has_index2)
6016 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6017 else
6018 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6019 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6020 break;
6021
6022 case PROGRAM_IMMEDIATE:
6023 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6024 src = t->immediates[src_reg->index];
6025 break;
6026
6027 case PROGRAM_INPUT:
6028 /* GLSL inputs are 64-bit containers, so we have to
6029 * map back to the original index and add the offset after
6030 * mapping. */
6031 index -= double_reg2;
6032 if (!src_reg->array_id) {
6033 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6034 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6035 src = t->inputs[t->inputMapping[index] + double_reg2];
6036 }
6037 else {
6038 struct inout_decl *decl = find_inout_array(t->input_decls,
6039 t->num_input_decls,
6040 src_reg->array_id);
6041 unsigned mesa_index = decl->mesa_index;
6042 int slot = t->inputMapping[mesa_index];
6043
6044 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6045
6046 src = t->inputs[slot];
6047 src.ArrayID = src_reg->array_id;
6048 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6049 }
6050 break;
6051
6052 case PROGRAM_ADDRESS:
6053 src = ureg_src(t->address[src_reg->index]);
6054 break;
6055
6056 case PROGRAM_SYSTEM_VALUE:
6057 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6058 src = t->systemValues[src_reg->index];
6059 break;
6060
6061 case PROGRAM_HW_ATOMIC:
6062 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6063 src_reg->array_id);
6064 break;
6065
6066 default:
6067 assert(!"unknown src register file");
6068 return ureg_src_undef();
6069 }
6070
6071 if (src_reg->has_index2) {
6072 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6073 * and UBO constant buffers (buffer, position).
6074 */
6075 if (src_reg->reladdr2)
6076 src = ureg_src_dimension_indirect(src,
6077 translate_addr(t, src_reg->reladdr2, 1),
6078 src_reg->index2D);
6079 else
6080 src = ureg_src_dimension(src, src_reg->index2D);
6081 }
6082
6083 src = ureg_swizzle(src,
6084 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6085 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6086 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6087 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6088
6089 if (src_reg->abs)
6090 src = ureg_abs(src);
6091
6092 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6093 src = ureg_negate(src);
6094
6095 if (src_reg->reladdr != NULL) {
6096 assert(src_reg->file != PROGRAM_TEMPORARY);
6097 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6098 }
6099
6100 return src;
6101 }
6102
6103 static struct tgsi_texture_offset
6104 translate_tex_offset(struct st_translate *t,
6105 const st_src_reg *in_offset)
6106 {
6107 struct tgsi_texture_offset offset;
6108 struct ureg_src src = translate_src(t, in_offset);
6109
6110 offset.File = src.File;
6111 offset.Index = src.Index;
6112 offset.SwizzleX = src.SwizzleX;
6113 offset.SwizzleY = src.SwizzleY;
6114 offset.SwizzleZ = src.SwizzleZ;
6115 offset.Padding = 0;
6116
6117 assert(!src.Indirect);
6118 assert(!src.DimIndirect);
6119 assert(!src.Dimension);
6120 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6121 assert(!src.Negate);
6122
6123 return offset;
6124 }
6125
6126 static void
6127 compile_tgsi_instruction(struct st_translate *t,
6128 const glsl_to_tgsi_instruction *inst)
6129 {
6130 struct ureg_program *ureg = t->ureg;
6131 int i;
6132 struct ureg_dst dst[2];
6133 struct ureg_src src[4];
6134 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6135
6136 int num_dst;
6137 int num_src;
6138 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6139
6140 num_dst = num_inst_dst_regs(inst);
6141 num_src = num_inst_src_regs(inst);
6142
6143 for (i = 0; i < num_dst; i++)
6144 dst[i] = translate_dst(t,
6145 &inst->dst[i],
6146 inst->saturate);
6147
6148 for (i = 0; i < num_src; i++)
6149 src[i] = translate_src(t, &inst->src[i]);
6150
6151 switch (inst->op) {
6152 case TGSI_OPCODE_BGNLOOP:
6153 case TGSI_OPCODE_ELSE:
6154 case TGSI_OPCODE_ENDLOOP:
6155 case TGSI_OPCODE_IF:
6156 case TGSI_OPCODE_UIF:
6157 assert(num_dst == 0);
6158 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6159 return;
6160
6161 case TGSI_OPCODE_TEX:
6162 case TGSI_OPCODE_TEX_LZ:
6163 case TGSI_OPCODE_TXB:
6164 case TGSI_OPCODE_TXD:
6165 case TGSI_OPCODE_TXL:
6166 case TGSI_OPCODE_TXP:
6167 case TGSI_OPCODE_TXQ:
6168 case TGSI_OPCODE_TXQS:
6169 case TGSI_OPCODE_TXF:
6170 case TGSI_OPCODE_TXF_LZ:
6171 case TGSI_OPCODE_TEX2:
6172 case TGSI_OPCODE_TXB2:
6173 case TGSI_OPCODE_TXL2:
6174 case TGSI_OPCODE_TG4:
6175 case TGSI_OPCODE_LODQ:
6176 case TGSI_OPCODE_SAMP2HND:
6177 if (inst->resource.file == PROGRAM_SAMPLER) {
6178 src[num_src] = t->samplers[inst->resource.index];
6179 if (t->tg4_component_in_swizzle && inst->op == TGSI_OPCODE_TG4)
6180 src[num_src].SwizzleX = inst->gather_component;
6181 } else {
6182 /* Bindless samplers. */
6183 src[num_src] = translate_src(t, &inst->resource);
6184 }
6185 assert(src[num_src].File != TGSI_FILE_NULL);
6186 if (inst->resource.reladdr)
6187 src[num_src] =
6188 ureg_src_indirect(src[num_src],
6189 translate_addr(t, inst->resource.reladdr, 2));
6190 num_src++;
6191 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6192 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6193 }
6194 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6195
6196 ureg_tex_insn(ureg,
6197 inst->op,
6198 dst, num_dst,
6199 tex_target,
6200 st_translate_texture_type(inst->tex_type),
6201 texoffsets, inst->tex_offset_num_offset,
6202 src, num_src);
6203 return;
6204
6205 case TGSI_OPCODE_RESQ:
6206 case TGSI_OPCODE_LOAD:
6207 case TGSI_OPCODE_ATOMUADD:
6208 case TGSI_OPCODE_ATOMXCHG:
6209 case TGSI_OPCODE_ATOMCAS:
6210 case TGSI_OPCODE_ATOMAND:
6211 case TGSI_OPCODE_ATOMOR:
6212 case TGSI_OPCODE_ATOMXOR:
6213 case TGSI_OPCODE_ATOMUMIN:
6214 case TGSI_OPCODE_ATOMUMAX:
6215 case TGSI_OPCODE_ATOMIMIN:
6216 case TGSI_OPCODE_ATOMIMAX:
6217 case TGSI_OPCODE_ATOMFADD:
6218 case TGSI_OPCODE_IMG2HND:
6219 case TGSI_OPCODE_ATOMINC_WRAP:
6220 case TGSI_OPCODE_ATOMDEC_WRAP:
6221 for (i = num_src - 1; i >= 0; i--)
6222 src[i + 1] = src[i];
6223 num_src++;
6224 if (inst->resource.file == PROGRAM_MEMORY) {
6225 src[0] = t->shared_memory;
6226 } else if (inst->resource.file == PROGRAM_BUFFER) {
6227 src[0] = t->buffers[inst->resource.index];
6228 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6229 src[0] = translate_src(t, &inst->resource);
6230 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6231 assert(inst->resource.has_index2);
6232 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6233 } else {
6234 assert(inst->resource.file != PROGRAM_UNDEFINED);
6235 if (inst->resource.file == PROGRAM_IMAGE) {
6236 src[0] = t->images[inst->resource.index];
6237 } else {
6238 /* Bindless images. */
6239 src[0] = translate_src(t, &inst->resource);
6240 }
6241 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6242 }
6243 if (inst->resource.reladdr)
6244 src[0] = ureg_src_indirect(src[0],
6245 translate_addr(t, inst->resource.reladdr, 2));
6246 assert(src[0].File != TGSI_FILE_NULL);
6247 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6248 inst->buffer_access,
6249 tex_target, inst->image_format);
6250 break;
6251
6252 case TGSI_OPCODE_STORE:
6253 if (inst->resource.file == PROGRAM_MEMORY) {
6254 dst[0] = ureg_dst(t->shared_memory);
6255 } else if (inst->resource.file == PROGRAM_BUFFER) {
6256 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6257 } else {
6258 if (inst->resource.file == PROGRAM_IMAGE) {
6259 dst[0] = ureg_dst(t->images[inst->resource.index]);
6260 } else {
6261 /* Bindless images. */
6262 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6263 }
6264 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6265 }
6266 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6267 if (inst->resource.reladdr)
6268 dst[0] = ureg_dst_indirect(dst[0],
6269 translate_addr(t, inst->resource.reladdr, 2));
6270 assert(dst[0].File != TGSI_FILE_NULL);
6271 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6272 inst->buffer_access,
6273 tex_target, inst->image_format);
6274 break;
6275
6276 default:
6277 ureg_insn(ureg,
6278 inst->op,
6279 dst, num_dst,
6280 src, num_src, inst->precise);
6281 break;
6282 }
6283 }
6284
6285 /* Invert SamplePos.y when rendering to the default framebuffer. */
6286 static void
6287 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6288 {
6289 struct ureg_program *ureg = t->ureg;
6290
6291 assert(wpos_y_transform >= 0);
6292 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6293 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6294 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6295 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6296
6297 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6298 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6299
6300 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6301 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6302 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6303 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6304 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6305 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6306 samplepos_sysval);
6307
6308 /* Use the result in place of the system value. */
6309 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6310 }
6311
6312
6313 /**
6314 * Emit the TGSI instructions for inverting and adjusting WPOS.
6315 * This code is unavoidable because it also depends on whether
6316 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6317 */
6318 static void
6319 emit_wpos_adjustment(struct gl_context *ctx,
6320 struct st_translate *t,
6321 int wpos_transform_const,
6322 boolean invert,
6323 GLfloat adjX, GLfloat adjY[2])
6324 {
6325 struct ureg_program *ureg = t->ureg;
6326
6327 assert(wpos_transform_const >= 0);
6328
6329 /* Fragment program uses fragment position input.
6330 * Need to replace instances of INPUT[WPOS] with temp T
6331 * where T = INPUT[WPOS] is inverted by Y.
6332 */
6333 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6334 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6335 struct ureg_src *wpos =
6336 ctx->Const.GLSLFragCoordIsSysVal ?
6337 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6338 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6339 struct ureg_src wpos_input = *wpos;
6340
6341 /* First, apply the coordinate shift: */
6342 if (adjX || adjY[0] || adjY[1]) {
6343 if (adjY[0] != adjY[1]) {
6344 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6345 * depending on whether inversion is actually going to be applied
6346 * or not, which is determined by testing against the inversion
6347 * state variable used below, which will be either +1 or -1.
6348 */
6349 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6350
6351 ureg_CMP(ureg, adj_temp,
6352 ureg_scalar(wpostrans, invert ? 2 : 0),
6353 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6354 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6355 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6356 } else {
6357 ureg_ADD(ureg, wpos_temp, wpos_input,
6358 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6359 }
6360 wpos_input = ureg_src(wpos_temp);
6361 } else {
6362 /* MOV wpos_temp, input[wpos]
6363 */
6364 ureg_MOV(ureg, wpos_temp, wpos_input);
6365 }
6366
6367 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6368 * inversion/identity, or the other way around if we're drawing to an FBO.
6369 */
6370 if (invert) {
6371 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6372 */
6373 ureg_MAD(ureg,
6374 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6375 wpos_input,
6376 ureg_scalar(wpostrans, 0),
6377 ureg_scalar(wpostrans, 1));
6378 } else {
6379 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6380 */
6381 ureg_MAD(ureg,
6382 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6383 wpos_input,
6384 ureg_scalar(wpostrans, 2),
6385 ureg_scalar(wpostrans, 3));
6386 }
6387
6388 /* Use wpos_temp as position input from here on:
6389 */
6390 *wpos = ureg_src(wpos_temp);
6391 }
6392
6393
6394 /**
6395 * Emit fragment position/ooordinate code.
6396 */
6397 static void
6398 emit_wpos(struct st_context *st,
6399 struct st_translate *t,
6400 const struct gl_program *program,
6401 struct ureg_program *ureg,
6402 int wpos_transform_const)
6403 {
6404 struct pipe_screen *pscreen = st->pipe->screen;
6405 GLfloat adjX = 0.0f;
6406 GLfloat adjY[2] = { 0.0f, 0.0f };
6407 boolean invert = FALSE;
6408
6409 /* Query the pixel center conventions supported by the pipe driver and set
6410 * adjX, adjY to help out if it cannot handle the requested one internally.
6411 *
6412 * The bias of the y-coordinate depends on whether y-inversion takes place
6413 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6414 * drawing to an FBO (causes additional inversion), and whether the pipe
6415 * driver origin and the requested origin differ (the latter condition is
6416 * stored in the 'invert' variable).
6417 *
6418 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6419 *
6420 * center shift only:
6421 * i -> h: +0.5
6422 * h -> i: -0.5
6423 *
6424 * inversion only:
6425 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6426 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6427 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6428 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6429 *
6430 * inversion and center shift:
6431 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6432 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6433 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6434 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6435 */
6436 if (program->info.fs.origin_upper_left) {
6437 /* Fragment shader wants origin in upper-left */
6438 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6439 /* the driver supports upper-left origin */
6440 }
6441 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6442 /* the driver supports lower-left origin, need to invert Y */
6443 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6444 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6445 invert = TRUE;
6446 }
6447 else
6448 assert(0);
6449 }
6450 else {
6451 /* Fragment shader wants origin in lower-left */
6452 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6453 /* the driver supports lower-left origin */
6454 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6455 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6456 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6457 /* the driver supports upper-left origin, need to invert Y */
6458 invert = TRUE;
6459 else
6460 assert(0);
6461 }
6462
6463 if (program->info.fs.pixel_center_integer) {
6464 /* Fragment shader wants pixel center integer */
6465 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6466 /* the driver supports pixel center integer */
6467 adjY[1] = 1.0f;
6468 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6469 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6470 }
6471 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6472 /* the driver supports pixel center half integer, need to bias X,Y */
6473 adjX = -0.5f;
6474 adjY[0] = -0.5f;
6475 adjY[1] = 0.5f;
6476 }
6477 else
6478 assert(0);
6479 }
6480 else {
6481 /* Fragment shader wants pixel center half integer */
6482 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6483 /* the driver supports pixel center half integer */
6484 }
6485 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6486 /* the driver supports pixel center integer, need to bias X,Y */
6487 adjX = adjY[0] = adjY[1] = 0.5f;
6488 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6489 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6490 }
6491 else
6492 assert(0);
6493 }
6494
6495 /* we invert after adjustment so that we avoid the MOV to temporary,
6496 * and reuse the adjustment ADD instead */
6497 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6498 }
6499
6500 /**
6501 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6502 * TGSI uses +1 for front, -1 for back.
6503 * This function converts the TGSI value to the GL value. Simply clamping/
6504 * saturating the value to [0,1] does the job.
6505 */
6506 static void
6507 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6508 {
6509 struct ureg_program *ureg = t->ureg;
6510 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6511 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6512
6513 if (ctx->Const.NativeIntegers) {
6514 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6515 }
6516 else {
6517 /* MOV_SAT face_temp, input[face] */
6518 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6519 }
6520
6521 /* Use face_temp as face input from here on: */
6522 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6523 }
6524
6525 static void
6526 emit_compute_block_size(const struct gl_program *prog,
6527 struct ureg_program *ureg) {
6528 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6529 prog->info.cs.local_size[0]);
6530 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6531 prog->info.cs.local_size[1]);
6532 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6533 prog->info.cs.local_size[2]);
6534 }
6535
6536 struct sort_inout_decls {
6537 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6538 return mapping[a.mesa_index] < mapping[b.mesa_index];
6539 }
6540
6541 const ubyte *mapping;
6542 };
6543
6544 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6545 *
6546 * This is for the benefit of older drivers which are broken when the
6547 * declarations aren't sorted in this way.
6548 */
6549 static void
6550 sort_inout_decls_by_slot(struct inout_decl *decls,
6551 unsigned count,
6552 const ubyte mapping[])
6553 {
6554 sort_inout_decls sorter;
6555 sorter.mapping = mapping;
6556 std::sort(decls, decls + count, sorter);
6557 }
6558
6559 static enum tgsi_interpolate_mode
6560 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6561 {
6562 switch (glsl_qual) {
6563 case INTERP_MODE_NONE:
6564 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6565 return TGSI_INTERPOLATE_COLOR;
6566 return TGSI_INTERPOLATE_PERSPECTIVE;
6567 case INTERP_MODE_SMOOTH:
6568 return TGSI_INTERPOLATE_PERSPECTIVE;
6569 case INTERP_MODE_FLAT:
6570 return TGSI_INTERPOLATE_CONSTANT;
6571 case INTERP_MODE_NOPERSPECTIVE:
6572 return TGSI_INTERPOLATE_LINEAR;
6573 default:
6574 assert(0 && "unexpected interp mode in st_translate_interp()");
6575 return TGSI_INTERPOLATE_PERSPECTIVE;
6576 }
6577 }
6578
6579 /**
6580 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6581 * \param program the program to translate
6582 * \param numInputs number of input registers used
6583 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6584 * input indexes
6585 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6586 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6587 * each input
6588 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6589 * \param numOutputs number of output registers used
6590 * \param outputMapping maps Mesa fragment program outputs to TGSI
6591 * generic outputs
6592 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6593 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6594 * each output
6595 *
6596 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6597 */
6598 extern "C" enum pipe_error
6599 st_translate_program(
6600 struct gl_context *ctx,
6601 enum pipe_shader_type procType,
6602 struct ureg_program *ureg,
6603 glsl_to_tgsi_visitor *program,
6604 const struct gl_program *proginfo,
6605 GLuint numInputs,
6606 const ubyte inputMapping[],
6607 const ubyte inputSlotToAttr[],
6608 const ubyte inputSemanticName[],
6609 const ubyte inputSemanticIndex[],
6610 const ubyte interpMode[],
6611 GLuint numOutputs,
6612 const ubyte outputMapping[],
6613 const ubyte outputSemanticName[],
6614 const ubyte outputSemanticIndex[])
6615 {
6616 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6617 struct st_translate *t;
6618 unsigned i;
6619 struct gl_program_constants *frag_const =
6620 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6621 enum pipe_error ret = PIPE_OK;
6622
6623 assert(numInputs <= ARRAY_SIZE(t->inputs));
6624 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6625
6626 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6627 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6628 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6629 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6630 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6631 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6632 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6633 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6634 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6635 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6636
6637 t = CALLOC_STRUCT(st_translate);
6638 if (!t) {
6639 ret = PIPE_ERROR_OUT_OF_MEMORY;
6640 goto out;
6641 }
6642
6643 t->procType = procType;
6644 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6645 t->tg4_component_in_swizzle = screen->get_param(screen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
6646 t->inputMapping = inputMapping;
6647 t->outputMapping = outputMapping;
6648 t->ureg = ureg;
6649 t->num_temp_arrays = program->next_array;
6650 if (t->num_temp_arrays)
6651 t->arrays = (struct ureg_dst*)
6652 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6653
6654 /*
6655 * Declare input attributes.
6656 */
6657 switch (procType) {
6658 case PIPE_SHADER_FRAGMENT:
6659 case PIPE_SHADER_GEOMETRY:
6660 case PIPE_SHADER_TESS_EVAL:
6661 case PIPE_SHADER_TESS_CTRL:
6662 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6663
6664 for (i = 0; i < program->num_inputs; ++i) {
6665 struct inout_decl *decl = &program->inputs[i];
6666 unsigned slot = inputMapping[decl->mesa_index];
6667 struct ureg_src src;
6668 ubyte tgsi_usage_mask = decl->usage_mask;
6669
6670 if (glsl_base_type_is_64bit(decl->base_type)) {
6671 if (tgsi_usage_mask == 1)
6672 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6673 else if (tgsi_usage_mask == 2)
6674 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6675 else
6676 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6677 }
6678
6679 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6680 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6681 if (procType == PIPE_SHADER_FRAGMENT) {
6682 assert(interpMode);
6683 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6684 (enum tgsi_interpolate_mode) interpMode[slot] :
6685 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6686
6687 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6688 }
6689
6690 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6691 (enum tgsi_semantic) inputSemanticName[slot],
6692 inputSemanticIndex[slot],
6693 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6694 decl->array_id, decl->size);
6695
6696 for (unsigned j = 0; j < decl->size; ++j) {
6697 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6698 /* The ArrayID is set up in dst_register */
6699 t->inputs[slot + j] = src;
6700 t->inputs[slot + j].ArrayID = 0;
6701 t->inputs[slot + j].Index += j;
6702 }
6703 }
6704 }
6705 break;
6706 case PIPE_SHADER_VERTEX:
6707 for (i = 0; i < numInputs; i++) {
6708 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6709 }
6710 break;
6711 case PIPE_SHADER_COMPUTE:
6712 break;
6713 default:
6714 assert(0);
6715 }
6716
6717 /*
6718 * Declare output attributes.
6719 */
6720 switch (procType) {
6721 case PIPE_SHADER_FRAGMENT:
6722 case PIPE_SHADER_COMPUTE:
6723 break;
6724 case PIPE_SHADER_GEOMETRY:
6725 case PIPE_SHADER_TESS_EVAL:
6726 case PIPE_SHADER_TESS_CTRL:
6727 case PIPE_SHADER_VERTEX:
6728 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6729
6730 for (i = 0; i < program->num_outputs; ++i) {
6731 struct inout_decl *decl = &program->outputs[i];
6732 unsigned slot = outputMapping[decl->mesa_index];
6733 struct ureg_dst dst;
6734 ubyte tgsi_usage_mask = decl->usage_mask;
6735
6736 if (glsl_base_type_is_64bit(decl->base_type)) {
6737 if (tgsi_usage_mask == 1)
6738 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6739 else if (tgsi_usage_mask == 2)
6740 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6741 else
6742 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6743 }
6744
6745 dst = ureg_DECL_output_layout(ureg,
6746 (enum tgsi_semantic) outputSemanticName[slot],
6747 outputSemanticIndex[slot],
6748 decl->gs_out_streams,
6749 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6750 dst.Invariant = decl->invariant;
6751 for (unsigned j = 0; j < decl->size; ++j) {
6752 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6753 /* The ArrayID is set up in dst_register */
6754 t->outputs[slot + j] = dst;
6755 t->outputs[slot + j].ArrayID = 0;
6756 t->outputs[slot + j].Index += j;
6757 t->outputs[slot + j].Invariant = decl->invariant;
6758 }
6759 }
6760 }
6761 break;
6762 default:
6763 assert(0);
6764 }
6765
6766 if (procType == PIPE_SHADER_FRAGMENT) {
6767 if (program->shader->Program->info.fs.early_fragment_tests ||
6768 program->shader->Program->info.fs.post_depth_coverage) {
6769 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6770
6771 if (program->shader->Program->info.fs.post_depth_coverage)
6772 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6773 }
6774
6775 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6776 /* Must do this after setting up t->inputs. */
6777 emit_wpos(st_context(ctx), t, proginfo, ureg,
6778 program->wpos_transform_const);
6779 }
6780
6781 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6782 emit_face_var(ctx, t);
6783
6784 for (i = 0; i < numOutputs; i++) {
6785 switch (outputSemanticName[i]) {
6786 case TGSI_SEMANTIC_POSITION:
6787 t->outputs[i] = ureg_DECL_output(ureg,
6788 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6789 outputSemanticIndex[i]);
6790 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6791 break;
6792 case TGSI_SEMANTIC_STENCIL:
6793 t->outputs[i] = ureg_DECL_output(ureg,
6794 TGSI_SEMANTIC_STENCIL, /* Stencil */
6795 outputSemanticIndex[i]);
6796 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6797 break;
6798 case TGSI_SEMANTIC_COLOR:
6799 t->outputs[i] = ureg_DECL_output(ureg,
6800 TGSI_SEMANTIC_COLOR,
6801 outputSemanticIndex[i]);
6802 break;
6803 case TGSI_SEMANTIC_SAMPLEMASK:
6804 t->outputs[i] = ureg_DECL_output(ureg,
6805 TGSI_SEMANTIC_SAMPLEMASK,
6806 outputSemanticIndex[i]);
6807 /* TODO: If we ever support more than 32 samples, this will have
6808 * to become an array.
6809 */
6810 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6811 break;
6812 default:
6813 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6814 ret = PIPE_ERROR_BAD_INPUT;
6815 goto out;
6816 }
6817 }
6818 }
6819 else if (procType == PIPE_SHADER_VERTEX) {
6820 for (i = 0; i < numOutputs; i++) {
6821 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6822 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6823 ureg_MOV(ureg,
6824 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6825 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6826 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6827 }
6828 }
6829 }
6830
6831 if (procType == PIPE_SHADER_COMPUTE) {
6832 emit_compute_block_size(proginfo, ureg);
6833 }
6834
6835 /* Declare address register.
6836 */
6837 if (program->num_address_regs > 0) {
6838 assert(program->num_address_regs <= 3);
6839 for (int i = 0; i < program->num_address_regs; i++)
6840 t->address[i] = ureg_DECL_address(ureg);
6841 }
6842
6843 /* Declare misc input registers
6844 */
6845 {
6846 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6847
6848 for (i = 0; sysInputs; i++) {
6849 if (sysInputs & (1ull << i)) {
6850 enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
6851
6852 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6853
6854 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6855 semName == TGSI_SEMANTIC_VERTEXID) {
6856 /* From Gallium perspective, these system values are always
6857 * integer, and require native integer support. However, if
6858 * native integer is supported on the vertex stage but not the
6859 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6860 * assumes these system values are floats. To resolve the
6861 * inconsistency, we insert a U2F.
6862 */
6863 struct st_context *st = st_context(ctx);
6864 struct pipe_screen *pscreen = st->pipe->screen;
6865 assert(procType == PIPE_SHADER_VERTEX);
6866 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6867 (void) pscreen;
6868 if (!ctx->Const.NativeIntegers) {
6869 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6870 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6871 t->systemValues[i]);
6872 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6873 }
6874 }
6875
6876 if (procType == PIPE_SHADER_FRAGMENT &&
6877 semName == TGSI_SEMANTIC_POSITION)
6878 emit_wpos(st_context(ctx), t, proginfo, ureg,
6879 program->wpos_transform_const);
6880
6881 if (procType == PIPE_SHADER_FRAGMENT &&
6882 semName == TGSI_SEMANTIC_SAMPLEPOS)
6883 emit_samplepos_adjustment(t, program->wpos_transform_const);
6884
6885 sysInputs &= ~(1ull << i);
6886 }
6887 }
6888 }
6889
6890 t->array_sizes = program->array_sizes;
6891 t->input_decls = program->inputs;
6892 t->num_input_decls = program->num_inputs;
6893 t->output_decls = program->outputs;
6894 t->num_output_decls = program->num_outputs;
6895
6896 /* Emit constants and uniforms. TGSI uses a single index space for these,
6897 * so we put all the translated regs in t->constants.
6898 */
6899 if (proginfo->Parameters) {
6900 t->constants = (struct ureg_src *)
6901 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6902 if (t->constants == NULL) {
6903 ret = PIPE_ERROR_OUT_OF_MEMORY;
6904 goto out;
6905 }
6906 t->num_constants = proginfo->Parameters->NumParameters;
6907
6908 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6909 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6910
6911 switch (proginfo->Parameters->Parameters[i].Type) {
6912 case PROGRAM_STATE_VAR:
6913 case PROGRAM_UNIFORM:
6914 t->constants[i] = ureg_DECL_constant(ureg, i);
6915 break;
6916
6917 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6918 * addressing of the const buffer.
6919 * FIXME: Be smarter and recognize param arrays:
6920 * indirect addressing is only valid within the referenced
6921 * array.
6922 */
6923 case PROGRAM_CONSTANT:
6924 if (program->indirect_addr_consts)
6925 t->constants[i] = ureg_DECL_constant(ureg, i);
6926 else
6927 t->constants[i] = emit_immediate(t,
6928 proginfo->Parameters->ParameterValues + pvo,
6929 proginfo->Parameters->Parameters[i].DataType,
6930 4);
6931 break;
6932 default:
6933 break;
6934 }
6935 }
6936 }
6937
6938 for (i = 0; i < proginfo->info.num_ubos; i++) {
6939 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6940 unsigned num_const_vecs = (size + 15) / 16;
6941 unsigned first, last;
6942 assert(num_const_vecs > 0);
6943 first = 0;
6944 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6945 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6946 }
6947
6948 /* Emit immediate values.
6949 */
6950 t->immediates = (struct ureg_src *)
6951 calloc(program->num_immediates, sizeof(struct ureg_src));
6952 if (t->immediates == NULL) {
6953 ret = PIPE_ERROR_OUT_OF_MEMORY;
6954 goto out;
6955 }
6956 t->num_immediates = program->num_immediates;
6957
6958 i = 0;
6959 foreach_in_list(immediate_storage, imm, &program->immediates) {
6960 assert(i < program->num_immediates);
6961 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6962 }
6963 assert(i == program->num_immediates);
6964
6965 /* texture samplers */
6966 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6967 if (program->samplers_used & (1u << i)) {
6968 enum tgsi_return_type type =
6969 st_translate_texture_type(program->sampler_types[i]);
6970
6971 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6972
6973 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6974 type, type, type, type);
6975 }
6976 }
6977
6978 /* Declare atomic and shader storage buffers. */
6979 {
6980 struct gl_program *prog = program->prog;
6981
6982 if (!st_context(ctx)->has_hw_atomics) {
6983 for (i = 0; i < prog->info.num_abos; i++) {
6984 unsigned index = (prog->info.num_ssbos +
6985 prog->sh.AtomicBuffers[i]->Binding);
6986 assert(prog->sh.AtomicBuffers[i]->Binding <
6987 frag_const->MaxAtomicBuffers);
6988 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6989 }
6990 } else {
6991 for (i = 0; i < program->num_atomics; i++) {
6992 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6993 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6994 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6995 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6996 ainfo->array_id);
6997 }
6998 }
6999
7000 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
7001 for (i = 0; i < prog->info.num_ssbos; i++) {
7002 t->buffers[i] = ureg_DECL_buffer(ureg, i, false);
7003 }
7004 }
7005
7006 if (program->use_shared_memory)
7007 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
7008
7009 for (i = 0; i < program->shader->Program->info.num_images; i++) {
7010 if (program->images_used & (1 << i)) {
7011 t->images[i] = ureg_DECL_image(ureg, i,
7012 program->image_targets[i],
7013 program->image_formats[i],
7014 program->image_wr[i],
7015 false);
7016 }
7017 }
7018
7019 /* Emit each instruction in turn:
7020 */
7021 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
7022 compile_tgsi_instruction(t, inst);
7023
7024 /* Set the next shader stage hint for VS and TES. */
7025 switch (procType) {
7026 case PIPE_SHADER_VERTEX:
7027 case PIPE_SHADER_TESS_EVAL:
7028 if (program->shader_program->SeparateShader)
7029 break;
7030
7031 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
7032 if (program->shader_program->_LinkedShaders[i]) {
7033 ureg_set_next_shader_processor(
7034 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
7035 break;
7036 }
7037 }
7038 break;
7039 default:
7040 ; /* nothing - silence compiler warning */
7041 }
7042
7043 out:
7044 if (t) {
7045 free(t->arrays);
7046 free(t->temps);
7047 free(t->constants);
7048 t->num_constants = 0;
7049 free(t->immediates);
7050 t->num_immediates = 0;
7051 FREE(t);
7052 }
7053
7054 return ret;
7055 }
7056 /* ----------------------------- End TGSI code ------------------------------ */
7057
7058
7059 /**
7060 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7061 * generating Mesa IR.
7062 */
7063 static struct gl_program *
7064 get_mesa_program_tgsi(struct gl_context *ctx,
7065 struct gl_shader_program *shader_program,
7066 struct gl_linked_shader *shader)
7067 {
7068 glsl_to_tgsi_visitor* v;
7069 struct gl_program *prog;
7070 struct gl_shader_compiler_options *options =
7071 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7072 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7073 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7074 unsigned skip_merge_registers;
7075
7076 validate_ir_tree(shader->ir);
7077
7078 prog = shader->Program;
7079
7080 prog->Parameters = _mesa_new_parameter_list();
7081 v = new glsl_to_tgsi_visitor();
7082 v->ctx = ctx;
7083 v->prog = prog;
7084 v->shader_program = shader_program;
7085 v->shader = shader;
7086 v->options = options;
7087 v->native_integers = ctx->Const.NativeIntegers;
7088
7089 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7090 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7091 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7092 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7093 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7094 PIPE_CAP_TGSI_TEX_TXF_LZ);
7095 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7096
7097 v->tg4_component_in_swizzle = pscreen->get_param(pscreen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
7098 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7099 _mesa_key_pointer_equal);
7100 skip_merge_registers =
7101 pscreen->get_shader_param(pscreen, ptarget,
7102 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7103
7104 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7105 prog->Parameters);
7106
7107 /* Remove reads from output registers. */
7108 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7109 lower_output_reads(shader->Stage, shader->ir);
7110
7111 /* Emit intermediate IR for main(). */
7112 visit_exec_list(shader->ir, v);
7113
7114 #if 0
7115 /* Print out some information (for debugging purposes) used by the
7116 * optimization passes. */
7117 {
7118 int i;
7119 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7120 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7121 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7122 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7123
7124 for (i = 0; i < v->next_temp; i++) {
7125 first_writes[i] = -1;
7126 first_reads[i] = -1;
7127 last_writes[i] = -1;
7128 last_reads[i] = -1;
7129 }
7130 v->get_first_temp_read(first_reads);
7131 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7132 v->get_last_temp_write(last_writes);
7133 for (i = 0; i < v->next_temp; i++)
7134 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7135 first_writes[i],
7136 last_reads[i],
7137 last_writes[i]);
7138 ralloc_free(first_writes);
7139 ralloc_free(first_reads);
7140 ralloc_free(last_writes);
7141 ralloc_free(last_reads);
7142 }
7143 #endif
7144
7145 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7146 v->simplify_cmp();
7147 v->copy_propagate();
7148
7149 while (v->eliminate_dead_code());
7150
7151 v->merge_two_dsts();
7152
7153 if (!skip_merge_registers) {
7154 v->split_arrays();
7155 v->copy_propagate();
7156 while (v->eliminate_dead_code());
7157
7158 v->merge_registers();
7159 v->copy_propagate();
7160 while (v->eliminate_dead_code());
7161 }
7162
7163 v->renumber_registers();
7164
7165 /* Write the END instruction. */
7166 v->emit_asm(NULL, TGSI_OPCODE_END);
7167
7168 if (ctx->_Shader->Flags & GLSL_DUMP) {
7169 _mesa_log("\n");
7170 _mesa_log("GLSL IR for linked %s program %d:\n",
7171 _mesa_shader_stage_to_string(shader->Stage),
7172 shader_program->Name);
7173 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7174 _mesa_log("\n\n");
7175 }
7176
7177 do_set_program_inouts(shader->ir, prog, shader->Stage);
7178
7179 _mesa_copy_linked_program_data(shader_program, shader);
7180
7181 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS)) {
7182 mark_array_io(v->inputs, v->num_inputs,
7183 &prog->info.inputs_read,
7184 prog->DualSlotInputs,
7185 &prog->info.patch_inputs_read);
7186
7187 mark_array_io(v->outputs, v->num_outputs,
7188 &prog->info.outputs_written, 0ULL,
7189 &prog->info.patch_outputs_written);
7190 } else {
7191 shrink_array_declarations(v->inputs, v->num_inputs,
7192 &prog->info.inputs_read,
7193 prog->DualSlotInputs,
7194 &prog->info.patch_inputs_read);
7195 shrink_array_declarations(v->outputs, v->num_outputs,
7196 &prog->info.outputs_written, 0ULL,
7197 &prog->info.patch_outputs_written);
7198 }
7199
7200 count_resources(v, prog);
7201
7202 /* The GLSL IR won't be needed anymore. */
7203 ralloc_free(shader->ir);
7204 shader->ir = NULL;
7205
7206 /* This must be done before the uniform storage is associated. */
7207 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7208 (prog->info.inputs_read & VARYING_BIT_POS ||
7209 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
7210 prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
7211 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7212 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7213 };
7214
7215 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7216 wposTransformState);
7217 }
7218
7219 /* Avoid reallocation of the program parameter list, because the uniform
7220 * storage is only associated with the original parameter list.
7221 * This should be enough for Bitmap and DrawPixels constants.
7222 */
7223 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7224
7225 /* This has to be done last. Any operation the can cause
7226 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7227 * program constant) has to happen before creating this linkage.
7228 */
7229 _mesa_associate_uniform_storage(ctx, shader_program, prog);
7230 if (!shader_program->data->LinkStatus) {
7231 free_glsl_to_tgsi_visitor(v);
7232 _mesa_reference_program(ctx, &shader->Program, NULL);
7233 return NULL;
7234 }
7235
7236 st_program(prog)->glsl_to_tgsi = v;
7237
7238 PRINT_STATS(v->print_stats());
7239
7240 return prog;
7241 }
7242
7243 /* See if there are unsupported control flow statements. */
7244 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7245 private:
7246 const struct gl_shader_compiler_options *options;
7247 public:
7248 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7249 : options(options),
7250 unsupported(false)
7251 {
7252 }
7253
7254 virtual ir_visitor_status visit_enter(ir_function *ir)
7255 {
7256 /* Other functions are skipped (same as glsl_to_tgsi). */
7257 if (strcmp(ir->name, "main") == 0)
7258 return visit_continue;
7259
7260 return visit_continue_with_parent;
7261 }
7262
7263 virtual ir_visitor_status visit_enter(ir_call *ir)
7264 {
7265 if (!ir->callee->is_intrinsic()) {
7266 unsupported = true; /* it's a function call */
7267 return visit_stop;
7268 }
7269 return visit_continue;
7270 }
7271
7272 virtual ir_visitor_status visit_enter(ir_return *ir)
7273 {
7274 if (options->EmitNoMainReturn) {
7275 unsupported = true;
7276 return visit_stop;
7277 }
7278 return visit_continue;
7279 }
7280
7281 bool unsupported;
7282 };
7283
7284 static bool
7285 has_unsupported_control_flow(exec_list *ir,
7286 const struct gl_shader_compiler_options *options)
7287 {
7288 ir_control_flow_info_visitor visitor(options);
7289 visit_list_elements(&visitor, ir);
7290 return visitor.unsupported;
7291 }
7292
7293 /**
7294 * Link a shader.
7295 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7296 * with code lowering and other optimizations.
7297 */
7298 GLboolean
7299 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7300 {
7301 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7302
7303 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7304 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7305 if (shader == NULL)
7306 continue;
7307
7308 exec_list *ir = shader->ir;
7309 gl_shader_stage stage = shader->Stage;
7310 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7311 const struct gl_shader_compiler_options *options =
7312 &ctx->Const.ShaderCompilerOptions[stage];
7313
7314 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7315 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7316 if (ctx->Const.GLSLOptimizeConservatively) {
7317 /* Do it once and repeat only if there's unsupported control flow. */
7318 do {
7319 do_common_optimization(ir, true, true, options,
7320 ctx->Const.NativeIntegers);
7321 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7322 options->MaxIfDepth, if_threshold);
7323 } while (has_unsupported_control_flow(ir, options));
7324 } else {
7325 /* Repeat it until it stops making changes. */
7326 bool progress;
7327 do {
7328 progress = do_common_optimization(ir, true, true, options,
7329 ctx->Const.NativeIntegers);
7330 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7331 options->MaxIfDepth, if_threshold);
7332 } while (progress);
7333 }
7334
7335 /* Do this again to lower ir_binop_vector_extract introduced
7336 * by optimization passes.
7337 */
7338 do_vec_index_to_cond_assign(ir);
7339
7340 validate_ir_tree(ir);
7341
7342 struct gl_program *linked_prog =
7343 get_mesa_program_tgsi(ctx, prog, shader);
7344 st_set_prog_affected_state_flags(linked_prog);
7345
7346 if (linked_prog) {
7347 if (!ctx->Driver.ProgramStringNotify(ctx,
7348 _mesa_shader_stage_to_program(i),
7349 linked_prog)) {
7350 _mesa_reference_program(ctx, &shader->Program, NULL);
7351 return GL_FALSE;
7352 }
7353 }
7354 }
7355
7356 return GL_TRUE;
7357 }