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glsl: Hard-code noise to zero in builtin_functions.cpp
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_to_tgsi_temprename.h"
56
57 #include "util/hash_table.h"
58 #include <algorithm>
59
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
63
64 #define MAX_GLSL_TEXTURE_OFFSET 4
65
66 #ifndef NDEBUG
67 #include "util/u_atomic.h"
68 #include "util/simple_mtx.h"
69 #include <fstream>
70 #include <ios>
71
72 /* Prepare to make it possible to specify log file */
73 static std::ofstream stats_log;
74
75 /* Helper function to check whether we want to write some statistics
76 * of the shader conversion.
77 */
78
79 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
80
81 static inline bool print_stats_enabled ()
82 {
83 static int stats_enabled = 0;
84
85 if (!stats_enabled) {
86 simple_mtx_lock(&print_stats_mutex);
87 if (!stats_enabled) {
88 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
89 if (stats_filename) {
90 bool write_header = std::ifstream(stats_filename).fail();
91 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
92 stats_enabled = stats_log.good() ? 1 : -1;
93 if (write_header)
94 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
95 } else {
96 stats_enabled = -1;
97 }
98 }
99 simple_mtx_unlock(&print_stats_mutex);
100 }
101 return stats_enabled > 0;
102 }
103 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
104 #else
105 #define PRINT_STATS(X)
106 #endif
107
108
109 static unsigned is_precise(const ir_variable *ir)
110 {
111 if (!ir)
112 return 0;
113 return ir->data.precise || ir->data.invariant;
114 }
115
116 class variable_storage {
117 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
118
119 public:
120 variable_storage(ir_variable *var, gl_register_file file, int index,
121 unsigned array_id = 0)
122 : file(file), index(index), component(0), var(var), array_id(array_id)
123 {
124 assert(file != PROGRAM_ARRAY || array_id != 0);
125 }
126
127 gl_register_file file;
128 int index;
129
130 /* Explicit component location. This is given in terms of the GLSL-style
131 * swizzles where each double is a single component, i.e. for 64-bit types
132 * it can only be 0 or 1.
133 */
134 int component;
135 ir_variable *var; /* variable that maps to this, if any */
136 unsigned array_id;
137 };
138
139 class immediate_storage : public exec_node {
140 public:
141 immediate_storage(gl_constant_value *values, int size32, GLenum type)
142 {
143 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
144 this->size32 = size32;
145 this->type = type;
146 }
147
148 /* doubles are stored across 2 gl_constant_values */
149 gl_constant_value values[4];
150 int size32; /**< Number of 32-bit components (1-4) */
151 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
152 };
153
154 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
155 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
156
157 struct inout_decl {
158 unsigned mesa_index;
159 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
160 unsigned size;
161 unsigned interp_loc;
162 unsigned gs_out_streams;
163 enum glsl_interp_mode interp;
164 enum glsl_base_type base_type;
165 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
166 bool invariant;
167 };
168
169 static struct inout_decl *
170 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
171 {
172 assert(array_id != 0);
173
174 for (unsigned i = 0; i < count; i++) {
175 struct inout_decl *decl = &decls[i];
176
177 if (array_id == decl->array_id) {
178 return decl;
179 }
180 }
181
182 return NULL;
183 }
184
185 static enum glsl_base_type
186 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
187 {
188 if (!array_id)
189 return GLSL_TYPE_ERROR;
190 struct inout_decl *decl = find_inout_array(decls, count, array_id);
191 if (decl)
192 return decl->base_type;
193 return GLSL_TYPE_ERROR;
194 }
195
196 struct hwatomic_decl {
197 unsigned location;
198 unsigned binding;
199 unsigned size;
200 unsigned array_id;
201 };
202
203 struct glsl_to_tgsi_visitor : public ir_visitor {
204 public:
205 glsl_to_tgsi_visitor();
206 ~glsl_to_tgsi_visitor();
207
208 struct gl_context *ctx;
209 struct gl_program *prog;
210 struct gl_shader_program *shader_program;
211 struct gl_linked_shader *shader;
212 struct gl_shader_compiler_options *options;
213
214 int next_temp;
215
216 unsigned *array_sizes;
217 unsigned max_num_arrays;
218 unsigned next_array;
219
220 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
221 unsigned num_inputs;
222 unsigned num_input_arrays;
223 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
224 unsigned num_outputs;
225 unsigned num_output_arrays;
226
227 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
228 unsigned num_atomics;
229 unsigned num_atomic_arrays;
230 int num_address_regs;
231 uint32_t samplers_used;
232 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
233 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
234 int images_used;
235 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
236 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
237 bool image_wr[PIPE_MAX_SHADER_IMAGES];
238 bool indirect_addr_consts;
239 int wpos_transform_const;
240
241 bool native_integers;
242 bool have_sqrt;
243 bool have_fma;
244 bool use_shared_memory;
245 bool has_tex_txf_lz;
246 bool precise;
247 bool need_uarl;
248 bool tg4_component_in_swizzle;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_demote *);
288 virtual void visit(ir_texture *);
289 virtual void visit(ir_if *);
290 virtual void visit(ir_emit_vertex *);
291 virtual void visit(ir_end_primitive *);
292 virtual void visit(ir_barrier *);
293 /*@}*/
294
295 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
296
297 void visit_atomic_counter_intrinsic(ir_call *);
298 void visit_ssbo_intrinsic(ir_call *);
299 void visit_membar_intrinsic(ir_call *);
300 void visit_shared_intrinsic(ir_call *);
301 void visit_image_intrinsic(ir_call *);
302 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
303
304 st_src_reg result;
305
306 /** List of variable_storage */
307 struct hash_table *variables;
308
309 /** List of immediate_storage */
310 exec_list immediates;
311 unsigned num_immediates;
312
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions;
315
316 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
317 st_dst_reg dst = undef_dst,
318 st_src_reg src0 = undef_src,
319 st_src_reg src1 = undef_src,
320 st_src_reg src2 = undef_src,
321 st_src_reg src3 = undef_src);
322
323 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
324 st_dst_reg dst, st_dst_reg dst1,
325 st_src_reg src0 = undef_src,
326 st_src_reg src1 = undef_src,
327 st_src_reg src2 = undef_src,
328 st_src_reg src3 = undef_src);
329
330 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
331 st_dst_reg dst,
332 st_src_reg src0, st_src_reg src1);
333
334 /**
335 * Emit the correct dot-product instruction for the type of arguments
336 */
337 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
338 st_dst_reg dst,
339 st_src_reg src0,
340 st_src_reg src1,
341 unsigned elements);
342
343 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
344 st_dst_reg dst, st_src_reg src0);
345
346 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
347 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
348
349 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
350
351 void get_deref_offsets(ir_dereference *ir,
352 unsigned *array_size,
353 unsigned *base,
354 uint16_t *index,
355 st_src_reg *reladdr,
356 bool opaque);
357 void calc_deref_offsets(ir_dereference *tail,
358 unsigned *array_elements,
359 uint16_t *index,
360 st_src_reg *indirect,
361 unsigned *location);
362 st_src_reg canonicalize_gather_offset(st_src_reg offset);
363 bool handle_bound_deref(ir_dereference *ir);
364
365 bool try_emit_mad(ir_expression *ir,
366 int mul_operand);
367 bool try_emit_mad_for_and_not(ir_expression *ir,
368 int mul_operand);
369
370 void emit_swz(ir_expression *ir);
371
372 bool process_move_condition(ir_rvalue *ir);
373
374 void simplify_cmp(void);
375
376 void rename_temp_registers(struct rename_reg_pair *renames);
377 void get_first_temp_read(int *first_reads);
378 void get_first_temp_write(int *first_writes);
379 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
380 void get_last_temp_write(int *last_writes);
381
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
384
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
389
390 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
391 st_dst_reg *l, st_src_reg *r,
392 st_src_reg *cond, bool cond_swap);
393
394 void print_stats();
395
396 void *mem_ctx;
397 };
398
399 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
400 GLSL_TYPE_FLOAT, 0);
401 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
402 GLSL_TYPE_FLOAT, 1);
403 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
404 GLSL_TYPE_FLOAT, 2);
405
406 static void
407 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
408 PRINTFLIKE(2, 3);
409
410 static void
411 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
412 {
413 va_list args;
414 va_start(args, fmt);
415 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
416 va_end(args);
417
418 prog->data->LinkStatus = LINKING_FAILURE;
419 }
420
421 int
422 swizzle_for_size(int size)
423 {
424 static const int size_swizzles[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
428 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
429 };
430
431 assert((size >= 1) && (size <= 4));
432 return size_swizzles[size - 1];
433 }
434
435
436 glsl_to_tgsi_instruction *
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
438 st_dst_reg dst, st_dst_reg dst1,
439 st_src_reg src0, st_src_reg src1,
440 st_src_reg src2, st_src_reg src3)
441 {
442 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
443 int num_reladdr = 0, i, j;
444 bool dst_is_64bit[2];
445
446 op = get_opcode(op, dst, src0, src1);
447
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
451 */
452 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
453 assert(!dst1.reladdr); /* should be lowered in earlier passes */
454 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
455 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
456 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
457 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
458
459 reladdr_to_temp(ir, &src3, &num_reladdr);
460 reladdr_to_temp(ir, &src2, &num_reladdr);
461 reladdr_to_temp(ir, &src1, &num_reladdr);
462 reladdr_to_temp(ir, &src0, &num_reladdr);
463
464 if (dst.reladdr || dst.reladdr2) {
465 if (dst.reladdr)
466 emit_arl(ir, address_reg, *dst.reladdr);
467 if (dst.reladdr2)
468 emit_arl(ir, address_reg2, *dst.reladdr2);
469 num_reladdr--;
470 }
471
472 assert(num_reladdr == 0);
473
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
476
477 inst->op = op;
478 inst->precise = this->precise;
479 inst->info = tgsi_get_opcode_info(op);
480 inst->dst[0] = dst;
481 inst->dst[1] = dst1;
482 inst->src[0] = src0;
483 inst->src[1] = src1;
484 inst->src[2] = src2;
485 inst->src[3] = src3;
486 inst->is_64bit_expanded = false;
487 inst->ir = ir;
488 inst->dead_mask = 0;
489 inst->tex_offsets = NULL;
490 inst->tex_offset_num_offset = 0;
491 inst->saturate = 0;
492 inst->tex_shadow = 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
495 */
496 inst->tex_type = GLSL_TYPE_FLOAT;
497
498 /* Update indirect addressing status used by TGSI */
499 if (dst.reladdr || dst.reladdr2) {
500 switch (dst.file) {
501 case PROGRAM_STATE_VAR:
502 case PROGRAM_CONSTANT:
503 case PROGRAM_UNIFORM:
504 this->indirect_addr_consts = true;
505 break;
506 case PROGRAM_IMMEDIATE:
507 assert(!"immediates should not have indirect addressing");
508 break;
509 default:
510 break;
511 }
512 }
513 else {
514 for (i = 0; i < 4; i++) {
515 if (inst->src[i].reladdr) {
516 switch (inst->src[i].file) {
517 case PROGRAM_STATE_VAR:
518 case PROGRAM_CONSTANT:
519 case PROGRAM_UNIFORM:
520 this->indirect_addr_consts = true;
521 break;
522 case PROGRAM_IMMEDIATE:
523 assert(!"immediates should not have indirect addressing");
524 break;
525 default:
526 break;
527 }
528 }
529 }
530 }
531
532 /*
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
536 *
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
541 *
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
544 *
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
549 */
550 for (j = 0; j < 2; j++) {
551 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
552 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
553 inst->dst[j].type == GLSL_TYPE_ARRAY) {
554 enum glsl_base_type type = find_array_type(this->outputs,
555 this->num_outputs,
556 inst->dst[j].array_id);
557 if (glsl_base_type_is_64bit(type))
558 dst_is_64bit[j] = true;
559 }
560 }
561
562 if (dst_is_64bit[0] || dst_is_64bit[1] ||
563 glsl_base_type_is_64bit(inst->src[0].type)) {
564 glsl_to_tgsi_instruction *dinst = NULL;
565 int initial_src_swz[4], initial_src_idx[4];
566 int initial_dst_idx[2], initial_dst_writemask[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
569 ? inst->dst[0].writemask : inst->dst[1].writemask;
570
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j = 0; j < 2; j++) {
573 initial_dst_writemask[j] = inst->dst[j].writemask;
574 initial_dst_idx[j] = inst->dst[j].index;
575 }
576
577 for (j = 0; j < 4; j++) {
578 initial_src_swz[j] = inst->src[j].swizzle;
579 initial_src_idx[j] = inst->src[j].index;
580 }
581
582 /*
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
585 */
586 st_src_reg addr;
587 while (writemask) {
588
589 int i = u_bit_scan(&writemask);
590
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
594 inst->op == TGSI_OPCODE_STORE) &&
595 addr.file == PROGRAM_UNDEFINED) {
596 /* We have to advance the buffer address by 16 */
597 addr = get_temp(glsl_type::uint_type);
598 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
599 inst->src[0], st_src_reg_for_int(16));
600 }
601
602 /* first time use previous instruction */
603 if (dinst == NULL) {
604 dinst = inst;
605 } else {
606 /* create a new instructions for subsequent attempts */
607 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
608 *dinst = *inst;
609 dinst->next = NULL;
610 dinst->prev = NULL;
611 }
612 this->instructions.push_tail(dinst);
613 dinst->is_64bit_expanded = true;
614
615 /* modify the destination if we are splitting */
616 for (j = 0; j < 2; j++) {
617 if (dst_is_64bit[j]) {
618 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
619 dinst->dst[j].index = initial_dst_idx[j];
620 if (i > 1) {
621 if (dinst->op == TGSI_OPCODE_LOAD ||
622 dinst->op == TGSI_OPCODE_STORE)
623 dinst->src[0] = addr;
624 if (dinst->op != TGSI_OPCODE_STORE)
625 dinst->dst[j].index++;
626 }
627 } else {
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
630 */
631 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
632 }
633 }
634
635 /* modify the src registers */
636 for (j = 0; j < 4; j++) {
637 int swz = GET_SWZ(initial_src_swz[j], i);
638
639 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
640 dinst->src[j].index = initial_src_idx[j];
641 if (swz > 1) {
642 dinst->src[j].double_reg2 = true;
643 dinst->src[j].index++;
644 }
645
646 if (swz & 1)
647 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
648 SWIZZLE_Z, SWIZZLE_W);
649 else
650 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
651 SWIZZLE_X, SWIZZLE_Y);
652
653 } else {
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
656 * integer src1
657 */
658 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
659 op == TGSI_OPCODE_I2D ||
660 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
661 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
662 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
663 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
664 }
665 }
666 }
667 }
668 inst = dinst;
669 } else {
670 this->instructions.push_tail(inst);
671 }
672
673
674 return inst;
675 }
676
677 glsl_to_tgsi_instruction *
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
679 st_dst_reg dst,
680 st_src_reg src0, st_src_reg src1,
681 st_src_reg src2, st_src_reg src3)
682 {
683 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
684 }
685
686 /**
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
689 */
690 enum tgsi_opcode
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
692 st_dst_reg dst,
693 st_src_reg src0, st_src_reg src1)
694 {
695 enum glsl_base_type type = GLSL_TYPE_FLOAT;
696
697 if (op == TGSI_OPCODE_MOV)
698 return op;
699
700 assert(src0.type != GLSL_TYPE_ARRAY);
701 assert(src0.type != GLSL_TYPE_STRUCT);
702 assert(src1.type != GLSL_TYPE_ARRAY);
703 assert(src1.type != GLSL_TYPE_STRUCT);
704
705 if (is_resource_instruction(op))
706 type = src1.type;
707 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
708 type = GLSL_TYPE_INT64;
709 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
710 type = GLSL_TYPE_UINT64;
711 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
712 type = GLSL_TYPE_DOUBLE;
713 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
714 type = GLSL_TYPE_FLOAT;
715 else if (native_integers)
716 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
717
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
730 else \
731 op = TGSI_OPCODE_##f; \
732 break;
733
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
748 else \
749 op = TGSI_OPCODE_##c; \
750 break;
751
752 switch (op) {
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
755 *
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
757 */
758 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
759 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
760 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
761 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
762 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
763 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
764 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
765 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
766 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
767 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
768 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
769 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
770 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
771 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
772 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
773 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
774
775 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
776 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
777 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
778 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
779 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
780 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
781 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
782 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
783 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
784
785 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
786 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
787 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
788 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
789
790 default:
791 break;
792 }
793
794 assert(op != TGSI_OPCODE_LAST);
795 return op;
796 }
797
798 glsl_to_tgsi_instruction *
799 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
800 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
801 unsigned elements)
802 {
803 static const enum tgsi_opcode dot_opcodes[] = {
804 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
805 };
806
807 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
808 }
809
810 /**
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
812 *
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
817 */
818 void
819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
820 st_dst_reg dst,
821 st_src_reg orig_src0, st_src_reg orig_src1)
822 {
823 int i, j;
824 int done_mask = ~dst.writemask;
825
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
828 * dst channels.
829 */
830 for (i = 0; i < 4; i++) {
831 GLuint this_mask = (1 << i);
832 st_src_reg src0 = orig_src0;
833 st_src_reg src1 = orig_src1;
834
835 if (done_mask & this_mask)
836 continue;
837
838 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
839 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
840 for (j = i + 1; j < 4; j++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
843 * well.
844 */
845 if (!(done_mask & (1 << j)) &&
846 GET_SWZ(src0.swizzle, j) == src0_swiz &&
847 GET_SWZ(src1.swizzle, j) == src1_swiz) {
848 this_mask |= (1 << j);
849 }
850 }
851 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
852 src0_swiz, src0_swiz);
853 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
854 src1_swiz, src1_swiz);
855
856 dst.writemask = this_mask;
857 emit_asm(ir, op, dst, src0, src1);
858 done_mask |= this_mask;
859 }
860 }
861
862 void
863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
864 st_dst_reg dst, st_src_reg src0)
865 {
866 st_src_reg undef = undef_src;
867
868 undef.swizzle = SWIZZLE_XXXX;
869
870 emit_scalar(ir, op, dst, src0, undef);
871 }
872
873 void
874 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
875 st_dst_reg dst, st_src_reg src0)
876 {
877 enum tgsi_opcode op = TGSI_OPCODE_ARL;
878
879 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
880 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
881 return;
882
883 op = TGSI_OPCODE_UARL;
884 }
885
886 assert(dst.file == PROGRAM_ADDRESS);
887 if (dst.index >= this->num_address_regs)
888 this->num_address_regs = dst.index + 1;
889
890 emit_asm(NULL, op, dst, src0);
891 }
892
893 int
894 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
895 gl_constant_value values[8], int size,
896 GLenum datatype,
897 uint16_t *swizzle_out)
898 {
899 if (file == PROGRAM_CONSTANT) {
900 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
901 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
902 values, size, datatype,
903 &swizzle);
904 if (swizzle_out)
905 *swizzle_out = swizzle;
906 return result;
907 }
908
909 assert(file == PROGRAM_IMMEDIATE);
910
911 int index = 0;
912 immediate_storage *entry;
913 int size32 = size * ((datatype == GL_DOUBLE ||
914 datatype == GL_INT64_ARB ||
915 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
916 int i;
917
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
920 */
921 foreach_in_list(immediate_storage, entry, &this->immediates) {
922 immediate_storage *tmp = entry;
923
924 for (i = 0; i * 4 < size32; i++) {
925 int slot_size = MIN2(size32 - (i * 4), 4);
926 if (tmp->type != datatype || tmp->size32 != slot_size)
927 break;
928 if (memcmp(tmp->values, &values[i * 4],
929 slot_size * sizeof(gl_constant_value)))
930 break;
931
932 /* Everything matches, keep going until the full size is matched */
933 tmp = (immediate_storage *)tmp->next;
934 }
935
936 /* The full value matched */
937 if (i * 4 >= size32)
938 return index;
939
940 index++;
941 }
942
943 for (i = 0; i * 4 < size32; i++) {
944 int slot_size = MIN2(size32 - (i * 4), 4);
945 /* Add this immediate to the list. */
946 entry = new(mem_ctx) immediate_storage(&values[i * 4],
947 slot_size, datatype);
948 this->immediates.push_tail(entry);
949 this->num_immediates++;
950 }
951 return index;
952 }
953
954 st_src_reg
955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
956 {
957 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
958 union gl_constant_value uval;
959
960 uval.f = val;
961 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
962
963 return src;
964 }
965
966 st_src_reg
967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
968 {
969 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
970 union gl_constant_value uval[2];
971
972 memcpy(uval, &val, sizeof(uval));
973 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
974 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
975 return src;
976 }
977
978 st_src_reg
979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
980 {
981 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
982 union gl_constant_value uval;
983
984 assert(native_integers);
985
986 uval.i = val;
987 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
988
989 return src;
990 }
991
992 st_src_reg
993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
994 {
995 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
996 union gl_constant_value uval[2];
997
998 memcpy(uval, &val, sizeof(uval));
999 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
1000 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1001
1002 return src;
1003 }
1004
1005 st_src_reg
1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1007 {
1008 if (native_integers)
1009 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1010 st_src_reg_for_int(val);
1011 else
1012 return st_src_reg_for_float(val);
1013 }
1014
1015 static int
1016 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1017 {
1018 return type->count_attribute_slots(is_vs_input);
1019 }
1020
1021 static int
1022 type_size(const struct glsl_type *type)
1023 {
1024 return type->count_attribute_slots(false);
1025 }
1026
1027 static void
1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1029 exec_list *instructions, ir_constant *access)
1030 {
1031 /**
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1034 */
1035 enum tgsi_opcode op = inst->op;
1036 do {
1037 inst->resource = *buf;
1038 if (access)
1039 inst->buffer_access = access->value.u[0];
1040
1041 if (inst == instructions->get_head_raw())
1042 break;
1043 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1044
1045 if (inst->op == TGSI_OPCODE_UADD) {
1046 if (inst == instructions->get_head_raw())
1047 break;
1048 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1049 }
1050 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1051 }
1052
1053 /**
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1056 *
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1061 */
1062 static bool
1063 type_has_array_or_matrix(const glsl_type *type)
1064 {
1065 if (type->is_array() || type->is_matrix())
1066 return true;
1067
1068 if (type->is_struct()) {
1069 for (unsigned i = 0; i < type->length; i++) {
1070 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1071 return true;
1072 }
1073 }
1074 }
1075
1076 return false;
1077 }
1078
1079
1080 /**
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1083 * storage).
1084 */
1085 st_src_reg
1086 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1087 {
1088 st_src_reg src;
1089
1090 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1091 src.reladdr = NULL;
1092 src.negate = 0;
1093 src.abs = 0;
1094
1095 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1096 if (next_array >= max_num_arrays) {
1097 max_num_arrays += 32;
1098 array_sizes = (unsigned*)
1099 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1100 }
1101
1102 src.file = PROGRAM_ARRAY;
1103 src.index = 0;
1104 src.array_id = next_array + 1;
1105 array_sizes[next_array] = type_size(type);
1106 ++next_array;
1107
1108 } else {
1109 src.file = PROGRAM_TEMPORARY;
1110 src.index = next_temp;
1111 next_temp += type_size(type);
1112 }
1113
1114 if (type->is_array() || type->is_struct()) {
1115 src.swizzle = SWIZZLE_NOOP;
1116 } else {
1117 src.swizzle = swizzle_for_size(type->vector_elements);
1118 }
1119
1120 return src;
1121 }
1122
1123 variable_storage *
1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1125 {
1126 struct hash_entry *entry;
1127
1128 entry = _mesa_hash_table_search(this->variables, var);
1129 if (!entry)
1130 return NULL;
1131
1132 return (variable_storage *)entry->data;
1133 }
1134
1135 void
1136 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1137 {
1138 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1139 unsigned int i;
1140 const ir_state_slot *const slots = ir->get_state_slots();
1141 assert(slots != NULL);
1142
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1147 * out.
1148 */
1149 for (i = 0; i < ir->get_num_state_slots(); i++) {
1150 if (slots[i].swizzle != SWIZZLE_XYZW) {
1151 break;
1152 }
1153 }
1154
1155 variable_storage *storage;
1156 st_dst_reg dst;
1157 if (i == ir->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1160
1161 _mesa_hash_table_insert(this->variables, ir, storage);
1162
1163 dst = undef_dst;
1164 } else {
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1168 */
1169 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1170
1171 dst = st_dst_reg(get_temp(ir->type));
1172
1173 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1174 dst.array_id);
1175
1176 _mesa_hash_table_insert(this->variables, ir, storage);
1177 }
1178
1179
1180 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1181 int index = _mesa_add_state_reference(this->prog->Parameters,
1182 slots[i].tokens);
1183
1184 if (storage->file == PROGRAM_STATE_VAR) {
1185 if (storage->index == -1) {
1186 storage->index = index;
1187 } else {
1188 assert(index == storage->index + (int)i);
1189 }
1190 } else {
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1195 */
1196 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1197 src.swizzle = slots[i].swizzle;
1198 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1200 dst.index++;
1201 }
1202 }
1203
1204 if (storage->file == PROGRAM_TEMPORARY &&
1205 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1206 fail_link(this->shader_program,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir->name, dst.index - storage->index,
1209 type_size(ir->type));
1210 }
1211 }
1212 }
1213
1214 void
1215 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1216 {
1217 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1218
1219 visit_exec_list(&ir->body_instructions, this);
1220
1221 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1222 }
1223
1224 void
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1226 {
1227 switch (ir->mode) {
1228 case ir_loop_jump::jump_break:
1229 emit_asm(NULL, TGSI_OPCODE_BRK);
1230 break;
1231 case ir_loop_jump::jump_continue:
1232 emit_asm(NULL, TGSI_OPCODE_CONT);
1233 break;
1234 }
1235 }
1236
1237
1238 void
1239 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1240 {
1241 assert(0);
1242 (void)ir;
1243 }
1244
1245 void
1246 glsl_to_tgsi_visitor::visit(ir_function *ir)
1247 {
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1250 */
1251 if (strcmp(ir->name, "main") == 0) {
1252 const ir_function_signature *sig;
1253 exec_list empty;
1254
1255 sig = ir->matching_signature(NULL, &empty, false);
1256
1257 assert(sig);
1258
1259 foreach_in_list(ir_instruction, ir, &sig->body) {
1260 ir->accept(this);
1261 }
1262 }
1263 }
1264
1265 bool
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1267 {
1268 int nonmul_operand = 1 - mul_operand;
1269 st_src_reg a, b, c;
1270 st_dst_reg result_dst;
1271
1272 // there is no TGSI opcode for this
1273 if (ir->type->is_integer_64())
1274 return false;
1275
1276 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1277 if (!expr || expr->operation != ir_binop_mul)
1278 return false;
1279
1280 expr->operands[0]->accept(this);
1281 a = this->result;
1282 expr->operands[1]->accept(this);
1283 b = this->result;
1284 ir->operands[nonmul_operand]->accept(this);
1285 c = this->result;
1286
1287 this->result = get_temp(ir->type);
1288 result_dst = st_dst_reg(this->result);
1289 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1290 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1291
1292 return true;
1293 }
1294
1295 /**
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1297 *
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1302 *
1303 * - a * !b
1304 * - a * (1 - b)
1305 * - (a * 1) - (a * b)
1306 * - a + -(a * b)
1307 * - a + (a * -b)
1308 *
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1310 * instruction.
1311 */
1312 bool
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1314 int try_operand)
1315 {
1316 const int other_operand = 1 - try_operand;
1317 st_src_reg a, b;
1318
1319 ir_expression *expr = ir->operands[try_operand]->as_expression();
1320 if (!expr || expr->operation != ir_unop_logic_not)
1321 return false;
1322
1323 ir->operands[other_operand]->accept(this);
1324 a = this->result;
1325 expr->operands[0]->accept(this);
1326 b = this->result;
1327
1328 b.negate = ~b.negate;
1329
1330 this->result = get_temp(ir->type);
1331 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1332
1333 return true;
1334 }
1335
1336 void
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1338 st_src_reg *reg, int *num_reladdr)
1339 {
1340 if (!reg->reladdr && !reg->reladdr2)
1341 return;
1342
1343 if (reg->reladdr)
1344 emit_arl(ir, address_reg, *reg->reladdr);
1345 if (reg->reladdr2)
1346 emit_arl(ir, address_reg2, *reg->reladdr2);
1347
1348 if (*num_reladdr != 1) {
1349 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1350
1351 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1352 *reg = temp;
1353 }
1354
1355 (*num_reladdr)--;
1356 }
1357
1358 void
1359 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1360 {
1361 st_src_reg op[ARRAY_SIZE(ir->operands)];
1362
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1364 */
1365 if (!this->precise && ir->operation == ir_binop_add) {
1366 if (try_emit_mad(ir, 1))
1367 return;
1368 if (try_emit_mad(ir, 0))
1369 return;
1370 }
1371
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1373 */
1374 if (!native_integers && ir->operation == ir_binop_logic_and) {
1375 if (try_emit_mad_for_and_not(ir, 1))
1376 return;
1377 if (try_emit_mad_for_and_not(ir, 0))
1378 return;
1379 }
1380
1381 if (ir->operation == ir_quadop_vector)
1382 assert(!"ir_quadop_vector should have been lowered");
1383
1384 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1385 this->result.file = PROGRAM_UNDEFINED;
1386 ir->operands[operand]->accept(this);
1387 if (this->result.file == PROGRAM_UNDEFINED) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir->operands[operand]->print();
1390 printf("\n");
1391 exit(1);
1392 }
1393 op[operand] = this->result;
1394
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1397 */
1398 assert(!ir->operands[operand]->type->is_matrix());
1399 }
1400
1401 visit_expression(ir, op);
1402 }
1403
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1407 */
1408 void
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1410 {
1411 st_src_reg result_src;
1412 st_dst_reg result_dst;
1413
1414 int vector_elements = ir->operands[0]->type->vector_elements;
1415 if (ir->operands[1] &&
1416 ir->operation != ir_binop_interpolate_at_offset &&
1417 ir->operation != ir_binop_interpolate_at_sample) {
1418 st_src_reg *swz_op = NULL;
1419 if (vector_elements > ir->operands[1]->type->vector_elements) {
1420 assert(ir->operands[1]->type->vector_elements == 1);
1421 swz_op = &op[1];
1422 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1423 assert(ir->operands[0]->type->vector_elements == 1);
1424 swz_op = &op[0];
1425 }
1426 if (swz_op) {
1427 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1428 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1429 swizzle_x, swizzle_x);
1430 }
1431 vector_elements = MAX2(vector_elements,
1432 ir->operands[1]->type->vector_elements);
1433 }
1434 if (ir->operands[2] &&
1435 ir->operands[2]->type->vector_elements != vector_elements) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir->operands[2]->type->vector_elements == 1);
1438 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1439 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1440 swizzle_x, swizzle_x);
1441 }
1442
1443 this->result.file = PROGRAM_UNDEFINED;
1444
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1447 */
1448 result_src = get_temp(ir->type);
1449 /* convenience for the emit functions below. */
1450 result_dst = st_dst_reg(result_src);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1453 * sequences.
1454 */
1455 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1456
1457 switch (ir->operation) {
1458 case ir_unop_logic_not:
1459 if (result_dst.type != GLSL_TYPE_FLOAT)
1460 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1461 else {
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1466 */
1467 op[0].negate = ~op[0].negate;
1468 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1469 st_src_reg_for_float(1.0));
1470 }
1471 break;
1472 case ir_unop_neg:
1473 if (result_dst.type == GLSL_TYPE_INT64 ||
1474 result_dst.type == GLSL_TYPE_UINT64)
1475 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1476 else if (result_dst.type == GLSL_TYPE_INT ||
1477 result_dst.type == GLSL_TYPE_UINT)
1478 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1479 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1480 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1481 else {
1482 op[0].negate = ~op[0].negate;
1483 result_src = op[0];
1484 }
1485 break;
1486 case ir_unop_subroutine_to_int:
1487 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1488 break;
1489 case ir_unop_abs:
1490 if (result_dst.type == GLSL_TYPE_FLOAT)
1491 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1492 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1493 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1494 else if (result_dst.type == GLSL_TYPE_INT64 ||
1495 result_dst.type == GLSL_TYPE_UINT64)
1496 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1497 else
1498 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1499 break;
1500 case ir_unop_sign:
1501 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1502 break;
1503 case ir_unop_rcp:
1504 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1505 break;
1506
1507 case ir_unop_exp2:
1508 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1509 break;
1510 case ir_unop_exp:
1511 assert(!"not reached: should be handled by exp_to_exp2");
1512 break;
1513 case ir_unop_log:
1514 assert(!"not reached: should be handled by log_to_log2");
1515 break;
1516 case ir_unop_log2:
1517 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1518 break;
1519 case ir_unop_sin:
1520 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1521 break;
1522 case ir_unop_cos:
1523 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1524 break;
1525 case ir_unop_saturate: {
1526 glsl_to_tgsi_instruction *inst;
1527 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1528 inst->saturate = true;
1529 break;
1530 }
1531
1532 case ir_unop_dFdx:
1533 case ir_unop_dFdx_coarse:
1534 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1535 break;
1536 case ir_unop_dFdx_fine:
1537 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1538 break;
1539 case ir_unop_dFdy:
1540 case ir_unop_dFdy_coarse:
1541 case ir_unop_dFdy_fine:
1542 {
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1546 */
1547 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1548 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1549
1550 unsigned transform_y_index =
1551 _mesa_add_state_reference(this->prog->Parameters,
1552 transform_y_state);
1553
1554 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1555 transform_y_index,
1556 glsl_type::vec4_type);
1557 transform_y.swizzle = SWIZZLE_XXXX;
1558
1559 st_src_reg temp = get_temp(glsl_type::vec4_type);
1560
1561 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1562 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1563 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1564 break;
1565 }
1566
1567 case ir_unop_frexp_sig:
1568 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1569 break;
1570
1571 case ir_unop_frexp_exp:
1572 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1573 break;
1574
1575 case ir_binop_add:
1576 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1577 break;
1578 case ir_binop_sub:
1579 op[1].negate = ~op[1].negate;
1580 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1581 break;
1582
1583 case ir_binop_mul:
1584 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1585 break;
1586 case ir_binop_div:
1587 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1588 break;
1589 case ir_binop_mod:
1590 if (result_dst.type == GLSL_TYPE_FLOAT)
1591 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1592 else
1593 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1594 break;
1595
1596 case ir_binop_less:
1597 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1598 break;
1599 case ir_binop_gequal:
1600 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1601 break;
1602 case ir_binop_equal:
1603 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1604 break;
1605 case ir_binop_nequal:
1606 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1607 break;
1608 case ir_binop_all_equal:
1609 /* "==" operator producing a scalar boolean. */
1610 if (ir->operands[0]->type->is_vector() ||
1611 ir->operands[1]->type->is_vector()) {
1612 st_src_reg temp = get_temp(native_integers ?
1613 glsl_type::uvec4_type :
1614 glsl_type::vec4_type);
1615
1616 if (native_integers) {
1617 st_dst_reg temp_dst = st_dst_reg(temp);
1618 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1619
1620 if (ir->operands[0]->type->is_boolean() &&
1621 ir->operands[1]->as_constant() &&
1622 ir->operands[1]->as_constant()->is_one()) {
1623 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1624 } else {
1625 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1626 }
1627
1628 /* Emit 1-3 AND operations to combine the SEQ results. */
1629 switch (ir->operands[0]->type->vector_elements) {
1630 case 2:
1631 break;
1632 case 3:
1633 temp_dst.writemask = WRITEMASK_Y;
1634 temp1.swizzle = SWIZZLE_YYYY;
1635 temp2.swizzle = SWIZZLE_ZZZZ;
1636 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1637 break;
1638 case 4:
1639 temp_dst.writemask = WRITEMASK_X;
1640 temp1.swizzle = SWIZZLE_XXXX;
1641 temp2.swizzle = SWIZZLE_YYYY;
1642 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1643 temp_dst.writemask = WRITEMASK_Y;
1644 temp1.swizzle = SWIZZLE_ZZZZ;
1645 temp2.swizzle = SWIZZLE_WWWW;
1646 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1647 }
1648
1649 temp1.swizzle = SWIZZLE_XXXX;
1650 temp2.swizzle = SWIZZLE_YYYY;
1651 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1652 } else {
1653 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1654
1655 /* After the dot-product, the value will be an integer on the
1656 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1657 */
1658 emit_dp(ir, result_dst, temp, temp, vector_elements);
1659
1660 /* Negating the result of the dot-product gives values on the range
1661 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1662 * This is achieved using SGE.
1663 */
1664 st_src_reg sge_src = result_src;
1665 sge_src.negate = ~sge_src.negate;
1666 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1667 st_src_reg_for_float(0.0));
1668 }
1669 } else {
1670 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1671 }
1672 break;
1673 case ir_binop_any_nequal:
1674 /* "!=" operator producing a scalar boolean. */
1675 if (ir->operands[0]->type->is_vector() ||
1676 ir->operands[1]->type->is_vector()) {
1677 st_src_reg temp = get_temp(native_integers ?
1678 glsl_type::uvec4_type :
1679 glsl_type::vec4_type);
1680 if (ir->operands[0]->type->is_boolean() &&
1681 ir->operands[1]->as_constant() &&
1682 ir->operands[1]->as_constant()->is_zero()) {
1683 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1684 } else {
1685 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1686 }
1687
1688 if (native_integers) {
1689 st_dst_reg temp_dst = st_dst_reg(temp);
1690 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1691
1692 /* Emit 1-3 OR operations to combine the SNE results. */
1693 switch (ir->operands[0]->type->vector_elements) {
1694 case 2:
1695 break;
1696 case 3:
1697 temp_dst.writemask = WRITEMASK_Y;
1698 temp1.swizzle = SWIZZLE_YYYY;
1699 temp2.swizzle = SWIZZLE_ZZZZ;
1700 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1701 break;
1702 case 4:
1703 temp_dst.writemask = WRITEMASK_X;
1704 temp1.swizzle = SWIZZLE_XXXX;
1705 temp2.swizzle = SWIZZLE_YYYY;
1706 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1707 temp_dst.writemask = WRITEMASK_Y;
1708 temp1.swizzle = SWIZZLE_ZZZZ;
1709 temp2.swizzle = SWIZZLE_WWWW;
1710 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1711 }
1712
1713 temp1.swizzle = SWIZZLE_XXXX;
1714 temp2.swizzle = SWIZZLE_YYYY;
1715 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1716 } else {
1717 /* After the dot-product, the value will be an integer on the
1718 * range [0,4]. Zero stays zero, and positive values become 1.0.
1719 */
1720 glsl_to_tgsi_instruction *const dp =
1721 emit_dp(ir, result_dst, temp, temp, vector_elements);
1722 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1723 /* The clamping to [0,1] can be done for free in the fragment
1724 * shader with a saturate.
1725 */
1726 dp->saturate = true;
1727 } else {
1728 /* Negating the result of the dot-product gives values on the
1729 * range [-4, 0]. Zero stays zero, and negative values become
1730 * 1.0. This achieved using SLT.
1731 */
1732 st_src_reg slt_src = result_src;
1733 slt_src.negate = ~slt_src.negate;
1734 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1735 st_src_reg_for_float(0.0));
1736 }
1737 }
1738 } else {
1739 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1740 }
1741 break;
1742
1743 case ir_binop_logic_xor:
1744 if (native_integers)
1745 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1746 else
1747 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1748 break;
1749
1750 case ir_binop_logic_or: {
1751 if (native_integers) {
1752 /* If integers are used as booleans, we can use an actual "or"
1753 * instruction.
1754 */
1755 assert(native_integers);
1756 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1757 } else {
1758 /* After the addition, the value will be an integer on the
1759 * range [0,2]. Zero stays zero, and positive values become 1.0.
1760 */
1761 glsl_to_tgsi_instruction *add =
1762 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1763 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1764 /* The clamping to [0,1] can be done for free in the fragment
1765 * shader with a saturate if floats are being used as boolean
1766 * values.
1767 */
1768 add->saturate = true;
1769 } else {
1770 /* Negating the result of the addition gives values on the range
1771 * [-2, 0]. Zero stays zero, and negative values become 1.0
1772 * This is achieved using SLT.
1773 */
1774 st_src_reg slt_src = result_src;
1775 slt_src.negate = ~slt_src.negate;
1776 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1777 st_src_reg_for_float(0.0));
1778 }
1779 }
1780 break;
1781 }
1782
1783 case ir_binop_logic_and:
1784 /* If native integers are disabled, the bool args are stored as float 0.0
1785 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1786 * actual AND opcode.
1787 */
1788 if (native_integers)
1789 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1790 else
1791 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1792 break;
1793
1794 case ir_binop_dot:
1795 assert(ir->operands[0]->type->is_vector());
1796 assert(ir->operands[0]->type == ir->operands[1]->type);
1797 emit_dp(ir, result_dst, op[0], op[1],
1798 ir->operands[0]->type->vector_elements);
1799 break;
1800
1801 case ir_unop_sqrt:
1802 if (have_sqrt) {
1803 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1804 } else {
1805 /* This is the only instruction sequence that makes the game "Risen"
1806 * render correctly. ABS is not required for the game, but since GLSL
1807 * declares negative values as "undefined", allowing us to do whatever
1808 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1809 * behavior.
1810 */
1811 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1812 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1813 }
1814 break;
1815 case ir_unop_rsq:
1816 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1817 break;
1818 case ir_unop_i2f:
1819 if (native_integers) {
1820 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1821 break;
1822 }
1823 /* fallthrough to next case otherwise */
1824 case ir_unop_b2f:
1825 if (native_integers) {
1826 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1827 st_src_reg_for_float(1.0));
1828 break;
1829 }
1830 /* fallthrough to next case otherwise */
1831 case ir_unop_i2u:
1832 case ir_unop_u2i:
1833 case ir_unop_i642u64:
1834 case ir_unop_u642i64:
1835 /* Converting between signed and unsigned integers is a no-op. */
1836 result_src = op[0];
1837 result_src.type = result_dst.type;
1838 break;
1839 case ir_unop_b2i:
1840 if (native_integers) {
1841 /* Booleans are stored as integers using ~0 for true and 0 for false.
1842 * GLSL requires that int(bool) return 1 for true and 0 for false.
1843 * This conversion is done with AND, but it could be done with NEG.
1844 */
1845 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1846 st_src_reg_for_int(1));
1847 } else {
1848 /* Booleans and integers are both stored as floats when native
1849 * integers are disabled.
1850 */
1851 result_src = op[0];
1852 }
1853 break;
1854 case ir_unop_f2i:
1855 if (native_integers)
1856 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1857 else
1858 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1859 break;
1860 case ir_unop_f2u:
1861 if (native_integers)
1862 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1863 else
1864 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1865 break;
1866 case ir_unop_bitcast_f2i:
1867 case ir_unop_bitcast_f2u:
1868 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1869 if (op[0].negate || op[0].abs)
1870 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1871 else
1872 result_src = op[0];
1873 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1874 GLSL_TYPE_UINT;
1875 break;
1876 case ir_unop_bitcast_i2f:
1877 case ir_unop_bitcast_u2f:
1878 result_src = op[0];
1879 result_src.type = GLSL_TYPE_FLOAT;
1880 break;
1881 case ir_unop_f2b:
1882 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1883 st_src_reg_for_float(0.0));
1884 break;
1885 case ir_unop_d2b:
1886 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1887 st_src_reg_for_double(0.0));
1888 break;
1889 case ir_unop_i2b:
1890 if (native_integers)
1891 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1892 st_src_reg_for_int(0));
1893 else
1894 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1895 st_src_reg_for_float(0.0));
1896 break;
1897 case ir_unop_bitcast_u642d:
1898 case ir_unop_bitcast_i642d:
1899 result_src = op[0];
1900 result_src.type = GLSL_TYPE_DOUBLE;
1901 break;
1902 case ir_unop_bitcast_d2i64:
1903 result_src = op[0];
1904 result_src.type = GLSL_TYPE_INT64;
1905 break;
1906 case ir_unop_bitcast_d2u64:
1907 result_src = op[0];
1908 result_src.type = GLSL_TYPE_UINT64;
1909 break;
1910 case ir_unop_trunc:
1911 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1912 break;
1913 case ir_unop_ceil:
1914 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1915 break;
1916 case ir_unop_floor:
1917 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1918 break;
1919 case ir_unop_round_even:
1920 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1921 break;
1922 case ir_unop_fract:
1923 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1924 break;
1925
1926 case ir_binop_min:
1927 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1928 break;
1929 case ir_binop_max:
1930 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1931 break;
1932 case ir_binop_pow:
1933 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1934 break;
1935
1936 case ir_unop_bit_not:
1937 if (native_integers) {
1938 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1939 break;
1940 }
1941 case ir_unop_u2f:
1942 if (native_integers) {
1943 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1944 break;
1945 }
1946 case ir_binop_lshift:
1947 case ir_binop_rshift:
1948 if (native_integers) {
1949 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1950 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1951 st_src_reg count;
1952
1953 if (glsl_base_type_is_64bit(op[0].type)) {
1954 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1955 * 64 bits.
1956 */
1957 count = get_temp(glsl_type::u64vec(ir->operands[1]
1958 ->type->components()));
1959 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1960 } else {
1961 count = op[1];
1962 }
1963
1964 emit_asm(ir, opcode, result_dst, op[0], count);
1965 break;
1966 }
1967 case ir_binop_bit_and:
1968 if (native_integers) {
1969 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1970 break;
1971 }
1972 case ir_binop_bit_xor:
1973 if (native_integers) {
1974 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1975 break;
1976 }
1977 case ir_binop_bit_or:
1978 if (native_integers) {
1979 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1980 break;
1981 }
1982
1983 assert(!"GLSL 1.30 features unsupported");
1984 break;
1985
1986 case ir_binop_ubo_load: {
1987 if (ctx->Const.UseSTD430AsDefaultPacking) {
1988 ir_rvalue *block = ir->operands[0];
1989 ir_rvalue *offset = ir->operands[1];
1990 ir_constant *const_block = block->as_constant();
1991
1992 st_src_reg cbuf(PROGRAM_CONSTANT,
1993 (const_block ? const_block->value.u[0] + 1 : 1),
1994 ir->type->base_type);
1995
1996 cbuf.has_index2 = true;
1997
1998 if (!const_block) {
1999 block->accept(this);
2000 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2001 *cbuf.reladdr = this->result;
2002 emit_arl(ir, sampler_reladdr, this->result);
2003 }
2004
2005 /* Calculate the surface offset */
2006 offset->accept(this);
2007 st_src_reg off = this->result;
2008
2009 glsl_to_tgsi_instruction *inst =
2010 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2011
2012 if (result_dst.type == GLSL_TYPE_BOOL)
2013 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2014 st_src_reg_for_int(0));
2015
2016 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2017 NULL);
2018 } else {
2019 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2020 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2021 unsigned const_offset = const_offset_ir ?
2022 const_offset_ir->value.u[0] : 0;
2023 unsigned const_block = const_uniform_block ?
2024 const_uniform_block->value.u[0] + 1 : 1;
2025 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2026 st_src_reg cbuf;
2027
2028 cbuf.type = ir->type->base_type;
2029 cbuf.file = PROGRAM_CONSTANT;
2030 cbuf.index = 0;
2031 cbuf.reladdr = NULL;
2032 cbuf.negate = 0;
2033 cbuf.abs = 0;
2034 cbuf.index2D = const_block;
2035
2036 assert(ir->type->is_vector() || ir->type->is_scalar());
2037
2038 if (const_offset_ir) {
2039 /* Constant index into constant buffer */
2040 cbuf.reladdr = NULL;
2041 cbuf.index = const_offset / 16;
2042 } else {
2043 ir_expression *offset_expr = ir->operands[1]->as_expression();
2044 st_src_reg offset = op[1];
2045
2046 /* The OpenGL spec is written in such a way that accesses with
2047 * non-constant offset are almost always vec4-aligned. The only
2048 * exception to this are members of structs in arrays of structs:
2049 * each struct in an array of structs is at least vec4-aligned,
2050 * but single-element and [ui]vec2 members of the struct may be at
2051 * an offset that is not a multiple of 16 bytes.
2052 *
2053 * Here, we extract that offset, relying on previous passes to
2054 * always generate offset expressions of the form
2055 * (+ expr constant_offset).
2056 *
2057 * Note that the std430 layout, which allows more cases of
2058 * alignment less than vec4 in arrays, is not supported for
2059 * uniform blocks, so we do not have to deal with it here.
2060 */
2061 if (offset_expr && offset_expr->operation == ir_binop_add) {
2062 const_offset_ir = offset_expr->operands[1]->as_constant();
2063 if (const_offset_ir) {
2064 const_offset = const_offset_ir->value.u[0];
2065 cbuf.index = const_offset / 16;
2066 offset_expr->operands[0]->accept(this);
2067 offset = this->result;
2068 }
2069 }
2070
2071 /* Relative/variable index into constant buffer */
2072 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2073 st_src_reg_for_int(4));
2074 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2075 *cbuf.reladdr = index_reg;
2076 }
2077
2078 if (const_uniform_block) {
2079 /* Constant constant buffer */
2080 cbuf.reladdr2 = NULL;
2081 } else {
2082 /* Relative/variable constant buffer */
2083 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2084 *cbuf.reladdr2 = op[0];
2085 }
2086 cbuf.has_index2 = true;
2087
2088 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2089 if (glsl_base_type_is_64bit(cbuf.type))
2090 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2091 const_offset % 16 / 8,
2092 const_offset % 16 / 8,
2093 const_offset % 16 / 8);
2094 else
2095 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2096 const_offset % 16 / 4,
2097 const_offset % 16 / 4,
2098 const_offset % 16 / 4);
2099
2100 if (ir->type->is_boolean()) {
2101 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2102 st_src_reg_for_int(0));
2103 } else {
2104 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2105 }
2106 }
2107 break;
2108 }
2109 case ir_triop_lrp:
2110 /* note: we have to reorder the three args here */
2111 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2112 break;
2113 case ir_triop_csel:
2114 if (this->ctx->Const.NativeIntegers)
2115 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2116 else {
2117 op[0].negate = ~op[0].negate;
2118 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2119 }
2120 break;
2121 case ir_triop_bitfield_extract:
2122 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2123 break;
2124 case ir_quadop_bitfield_insert:
2125 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2126 break;
2127 case ir_unop_bitfield_reverse:
2128 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2129 break;
2130 case ir_unop_bit_count:
2131 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2132 break;
2133 case ir_unop_find_msb:
2134 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2135 break;
2136 case ir_unop_find_lsb:
2137 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2138 break;
2139 case ir_binop_imul_high:
2140 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2141 break;
2142 case ir_triop_fma:
2143 /* In theory, MAD is incorrect here. */
2144 if (have_fma)
2145 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2146 else
2147 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2148 break;
2149 case ir_unop_interpolate_at_centroid:
2150 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2151 break;
2152 case ir_binop_interpolate_at_offset: {
2153 /* The y coordinate needs to be flipped for the default fb */
2154 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2155 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2156
2157 unsigned transform_y_index =
2158 _mesa_add_state_reference(this->prog->Parameters,
2159 transform_y_state);
2160
2161 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2162 transform_y_index,
2163 glsl_type::vec4_type);
2164 transform_y.swizzle = SWIZZLE_XXXX;
2165
2166 st_src_reg temp = get_temp(glsl_type::vec2_type);
2167 st_dst_reg temp_dst = st_dst_reg(temp);
2168
2169 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2170 temp_dst.writemask = WRITEMASK_Y;
2171 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2172 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2173 break;
2174 }
2175 case ir_binop_interpolate_at_sample:
2176 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2177 break;
2178
2179 case ir_unop_d2f:
2180 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2181 break;
2182 case ir_unop_f2d:
2183 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2184 break;
2185 case ir_unop_d2i:
2186 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2187 break;
2188 case ir_unop_i2d:
2189 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2190 break;
2191 case ir_unop_d2u:
2192 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2193 break;
2194 case ir_unop_u2d:
2195 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2196 break;
2197 case ir_unop_unpack_double_2x32:
2198 case ir_unop_pack_double_2x32:
2199 case ir_unop_unpack_int_2x32:
2200 case ir_unop_pack_int_2x32:
2201 case ir_unop_unpack_uint_2x32:
2202 case ir_unop_pack_uint_2x32:
2203 case ir_unop_unpack_sampler_2x32:
2204 case ir_unop_pack_sampler_2x32:
2205 case ir_unop_unpack_image_2x32:
2206 case ir_unop_pack_image_2x32:
2207 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2208 break;
2209
2210 case ir_binop_ldexp:
2211 if (ir->operands[0]->type->is_double()) {
2212 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2213 } else if (ir->operands[0]->type->is_float()) {
2214 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2215 } else {
2216 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2217 }
2218 break;
2219
2220 case ir_unop_pack_half_2x16:
2221 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2222 break;
2223 case ir_unop_unpack_half_2x16:
2224 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2225 break;
2226
2227 case ir_unop_get_buffer_size: {
2228 ir_constant *const_offset = ir->operands[0]->as_constant();
2229 st_src_reg buffer(
2230 PROGRAM_BUFFER,
2231 const_offset ? const_offset->value.u[0] : 0,
2232 GLSL_TYPE_UINT);
2233 if (!const_offset) {
2234 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2235 *buffer.reladdr = op[0];
2236 emit_arl(ir, sampler_reladdr, op[0]);
2237 }
2238 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2239 break;
2240 }
2241
2242 case ir_unop_u2i64:
2243 case ir_unop_u2u64:
2244 case ir_unop_b2i64: {
2245 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2246 st_dst_reg temp_dst = st_dst_reg(temp);
2247 unsigned orig_swz = op[0].swizzle;
2248 /*
2249 * To convert unsigned to 64-bit:
2250 * zero Y channel, copy X channel.
2251 */
2252 temp_dst.writemask = WRITEMASK_Y;
2253 if (vector_elements > 1)
2254 temp_dst.writemask |= WRITEMASK_W;
2255 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2256 temp_dst.writemask = WRITEMASK_X;
2257 if (vector_elements > 1)
2258 temp_dst.writemask |= WRITEMASK_Z;
2259 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2260 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2261 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2262 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2263 else
2264 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2265 result_src = temp;
2266 result_src.type = GLSL_TYPE_UINT64;
2267 if (vector_elements > 2) {
2268 /* Subtle: We rely on the fact that get_temp here returns the next
2269 * TGSI temporary register directly after the temp register used for
2270 * the first two components, so that the result gets picked up
2271 * automatically.
2272 */
2273 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2274 st_dst_reg temp_dst = st_dst_reg(temp);
2275 temp_dst.writemask = WRITEMASK_Y;
2276 if (vector_elements > 3)
2277 temp_dst.writemask |= WRITEMASK_W;
2278 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2279
2280 temp_dst.writemask = WRITEMASK_X;
2281 if (vector_elements > 3)
2282 temp_dst.writemask |= WRITEMASK_Z;
2283 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2284 GET_SWZ(orig_swz, 2),
2285 GET_SWZ(orig_swz, 3),
2286 GET_SWZ(orig_swz, 3));
2287 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2288 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2289 else
2290 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2291 st_src_reg_for_int(1));
2292 }
2293 break;
2294 }
2295 case ir_unop_i642i:
2296 case ir_unop_u642i:
2297 case ir_unop_u642u:
2298 case ir_unop_i642u: {
2299 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2300 st_dst_reg temp_dst = st_dst_reg(temp);
2301 unsigned orig_swz = op[0].swizzle;
2302 unsigned orig_idx = op[0].index;
2303 int el;
2304 temp_dst.writemask = WRITEMASK_X;
2305
2306 for (el = 0; el < vector_elements; el++) {
2307 unsigned swz = GET_SWZ(orig_swz, el);
2308 if (swz & 1)
2309 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2310 SWIZZLE_Z, SWIZZLE_Z);
2311 else
2312 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2313 SWIZZLE_X, SWIZZLE_X);
2314 if (swz > 2)
2315 op[0].index = orig_idx + 1;
2316 op[0].type = GLSL_TYPE_UINT;
2317 temp_dst.writemask = WRITEMASK_X << el;
2318 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2319 }
2320 result_src = temp;
2321 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2322 result_src.type = GLSL_TYPE_UINT;
2323 else
2324 result_src.type = GLSL_TYPE_INT;
2325 break;
2326 }
2327 case ir_unop_i642b:
2328 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2329 st_src_reg_for_int64(0));
2330 break;
2331 case ir_unop_i642f:
2332 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2333 break;
2334 case ir_unop_u642f:
2335 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2336 break;
2337 case ir_unop_i642d:
2338 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2339 break;
2340 case ir_unop_u642d:
2341 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2342 break;
2343 case ir_unop_i2i64:
2344 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2345 break;
2346 case ir_unop_f2i64:
2347 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2348 break;
2349 case ir_unop_d2i64:
2350 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2351 break;
2352 case ir_unop_i2u64:
2353 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2354 break;
2355 case ir_unop_f2u64:
2356 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2357 break;
2358 case ir_unop_d2u64:
2359 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2360 break;
2361 /* these might be needed */
2362 case ir_unop_pack_snorm_2x16:
2363 case ir_unop_pack_unorm_2x16:
2364 case ir_unop_pack_snorm_4x8:
2365 case ir_unop_pack_unorm_4x8:
2366
2367 case ir_unop_unpack_snorm_2x16:
2368 case ir_unop_unpack_unorm_2x16:
2369 case ir_unop_unpack_snorm_4x8:
2370 case ir_unop_unpack_unorm_4x8:
2371
2372 case ir_quadop_vector:
2373 case ir_binop_vector_extract:
2374 case ir_triop_vector_insert:
2375 case ir_binop_carry:
2376 case ir_binop_borrow:
2377 case ir_unop_ssbo_unsized_array_length:
2378 case ir_unop_atan:
2379 case ir_binop_atan2:
2380 case ir_unop_clz:
2381 case ir_binop_add_sat:
2382 case ir_binop_sub_sat:
2383 case ir_binop_abs_sub:
2384 case ir_binop_avg:
2385 case ir_binop_avg_round:
2386 case ir_binop_mul_32x16:
2387 case ir_unop_f162f:
2388 case ir_unop_f2f16:
2389 case ir_unop_f2fmp:
2390 case ir_unop_f162b:
2391 case ir_unop_b2f16:
2392 /* This operation is not supported, or should have already been handled.
2393 */
2394 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2395 break;
2396 }
2397
2398 this->result = result_src;
2399 }
2400
2401
2402 void
2403 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2404 {
2405 st_src_reg src;
2406 int i;
2407 int swizzle[4] = {0};
2408
2409 /* Note that this is only swizzles in expressions, not those on the left
2410 * hand side of an assignment, which do write masking. See ir_assignment
2411 * for that.
2412 */
2413
2414 ir->val->accept(this);
2415 src = this->result;
2416 assert(src.file != PROGRAM_UNDEFINED);
2417 assert(ir->type->vector_elements > 0);
2418
2419 for (i = 0; i < 4; i++) {
2420 if (i < ir->type->vector_elements) {
2421 switch (i) {
2422 case 0:
2423 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2424 break;
2425 case 1:
2426 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2427 break;
2428 case 2:
2429 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2430 break;
2431 case 3:
2432 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2433 break;
2434 }
2435 } else {
2436 /* If the type is smaller than a vec4, replicate the last
2437 * channel out.
2438 */
2439 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2440 }
2441 }
2442
2443 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2444
2445 this->result = src;
2446 }
2447
2448 /* Test if the variable is an array. Note that geometry and
2449 * tessellation shader inputs are outputs are always arrays (except
2450 * for patch inputs), so only the array element type is considered.
2451 */
2452 static bool
2453 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2454 {
2455 const glsl_type *type = var->type;
2456
2457 *remove_array = false;
2458
2459 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2460 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2461 return false;
2462
2463 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2464 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2465 stage == MESA_SHADER_TESS_CTRL) &&
2466 !var->data.patch) {
2467 if (!var->type->is_array())
2468 return false; /* a system value probably */
2469
2470 type = var->type->fields.array;
2471 *remove_array = true;
2472 }
2473
2474 return type->is_array() || type->is_matrix();
2475 }
2476
2477 static unsigned
2478 st_translate_interp_loc(ir_variable *var)
2479 {
2480 if (var->data.centroid)
2481 return TGSI_INTERPOLATE_LOC_CENTROID;
2482 else if (var->data.sample)
2483 return TGSI_INTERPOLATE_LOC_SAMPLE;
2484 else
2485 return TGSI_INTERPOLATE_LOC_CENTER;
2486 }
2487
2488 void
2489 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2490 {
2491 variable_storage *entry;
2492 ir_variable *var = ir->var;
2493 bool remove_array;
2494
2495 if (handle_bound_deref(ir->as_dereference()))
2496 return;
2497
2498 entry = find_variable_storage(ir->var);
2499
2500 if (!entry) {
2501 switch (var->data.mode) {
2502 case ir_var_uniform:
2503 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2504 var->data.param_index);
2505 _mesa_hash_table_insert(this->variables, var, entry);
2506 break;
2507 case ir_var_shader_in: {
2508 /* The linker assigns locations for varyings and attributes,
2509 * including deprecated builtins (like gl_Color), user-assign
2510 * generic attributes (glBindVertexLocation), and
2511 * user-defined varyings.
2512 */
2513 assert(var->data.location != -1);
2514
2515 const glsl_type *type_without_array = var->type->without_array();
2516 struct inout_decl *decl = &inputs[num_inputs];
2517 unsigned component = var->data.location_frac;
2518 unsigned num_components;
2519 num_inputs++;
2520
2521 if (type_without_array->is_64bit())
2522 component = component / 2;
2523 if (type_without_array->vector_elements)
2524 num_components = type_without_array->vector_elements;
2525 else
2526 num_components = 4;
2527
2528 decl->mesa_index = var->data.location;
2529 decl->interp = (glsl_interp_mode) var->data.interpolation;
2530 decl->interp_loc = st_translate_interp_loc(var);
2531 decl->base_type = type_without_array->base_type;
2532 decl->usage_mask = u_bit_consecutive(component, num_components);
2533
2534 if (is_inout_array(shader->Stage, var, &remove_array)) {
2535 decl->array_id = num_input_arrays + 1;
2536 num_input_arrays++;
2537 } else {
2538 decl->array_id = 0;
2539 }
2540
2541 if (remove_array)
2542 decl->size = type_size(var->type->fields.array);
2543 else
2544 decl->size = type_size(var->type);
2545
2546 entry = new(mem_ctx) variable_storage(var,
2547 PROGRAM_INPUT,
2548 decl->mesa_index,
2549 decl->array_id);
2550 entry->component = component;
2551
2552 _mesa_hash_table_insert(this->variables, var, entry);
2553
2554 break;
2555 }
2556 case ir_var_shader_out: {
2557 assert(var->data.location != -1);
2558
2559 const glsl_type *type_without_array = var->type->without_array();
2560 struct inout_decl *decl = &outputs[num_outputs];
2561 unsigned component = var->data.location_frac;
2562 unsigned num_components;
2563 num_outputs++;
2564
2565 decl->invariant = var->data.invariant;
2566
2567 if (type_without_array->is_64bit())
2568 component = component / 2;
2569 if (type_without_array->vector_elements)
2570 num_components = type_without_array->vector_elements;
2571 else
2572 num_components = 4;
2573
2574 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2575 decl->base_type = type_without_array->base_type;
2576 decl->usage_mask = u_bit_consecutive(component, num_components);
2577 if (var->data.stream & (1u << 31)) {
2578 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2579 } else {
2580 assert(var->data.stream < 4);
2581 decl->gs_out_streams = 0;
2582 for (unsigned i = 0; i < num_components; ++i)
2583 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2584 }
2585
2586 if (is_inout_array(shader->Stage, var, &remove_array)) {
2587 decl->array_id = num_output_arrays + 1;
2588 num_output_arrays++;
2589 } else {
2590 decl->array_id = 0;
2591 }
2592
2593 if (remove_array)
2594 decl->size = type_size(var->type->fields.array);
2595 else
2596 decl->size = type_size(var->type);
2597
2598 if (var->data.fb_fetch_output) {
2599 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2600 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2601 var->type, component, decl->array_id);
2602 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2603 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2604 dst.array_id);
2605 } else {
2606 entry = new(mem_ctx) variable_storage(var,
2607 PROGRAM_OUTPUT,
2608 decl->mesa_index,
2609 decl->array_id);
2610 }
2611 entry->component = component;
2612
2613 _mesa_hash_table_insert(this->variables, var, entry);
2614
2615 break;
2616 }
2617 case ir_var_system_value:
2618 entry = new(mem_ctx) variable_storage(var,
2619 PROGRAM_SYSTEM_VALUE,
2620 var->data.location);
2621 break;
2622 case ir_var_auto:
2623 case ir_var_temporary:
2624 st_src_reg src = get_temp(var->type);
2625
2626 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2627 src.array_id);
2628 _mesa_hash_table_insert(this->variables, var, entry);
2629
2630 break;
2631 }
2632
2633 if (!entry) {
2634 printf("Failed to make storage for %s\n", var->name);
2635 exit(1);
2636 }
2637 }
2638
2639 this->result = st_src_reg(entry->file, entry->index, var->type,
2640 entry->component, entry->array_id);
2641 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2642 var->data.mode == ir_var_shader_in &&
2643 var->type->without_array()->is_double())
2644 this->result.is_double_vertex_input = true;
2645 if (!native_integers)
2646 this->result.type = GLSL_TYPE_FLOAT;
2647 }
2648
2649 static void
2650 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2651 GLbitfield64* usage_mask,
2652 GLbitfield64 double_usage_mask,
2653 GLbitfield* patch_usage_mask)
2654 {
2655 unsigned i;
2656 int j;
2657
2658 /* Fix array declarations by removing unused array elements at both ends
2659 * of the arrays. For example, mat4[3] where only mat[1] is used.
2660 */
2661 for (i = 0; i < count; i++) {
2662 struct inout_decl *decl = &decls[i];
2663 if (!decl->array_id)
2664 continue;
2665
2666 /* Shrink the beginning. */
2667 for (j = 0; j < (int)decl->size; j++) {
2668 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2669 if (*patch_usage_mask &
2670 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2671 break;
2672 }
2673 else {
2674 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2675 break;
2676 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2677 break;
2678 }
2679
2680 decl->mesa_index++;
2681 decl->size--;
2682 j--;
2683 }
2684
2685 /* Shrink the end. */
2686 for (j = decl->size-1; j >= 0; j--) {
2687 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2688 if (*patch_usage_mask &
2689 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2690 break;
2691 }
2692 else {
2693 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2694 break;
2695 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2696 break;
2697 }
2698
2699 decl->size--;
2700 }
2701
2702 /* When not all entries of an array are accessed, we mark them as used
2703 * here anyway, to ensure that the input/output mapping logic doesn't get
2704 * confused.
2705 *
2706 * TODO This happens when an array isn't used via indirect access, which
2707 * some game ports do (at least eON-based). There is an optimization
2708 * opportunity here by replacing the array declaration with non-array
2709 * declarations of those slots that are actually used.
2710 */
2711 for (j = 1; j < (int)decl->size; ++j) {
2712 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2713 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2714 else
2715 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2716 }
2717 }
2718 }
2719
2720
2721 static void
2722 mark_array_io(struct inout_decl *decls, unsigned count,
2723 GLbitfield64* usage_mask,
2724 GLbitfield64 double_usage_mask,
2725 GLbitfield* patch_usage_mask)
2726 {
2727 unsigned i;
2728 int j;
2729
2730 /* Fix array declarations by removing unused array elements at both ends
2731 * of the arrays. For example, mat4[3] where only mat[1] is used.
2732 */
2733 for (i = 0; i < count; i++) {
2734 struct inout_decl *decl = &decls[i];
2735 if (!decl->array_id)
2736 continue;
2737
2738 /* When not all entries of an array are accessed, we mark them as used
2739 * here anyway, to ensure that the input/output mapping logic doesn't get
2740 * confused.
2741 *
2742 * TODO This happens when an array isn't used via indirect access, which
2743 * some game ports do (at least eON-based). There is an optimization
2744 * opportunity here by replacing the array declaration with non-array
2745 * declarations of those slots that are actually used.
2746 */
2747 for (j = 0; j < (int)decl->size; ++j) {
2748 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2749 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2750 else
2751 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2752 }
2753 }
2754 }
2755
2756 void
2757 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2758 {
2759 ir_constant *index;
2760 st_src_reg src;
2761 bool is_2D = false;
2762 ir_variable *var = ir->variable_referenced();
2763
2764 if (handle_bound_deref(ir->as_dereference()))
2765 return;
2766
2767 /* We only need the logic provided by count_vec4_slots()
2768 * for arrays of structs. Indirect sampler and image indexing is handled
2769 * elsewhere.
2770 */
2771 int element_size = ir->type->without_array()->is_struct() ?
2772 ir->type->count_vec4_slots(false, var->data.bindless) :
2773 type_size(ir->type);
2774
2775 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2776
2777 ir->array->accept(this);
2778 src = this->result;
2779
2780 if (!src.has_index2) {
2781 switch (this->prog->Target) {
2782 case GL_TESS_CONTROL_PROGRAM_NV:
2783 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2784 !ir->variable_referenced()->data.patch;
2785 break;
2786 case GL_TESS_EVALUATION_PROGRAM_NV:
2787 is_2D = src.file == PROGRAM_INPUT &&
2788 !ir->variable_referenced()->data.patch;
2789 break;
2790 case GL_GEOMETRY_PROGRAM_NV:
2791 is_2D = src.file == PROGRAM_INPUT;
2792 break;
2793 }
2794 }
2795
2796 if (is_2D)
2797 element_size = 1;
2798
2799 if (index) {
2800
2801 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2802 src.file == PROGRAM_INPUT)
2803 element_size = attrib_type_size(ir->type, true);
2804 if (is_2D) {
2805 src.index2D = index->value.i[0];
2806 src.has_index2 = true;
2807 } else
2808 src.index += index->value.i[0] * element_size;
2809 } else {
2810 /* Variable index array dereference. It eats the "vec4" of the
2811 * base of the array and an index that offsets the TGSI register
2812 * index.
2813 */
2814 ir->array_index->accept(this);
2815
2816 st_src_reg index_reg;
2817
2818 if (element_size == 1) {
2819 index_reg = this->result;
2820 } else {
2821 index_reg = get_temp(native_integers ?
2822 glsl_type::int_type : glsl_type::float_type);
2823
2824 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2825 this->result, st_src_reg_for_type(index_reg.type, element_size));
2826 }
2827
2828 /* If there was already a relative address register involved, add the
2829 * new and the old together to get the new offset.
2830 */
2831 if (!is_2D && src.reladdr != NULL) {
2832 st_src_reg accum_reg = get_temp(native_integers ?
2833 glsl_type::int_type : glsl_type::float_type);
2834
2835 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2836 index_reg, *src.reladdr);
2837
2838 index_reg = accum_reg;
2839 }
2840
2841 if (is_2D) {
2842 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2843 *src.reladdr2 = index_reg;
2844 src.index2D = 0;
2845 src.has_index2 = true;
2846 } else {
2847 src.reladdr = ralloc(mem_ctx, st_src_reg);
2848 *src.reladdr = index_reg;
2849 }
2850 }
2851
2852 /* Change the register type to the element type of the array. */
2853 src.type = ir->type->base_type;
2854
2855 this->result = src;
2856 }
2857
2858 void
2859 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2860 {
2861 unsigned int i;
2862 const glsl_type *struct_type = ir->record->type;
2863 ir_variable *var = ir->record->variable_referenced();
2864 int offset = 0;
2865
2866 if (handle_bound_deref(ir->as_dereference()))
2867 return;
2868
2869 ir->record->accept(this);
2870
2871 assert(ir->field_idx >= 0);
2872 assert(var);
2873 for (i = 0; i < struct_type->length; i++) {
2874 if (i == (unsigned) ir->field_idx)
2875 break;
2876 const glsl_type *member_type = struct_type->fields.structure[i].type;
2877 offset += member_type->count_vec4_slots(false, var->data.bindless);
2878 }
2879
2880 /* If the type is smaller than a vec4, replicate the last channel out. */
2881 if (ir->type->is_scalar() || ir->type->is_vector())
2882 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2883 else
2884 this->result.swizzle = SWIZZLE_NOOP;
2885
2886 this->result.index += offset;
2887 this->result.type = ir->type->base_type;
2888 }
2889
2890 /**
2891 * We want to be careful in assignment setup to hit the actual storage
2892 * instead of potentially using a temporary like we might with the
2893 * ir_dereference handler.
2894 */
2895 static st_dst_reg
2896 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2897 {
2898 /* The LHS must be a dereference. If the LHS is a variable indexed array
2899 * access of a vector, it must be separated into a series conditional moves
2900 * before reaching this point (see ir_vec_index_to_cond_assign).
2901 */
2902 assert(ir->as_dereference());
2903 ir_dereference_array *deref_array = ir->as_dereference_array();
2904 if (deref_array) {
2905 assert(!deref_array->array->type->is_vector());
2906 }
2907
2908 /* Use the rvalue deref handler for the most part. We write swizzles using
2909 * the writemask, but we do extract the base component for enhanced layouts
2910 * from the source swizzle.
2911 */
2912 ir->accept(v);
2913 *component = GET_SWZ(v->result.swizzle, 0);
2914 return st_dst_reg(v->result);
2915 }
2916
2917 /**
2918 * Process the condition of a conditional assignment
2919 *
2920 * Examines the condition of a conditional assignment to generate the optimal
2921 * first operand of a \c CMP instruction. If the condition is a relational
2922 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2923 * used as the source for the \c CMP instruction. Otherwise the comparison
2924 * is processed to a boolean result, and the boolean result is used as the
2925 * operand to the CMP instruction.
2926 */
2927 bool
2928 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2929 {
2930 ir_rvalue *src_ir = ir;
2931 bool negate = true;
2932 bool switch_order = false;
2933
2934 ir_expression *const expr = ir->as_expression();
2935
2936 if (native_integers) {
2937 if ((expr != NULL) && (expr->num_operands == 2)) {
2938 enum glsl_base_type type = expr->operands[0]->type->base_type;
2939 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2940 type == GLSL_TYPE_BOOL) {
2941 if (expr->operation == ir_binop_equal) {
2942 if (expr->operands[0]->is_zero()) {
2943 src_ir = expr->operands[1];
2944 switch_order = true;
2945 }
2946 else if (expr->operands[1]->is_zero()) {
2947 src_ir = expr->operands[0];
2948 switch_order = true;
2949 }
2950 }
2951 else if (expr->operation == ir_binop_nequal) {
2952 if (expr->operands[0]->is_zero()) {
2953 src_ir = expr->operands[1];
2954 }
2955 else if (expr->operands[1]->is_zero()) {
2956 src_ir = expr->operands[0];
2957 }
2958 }
2959 }
2960 }
2961
2962 src_ir->accept(this);
2963 return switch_order;
2964 }
2965
2966 if ((expr != NULL) && (expr->num_operands == 2)) {
2967 bool zero_on_left = false;
2968
2969 if (expr->operands[0]->is_zero()) {
2970 src_ir = expr->operands[1];
2971 zero_on_left = true;
2972 } else if (expr->operands[1]->is_zero()) {
2973 src_ir = expr->operands[0];
2974 zero_on_left = false;
2975 }
2976
2977 /* a is - 0 + - 0 +
2978 * (a < 0) T F F ( a < 0) T F F
2979 * (0 < a) F F T (-a < 0) F F T
2980 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2981 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2982 *
2983 * Note that exchanging the order of 0 and 'a' in the comparison simply
2984 * means that the value of 'a' should be negated.
2985 */
2986 if (src_ir != ir) {
2987 switch (expr->operation) {
2988 case ir_binop_less:
2989 switch_order = false;
2990 negate = zero_on_left;
2991 break;
2992
2993 case ir_binop_gequal:
2994 switch_order = true;
2995 negate = zero_on_left;
2996 break;
2997
2998 default:
2999 /* This isn't the right kind of comparison afterall, so make sure
3000 * the whole condition is visited.
3001 */
3002 src_ir = ir;
3003 break;
3004 }
3005 }
3006 }
3007
3008 src_ir->accept(this);
3009
3010 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3011 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3012 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3013 * computing the condition.
3014 */
3015 if (negate)
3016 this->result.negate = ~this->result.negate;
3017
3018 return switch_order;
3019 }
3020
3021 void
3022 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
3023 st_dst_reg *l, st_src_reg *r,
3024 st_src_reg *cond, bool cond_swap)
3025 {
3026 if (type->is_struct()) {
3027 for (unsigned int i = 0; i < type->length; i++) {
3028 emit_block_mov(ir, type->fields.structure[i].type, l, r,
3029 cond, cond_swap);
3030 }
3031 return;
3032 }
3033
3034 if (type->is_array()) {
3035 for (unsigned int i = 0; i < type->length; i++) {
3036 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
3037 }
3038 return;
3039 }
3040
3041 if (type->is_matrix()) {
3042 const struct glsl_type *vec_type;
3043
3044 vec_type = glsl_type::get_instance(type->is_double()
3045 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3046 type->vector_elements, 1);
3047
3048 for (int i = 0; i < type->matrix_columns; i++) {
3049 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3050 }
3051 return;
3052 }
3053
3054 assert(type->is_scalar() || type->is_vector());
3055
3056 l->type = type->base_type;
3057 r->type = type->base_type;
3058 if (cond) {
3059 st_src_reg l_src = st_src_reg(*l);
3060
3061 if (l_src.file == PROGRAM_OUTPUT &&
3062 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3063 (l_src.index == FRAG_RESULT_DEPTH ||
3064 l_src.index == FRAG_RESULT_STENCIL)) {
3065 /* This is a special case because the source swizzles will be shifted
3066 * later to account for the difference between GLSL (where they're
3067 * plain floats) and TGSI (where they're Z and Y components). */
3068 l_src.swizzle = SWIZZLE_XXXX;
3069 }
3070
3071 if (native_integers) {
3072 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3073 cond_swap ? l_src : *r,
3074 cond_swap ? *r : l_src);
3075 } else {
3076 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3077 cond_swap ? l_src : *r,
3078 cond_swap ? *r : l_src);
3079 }
3080 } else {
3081 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3082 }
3083 l->index++;
3084 r->index++;
3085 if (type->is_dual_slot()) {
3086 l->index++;
3087 if (r->is_double_vertex_input == false)
3088 r->index++;
3089 }
3090 }
3091
3092 void
3093 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3094 {
3095 int dst_component;
3096 st_dst_reg l;
3097 st_src_reg r;
3098
3099 /* all generated instructions need to be flaged as precise */
3100 this->precise = is_precise(ir->lhs->variable_referenced());
3101 ir->rhs->accept(this);
3102 r = this->result;
3103
3104 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3105
3106 {
3107 int swizzles[4];
3108 int first_enabled_chan = 0;
3109 int rhs_chan = 0;
3110 ir_variable *variable = ir->lhs->variable_referenced();
3111
3112 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3113 variable->data.mode == ir_var_shader_out &&
3114 (variable->data.location == FRAG_RESULT_DEPTH ||
3115 variable->data.location == FRAG_RESULT_STENCIL)) {
3116 assert(ir->lhs->type->is_scalar());
3117 assert(ir->write_mask == WRITEMASK_X);
3118
3119 if (variable->data.location == FRAG_RESULT_DEPTH)
3120 l.writemask = WRITEMASK_Z;
3121 else {
3122 assert(variable->data.location == FRAG_RESULT_STENCIL);
3123 l.writemask = WRITEMASK_Y;
3124 }
3125 } else if (ir->write_mask == 0) {
3126 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3127
3128 unsigned num_elements =
3129 ir->lhs->type->without_array()->vector_elements;
3130
3131 if (num_elements) {
3132 l.writemask = u_bit_consecutive(0, num_elements);
3133 } else {
3134 /* The type is a struct or an array of (array of) structs. */
3135 l.writemask = WRITEMASK_XYZW;
3136 }
3137 } else {
3138 l.writemask = ir->write_mask;
3139 }
3140
3141 for (int i = 0; i < 4; i++) {
3142 if (l.writemask & (1 << i)) {
3143 first_enabled_chan = GET_SWZ(r.swizzle, i);
3144 break;
3145 }
3146 }
3147
3148 l.writemask = l.writemask << dst_component;
3149
3150 /* Swizzle a small RHS vector into the channels being written.
3151 *
3152 * glsl ir treats write_mask as dictating how many channels are
3153 * present on the RHS while TGSI treats write_mask as just
3154 * showing which channels of the vec4 RHS get written.
3155 */
3156 for (int i = 0; i < 4; i++) {
3157 if (l.writemask & (1 << i))
3158 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3159 else
3160 swizzles[i] = first_enabled_chan;
3161 }
3162 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3163 swizzles[2], swizzles[3]);
3164 }
3165
3166 assert(l.file != PROGRAM_UNDEFINED);
3167 assert(r.file != PROGRAM_UNDEFINED);
3168
3169 if (ir->condition) {
3170 const bool switch_order = this->process_move_condition(ir->condition);
3171 st_src_reg condition = this->result;
3172
3173 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3174 } else if (ir->rhs->as_expression() &&
3175 this->instructions.get_tail() &&
3176 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3177 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3178 type_size(ir->lhs->type) == 1 &&
3179 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3180 /* To avoid emitting an extra MOV when assigning an expression to a
3181 * variable, emit the last instruction of the expression again, but
3182 * replace the destination register with the target of the assignment.
3183 * Dead code elimination will remove the original instruction.
3184 */
3185 glsl_to_tgsi_instruction *inst, *new_inst;
3186 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3187 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3188 new_inst->saturate = inst->saturate;
3189 new_inst->resource = inst->resource;
3190 inst->dead_mask = inst->dst[0].writemask;
3191 } else {
3192 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3193 }
3194 this->precise = 0;
3195 }
3196
3197
3198 void
3199 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3200 {
3201 st_src_reg src;
3202 GLdouble stack_vals[4] = { 0 };
3203 gl_constant_value *values = (gl_constant_value *) stack_vals;
3204 GLenum gl_type = GL_NONE;
3205 unsigned int i, elements;
3206 static int in_array = 0;
3207 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3208
3209 /* Unfortunately, 4 floats is all we can get into
3210 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3211 * aggregate constant and move each constant value into it. If we
3212 * get lucky, copy propagation will eliminate the extra moves.
3213 */
3214 if (ir->type->is_struct()) {
3215 st_src_reg temp_base = get_temp(ir->type);
3216 st_dst_reg temp = st_dst_reg(temp_base);
3217
3218 for (i = 0; i < ir->type->length; i++) {
3219 ir_constant *const field_value = ir->get_record_field(i);
3220 int size = type_size(field_value->type);
3221
3222 assert(size > 0);
3223
3224 field_value->accept(this);
3225 src = this->result;
3226
3227 for (unsigned j = 0; j < (unsigned int)size; j++) {
3228 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3229
3230 src.index++;
3231 temp.index++;
3232 }
3233 }
3234 this->result = temp_base;
3235 return;
3236 }
3237
3238 if (ir->type->is_array()) {
3239 st_src_reg temp_base = get_temp(ir->type);
3240 st_dst_reg temp = st_dst_reg(temp_base);
3241 int size = type_size(ir->type->fields.array);
3242
3243 assert(size > 0);
3244 in_array++;
3245
3246 for (i = 0; i < ir->type->length; i++) {
3247 ir->const_elements[i]->accept(this);
3248 src = this->result;
3249 for (int j = 0; j < size; j++) {
3250 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3251
3252 src.index++;
3253 temp.index++;
3254 }
3255 }
3256 this->result = temp_base;
3257 in_array--;
3258 return;
3259 }
3260
3261 if (ir->type->is_matrix()) {
3262 st_src_reg mat = get_temp(ir->type);
3263 st_dst_reg mat_column = st_dst_reg(mat);
3264
3265 for (i = 0; i < ir->type->matrix_columns; i++) {
3266 switch (ir->type->base_type) {
3267 case GLSL_TYPE_FLOAT:
3268 values = (gl_constant_value *)
3269 &ir->value.f[i * ir->type->vector_elements];
3270
3271 src = st_src_reg(file, -1, ir->type->base_type);
3272 src.index = add_constant(file,
3273 values,
3274 ir->type->vector_elements,
3275 GL_FLOAT,
3276 &src.swizzle);
3277 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3278 break;
3279 case GLSL_TYPE_DOUBLE:
3280 values = (gl_constant_value *)
3281 &ir->value.d[i * ir->type->vector_elements];
3282 src = st_src_reg(file, -1, ir->type->base_type);
3283 src.index = add_constant(file,
3284 values,
3285 ir->type->vector_elements,
3286 GL_DOUBLE,
3287 &src.swizzle);
3288 if (ir->type->vector_elements >= 2) {
3289 mat_column.writemask = WRITEMASK_XY;
3290 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3291 SWIZZLE_X, SWIZZLE_Y);
3292 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3293 } else {
3294 mat_column.writemask = WRITEMASK_X;
3295 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3296 SWIZZLE_X, SWIZZLE_X);
3297 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3298 }
3299 src.index++;
3300 if (ir->type->vector_elements > 2) {
3301 if (ir->type->vector_elements == 4) {
3302 mat_column.writemask = WRITEMASK_ZW;
3303 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3304 SWIZZLE_X, SWIZZLE_Y);
3305 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3306 } else {
3307 mat_column.writemask = WRITEMASK_Z;
3308 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3309 SWIZZLE_Y, SWIZZLE_Y);
3310 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3311 mat_column.writemask = WRITEMASK_XYZW;
3312 src.swizzle = SWIZZLE_XYZW;
3313 }
3314 mat_column.index++;
3315 }
3316 break;
3317 default:
3318 unreachable("Illegal matrix constant type.\n");
3319 break;
3320 }
3321 mat_column.index++;
3322 }
3323 this->result = mat;
3324 return;
3325 }
3326
3327 elements = ir->type->vector_elements;
3328 switch (ir->type->base_type) {
3329 case GLSL_TYPE_FLOAT:
3330 gl_type = GL_FLOAT;
3331 for (i = 0; i < ir->type->vector_elements; i++) {
3332 values[i].f = ir->value.f[i];
3333 }
3334 break;
3335 case GLSL_TYPE_DOUBLE:
3336 gl_type = GL_DOUBLE;
3337 for (i = 0; i < ir->type->vector_elements; i++) {
3338 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3339 }
3340 break;
3341 case GLSL_TYPE_INT64:
3342 gl_type = GL_INT64_ARB;
3343 for (i = 0; i < ir->type->vector_elements; i++) {
3344 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3345 }
3346 break;
3347 case GLSL_TYPE_UINT64:
3348 gl_type = GL_UNSIGNED_INT64_ARB;
3349 for (i = 0; i < ir->type->vector_elements; i++) {
3350 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3351 }
3352 break;
3353 case GLSL_TYPE_UINT:
3354 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3355 for (i = 0; i < ir->type->vector_elements; i++) {
3356 if (native_integers)
3357 values[i].u = ir->value.u[i];
3358 else
3359 values[i].f = ir->value.u[i];
3360 }
3361 break;
3362 case GLSL_TYPE_INT:
3363 gl_type = native_integers ? GL_INT : GL_FLOAT;
3364 for (i = 0; i < ir->type->vector_elements; i++) {
3365 if (native_integers)
3366 values[i].i = ir->value.i[i];
3367 else
3368 values[i].f = ir->value.i[i];
3369 }
3370 break;
3371 case GLSL_TYPE_BOOL:
3372 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3373 for (i = 0; i < ir->type->vector_elements; i++) {
3374 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3375 }
3376 break;
3377 case GLSL_TYPE_SAMPLER:
3378 case GLSL_TYPE_IMAGE:
3379 gl_type = GL_UNSIGNED_INT;
3380 elements = 2;
3381 values[0].u = ir->value.u64[0] & 0xffffffff;
3382 values[1].u = ir->value.u64[0] >> 32;
3383 break;
3384 default:
3385 assert(!"Non-float/uint/int/bool/sampler/image constant");
3386 }
3387
3388 this->result = st_src_reg(file, -1, ir->type);
3389 this->result.index = add_constant(file,
3390 values,
3391 elements,
3392 gl_type,
3393 &this->result.swizzle);
3394 }
3395
3396 void
3397 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3398 {
3399 exec_node *param = ir->actual_parameters.get_head();
3400 ir_dereference *deref = static_cast<ir_dereference *>(param);
3401 ir_variable *location = deref->variable_referenced();
3402 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3403 /* Calculate the surface offset */
3404 st_src_reg offset;
3405 unsigned array_size = 0, base = 0;
3406 uint16_t index = 0;
3407 st_src_reg resource;
3408
3409 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3410
3411 if (has_hw_atomics) {
3412 variable_storage *entry = find_variable_storage(location);
3413 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3414 location->data.binding);
3415
3416 if (!entry) {
3417 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3418 num_atomics);
3419 _mesa_hash_table_insert(this->variables, location, entry);
3420
3421 atomic_info[num_atomics].location = location->data.location;
3422 atomic_info[num_atomics].binding = location->data.binding;
3423 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3424 if (atomic_info[num_atomics].size == 0)
3425 atomic_info[num_atomics].size = 1;
3426 atomic_info[num_atomics].array_id = 0;
3427 num_atomics++;
3428 }
3429
3430 if (offset.file != PROGRAM_UNDEFINED) {
3431 if (atomic_info[entry->index].array_id == 0) {
3432 num_atomic_arrays++;
3433 atomic_info[entry->index].array_id = num_atomic_arrays;
3434 }
3435 buffer.array_id = atomic_info[entry->index].array_id;
3436 }
3437
3438 buffer.index = index;
3439 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3440 buffer.has_index2 = true;
3441
3442 if (offset.file != PROGRAM_UNDEFINED) {
3443 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3444 *buffer.reladdr = offset;
3445 emit_arl(ir, sampler_reladdr, offset);
3446 }
3447 offset = st_src_reg_for_int(0);
3448
3449 resource = buffer;
3450 } else {
3451 st_src_reg buffer(PROGRAM_BUFFER,
3452 prog->info.num_ssbos +
3453 location->data.binding,
3454 GLSL_TYPE_ATOMIC_UINT);
3455
3456 if (offset.file != PROGRAM_UNDEFINED) {
3457 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3458 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3459 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3460 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3461 } else {
3462 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3463 }
3464 resource = buffer;
3465 }
3466
3467 ir->return_deref->accept(this);
3468 st_dst_reg dst(this->result);
3469 dst.writemask = WRITEMASK_X;
3470
3471 glsl_to_tgsi_instruction *inst;
3472
3473 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3474 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3475 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3476 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3477 st_src_reg_for_int(1));
3478 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3479 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3480 st_src_reg_for_int(-1));
3481 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3482 } else {
3483 param = param->get_next();
3484 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3485 val->accept(this);
3486
3487 st_src_reg data = this->result, data2 = undef_src;
3488 enum tgsi_opcode opcode;
3489 switch (ir->callee->intrinsic_id) {
3490 case ir_intrinsic_atomic_counter_add:
3491 opcode = TGSI_OPCODE_ATOMUADD;
3492 break;
3493 case ir_intrinsic_atomic_counter_min:
3494 opcode = TGSI_OPCODE_ATOMIMIN;
3495 break;
3496 case ir_intrinsic_atomic_counter_max:
3497 opcode = TGSI_OPCODE_ATOMIMAX;
3498 break;
3499 case ir_intrinsic_atomic_counter_and:
3500 opcode = TGSI_OPCODE_ATOMAND;
3501 break;
3502 case ir_intrinsic_atomic_counter_or:
3503 opcode = TGSI_OPCODE_ATOMOR;
3504 break;
3505 case ir_intrinsic_atomic_counter_xor:
3506 opcode = TGSI_OPCODE_ATOMXOR;
3507 break;
3508 case ir_intrinsic_atomic_counter_exchange:
3509 opcode = TGSI_OPCODE_ATOMXCHG;
3510 break;
3511 case ir_intrinsic_atomic_counter_comp_swap: {
3512 opcode = TGSI_OPCODE_ATOMCAS;
3513 param = param->get_next();
3514 val = ((ir_instruction *)param)->as_rvalue();
3515 val->accept(this);
3516 data2 = this->result;
3517 break;
3518 }
3519 default:
3520 assert(!"Unexpected intrinsic");
3521 return;
3522 }
3523
3524 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3525 }
3526
3527 inst->resource = resource;
3528 }
3529
3530 void
3531 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3532 {
3533 exec_node *param = ir->actual_parameters.get_head();
3534
3535 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3536
3537 param = param->get_next();
3538 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3539
3540 ir_constant *const_block = block->as_constant();
3541 st_src_reg buffer(
3542 PROGRAM_BUFFER,
3543 const_block ? const_block->value.u[0] : 0,
3544 GLSL_TYPE_UINT);
3545
3546 if (!const_block) {
3547 block->accept(this);
3548 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3549 *buffer.reladdr = this->result;
3550 emit_arl(ir, sampler_reladdr, this->result);
3551 }
3552
3553 /* Calculate the surface offset */
3554 offset->accept(this);
3555 st_src_reg off = this->result;
3556
3557 st_dst_reg dst = undef_dst;
3558 if (ir->return_deref) {
3559 ir->return_deref->accept(this);
3560 dst = st_dst_reg(this->result);
3561 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3562 }
3563
3564 glsl_to_tgsi_instruction *inst;
3565
3566 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3567 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3568 if (dst.type == GLSL_TYPE_BOOL)
3569 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3570 st_src_reg_for_int(0));
3571 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3572 param = param->get_next();
3573 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3574 val->accept(this);
3575
3576 param = param->get_next();
3577 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3578 assert(write_mask);
3579 dst.writemask = write_mask->value.u[0];
3580
3581 dst.type = this->result.type;
3582 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3583 } else {
3584 param = param->get_next();
3585 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3586 val->accept(this);
3587
3588 st_src_reg data = this->result, data2 = undef_src;
3589 enum tgsi_opcode opcode;
3590 switch (ir->callee->intrinsic_id) {
3591 case ir_intrinsic_ssbo_atomic_add:
3592 opcode = TGSI_OPCODE_ATOMUADD;
3593 break;
3594 case ir_intrinsic_ssbo_atomic_min:
3595 opcode = TGSI_OPCODE_ATOMIMIN;
3596 break;
3597 case ir_intrinsic_ssbo_atomic_max:
3598 opcode = TGSI_OPCODE_ATOMIMAX;
3599 break;
3600 case ir_intrinsic_ssbo_atomic_and:
3601 opcode = TGSI_OPCODE_ATOMAND;
3602 break;
3603 case ir_intrinsic_ssbo_atomic_or:
3604 opcode = TGSI_OPCODE_ATOMOR;
3605 break;
3606 case ir_intrinsic_ssbo_atomic_xor:
3607 opcode = TGSI_OPCODE_ATOMXOR;
3608 break;
3609 case ir_intrinsic_ssbo_atomic_exchange:
3610 opcode = TGSI_OPCODE_ATOMXCHG;
3611 break;
3612 case ir_intrinsic_ssbo_atomic_comp_swap:
3613 opcode = TGSI_OPCODE_ATOMCAS;
3614 param = param->get_next();
3615 val = ((ir_instruction *)param)->as_rvalue();
3616 val->accept(this);
3617 data2 = this->result;
3618 break;
3619 default:
3620 assert(!"Unexpected intrinsic");
3621 return;
3622 }
3623
3624 inst = emit_asm(ir, opcode, dst, off, data, data2);
3625 }
3626
3627 param = param->get_next();
3628 ir_constant *access = NULL;
3629 if (!param->is_tail_sentinel()) {
3630 access = ((ir_instruction *)param)->as_constant();
3631 assert(access);
3632 }
3633
3634 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3635 }
3636
3637 void
3638 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3639 {
3640 switch (ir->callee->intrinsic_id) {
3641 case ir_intrinsic_memory_barrier:
3642 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3643 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3644 TGSI_MEMBAR_ATOMIC_BUFFER |
3645 TGSI_MEMBAR_SHADER_IMAGE |
3646 TGSI_MEMBAR_SHARED));
3647 break;
3648 case ir_intrinsic_memory_barrier_atomic_counter:
3649 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3650 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3651 break;
3652 case ir_intrinsic_memory_barrier_buffer:
3653 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3654 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3655 break;
3656 case ir_intrinsic_memory_barrier_image:
3657 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3658 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3659 break;
3660 case ir_intrinsic_memory_barrier_shared:
3661 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3662 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3663 break;
3664 case ir_intrinsic_group_memory_barrier:
3665 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3666 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3667 TGSI_MEMBAR_ATOMIC_BUFFER |
3668 TGSI_MEMBAR_SHADER_IMAGE |
3669 TGSI_MEMBAR_SHARED |
3670 TGSI_MEMBAR_THREAD_GROUP));
3671 break;
3672 default:
3673 assert(!"Unexpected memory barrier intrinsic");
3674 }
3675 }
3676
3677 void
3678 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3679 {
3680 exec_node *param = ir->actual_parameters.get_head();
3681
3682 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3683
3684 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3685
3686 /* Calculate the surface offset */
3687 offset->accept(this);
3688 st_src_reg off = this->result;
3689
3690 st_dst_reg dst = undef_dst;
3691 if (ir->return_deref) {
3692 ir->return_deref->accept(this);
3693 dst = st_dst_reg(this->result);
3694 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3695 }
3696
3697 glsl_to_tgsi_instruction *inst;
3698
3699 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3700 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3701 inst->resource = buffer;
3702 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3703 param = param->get_next();
3704 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3705 val->accept(this);
3706
3707 param = param->get_next();
3708 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3709 assert(write_mask);
3710 dst.writemask = write_mask->value.u[0];
3711
3712 dst.type = this->result.type;
3713 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3714 inst->resource = buffer;
3715 } else {
3716 param = param->get_next();
3717 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3718 val->accept(this);
3719
3720 st_src_reg data = this->result, data2 = undef_src;
3721 enum tgsi_opcode opcode;
3722 switch (ir->callee->intrinsic_id) {
3723 case ir_intrinsic_shared_atomic_add:
3724 opcode = TGSI_OPCODE_ATOMUADD;
3725 break;
3726 case ir_intrinsic_shared_atomic_min:
3727 opcode = TGSI_OPCODE_ATOMIMIN;
3728 break;
3729 case ir_intrinsic_shared_atomic_max:
3730 opcode = TGSI_OPCODE_ATOMIMAX;
3731 break;
3732 case ir_intrinsic_shared_atomic_and:
3733 opcode = TGSI_OPCODE_ATOMAND;
3734 break;
3735 case ir_intrinsic_shared_atomic_or:
3736 opcode = TGSI_OPCODE_ATOMOR;
3737 break;
3738 case ir_intrinsic_shared_atomic_xor:
3739 opcode = TGSI_OPCODE_ATOMXOR;
3740 break;
3741 case ir_intrinsic_shared_atomic_exchange:
3742 opcode = TGSI_OPCODE_ATOMXCHG;
3743 break;
3744 case ir_intrinsic_shared_atomic_comp_swap:
3745 opcode = TGSI_OPCODE_ATOMCAS;
3746 param = param->get_next();
3747 val = ((ir_instruction *)param)->as_rvalue();
3748 val->accept(this);
3749 data2 = this->result;
3750 break;
3751 default:
3752 assert(!"Unexpected intrinsic");
3753 return;
3754 }
3755
3756 inst = emit_asm(ir, opcode, dst, off, data, data2);
3757 inst->resource = buffer;
3758 }
3759 }
3760
3761 static void
3762 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3763 bool *memory_coherent, bool *memory_volatile,
3764 bool *memory_restrict, bool *memory_read_only,
3765 enum pipe_format *image_format)
3766 {
3767
3768 switch (ir->ir_type) {
3769 case ir_type_dereference_record: {
3770 ir_dereference_record *deref_record = ir->as_dereference_record();
3771 const glsl_type *struct_type = deref_record->record->type;
3772 int fild_idx = deref_record->field_idx;
3773
3774 *type = struct_type->fields.structure[fild_idx].type->without_array();
3775 *memory_coherent =
3776 struct_type->fields.structure[fild_idx].memory_coherent;
3777 *memory_volatile =
3778 struct_type->fields.structure[fild_idx].memory_volatile;
3779 *memory_restrict =
3780 struct_type->fields.structure[fild_idx].memory_restrict;
3781 *memory_read_only =
3782 struct_type->fields.structure[fild_idx].memory_read_only;
3783 *image_format =
3784 struct_type->fields.structure[fild_idx].image_format;
3785 break;
3786 }
3787
3788 case ir_type_dereference_array: {
3789 ir_dereference_array *deref_arr = ir->as_dereference_array();
3790 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3791 memory_coherent, memory_volatile, memory_restrict,
3792 memory_read_only, image_format);
3793 break;
3794 }
3795
3796 case ir_type_dereference_variable: {
3797 ir_variable *var = ir->variable_referenced();
3798
3799 *type = var->type->without_array();
3800 *memory_coherent = var->data.memory_coherent;
3801 *memory_volatile = var->data.memory_volatile;
3802 *memory_restrict = var->data.memory_restrict;
3803 *memory_read_only = var->data.memory_read_only;
3804 *image_format = var->data.image_format;
3805 break;
3806 }
3807
3808 default:
3809 break;
3810 }
3811 }
3812
3813 void
3814 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3815 {
3816 exec_node *param = ir->actual_parameters.get_head();
3817
3818 ir_dereference *img = (ir_dereference *)param;
3819 const ir_variable *imgvar = img->variable_referenced();
3820 unsigned sampler_array_size = 1, sampler_base = 0;
3821 bool memory_coherent = false, memory_volatile = false,
3822 memory_restrict = false, memory_read_only = false;
3823 enum pipe_format image_format = PIPE_FORMAT_NONE;
3824 const glsl_type *type = NULL;
3825
3826 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3827 &memory_restrict, &memory_read_only, &image_format);
3828
3829 st_src_reg reladdr;
3830 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3831 uint16_t index = 0;
3832 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3833 &index, &reladdr, !imgvar->contains_bindless());
3834
3835 image.index = index;
3836 if (reladdr.file != PROGRAM_UNDEFINED) {
3837 image.reladdr = ralloc(mem_ctx, st_src_reg);
3838 *image.reladdr = reladdr;
3839 emit_arl(ir, sampler_reladdr, reladdr);
3840 }
3841
3842 st_dst_reg dst = undef_dst;
3843 if (ir->return_deref) {
3844 ir->return_deref->accept(this);
3845 dst = st_dst_reg(this->result);
3846 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3847 }
3848
3849 glsl_to_tgsi_instruction *inst;
3850
3851 st_src_reg bindless;
3852 if (imgvar->contains_bindless()) {
3853 img->accept(this);
3854 bindless = this->result;
3855 }
3856
3857 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3858 dst.writemask = WRITEMASK_XYZ;
3859 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3860 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3861 st_src_reg res = get_temp(glsl_type::ivec4_type);
3862 st_dst_reg dstres = st_dst_reg(res);
3863 dstres.writemask = WRITEMASK_W;
3864 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3865 res.swizzle = SWIZZLE_WWWW;
3866 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3867 } else {
3868 st_src_reg arg1 = undef_src, arg2 = undef_src;
3869 st_src_reg coord;
3870 st_dst_reg coord_dst;
3871 coord = get_temp(glsl_type::ivec4_type);
3872 coord_dst = st_dst_reg(coord);
3873 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3874 param = param->get_next();
3875 ((ir_dereference *)param)->accept(this);
3876 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3877 coord.swizzle = SWIZZLE_XXXX;
3878 switch (type->coordinate_components()) {
3879 case 4: assert(!"unexpected coord count");
3880 /* fallthrough */
3881 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3882 /* fallthrough */
3883 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3884 }
3885
3886 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3887 param = param->get_next();
3888 ((ir_dereference *)param)->accept(this);
3889 st_src_reg sample = this->result;
3890 sample.swizzle = SWIZZLE_XXXX;
3891 coord_dst.writemask = WRITEMASK_W;
3892 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3893 coord.swizzle |= SWIZZLE_W << 9;
3894 }
3895
3896 param = param->get_next();
3897 if (!param->is_tail_sentinel()) {
3898 ((ir_dereference *)param)->accept(this);
3899 arg1 = this->result;
3900 param = param->get_next();
3901 }
3902
3903 if (!param->is_tail_sentinel()) {
3904 ((ir_dereference *)param)->accept(this);
3905 arg2 = this->result;
3906 param = param->get_next();
3907 }
3908
3909 assert(param->is_tail_sentinel());
3910
3911 enum tgsi_opcode opcode;
3912 switch (ir->callee->intrinsic_id) {
3913 case ir_intrinsic_image_load:
3914 opcode = TGSI_OPCODE_LOAD;
3915 break;
3916 case ir_intrinsic_image_store:
3917 opcode = TGSI_OPCODE_STORE;
3918 break;
3919 case ir_intrinsic_image_atomic_add:
3920 opcode = TGSI_OPCODE_ATOMUADD;
3921 break;
3922 case ir_intrinsic_image_atomic_min:
3923 opcode = TGSI_OPCODE_ATOMIMIN;
3924 break;
3925 case ir_intrinsic_image_atomic_max:
3926 opcode = TGSI_OPCODE_ATOMIMAX;
3927 break;
3928 case ir_intrinsic_image_atomic_and:
3929 opcode = TGSI_OPCODE_ATOMAND;
3930 break;
3931 case ir_intrinsic_image_atomic_or:
3932 opcode = TGSI_OPCODE_ATOMOR;
3933 break;
3934 case ir_intrinsic_image_atomic_xor:
3935 opcode = TGSI_OPCODE_ATOMXOR;
3936 break;
3937 case ir_intrinsic_image_atomic_exchange:
3938 opcode = TGSI_OPCODE_ATOMXCHG;
3939 break;
3940 case ir_intrinsic_image_atomic_comp_swap:
3941 opcode = TGSI_OPCODE_ATOMCAS;
3942 break;
3943 case ir_intrinsic_image_atomic_inc_wrap: {
3944 /* There's a bit of disagreement between GLSL and the hardware. The
3945 * hardware wants to wrap after the given wrap value, while GLSL
3946 * wants to wrap at the value. Subtract 1 to make up the difference.
3947 */
3948 st_src_reg wrap = get_temp(glsl_type::uint_type);
3949 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(wrap),
3950 arg1, st_src_reg_for_int(-1));
3951 arg1 = wrap;
3952 opcode = TGSI_OPCODE_ATOMINC_WRAP;
3953 break;
3954 }
3955 case ir_intrinsic_image_atomic_dec_wrap:
3956 opcode = TGSI_OPCODE_ATOMDEC_WRAP;
3957 break;
3958 default:
3959 assert(!"Unexpected intrinsic");
3960 return;
3961 }
3962
3963 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3964 if (opcode == TGSI_OPCODE_STORE)
3965 inst->dst[0].writemask = WRITEMASK_XYZW;
3966 }
3967
3968 if (imgvar->contains_bindless()) {
3969 inst->resource = bindless;
3970 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3971 SWIZZLE_X, SWIZZLE_Y);
3972 } else {
3973 inst->resource = image;
3974 inst->sampler_array_size = sampler_array_size;
3975 inst->sampler_base = sampler_base;
3976 }
3977
3978 inst->tex_target = type->sampler_index();
3979 inst->image_format = image_format;
3980 inst->read_only = memory_read_only;
3981
3982 if (memory_coherent)
3983 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3984 if (memory_restrict)
3985 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3986 if (memory_volatile)
3987 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3988 }
3989
3990 void
3991 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
3992 {
3993 ir->return_deref->accept(this);
3994 st_dst_reg dst = st_dst_reg(this->result);
3995
3996 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
3997
3998 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
3999 unsigned num_src = 0;
4000 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
4001 assert(num_src < ARRAY_SIZE(src));
4002
4003 this->result.file = PROGRAM_UNDEFINED;
4004 param->accept(this);
4005 assert(this->result.file != PROGRAM_UNDEFINED);
4006
4007 src[num_src] = this->result;
4008 num_src++;
4009 }
4010
4011 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
4012 }
4013
4014 void
4015 glsl_to_tgsi_visitor::visit(ir_call *ir)
4016 {
4017 ir_function_signature *sig = ir->callee;
4018
4019 /* Filter out intrinsics */
4020 switch (sig->intrinsic_id) {
4021 case ir_intrinsic_atomic_counter_read:
4022 case ir_intrinsic_atomic_counter_increment:
4023 case ir_intrinsic_atomic_counter_predecrement:
4024 case ir_intrinsic_atomic_counter_add:
4025 case ir_intrinsic_atomic_counter_min:
4026 case ir_intrinsic_atomic_counter_max:
4027 case ir_intrinsic_atomic_counter_and:
4028 case ir_intrinsic_atomic_counter_or:
4029 case ir_intrinsic_atomic_counter_xor:
4030 case ir_intrinsic_atomic_counter_exchange:
4031 case ir_intrinsic_atomic_counter_comp_swap:
4032 visit_atomic_counter_intrinsic(ir);
4033 return;
4034
4035 case ir_intrinsic_ssbo_load:
4036 case ir_intrinsic_ssbo_store:
4037 case ir_intrinsic_ssbo_atomic_add:
4038 case ir_intrinsic_ssbo_atomic_min:
4039 case ir_intrinsic_ssbo_atomic_max:
4040 case ir_intrinsic_ssbo_atomic_and:
4041 case ir_intrinsic_ssbo_atomic_or:
4042 case ir_intrinsic_ssbo_atomic_xor:
4043 case ir_intrinsic_ssbo_atomic_exchange:
4044 case ir_intrinsic_ssbo_atomic_comp_swap:
4045 visit_ssbo_intrinsic(ir);
4046 return;
4047
4048 case ir_intrinsic_memory_barrier:
4049 case ir_intrinsic_memory_barrier_atomic_counter:
4050 case ir_intrinsic_memory_barrier_buffer:
4051 case ir_intrinsic_memory_barrier_image:
4052 case ir_intrinsic_memory_barrier_shared:
4053 case ir_intrinsic_group_memory_barrier:
4054 visit_membar_intrinsic(ir);
4055 return;
4056
4057 case ir_intrinsic_shared_load:
4058 case ir_intrinsic_shared_store:
4059 case ir_intrinsic_shared_atomic_add:
4060 case ir_intrinsic_shared_atomic_min:
4061 case ir_intrinsic_shared_atomic_max:
4062 case ir_intrinsic_shared_atomic_and:
4063 case ir_intrinsic_shared_atomic_or:
4064 case ir_intrinsic_shared_atomic_xor:
4065 case ir_intrinsic_shared_atomic_exchange:
4066 case ir_intrinsic_shared_atomic_comp_swap:
4067 visit_shared_intrinsic(ir);
4068 return;
4069
4070 case ir_intrinsic_image_load:
4071 case ir_intrinsic_image_store:
4072 case ir_intrinsic_image_atomic_add:
4073 case ir_intrinsic_image_atomic_min:
4074 case ir_intrinsic_image_atomic_max:
4075 case ir_intrinsic_image_atomic_and:
4076 case ir_intrinsic_image_atomic_or:
4077 case ir_intrinsic_image_atomic_xor:
4078 case ir_intrinsic_image_atomic_exchange:
4079 case ir_intrinsic_image_atomic_comp_swap:
4080 case ir_intrinsic_image_size:
4081 case ir_intrinsic_image_samples:
4082 case ir_intrinsic_image_atomic_inc_wrap:
4083 case ir_intrinsic_image_atomic_dec_wrap:
4084 visit_image_intrinsic(ir);
4085 return;
4086
4087 case ir_intrinsic_shader_clock:
4088 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4089 return;
4090
4091 case ir_intrinsic_vote_all:
4092 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4093 return;
4094 case ir_intrinsic_vote_any:
4095 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4096 return;
4097 case ir_intrinsic_vote_eq:
4098 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4099 return;
4100 case ir_intrinsic_ballot:
4101 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4102 return;
4103 case ir_intrinsic_read_first_invocation:
4104 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4105 return;
4106 case ir_intrinsic_read_invocation:
4107 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4108 return;
4109
4110 case ir_intrinsic_helper_invocation:
4111 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_HELPER);
4112 return;
4113
4114 case ir_intrinsic_invalid:
4115 case ir_intrinsic_generic_load:
4116 case ir_intrinsic_generic_store:
4117 case ir_intrinsic_generic_atomic_add:
4118 case ir_intrinsic_generic_atomic_and:
4119 case ir_intrinsic_generic_atomic_or:
4120 case ir_intrinsic_generic_atomic_xor:
4121 case ir_intrinsic_generic_atomic_min:
4122 case ir_intrinsic_generic_atomic_max:
4123 case ir_intrinsic_generic_atomic_exchange:
4124 case ir_intrinsic_generic_atomic_comp_swap:
4125 case ir_intrinsic_begin_invocation_interlock:
4126 case ir_intrinsic_end_invocation_interlock:
4127 unreachable("Invalid intrinsic");
4128 }
4129 }
4130
4131 void
4132 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4133 unsigned *array_elements,
4134 uint16_t *index,
4135 st_src_reg *indirect,
4136 unsigned *location)
4137 {
4138 switch (tail->ir_type) {
4139 case ir_type_dereference_record: {
4140 ir_dereference_record *deref_record = tail->as_dereference_record();
4141 const glsl_type *struct_type = deref_record->record->type;
4142 int field_index = deref_record->field_idx;
4143
4144 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4145
4146 assert(field_index >= 0);
4147 *location += struct_type->struct_location_offset(field_index);
4148 break;
4149 }
4150
4151 case ir_type_dereference_array: {
4152 ir_dereference_array *deref_arr = tail->as_dereference_array();
4153
4154 void *mem_ctx = ralloc_parent(deref_arr);
4155 ir_constant *array_index =
4156 deref_arr->array_index->constant_expression_value(mem_ctx);
4157
4158 if (!array_index) {
4159 st_src_reg temp_reg;
4160 st_dst_reg temp_dst;
4161
4162 temp_reg = get_temp(glsl_type::uint_type);
4163 temp_dst = st_dst_reg(temp_reg);
4164 temp_dst.writemask = 1;
4165
4166 deref_arr->array_index->accept(this);
4167 if (*array_elements != 1)
4168 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4169 else
4170 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4171
4172 if (indirect->file == PROGRAM_UNDEFINED)
4173 *indirect = temp_reg;
4174 else {
4175 temp_dst = st_dst_reg(*indirect);
4176 temp_dst.writemask = 1;
4177 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4178 }
4179 } else
4180 *index += array_index->value.u[0] * *array_elements;
4181
4182 *array_elements *= deref_arr->array->type->length;
4183
4184 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4185 break;
4186 }
4187 default:
4188 break;
4189 }
4190 }
4191
4192 void
4193 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4194 unsigned *array_size,
4195 unsigned *base,
4196 uint16_t *index,
4197 st_src_reg *reladdr,
4198 bool opaque)
4199 {
4200 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4201 unsigned location = 0;
4202 ir_variable *var = ir->variable_referenced();
4203
4204 reladdr->reset();
4205
4206 *base = 0;
4207 *array_size = 1;
4208
4209 assert(var);
4210 location = var->data.location;
4211 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4212
4213 /*
4214 * If we end up with no indirect then adjust the base to the index,
4215 * and set the array size to 1.
4216 */
4217 if (reladdr->file == PROGRAM_UNDEFINED) {
4218 *base = *index;
4219 *array_size = 1;
4220 }
4221
4222 if (opaque) {
4223 assert(location != 0xffffffff);
4224 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4225 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4226 }
4227 }
4228
4229 st_src_reg
4230 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4231 {
4232 if (offset.reladdr || offset.reladdr2 ||
4233 offset.has_index2 ||
4234 offset.file == PROGRAM_UNIFORM ||
4235 offset.file == PROGRAM_CONSTANT ||
4236 offset.file == PROGRAM_STATE_VAR) {
4237 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4238 st_dst_reg tmp_dst = st_dst_reg(tmp);
4239 tmp_dst.writemask = WRITEMASK_XY;
4240 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4241 return tmp;
4242 }
4243
4244 return offset;
4245 }
4246
4247 bool
4248 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4249 {
4250 ir_variable *var = ir->variable_referenced();
4251
4252 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4253 !(ir->type->is_image() || ir->type->is_sampler()))
4254 return false;
4255
4256 /* Convert from bound sampler/image to bindless handle. */
4257 bool is_image = ir->type->is_image();
4258 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4259 uint16_t index = 0;
4260 unsigned array_size = 1, base = 0;
4261 st_src_reg reladdr;
4262 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4263
4264 resource.index = index;
4265 if (reladdr.file != PROGRAM_UNDEFINED) {
4266 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4267 *resource.reladdr = reladdr;
4268 emit_arl(ir, sampler_reladdr, reladdr);
4269 }
4270
4271 this->result = get_temp(glsl_type::uvec2_type);
4272 st_dst_reg dst(this->result);
4273 dst.writemask = WRITEMASK_XY;
4274
4275 glsl_to_tgsi_instruction *inst = emit_asm(
4276 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4277
4278 inst->tex_target = ir->type->sampler_index();
4279 inst->resource = resource;
4280 inst->sampler_array_size = array_size;
4281 inst->sampler_base = base;
4282
4283 return true;
4284 }
4285
4286 void
4287 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4288 {
4289 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4290 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4291 st_src_reg levels_src, reladdr;
4292 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4293 glsl_to_tgsi_instruction *inst = NULL;
4294 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4295 const glsl_type *sampler_type = ir->sampler->type;
4296 unsigned sampler_array_size = 1, sampler_base = 0;
4297 bool is_cube_array = false;
4298 ir_variable *var = ir->sampler->variable_referenced();
4299 unsigned i;
4300
4301 /* if we are a cube array sampler or a cube shadow */
4302 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4303 is_cube_array = sampler_type->sampler_array;
4304 }
4305
4306 if (ir->coordinate) {
4307 ir->coordinate->accept(this);
4308
4309 /* Put our coords in a temp. We'll need to modify them for shadow,
4310 * projection, or LOD, so the only case we'd use it as-is is if
4311 * we're doing plain old texturing. The optimization passes on
4312 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4313 */
4314 coord = get_temp(glsl_type::vec4_type);
4315 coord_dst = st_dst_reg(coord);
4316 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4317 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4318 }
4319
4320 if (ir->projector) {
4321 ir->projector->accept(this);
4322 projector = this->result;
4323 }
4324
4325 /* Storage for our result. Ideally for an assignment we'd be using
4326 * the actual storage for the result here, instead.
4327 */
4328 result_src = get_temp(ir->type);
4329 result_dst = st_dst_reg(result_src);
4330 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4331
4332 switch (ir->op) {
4333 case ir_tex:
4334 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4335 if (ir->offset) {
4336 ir->offset->accept(this);
4337 offset[0] = this->result;
4338 }
4339 break;
4340 case ir_txb:
4341 if (is_cube_array ||
4342 (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) {
4343 opcode = TGSI_OPCODE_TXB2;
4344 }
4345 else {
4346 opcode = TGSI_OPCODE_TXB;
4347 }
4348 ir->lod_info.bias->accept(this);
4349 lod_info = this->result;
4350 if (ir->offset) {
4351 ir->offset->accept(this);
4352 offset[0] = this->result;
4353 }
4354 break;
4355 case ir_txl:
4356 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4357 opcode = TGSI_OPCODE_TEX_LZ;
4358 } else {
4359 opcode = (is_cube_array || (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4360 ir->lod_info.lod->accept(this);
4361 lod_info = this->result;
4362 }
4363 if (ir->offset) {
4364 ir->offset->accept(this);
4365 offset[0] = this->result;
4366 }
4367 break;
4368 case ir_txd:
4369 opcode = TGSI_OPCODE_TXD;
4370 ir->lod_info.grad.dPdx->accept(this);
4371 dx = this->result;
4372 ir->lod_info.grad.dPdy->accept(this);
4373 dy = this->result;
4374 if (ir->offset) {
4375 ir->offset->accept(this);
4376 offset[0] = this->result;
4377 }
4378 break;
4379 case ir_txs:
4380 opcode = TGSI_OPCODE_TXQ;
4381 ir->lod_info.lod->accept(this);
4382 lod_info = this->result;
4383 break;
4384 case ir_query_levels:
4385 opcode = TGSI_OPCODE_TXQ;
4386 lod_info = undef_src;
4387 levels_src = get_temp(ir->type);
4388 break;
4389 case ir_txf:
4390 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4391 opcode = TGSI_OPCODE_TXF_LZ;
4392 } else {
4393 opcode = TGSI_OPCODE_TXF;
4394 ir->lod_info.lod->accept(this);
4395 lod_info = this->result;
4396 }
4397 if (ir->offset) {
4398 ir->offset->accept(this);
4399 offset[0] = this->result;
4400 }
4401 break;
4402 case ir_txf_ms:
4403 opcode = TGSI_OPCODE_TXF;
4404 ir->lod_info.sample_index->accept(this);
4405 sample_index = this->result;
4406 break;
4407 case ir_tg4:
4408 opcode = TGSI_OPCODE_TG4;
4409 ir->lod_info.component->accept(this);
4410 component = this->result;
4411 if (ir->offset) {
4412 ir->offset->accept(this);
4413 if (ir->offset->type->is_array()) {
4414 const glsl_type *elt_type = ir->offset->type->fields.array;
4415 for (i = 0; i < ir->offset->type->length; i++) {
4416 offset[i] = this->result;
4417 offset[i].index += i * type_size(elt_type);
4418 offset[i].type = elt_type->base_type;
4419 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4420 offset[i] = canonicalize_gather_offset(offset[i]);
4421 }
4422 } else {
4423 offset[0] = canonicalize_gather_offset(this->result);
4424 }
4425 }
4426 break;
4427 case ir_lod:
4428 opcode = TGSI_OPCODE_LODQ;
4429 break;
4430 case ir_texture_samples:
4431 opcode = TGSI_OPCODE_TXQS;
4432 break;
4433 case ir_samples_identical:
4434 unreachable("Unexpected ir_samples_identical opcode");
4435 }
4436
4437 if (ir->projector) {
4438 if (opcode == TGSI_OPCODE_TEX) {
4439 /* Slot the projector in as the last component of the coord. */
4440 coord_dst.writemask = WRITEMASK_W;
4441 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4442 coord_dst.writemask = WRITEMASK_XYZW;
4443 opcode = TGSI_OPCODE_TXP;
4444 } else {
4445 st_src_reg coord_w = coord;
4446 coord_w.swizzle = SWIZZLE_WWWW;
4447
4448 /* For the other TEX opcodes there's no projective version
4449 * since the last slot is taken up by LOD info. Do the
4450 * projective divide now.
4451 */
4452 coord_dst.writemask = WRITEMASK_W;
4453 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4454
4455 /* In the case where we have to project the coordinates "by hand,"
4456 * the shadow comparator value must also be projected.
4457 */
4458 st_src_reg tmp_src = coord;
4459 if (ir->shadow_comparator) {
4460 /* Slot the shadow value in as the second to last component of the
4461 * coord.
4462 */
4463 ir->shadow_comparator->accept(this);
4464
4465 tmp_src = get_temp(glsl_type::vec4_type);
4466 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4467
4468 /* Projective division not allowed for array samplers. */
4469 assert(!sampler_type->sampler_array);
4470
4471 tmp_dst.writemask = WRITEMASK_Z;
4472 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4473
4474 tmp_dst.writemask = WRITEMASK_XY;
4475 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4476 }
4477
4478 coord_dst.writemask = WRITEMASK_XYZ;
4479 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4480
4481 coord_dst.writemask = WRITEMASK_XYZW;
4482 coord.swizzle = SWIZZLE_XYZW;
4483 }
4484 }
4485
4486 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4487 * shadow comparator was put in the correct place (and projected) by the
4488 * code, above, that handles by-hand projection.
4489 */
4490 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4491 /* Slot the shadow value in as the second to last component of the
4492 * coord.
4493 */
4494 ir->shadow_comparator->accept(this);
4495
4496 if (is_cube_array) {
4497 if (lod_info.file != PROGRAM_UNDEFINED) {
4498 // If we have both a cube array *and* a bias/lod, stick the
4499 // comparator into the .Y of the second argument.
4500 st_src_reg tmp = get_temp(glsl_type::vec2_type);
4501 cube_sc_dst = st_dst_reg(tmp);
4502 cube_sc_dst.writemask = WRITEMASK_X;
4503 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, lod_info);
4504 lod_info = tmp;
4505 cube_sc_dst.writemask = WRITEMASK_Y;
4506 } else {
4507 cube_sc = get_temp(glsl_type::float_type);
4508 cube_sc_dst = st_dst_reg(cube_sc);
4509 cube_sc_dst.writemask = WRITEMASK_X;
4510 }
4511 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4512 }
4513 else {
4514 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4515 sampler_type->sampler_array) ||
4516 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4517 coord_dst.writemask = WRITEMASK_W;
4518 } else {
4519 coord_dst.writemask = WRITEMASK_Z;
4520 }
4521 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4522 coord_dst.writemask = WRITEMASK_XYZW;
4523 }
4524 }
4525
4526 if (ir->op == ir_txf_ms) {
4527 coord_dst.writemask = WRITEMASK_W;
4528 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4529 coord_dst.writemask = WRITEMASK_XYZW;
4530 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4531 opcode == TGSI_OPCODE_TXF) {
4532 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4533 coord_dst.writemask = WRITEMASK_W;
4534 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4535 coord_dst.writemask = WRITEMASK_XYZW;
4536 }
4537
4538 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4539
4540 uint16_t index = 0;
4541 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4542 &index, &reladdr, !var->contains_bindless());
4543
4544 sampler.index = index;
4545 if (reladdr.file != PROGRAM_UNDEFINED) {
4546 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4547 *sampler.reladdr = reladdr;
4548 emit_arl(ir, sampler_reladdr, reladdr);
4549 }
4550
4551 st_src_reg bindless;
4552 if (var->contains_bindless()) {
4553 ir->sampler->accept(this);
4554 bindless = this->result;
4555 }
4556
4557 if (opcode == TGSI_OPCODE_TXD)
4558 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4559 else if (opcode == TGSI_OPCODE_TXQ) {
4560 if (ir->op == ir_query_levels) {
4561 /* the level is stored in W */
4562 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4563 result_dst.writemask = WRITEMASK_X;
4564 levels_src.swizzle = SWIZZLE_WWWW;
4565 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4566 } else
4567 inst = emit_asm(ir, opcode, result_dst, lod_info);
4568 } else if (opcode == TGSI_OPCODE_TXQS) {
4569 inst = emit_asm(ir, opcode, result_dst);
4570 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4571 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4572 } else if (opcode == TGSI_OPCODE_TEX2) {
4573 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4574 } else if (opcode == TGSI_OPCODE_TG4) {
4575 if (is_cube_array && ir->shadow_comparator) {
4576 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4577 } else {
4578 if (this->tg4_component_in_swizzle) {
4579 inst = emit_asm(ir, opcode, result_dst, coord);
4580 int idx = 0;
4581 foreach_in_list(immediate_storage, entry, &this->immediates) {
4582 if (component.index == idx) {
4583 gl_constant_value value = entry->values[component.swizzle];
4584 inst->gather_component = value.i;
4585 break;
4586 }
4587 idx++;
4588 }
4589 } else {
4590 inst = emit_asm(ir, opcode, result_dst, coord, component);
4591 }
4592 }
4593 } else
4594 inst = emit_asm(ir, opcode, result_dst, coord);
4595
4596 if (ir->shadow_comparator)
4597 inst->tex_shadow = GL_TRUE;
4598
4599 if (var->contains_bindless()) {
4600 inst->resource = bindless;
4601 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4602 SWIZZLE_X, SWIZZLE_Y);
4603 } else {
4604 inst->resource = sampler;
4605 inst->sampler_array_size = sampler_array_size;
4606 inst->sampler_base = sampler_base;
4607 }
4608
4609 if (ir->offset) {
4610 if (!inst->tex_offsets)
4611 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4612 MAX_GLSL_TEXTURE_OFFSET);
4613
4614 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4615 offset[i].file != PROGRAM_UNDEFINED; i++)
4616 inst->tex_offsets[i] = offset[i];
4617 inst->tex_offset_num_offset = i;
4618 }
4619
4620 inst->tex_target = sampler_type->sampler_index();
4621 inst->tex_type = ir->type->base_type;
4622
4623 this->result = result_src;
4624 }
4625
4626 void
4627 glsl_to_tgsi_visitor::visit(ir_return *ir)
4628 {
4629 assert(!ir->get_value());
4630
4631 emit_asm(ir, TGSI_OPCODE_RET);
4632 }
4633
4634 void
4635 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4636 {
4637 if (ir->condition) {
4638 ir->condition->accept(this);
4639 st_src_reg condition = this->result;
4640
4641 /* Convert the bool condition to a float so we can negate. */
4642 if (native_integers) {
4643 st_src_reg temp = get_temp(ir->condition->type);
4644 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4645 condition, st_src_reg_for_float(1.0));
4646 condition = temp;
4647 }
4648
4649 condition.negate = ~condition.negate;
4650 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4651 } else {
4652 /* unconditional kil */
4653 emit_asm(ir, TGSI_OPCODE_KILL);
4654 }
4655 }
4656
4657 void
4658 glsl_to_tgsi_visitor::visit(ir_demote *ir)
4659 {
4660 emit_asm(ir, TGSI_OPCODE_DEMOTE);
4661 }
4662
4663 void
4664 glsl_to_tgsi_visitor::visit(ir_if *ir)
4665 {
4666 enum tgsi_opcode if_opcode;
4667 glsl_to_tgsi_instruction *if_inst;
4668
4669 ir->condition->accept(this);
4670 assert(this->result.file != PROGRAM_UNDEFINED);
4671
4672 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4673
4674 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4675
4676 this->instructions.push_tail(if_inst);
4677
4678 visit_exec_list(&ir->then_instructions, this);
4679
4680 if (!ir->else_instructions.is_empty()) {
4681 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4682 visit_exec_list(&ir->else_instructions, this);
4683 }
4684
4685 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4686 }
4687
4688
4689 void
4690 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4691 {
4692 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4693
4694 ir->stream->accept(this);
4695 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4696 }
4697
4698 void
4699 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4700 {
4701 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4702
4703 ir->stream->accept(this);
4704 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4705 }
4706
4707 void
4708 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4709 {
4710 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4711 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4712
4713 emit_asm(ir, TGSI_OPCODE_BARRIER);
4714 }
4715
4716 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4717 {
4718 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4719
4720 result.file = PROGRAM_UNDEFINED;
4721 next_temp = 1;
4722 array_sizes = NULL;
4723 max_num_arrays = 0;
4724 next_array = 0;
4725 num_inputs = 0;
4726 num_outputs = 0;
4727 num_input_arrays = 0;
4728 num_output_arrays = 0;
4729 num_atomics = 0;
4730 num_atomic_arrays = 0;
4731 num_immediates = 0;
4732 num_address_regs = 0;
4733 samplers_used = 0;
4734 images_used = 0;
4735 indirect_addr_consts = false;
4736 wpos_transform_const = -1;
4737 native_integers = false;
4738 mem_ctx = ralloc_context(NULL);
4739 ctx = NULL;
4740 prog = NULL;
4741 precise = 0;
4742 need_uarl = false;
4743 tg4_component_in_swizzle = false;
4744 shader_program = NULL;
4745 shader = NULL;
4746 options = NULL;
4747 have_sqrt = false;
4748 have_fma = false;
4749 use_shared_memory = false;
4750 has_tex_txf_lz = false;
4751 variables = NULL;
4752 }
4753
4754 static void var_destroy(struct hash_entry *entry)
4755 {
4756 variable_storage *storage = (variable_storage *)entry->data;
4757
4758 delete storage;
4759 }
4760
4761 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4762 {
4763 _mesa_hash_table_destroy(variables, var_destroy);
4764 free(array_sizes);
4765 ralloc_free(mem_ctx);
4766 }
4767
4768 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4769 {
4770 delete v;
4771 }
4772
4773
4774 /**
4775 * Count resources used by the given gpu program (number of texture
4776 * samplers, etc).
4777 */
4778 static void
4779 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4780 {
4781 v->samplers_used = 0;
4782 v->images_used = 0;
4783 prog->info.textures_used_by_txf = 0;
4784
4785 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4786 if (inst->info->is_tex) {
4787 for (int i = 0; i < inst->sampler_array_size; i++) {
4788 unsigned idx = inst->sampler_base + i;
4789 v->samplers_used |= 1u << idx;
4790
4791 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4792 v->sampler_types[idx] = inst->tex_type;
4793 v->sampler_targets[idx] =
4794 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4795
4796 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4797 prog->info.textures_used_by_txf |= 1u << idx;
4798 }
4799 }
4800 }
4801
4802 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4803 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4804
4805 if (inst->resource.file != PROGRAM_UNDEFINED && (
4806 is_resource_instruction(inst->op) ||
4807 inst->op == TGSI_OPCODE_STORE)) {
4808 if (inst->resource.file == PROGRAM_MEMORY) {
4809 v->use_shared_memory = true;
4810 } else if (inst->resource.file == PROGRAM_IMAGE) {
4811 for (int i = 0; i < inst->sampler_array_size; i++) {
4812 unsigned idx = inst->sampler_base + i;
4813 v->images_used |= 1 << idx;
4814 v->image_targets[idx] =
4815 st_translate_texture_target(inst->tex_target, false);
4816 v->image_formats[idx] = inst->image_format;
4817 v->image_wr[idx] = !inst->read_only;
4818 }
4819 }
4820 }
4821 }
4822 prog->SamplersUsed = v->samplers_used;
4823
4824 if (v->shader_program != NULL)
4825 _mesa_update_shader_textures_used(v->shader_program, prog);
4826 }
4827
4828 /**
4829 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4830 * are read from the given src in this instruction
4831 */
4832 static int
4833 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4834 {
4835 int read_mask = 0, comp;
4836
4837 /* Now, given the src swizzle and the written channels, find which
4838 * components are actually read
4839 */
4840 for (comp = 0; comp < 4; ++comp) {
4841 const unsigned coord = GET_SWZ(src.swizzle, comp);
4842 assert(coord < 4);
4843 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4844 read_mask |= 1 << coord;
4845 }
4846
4847 return read_mask;
4848 }
4849
4850 /**
4851 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4852 * instruction is the first instruction to write to register T0. There are
4853 * several lowering passes done in GLSL IR (e.g. branches and
4854 * relative addressing) that create a large number of conditional assignments
4855 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4856 *
4857 * Here is why this conversion is safe:
4858 * CMP T0, T1 T2 T0 can be expanded to:
4859 * if (T1 < 0.0)
4860 * MOV T0, T2;
4861 * else
4862 * MOV T0, T0;
4863 *
4864 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4865 * as the original program. If (T1 < 0.0) evaluates to false, executing
4866 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4867 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4868 * because any instruction that was going to read from T0 after this was going
4869 * to read a garbage value anyway.
4870 */
4871 void
4872 glsl_to_tgsi_visitor::simplify_cmp(void)
4873 {
4874 int tempWritesSize = 0;
4875 unsigned *tempWrites = NULL;
4876 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4877
4878 memset(outputWrites, 0, sizeof(outputWrites));
4879
4880 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4881 unsigned prevWriteMask = 0;
4882
4883 /* Give up if we encounter relative addressing or flow control. */
4884 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4885 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4886 inst->info->is_branch ||
4887 inst->op == TGSI_OPCODE_CONT ||
4888 inst->op == TGSI_OPCODE_END ||
4889 inst->op == TGSI_OPCODE_RET) {
4890 break;
4891 }
4892
4893 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4894 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4895 prevWriteMask = outputWrites[inst->dst[0].index];
4896 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4897 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4898 if (inst->dst[0].index >= tempWritesSize) {
4899 const int inc = 4096;
4900
4901 tempWrites = (unsigned*)
4902 realloc(tempWrites,
4903 (tempWritesSize + inc) * sizeof(unsigned));
4904 if (!tempWrites)
4905 return;
4906
4907 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4908 tempWritesSize += inc;
4909 }
4910
4911 prevWriteMask = tempWrites[inst->dst[0].index];
4912 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4913 } else
4914 continue;
4915
4916 /* For a CMP to be considered a conditional write, the destination
4917 * register and source register two must be the same. */
4918 if (inst->op == TGSI_OPCODE_CMP
4919 && !(inst->dst[0].writemask & prevWriteMask)
4920 && inst->src[2].file == inst->dst[0].file
4921 && inst->src[2].index == inst->dst[0].index
4922 && inst->dst[0].writemask ==
4923 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4924
4925 inst->op = TGSI_OPCODE_MOV;
4926 inst->info = tgsi_get_opcode_info(inst->op);
4927 inst->src[0] = inst->src[1];
4928 }
4929 }
4930
4931 free(tempWrites);
4932 }
4933
4934 static void
4935 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4936 {
4937 if (src && src->file == PROGRAM_TEMPORARY) {
4938 int old_idx = src->index;
4939 if (renames[old_idx].valid)
4940 src->index = renames[old_idx].new_reg;
4941 }
4942 }
4943
4944 /* Replaces all references to a temporary register index with another index. */
4945 void
4946 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4947 {
4948 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4949 unsigned j;
4950 for (j = 0; j < num_inst_src_regs(inst); j++) {
4951 rename_temp_handle_src(renames, &inst->src[j]);
4952 rename_temp_handle_src(renames, inst->src[j].reladdr);
4953 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4954 }
4955
4956 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4957 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4958 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4959 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4960 }
4961
4962 rename_temp_handle_src(renames, &inst->resource);
4963 rename_temp_handle_src(renames, inst->resource.reladdr);
4964 rename_temp_handle_src(renames, inst->resource.reladdr2);
4965
4966 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4967 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4968 int old_idx = inst->dst[j].index;
4969 if (renames[old_idx].valid)
4970 inst->dst[j].index = renames[old_idx].new_reg;
4971 }
4972 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4973 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4974 }
4975 }
4976 }
4977
4978 void
4979 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4980 {
4981 int depth = 0; /* loop depth */
4982 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4983 unsigned i = 0, j;
4984
4985 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4986 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4987 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4988 if (first_writes[inst->dst[j].index] == -1)
4989 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4990 }
4991 }
4992
4993 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4994 if (depth++ == 0)
4995 loop_start = i;
4996 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4997 if (--depth == 0)
4998 loop_start = -1;
4999 }
5000 assert(depth >= 0);
5001 i++;
5002 }
5003 }
5004
5005 void
5006 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
5007 {
5008 int depth = 0; /* loop depth */
5009 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5010 unsigned i = 0, j;
5011
5012 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5013 for (j = 0; j < num_inst_src_regs(inst); j++) {
5014 if (inst->src[j].file == PROGRAM_TEMPORARY) {
5015 if (first_reads[inst->src[j].index] == -1)
5016 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
5017 }
5018 }
5019 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5020 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
5021 if (first_reads[inst->tex_offsets[j].index] == -1)
5022 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
5023 }
5024 }
5025 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5026 if (depth++ == 0)
5027 loop_start = i;
5028 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5029 if (--depth == 0)
5030 loop_start = -1;
5031 }
5032 assert(depth >= 0);
5033 i++;
5034 }
5035 }
5036
5037 void
5038 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
5039 {
5040 int depth = 0; /* loop depth */
5041 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5042 unsigned i = 0, j;
5043 int k;
5044 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5045 for (j = 0; j < num_inst_src_regs(inst); j++) {
5046 if (inst->src[j].file == PROGRAM_TEMPORARY)
5047 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
5048 }
5049 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5050 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
5051 if (first_writes[inst->dst[j].index] == -1)
5052 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5053 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
5054 }
5055 }
5056 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5057 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
5058 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
5059 }
5060 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5061 if (depth++ == 0)
5062 loop_start = i;
5063 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5064 if (--depth == 0) {
5065 loop_start = -1;
5066 for (k = 0; k < this->next_temp; k++) {
5067 if (last_reads[k] == -2) {
5068 last_reads[k] = i;
5069 }
5070 }
5071 }
5072 }
5073 assert(depth >= 0);
5074 i++;
5075 }
5076 }
5077
5078 void
5079 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
5080 {
5081 int depth = 0; /* loop depth */
5082 int i = 0, k;
5083 unsigned j;
5084
5085 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5086 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5087 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5088 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5089 }
5090
5091 if (inst->op == TGSI_OPCODE_BGNLOOP)
5092 depth++;
5093 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5094 if (--depth == 0) {
5095 for (k = 0; k < this->next_temp; k++) {
5096 if (last_writes[k] == -2) {
5097 last_writes[k] = i;
5098 }
5099 }
5100 }
5101 assert(depth >= 0);
5102 i++;
5103 }
5104 }
5105
5106 /*
5107 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5108 * channels for copy propagation and updates following instructions to
5109 * use the original versions.
5110 *
5111 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5112 * will occur. As an example, a TXP production before this pass:
5113 *
5114 * 0: MOV TEMP[1], INPUT[4].xyyy;
5115 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5116 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5117 *
5118 * and after:
5119 *
5120 * 0: MOV TEMP[1], INPUT[4].xyyy;
5121 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5122 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5123 *
5124 * which allows for dead code elimination on TEMP[1]'s writes.
5125 */
5126 void
5127 glsl_to_tgsi_visitor::copy_propagate(void)
5128 {
5129 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5130 glsl_to_tgsi_instruction *,
5131 this->next_temp * 4);
5132 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5133 int level = 0;
5134
5135 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5136 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5137 || inst->dst[0].index < this->next_temp);
5138
5139 /* First, do any copy propagation possible into the src regs. */
5140 for (int r = 0; r < 3; r++) {
5141 glsl_to_tgsi_instruction *first = NULL;
5142 bool good = true;
5143 int acp_base = inst->src[r].index * 4;
5144
5145 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5146 inst->src[r].reladdr ||
5147 inst->src[r].reladdr2)
5148 continue;
5149
5150 /* See if we can find entries in the ACP consisting of MOVs
5151 * from the same src register for all the swizzled channels
5152 * of this src register reference.
5153 */
5154 for (int i = 0; i < 4; i++) {
5155 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5156 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5157
5158 if (!copy_chan) {
5159 good = false;
5160 break;
5161 }
5162
5163 assert(acp_level[acp_base + src_chan] <= level);
5164
5165 if (!first) {
5166 first = copy_chan;
5167 } else {
5168 if (first->src[0].file != copy_chan->src[0].file ||
5169 first->src[0].index != copy_chan->src[0].index ||
5170 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5171 first->src[0].index2D != copy_chan->src[0].index2D) {
5172 good = false;
5173 break;
5174 }
5175 }
5176 }
5177
5178 if (good) {
5179 /* We've now validated that we can copy-propagate to
5180 * replace this src register reference. Do it.
5181 */
5182 inst->src[r].file = first->src[0].file;
5183 inst->src[r].index = first->src[0].index;
5184 inst->src[r].index2D = first->src[0].index2D;
5185 inst->src[r].has_index2 = first->src[0].has_index2;
5186 inst->src[r].double_reg2 = first->src[0].double_reg2;
5187 inst->src[r].array_id = first->src[0].array_id;
5188
5189 int swizzle = 0;
5190 for (int i = 0; i < 4; i++) {
5191 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5192 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5193 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5194 }
5195 inst->src[r].swizzle = swizzle;
5196 }
5197 }
5198
5199 switch (inst->op) {
5200 case TGSI_OPCODE_BGNLOOP:
5201 case TGSI_OPCODE_ENDLOOP:
5202 /* End of a basic block, clear the ACP entirely. */
5203 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5204 break;
5205
5206 case TGSI_OPCODE_IF:
5207 case TGSI_OPCODE_UIF:
5208 ++level;
5209 break;
5210
5211 case TGSI_OPCODE_ENDIF:
5212 case TGSI_OPCODE_ELSE:
5213 /* Clear all channels written inside the block from the ACP, but
5214 * leaving those that were not touched.
5215 */
5216 for (int r = 0; r < this->next_temp; r++) {
5217 for (int c = 0; c < 4; c++) {
5218 if (!acp[4 * r + c])
5219 continue;
5220
5221 if (acp_level[4 * r + c] >= level)
5222 acp[4 * r + c] = NULL;
5223 }
5224 }
5225 if (inst->op == TGSI_OPCODE_ENDIF)
5226 --level;
5227 break;
5228
5229 default:
5230 /* Continuing the block, clear any written channels from
5231 * the ACP.
5232 */
5233 for (int d = 0; d < 2; d++) {
5234 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5235 /* Any temporary might be written, so no copy propagation
5236 * across this instruction.
5237 */
5238 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5239 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5240 inst->dst[d].reladdr) {
5241 /* Any output might be written, so no copy propagation
5242 * from outputs across this instruction.
5243 */
5244 for (int r = 0; r < this->next_temp; r++) {
5245 for (int c = 0; c < 4; c++) {
5246 if (!acp[4 * r + c])
5247 continue;
5248
5249 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5250 acp[4 * r + c] = NULL;
5251 }
5252 }
5253 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5254 inst->dst[d].file == PROGRAM_OUTPUT) {
5255 /* Clear where it's used as dst. */
5256 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5257 for (int c = 0; c < 4; c++) {
5258 if (inst->dst[d].writemask & (1 << c))
5259 acp[4 * inst->dst[d].index + c] = NULL;
5260 }
5261 }
5262
5263 /* Clear where it's used as src. */
5264 for (int r = 0; r < this->next_temp; r++) {
5265 for (int c = 0; c < 4; c++) {
5266 if (!acp[4 * r + c])
5267 continue;
5268
5269 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5270
5271 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5272 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5273 inst->dst[d].writemask & (1 << src_chan)) {
5274 acp[4 * r + c] = NULL;
5275 }
5276 }
5277 }
5278 }
5279 }
5280 break;
5281 }
5282
5283 /* If this is a copy, add it to the ACP. */
5284 if (inst->op == TGSI_OPCODE_MOV &&
5285 inst->dst[0].file == PROGRAM_TEMPORARY &&
5286 !(inst->dst[0].file == inst->src[0].file &&
5287 inst->dst[0].index == inst->src[0].index) &&
5288 !inst->dst[0].reladdr &&
5289 !inst->dst[0].reladdr2 &&
5290 !inst->saturate &&
5291 inst->src[0].file != PROGRAM_ARRAY &&
5292 (inst->src[0].file != PROGRAM_OUTPUT ||
5293 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5294 !inst->src[0].reladdr &&
5295 !inst->src[0].reladdr2 &&
5296 !inst->src[0].negate &&
5297 !inst->src[0].abs) {
5298 for (int i = 0; i < 4; i++) {
5299 if (inst->dst[0].writemask & (1 << i)) {
5300 acp[4 * inst->dst[0].index + i] = inst;
5301 acp_level[4 * inst->dst[0].index + i] = level;
5302 }
5303 }
5304 }
5305 }
5306
5307 ralloc_free(acp_level);
5308 ralloc_free(acp);
5309 }
5310
5311 static void
5312 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5313 {
5314 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5315 /* Clear where it's used as src. */
5316 int swz = GET_SWZ(reladdr->swizzle, 0);
5317 writes[4 * reladdr->index + swz] = NULL;
5318 }
5319 }
5320
5321 /*
5322 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5323 * code elimination.
5324 *
5325 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5326 * will occur. As an example, a TXP production after copy propagation but
5327 * before this pass:
5328 *
5329 * 0: MOV TEMP[1], INPUT[4].xyyy;
5330 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5331 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5332 *
5333 * and after this pass:
5334 *
5335 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5336 */
5337 int
5338 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5339 {
5340 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5341 glsl_to_tgsi_instruction *,
5342 this->next_temp * 4);
5343 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5344 int level = 0;
5345 int removed = 0;
5346
5347 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5348 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5349 || inst->dst[0].index < this->next_temp);
5350
5351 switch (inst->op) {
5352 case TGSI_OPCODE_BGNLOOP:
5353 case TGSI_OPCODE_ENDLOOP:
5354 case TGSI_OPCODE_CONT:
5355 case TGSI_OPCODE_BRK:
5356 /* End of a basic block, clear the write array entirely.
5357 *
5358 * This keeps us from killing dead code when the writes are
5359 * on either side of a loop, even when the register isn't touched
5360 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5361 * dead code of this type, so it shouldn't make a difference as long as
5362 * the dead code elimination pass in the GLSL compiler does its job.
5363 */
5364 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5365 break;
5366
5367 case TGSI_OPCODE_ENDIF:
5368 case TGSI_OPCODE_ELSE:
5369 /* Promote the recorded level of all channels written inside the
5370 * preceding if or else block to the level above the if/else block.
5371 */
5372 for (int r = 0; r < this->next_temp; r++) {
5373 for (int c = 0; c < 4; c++) {
5374 if (!writes[4 * r + c])
5375 continue;
5376
5377 if (write_level[4 * r + c] == level)
5378 write_level[4 * r + c] = level-1;
5379 }
5380 }
5381 if (inst->op == TGSI_OPCODE_ENDIF)
5382 --level;
5383 break;
5384
5385 case TGSI_OPCODE_IF:
5386 case TGSI_OPCODE_UIF:
5387 ++level;
5388 /* fallthrough to default case to mark the condition as read */
5389 default:
5390 /* Continuing the block, clear any channels from the write array that
5391 * are read by this instruction.
5392 */
5393 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5394 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5395 /* Any temporary might be read, so no dead code elimination
5396 * across this instruction.
5397 */
5398 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5399 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5400 /* Clear where it's used as src. */
5401 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5402 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5403 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5404 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5405
5406 for (int c = 0; c < 4; c++) {
5407 if (src_chans & (1 << c))
5408 writes[4 * inst->src[i].index + c] = NULL;
5409 }
5410 }
5411 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5412 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5413 }
5414 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5415 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5416 /* Any temporary might be read, so no dead code elimination
5417 * across this instruction.
5418 */
5419 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5420 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5421 /* Clear where it's used as src. */
5422 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5423 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5424 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5425 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5426
5427 for (int c = 0; c < 4; c++) {
5428 if (src_chans & (1 << c))
5429 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5430 }
5431 }
5432 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5433 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5434 }
5435
5436 if (inst->resource.file == PROGRAM_TEMPORARY) {
5437 int src_chans;
5438
5439 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5440 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5441 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5442 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5443
5444 for (int c = 0; c < 4; c++) {
5445 if (src_chans & (1 << c))
5446 writes[4 * inst->resource.index + c] = NULL;
5447 }
5448 }
5449 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5450 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5451
5452 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5453 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5454 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5455 }
5456 break;
5457 }
5458
5459 /* If this instruction writes to a temporary, add it to the write array.
5460 * If there is already an instruction in the write array for one or more
5461 * of the channels, flag that channel write as dead.
5462 */
5463 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5464 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5465 !inst->dst[i].reladdr) {
5466 for (int c = 0; c < 4; c++) {
5467 if (inst->dst[i].writemask & (1 << c)) {
5468 if (writes[4 * inst->dst[i].index + c]) {
5469 if (write_level[4 * inst->dst[i].index + c] < level)
5470 continue;
5471 else
5472 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5473 }
5474 writes[4 * inst->dst[i].index + c] = inst;
5475 write_level[4 * inst->dst[i].index + c] = level;
5476 }
5477 }
5478 }
5479 }
5480 }
5481
5482 /* Anything still in the write array at this point is dead code. */
5483 for (int r = 0; r < this->next_temp; r++) {
5484 for (int c = 0; c < 4; c++) {
5485 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5486 if (inst)
5487 inst->dead_mask |= (1 << c);
5488 }
5489 }
5490
5491 /* Now actually remove the instructions that are completely dead and update
5492 * the writemask of other instructions with dead channels.
5493 */
5494 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5495 if (!inst->dead_mask || !inst->dst[0].writemask)
5496 continue;
5497 /* No amount of dead masks should remove memory stores */
5498 if (inst->info->is_store)
5499 continue;
5500
5501 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5502 inst->remove();
5503 delete inst;
5504 removed++;
5505 } else {
5506 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5507 if (inst->dead_mask == WRITEMASK_XY ||
5508 inst->dead_mask == WRITEMASK_ZW)
5509 inst->dst[0].writemask &= ~(inst->dead_mask);
5510 } else
5511 inst->dst[0].writemask &= ~(inst->dead_mask);
5512 }
5513 }
5514
5515 ralloc_free(write_level);
5516 ralloc_free(writes);
5517
5518 return removed;
5519 }
5520
5521 /* merge DFRACEXP instructions into one. */
5522 void
5523 glsl_to_tgsi_visitor::merge_two_dsts(void)
5524 {
5525 /* We never delete inst, but we may delete its successor. */
5526 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5527 glsl_to_tgsi_instruction *inst2;
5528 unsigned defined;
5529
5530 if (num_inst_dst_regs(inst) != 2)
5531 continue;
5532
5533 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5534 inst->dst[1].file != PROGRAM_UNDEFINED)
5535 continue;
5536
5537 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5538 inst->dst[1].file != PROGRAM_UNDEFINED);
5539
5540 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5541 defined = 1;
5542 else
5543 defined = 0;
5544
5545 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5546 while (!inst2->is_tail_sentinel()) {
5547 if (inst->op == inst2->op &&
5548 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5549 inst->src[0].file == inst2->src[0].file &&
5550 inst->src[0].index == inst2->src[0].index &&
5551 inst->src[0].type == inst2->src[0].type &&
5552 inst->src[0].swizzle == inst2->src[0].swizzle)
5553 break;
5554 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5555 }
5556
5557 if (inst2->is_tail_sentinel()) {
5558 /* Undefined destinations are not allowed, substitute with an unused
5559 * temporary register.
5560 */
5561 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5562 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5563 inst->dst[defined ^ 1].writemask = 0;
5564 continue;
5565 }
5566
5567 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5568 inst2->remove();
5569 delete inst2;
5570 }
5571 }
5572
5573 template <typename st_reg>
5574 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5575 {
5576 if (reg.file == PROGRAM_ARRAY) {
5577 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5578 has_indirect_access[reg.array_id] = true;
5579 if (reg.reladdr)
5580 test_indirect_access(*reg.reladdr, has_indirect_access);
5581 if (reg.reladdr2)
5582 test_indirect_access(*reg.reladdr2, has_indirect_access);
5583 }
5584 }
5585 }
5586
5587 template <typename st_reg>
5588 void remap_array(st_reg& reg, const int *array_remap_info,
5589 const bool *has_indirect_access)
5590 {
5591 if (reg.file == PROGRAM_ARRAY) {
5592 if (!has_indirect_access[reg.array_id]) {
5593 reg.file = PROGRAM_TEMPORARY;
5594 reg.index = reg.index + array_remap_info[reg.array_id];
5595 reg.array_id = 0;
5596 } else {
5597 reg.array_id = array_remap_info[reg.array_id];
5598 }
5599
5600 if (reg.reladdr)
5601 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5602
5603 if (reg.reladdr2)
5604 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5605 }
5606 }
5607
5608 /* One-dimensional arrays whose elements are only accessed directly are
5609 * replaced by an according set of temporary registers that then can become
5610 * subject to further optimization steps like copy propagation and
5611 * register merging.
5612 */
5613 void
5614 glsl_to_tgsi_visitor::split_arrays(void)
5615 {
5616 if (!next_array)
5617 return;
5618
5619 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5620
5621 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5622 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5623 test_indirect_access(inst->src[j], has_indirect_access);
5624
5625 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5626 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5627
5628 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5629 test_indirect_access(inst->dst[j], has_indirect_access);
5630
5631 test_indirect_access(inst->resource, has_indirect_access);
5632 }
5633
5634 unsigned array_offset = 0;
5635 unsigned n_remaining_arrays = 0;
5636
5637 /* Double use: For arrays that get split this value will contain
5638 * the base index of the temporary registers this array is replaced
5639 * with. For arrays that remain it contains the new array ID.
5640 */
5641 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5642 next_array + 1);
5643
5644 for (unsigned i = 1; i <= next_array; ++i) {
5645 if (!has_indirect_access[i]) {
5646 array_remap_info[i] = this->next_temp + array_offset;
5647 array_offset += array_sizes[i - 1];
5648 } else {
5649 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5650 array_remap_info[i] = ++n_remaining_arrays;
5651 }
5652 }
5653
5654 if (next_array != n_remaining_arrays) {
5655 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5656 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5657 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5658
5659 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5660 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5661
5662 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5663 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5664 }
5665 remap_array(inst->resource, array_remap_info, has_indirect_access);
5666 }
5667 }
5668
5669 ralloc_free(has_indirect_access);
5670 this->next_temp += array_offset;
5671 next_array = n_remaining_arrays;
5672 }
5673
5674 /* Merges temporary registers together where possible to reduce the number of
5675 * registers needed to run a program.
5676 *
5677 * Produces optimal code only after copy propagation and dead code elimination
5678 * have been run. */
5679 void
5680 glsl_to_tgsi_visitor::merge_registers(void)
5681 {
5682 class array_live_range *arr_live_ranges = NULL;
5683
5684 struct register_live_range *reg_live_ranges =
5685 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5686
5687 if (this->next_array > 0) {
5688 arr_live_ranges = new array_live_range[this->next_array];
5689 for (unsigned i = 0; i < this->next_array; ++i)
5690 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5691 }
5692
5693
5694 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5695 this->next_temp, reg_live_ranges,
5696 this->next_array, arr_live_ranges)) {
5697 struct rename_reg_pair *renames =
5698 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5699 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5700 reg_live_ranges, renames);
5701 rename_temp_registers(renames);
5702
5703 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5704 &this->instructions, arr_live_ranges);
5705 }
5706
5707 if (arr_live_ranges)
5708 delete[] arr_live_ranges;
5709
5710 ralloc_free(reg_live_ranges);
5711 }
5712
5713 /* Reassign indices to temporary registers by reusing unused indices created
5714 * by optimization passes. */
5715 void
5716 glsl_to_tgsi_visitor::renumber_registers(void)
5717 {
5718 int i = 0;
5719 int new_index = 0;
5720 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5721 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5722
5723 for (i = 0; i < this->next_temp; i++) {
5724 first_writes[i] = -1;
5725 }
5726 get_first_temp_write(first_writes);
5727
5728 for (i = 0; i < this->next_temp; i++) {
5729 if (first_writes[i] < 0) continue;
5730 if (i != new_index) {
5731 renames[i].new_reg = new_index;
5732 renames[i].valid = true;
5733 }
5734 new_index++;
5735 }
5736
5737 rename_temp_registers(renames);
5738 this->next_temp = new_index;
5739 ralloc_free(renames);
5740 ralloc_free(first_writes);
5741 }
5742
5743 #ifndef NDEBUG
5744 void glsl_to_tgsi_visitor::print_stats()
5745 {
5746 int narray_registers = 0;
5747 for (unsigned i = 0; i < this->next_array; ++i)
5748 narray_registers += this->array_sizes[i];
5749
5750 int ninstructions = 0;
5751 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5752 ++ninstructions;
5753 }
5754
5755 simple_mtx_lock(&print_stats_mutex);
5756 stats_log << next_array << ", "
5757 << next_temp << ", "
5758 << narray_registers << ", "
5759 << next_temp + narray_registers << ", "
5760 << ninstructions << "\n";
5761 simple_mtx_unlock(&print_stats_mutex);
5762 }
5763 #endif
5764 /* ------------------------- TGSI conversion stuff -------------------------- */
5765
5766 /**
5767 * Intermediate state used during shader translation.
5768 */
5769 struct st_translate {
5770 struct ureg_program *ureg;
5771
5772 unsigned temps_size;
5773 struct ureg_dst *temps;
5774
5775 struct ureg_dst *arrays;
5776 unsigned num_temp_arrays;
5777 struct ureg_src *constants;
5778 int num_constants;
5779 struct ureg_src *immediates;
5780 int num_immediates;
5781 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5782 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5783 struct ureg_dst address[3];
5784 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5785 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5786 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5787 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5788 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5789 struct ureg_src shared_memory;
5790 unsigned *array_sizes;
5791 struct inout_decl *input_decls;
5792 unsigned num_input_decls;
5793 struct inout_decl *output_decls;
5794 unsigned num_output_decls;
5795
5796 const ubyte *inputMapping;
5797 const ubyte *outputMapping;
5798
5799 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5800 bool need_uarl;
5801 bool tg4_component_in_swizzle;
5802 };
5803
5804 /**
5805 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5806 */
5807 static struct ureg_src
5808 emit_immediate(struct st_translate *t,
5809 gl_constant_value values[4],
5810 GLenum type, int size)
5811 {
5812 struct ureg_program *ureg = t->ureg;
5813
5814 switch (type) {
5815 case GL_FLOAT:
5816 return ureg_DECL_immediate(ureg, &values[0].f, size);
5817 case GL_DOUBLE:
5818 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5819 case GL_INT64_ARB:
5820 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5821 case GL_UNSIGNED_INT64_ARB:
5822 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5823 case GL_INT:
5824 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5825 case GL_UNSIGNED_INT:
5826 case GL_BOOL:
5827 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5828 default:
5829 assert(!"should not get here - type must be float, int, uint, or bool");
5830 return ureg_src_undef();
5831 }
5832 }
5833
5834 /**
5835 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5836 */
5837 static struct ureg_dst
5838 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5839 unsigned array_id)
5840 {
5841 unsigned array;
5842
5843 switch (file) {
5844 case PROGRAM_UNDEFINED:
5845 return ureg_dst_undef();
5846
5847 case PROGRAM_TEMPORARY:
5848 /* Allocate space for temporaries on demand. */
5849 if (index >= t->temps_size) {
5850 const int inc = align(index - t->temps_size + 1, 4096);
5851
5852 t->temps = (struct ureg_dst*)
5853 realloc(t->temps,
5854 (t->temps_size + inc) * sizeof(struct ureg_dst));
5855 if (!t->temps)
5856 return ureg_dst_undef();
5857
5858 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5859 t->temps_size += inc;
5860 }
5861
5862 if (ureg_dst_is_undef(t->temps[index]))
5863 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5864
5865 return t->temps[index];
5866
5867 case PROGRAM_ARRAY:
5868 assert(array_id && array_id <= t->num_temp_arrays);
5869 array = array_id - 1;
5870
5871 if (ureg_dst_is_undef(t->arrays[array]))
5872 t->arrays[array] = ureg_DECL_array_temporary(
5873 t->ureg, t->array_sizes[array], TRUE);
5874
5875 return ureg_dst_array_offset(t->arrays[array], index);
5876
5877 case PROGRAM_OUTPUT:
5878 if (!array_id) {
5879 if (t->procType == PIPE_SHADER_FRAGMENT)
5880 assert(index < 2 * FRAG_RESULT_MAX);
5881 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5882 t->procType == PIPE_SHADER_TESS_EVAL)
5883 assert(index < VARYING_SLOT_TESS_MAX);
5884 else
5885 assert(index < VARYING_SLOT_MAX);
5886
5887 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5888 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5889 return t->outputs[t->outputMapping[index]];
5890 }
5891 else {
5892 struct inout_decl *decl =
5893 find_inout_array(t->output_decls,
5894 t->num_output_decls, array_id);
5895 unsigned mesa_index = decl->mesa_index;
5896 int slot = t->outputMapping[mesa_index];
5897
5898 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5899
5900 struct ureg_dst dst = t->outputs[slot];
5901 dst.ArrayID = array_id;
5902 return ureg_dst_array_offset(dst, index - mesa_index);
5903 }
5904
5905 case PROGRAM_ADDRESS:
5906 return t->address[index];
5907
5908 default:
5909 assert(!"unknown dst register file");
5910 return ureg_dst_undef();
5911 }
5912 }
5913
5914 static struct ureg_src
5915 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5916
5917 static struct ureg_src
5918 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5919 unsigned addr_index)
5920 {
5921 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5922 return ureg_src(t->address[addr_index]);
5923
5924 return translate_src(t, reladdr);
5925 }
5926
5927 /**
5928 * Create a TGSI ureg_dst register from an st_dst_reg.
5929 */
5930 static struct ureg_dst
5931 translate_dst(struct st_translate *t,
5932 const st_dst_reg *dst_reg,
5933 bool saturate)
5934 {
5935 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5936 dst_reg->array_id);
5937
5938 if (dst.File == TGSI_FILE_NULL)
5939 return dst;
5940
5941 dst = ureg_writemask(dst, dst_reg->writemask);
5942
5943 if (saturate)
5944 dst = ureg_saturate(dst);
5945
5946 if (dst_reg->reladdr != NULL) {
5947 assert(dst_reg->file != PROGRAM_TEMPORARY);
5948 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5949 }
5950
5951 if (dst_reg->has_index2) {
5952 if (dst_reg->reladdr2)
5953 dst = ureg_dst_dimension_indirect(dst,
5954 translate_addr(t, dst_reg->reladdr2, 1),
5955 dst_reg->index2D);
5956 else
5957 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5958 }
5959
5960 return dst;
5961 }
5962
5963 /**
5964 * Create a TGSI ureg_src register from an st_src_reg.
5965 */
5966 static struct ureg_src
5967 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5968 {
5969 struct ureg_src src;
5970 int index = src_reg->index;
5971 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5972
5973 switch (src_reg->file) {
5974 case PROGRAM_UNDEFINED:
5975 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5976 break;
5977
5978 case PROGRAM_TEMPORARY:
5979 case PROGRAM_ARRAY:
5980 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5981 src_reg->array_id));
5982 break;
5983
5984 case PROGRAM_OUTPUT: {
5985 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5986 src_reg->array_id);
5987 assert(dst.WriteMask != 0);
5988 unsigned shift = ffs(dst.WriteMask) - 1;
5989 src = ureg_swizzle(ureg_src(dst),
5990 shift,
5991 MIN2(shift + 1, 3),
5992 MIN2(shift + 2, 3),
5993 MIN2(shift + 3, 3));
5994 break;
5995 }
5996
5997 case PROGRAM_UNIFORM:
5998 assert(src_reg->index >= 0);
5999 src = src_reg->index < t->num_constants ?
6000 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6001 break;
6002 case PROGRAM_STATE_VAR:
6003 case PROGRAM_CONSTANT: /* ie, immediate */
6004 if (src_reg->has_index2)
6005 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6006 else
6007 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6008 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6009 break;
6010
6011 case PROGRAM_IMMEDIATE:
6012 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6013 src = t->immediates[src_reg->index];
6014 break;
6015
6016 case PROGRAM_INPUT:
6017 /* GLSL inputs are 64-bit containers, so we have to
6018 * map back to the original index and add the offset after
6019 * mapping. */
6020 index -= double_reg2;
6021 if (!src_reg->array_id) {
6022 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6023 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6024 src = t->inputs[t->inputMapping[index] + double_reg2];
6025 }
6026 else {
6027 struct inout_decl *decl = find_inout_array(t->input_decls,
6028 t->num_input_decls,
6029 src_reg->array_id);
6030 unsigned mesa_index = decl->mesa_index;
6031 int slot = t->inputMapping[mesa_index];
6032
6033 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6034
6035 src = t->inputs[slot];
6036 src.ArrayID = src_reg->array_id;
6037 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6038 }
6039 break;
6040
6041 case PROGRAM_ADDRESS:
6042 src = ureg_src(t->address[src_reg->index]);
6043 break;
6044
6045 case PROGRAM_SYSTEM_VALUE:
6046 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6047 src = t->systemValues[src_reg->index];
6048 break;
6049
6050 case PROGRAM_HW_ATOMIC:
6051 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6052 src_reg->array_id);
6053 break;
6054
6055 default:
6056 assert(!"unknown src register file");
6057 return ureg_src_undef();
6058 }
6059
6060 if (src_reg->has_index2) {
6061 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6062 * and UBO constant buffers (buffer, position).
6063 */
6064 if (src_reg->reladdr2)
6065 src = ureg_src_dimension_indirect(src,
6066 translate_addr(t, src_reg->reladdr2, 1),
6067 src_reg->index2D);
6068 else
6069 src = ureg_src_dimension(src, src_reg->index2D);
6070 }
6071
6072 src = ureg_swizzle(src,
6073 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6074 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6075 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6076 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6077
6078 if (src_reg->abs)
6079 src = ureg_abs(src);
6080
6081 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6082 src = ureg_negate(src);
6083
6084 if (src_reg->reladdr != NULL) {
6085 assert(src_reg->file != PROGRAM_TEMPORARY);
6086 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6087 }
6088
6089 return src;
6090 }
6091
6092 static struct tgsi_texture_offset
6093 translate_tex_offset(struct st_translate *t,
6094 const st_src_reg *in_offset)
6095 {
6096 struct tgsi_texture_offset offset;
6097 struct ureg_src src = translate_src(t, in_offset);
6098
6099 offset.File = src.File;
6100 offset.Index = src.Index;
6101 offset.SwizzleX = src.SwizzleX;
6102 offset.SwizzleY = src.SwizzleY;
6103 offset.SwizzleZ = src.SwizzleZ;
6104 offset.Padding = 0;
6105
6106 assert(!src.Indirect);
6107 assert(!src.DimIndirect);
6108 assert(!src.Dimension);
6109 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6110 assert(!src.Negate);
6111
6112 return offset;
6113 }
6114
6115 static void
6116 compile_tgsi_instruction(struct st_translate *t,
6117 const glsl_to_tgsi_instruction *inst)
6118 {
6119 struct ureg_program *ureg = t->ureg;
6120 int i;
6121 struct ureg_dst dst[2];
6122 struct ureg_src src[4];
6123 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6124
6125 int num_dst;
6126 int num_src;
6127 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6128
6129 num_dst = num_inst_dst_regs(inst);
6130 num_src = num_inst_src_regs(inst);
6131
6132 for (i = 0; i < num_dst; i++)
6133 dst[i] = translate_dst(t,
6134 &inst->dst[i],
6135 inst->saturate);
6136
6137 for (i = 0; i < num_src; i++)
6138 src[i] = translate_src(t, &inst->src[i]);
6139
6140 switch (inst->op) {
6141 case TGSI_OPCODE_BGNLOOP:
6142 case TGSI_OPCODE_ELSE:
6143 case TGSI_OPCODE_ENDLOOP:
6144 case TGSI_OPCODE_IF:
6145 case TGSI_OPCODE_UIF:
6146 assert(num_dst == 0);
6147 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6148 return;
6149
6150 case TGSI_OPCODE_TEX:
6151 case TGSI_OPCODE_TEX_LZ:
6152 case TGSI_OPCODE_TXB:
6153 case TGSI_OPCODE_TXD:
6154 case TGSI_OPCODE_TXL:
6155 case TGSI_OPCODE_TXP:
6156 case TGSI_OPCODE_TXQ:
6157 case TGSI_OPCODE_TXQS:
6158 case TGSI_OPCODE_TXF:
6159 case TGSI_OPCODE_TXF_LZ:
6160 case TGSI_OPCODE_TEX2:
6161 case TGSI_OPCODE_TXB2:
6162 case TGSI_OPCODE_TXL2:
6163 case TGSI_OPCODE_TG4:
6164 case TGSI_OPCODE_LODQ:
6165 case TGSI_OPCODE_SAMP2HND:
6166 if (inst->resource.file == PROGRAM_SAMPLER) {
6167 src[num_src] = t->samplers[inst->resource.index];
6168 if (t->tg4_component_in_swizzle && inst->op == TGSI_OPCODE_TG4)
6169 src[num_src].SwizzleX = inst->gather_component;
6170 } else {
6171 /* Bindless samplers. */
6172 src[num_src] = translate_src(t, &inst->resource);
6173 }
6174 assert(src[num_src].File != TGSI_FILE_NULL);
6175 if (inst->resource.reladdr)
6176 src[num_src] =
6177 ureg_src_indirect(src[num_src],
6178 translate_addr(t, inst->resource.reladdr, 2));
6179 num_src++;
6180 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6181 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6182 }
6183 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6184
6185 ureg_tex_insn(ureg,
6186 inst->op,
6187 dst, num_dst,
6188 tex_target,
6189 st_translate_texture_type(inst->tex_type),
6190 texoffsets, inst->tex_offset_num_offset,
6191 src, num_src);
6192 return;
6193
6194 case TGSI_OPCODE_RESQ:
6195 case TGSI_OPCODE_LOAD:
6196 case TGSI_OPCODE_ATOMUADD:
6197 case TGSI_OPCODE_ATOMXCHG:
6198 case TGSI_OPCODE_ATOMCAS:
6199 case TGSI_OPCODE_ATOMAND:
6200 case TGSI_OPCODE_ATOMOR:
6201 case TGSI_OPCODE_ATOMXOR:
6202 case TGSI_OPCODE_ATOMUMIN:
6203 case TGSI_OPCODE_ATOMUMAX:
6204 case TGSI_OPCODE_ATOMIMIN:
6205 case TGSI_OPCODE_ATOMIMAX:
6206 case TGSI_OPCODE_ATOMFADD:
6207 case TGSI_OPCODE_IMG2HND:
6208 case TGSI_OPCODE_ATOMINC_WRAP:
6209 case TGSI_OPCODE_ATOMDEC_WRAP:
6210 for (i = num_src - 1; i >= 0; i--)
6211 src[i + 1] = src[i];
6212 num_src++;
6213 if (inst->resource.file == PROGRAM_MEMORY) {
6214 src[0] = t->shared_memory;
6215 } else if (inst->resource.file == PROGRAM_BUFFER) {
6216 src[0] = t->buffers[inst->resource.index];
6217 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6218 src[0] = translate_src(t, &inst->resource);
6219 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6220 assert(inst->resource.has_index2);
6221 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6222 } else {
6223 assert(inst->resource.file != PROGRAM_UNDEFINED);
6224 if (inst->resource.file == PROGRAM_IMAGE) {
6225 src[0] = t->images[inst->resource.index];
6226 } else {
6227 /* Bindless images. */
6228 src[0] = translate_src(t, &inst->resource);
6229 }
6230 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6231 }
6232 if (inst->resource.reladdr)
6233 src[0] = ureg_src_indirect(src[0],
6234 translate_addr(t, inst->resource.reladdr, 2));
6235 assert(src[0].File != TGSI_FILE_NULL);
6236 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6237 inst->buffer_access,
6238 tex_target, inst->image_format);
6239 break;
6240
6241 case TGSI_OPCODE_STORE:
6242 if (inst->resource.file == PROGRAM_MEMORY) {
6243 dst[0] = ureg_dst(t->shared_memory);
6244 } else if (inst->resource.file == PROGRAM_BUFFER) {
6245 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6246 } else {
6247 if (inst->resource.file == PROGRAM_IMAGE) {
6248 dst[0] = ureg_dst(t->images[inst->resource.index]);
6249 } else {
6250 /* Bindless images. */
6251 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6252 }
6253 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6254 }
6255 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6256 if (inst->resource.reladdr)
6257 dst[0] = ureg_dst_indirect(dst[0],
6258 translate_addr(t, inst->resource.reladdr, 2));
6259 assert(dst[0].File != TGSI_FILE_NULL);
6260 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6261 inst->buffer_access,
6262 tex_target, inst->image_format);
6263 break;
6264
6265 default:
6266 ureg_insn(ureg,
6267 inst->op,
6268 dst, num_dst,
6269 src, num_src, inst->precise);
6270 break;
6271 }
6272 }
6273
6274 /* Invert SamplePos.y when rendering to the default framebuffer. */
6275 static void
6276 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6277 {
6278 struct ureg_program *ureg = t->ureg;
6279
6280 assert(wpos_y_transform >= 0);
6281 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6282 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6283 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6284 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6285
6286 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6287 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6288
6289 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6290 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6291 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6292 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6293 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6294 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6295 samplepos_sysval);
6296
6297 /* Use the result in place of the system value. */
6298 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6299 }
6300
6301
6302 /**
6303 * Emit the TGSI instructions for inverting and adjusting WPOS.
6304 * This code is unavoidable because it also depends on whether
6305 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6306 */
6307 static void
6308 emit_wpos_adjustment(struct gl_context *ctx,
6309 struct st_translate *t,
6310 int wpos_transform_const,
6311 boolean invert,
6312 GLfloat adjX, GLfloat adjY[2])
6313 {
6314 struct ureg_program *ureg = t->ureg;
6315
6316 assert(wpos_transform_const >= 0);
6317
6318 /* Fragment program uses fragment position input.
6319 * Need to replace instances of INPUT[WPOS] with temp T
6320 * where T = INPUT[WPOS] is inverted by Y.
6321 */
6322 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6323 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6324 struct ureg_src *wpos =
6325 ctx->Const.GLSLFragCoordIsSysVal ?
6326 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6327 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6328 struct ureg_src wpos_input = *wpos;
6329
6330 /* First, apply the coordinate shift: */
6331 if (adjX || adjY[0] || adjY[1]) {
6332 if (adjY[0] != adjY[1]) {
6333 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6334 * depending on whether inversion is actually going to be applied
6335 * or not, which is determined by testing against the inversion
6336 * state variable used below, which will be either +1 or -1.
6337 */
6338 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6339
6340 ureg_CMP(ureg, adj_temp,
6341 ureg_scalar(wpostrans, invert ? 2 : 0),
6342 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6343 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6344 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6345 } else {
6346 ureg_ADD(ureg, wpos_temp, wpos_input,
6347 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6348 }
6349 wpos_input = ureg_src(wpos_temp);
6350 } else {
6351 /* MOV wpos_temp, input[wpos]
6352 */
6353 ureg_MOV(ureg, wpos_temp, wpos_input);
6354 }
6355
6356 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6357 * inversion/identity, or the other way around if we're drawing to an FBO.
6358 */
6359 if (invert) {
6360 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6361 */
6362 ureg_MAD(ureg,
6363 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6364 wpos_input,
6365 ureg_scalar(wpostrans, 0),
6366 ureg_scalar(wpostrans, 1));
6367 } else {
6368 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6369 */
6370 ureg_MAD(ureg,
6371 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6372 wpos_input,
6373 ureg_scalar(wpostrans, 2),
6374 ureg_scalar(wpostrans, 3));
6375 }
6376
6377 /* Use wpos_temp as position input from here on:
6378 */
6379 *wpos = ureg_src(wpos_temp);
6380 }
6381
6382
6383 /**
6384 * Emit fragment position/ooordinate code.
6385 */
6386 static void
6387 emit_wpos(struct st_context *st,
6388 struct st_translate *t,
6389 const struct gl_program *program,
6390 struct ureg_program *ureg,
6391 int wpos_transform_const)
6392 {
6393 struct pipe_screen *pscreen = st->pipe->screen;
6394 GLfloat adjX = 0.0f;
6395 GLfloat adjY[2] = { 0.0f, 0.0f };
6396 boolean invert = FALSE;
6397
6398 /* Query the pixel center conventions supported by the pipe driver and set
6399 * adjX, adjY to help out if it cannot handle the requested one internally.
6400 *
6401 * The bias of the y-coordinate depends on whether y-inversion takes place
6402 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6403 * drawing to an FBO (causes additional inversion), and whether the pipe
6404 * driver origin and the requested origin differ (the latter condition is
6405 * stored in the 'invert' variable).
6406 *
6407 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6408 *
6409 * center shift only:
6410 * i -> h: +0.5
6411 * h -> i: -0.5
6412 *
6413 * inversion only:
6414 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6415 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6416 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6417 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6418 *
6419 * inversion and center shift:
6420 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6421 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6422 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6423 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6424 */
6425 if (program->info.fs.origin_upper_left) {
6426 /* Fragment shader wants origin in upper-left */
6427 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6428 /* the driver supports upper-left origin */
6429 }
6430 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6431 /* the driver supports lower-left origin, need to invert Y */
6432 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6433 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6434 invert = TRUE;
6435 }
6436 else
6437 assert(0);
6438 }
6439 else {
6440 /* Fragment shader wants origin in lower-left */
6441 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6442 /* the driver supports lower-left origin */
6443 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6444 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6445 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6446 /* the driver supports upper-left origin, need to invert Y */
6447 invert = TRUE;
6448 else
6449 assert(0);
6450 }
6451
6452 if (program->info.fs.pixel_center_integer) {
6453 /* Fragment shader wants pixel center integer */
6454 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6455 /* the driver supports pixel center integer */
6456 adjY[1] = 1.0f;
6457 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6458 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6459 }
6460 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6461 /* the driver supports pixel center half integer, need to bias X,Y */
6462 adjX = -0.5f;
6463 adjY[0] = -0.5f;
6464 adjY[1] = 0.5f;
6465 }
6466 else
6467 assert(0);
6468 }
6469 else {
6470 /* Fragment shader wants pixel center half integer */
6471 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6472 /* the driver supports pixel center half integer */
6473 }
6474 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6475 /* the driver supports pixel center integer, need to bias X,Y */
6476 adjX = adjY[0] = adjY[1] = 0.5f;
6477 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6478 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6479 }
6480 else
6481 assert(0);
6482 }
6483
6484 /* we invert after adjustment so that we avoid the MOV to temporary,
6485 * and reuse the adjustment ADD instead */
6486 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6487 }
6488
6489 /**
6490 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6491 * TGSI uses +1 for front, -1 for back.
6492 * This function converts the TGSI value to the GL value. Simply clamping/
6493 * saturating the value to [0,1] does the job.
6494 */
6495 static void
6496 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6497 {
6498 struct ureg_program *ureg = t->ureg;
6499 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6500 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6501
6502 if (ctx->Const.NativeIntegers) {
6503 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6504 }
6505 else {
6506 /* MOV_SAT face_temp, input[face] */
6507 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6508 }
6509
6510 /* Use face_temp as face input from here on: */
6511 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6512 }
6513
6514 static void
6515 emit_compute_block_size(const struct gl_program *prog,
6516 struct ureg_program *ureg) {
6517 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6518 prog->info.cs.local_size[0]);
6519 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6520 prog->info.cs.local_size[1]);
6521 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6522 prog->info.cs.local_size[2]);
6523 }
6524
6525 struct sort_inout_decls {
6526 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6527 return mapping[a.mesa_index] < mapping[b.mesa_index];
6528 }
6529
6530 const ubyte *mapping;
6531 };
6532
6533 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6534 *
6535 * This is for the benefit of older drivers which are broken when the
6536 * declarations aren't sorted in this way.
6537 */
6538 static void
6539 sort_inout_decls_by_slot(struct inout_decl *decls,
6540 unsigned count,
6541 const ubyte mapping[])
6542 {
6543 sort_inout_decls sorter;
6544 sorter.mapping = mapping;
6545 std::sort(decls, decls + count, sorter);
6546 }
6547
6548 static enum tgsi_interpolate_mode
6549 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6550 {
6551 switch (glsl_qual) {
6552 case INTERP_MODE_NONE:
6553 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6554 return TGSI_INTERPOLATE_COLOR;
6555 return TGSI_INTERPOLATE_PERSPECTIVE;
6556 case INTERP_MODE_SMOOTH:
6557 return TGSI_INTERPOLATE_PERSPECTIVE;
6558 case INTERP_MODE_FLAT:
6559 return TGSI_INTERPOLATE_CONSTANT;
6560 case INTERP_MODE_NOPERSPECTIVE:
6561 return TGSI_INTERPOLATE_LINEAR;
6562 default:
6563 assert(0 && "unexpected interp mode in st_translate_interp()");
6564 return TGSI_INTERPOLATE_PERSPECTIVE;
6565 }
6566 }
6567
6568 /**
6569 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6570 * \param program the program to translate
6571 * \param numInputs number of input registers used
6572 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6573 * input indexes
6574 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6575 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6576 * each input
6577 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6578 * \param numOutputs number of output registers used
6579 * \param outputMapping maps Mesa fragment program outputs to TGSI
6580 * generic outputs
6581 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6582 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6583 * each output
6584 *
6585 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6586 */
6587 extern "C" enum pipe_error
6588 st_translate_program(
6589 struct gl_context *ctx,
6590 enum pipe_shader_type procType,
6591 struct ureg_program *ureg,
6592 glsl_to_tgsi_visitor *program,
6593 const struct gl_program *proginfo,
6594 GLuint numInputs,
6595 const ubyte inputMapping[],
6596 const ubyte inputSlotToAttr[],
6597 const ubyte inputSemanticName[],
6598 const ubyte inputSemanticIndex[],
6599 const ubyte interpMode[],
6600 GLuint numOutputs,
6601 const ubyte outputMapping[],
6602 const ubyte outputSemanticName[],
6603 const ubyte outputSemanticIndex[])
6604 {
6605 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6606 struct st_translate *t;
6607 unsigned i;
6608 struct gl_program_constants *frag_const =
6609 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6610 enum pipe_error ret = PIPE_OK;
6611
6612 assert(numInputs <= ARRAY_SIZE(t->inputs));
6613 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6614
6615 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6616 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6617 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6618 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6619 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6620 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6621 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6622 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6623 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6624 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6625
6626 t = CALLOC_STRUCT(st_translate);
6627 if (!t) {
6628 ret = PIPE_ERROR_OUT_OF_MEMORY;
6629 goto out;
6630 }
6631
6632 t->procType = procType;
6633 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6634 t->tg4_component_in_swizzle = screen->get_param(screen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
6635 t->inputMapping = inputMapping;
6636 t->outputMapping = outputMapping;
6637 t->ureg = ureg;
6638 t->num_temp_arrays = program->next_array;
6639 if (t->num_temp_arrays)
6640 t->arrays = (struct ureg_dst*)
6641 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6642
6643 /*
6644 * Declare input attributes.
6645 */
6646 switch (procType) {
6647 case PIPE_SHADER_FRAGMENT:
6648 case PIPE_SHADER_GEOMETRY:
6649 case PIPE_SHADER_TESS_EVAL:
6650 case PIPE_SHADER_TESS_CTRL:
6651 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6652
6653 for (i = 0; i < program->num_inputs; ++i) {
6654 struct inout_decl *decl = &program->inputs[i];
6655 unsigned slot = inputMapping[decl->mesa_index];
6656 struct ureg_src src;
6657 ubyte tgsi_usage_mask = decl->usage_mask;
6658
6659 if (glsl_base_type_is_64bit(decl->base_type)) {
6660 if (tgsi_usage_mask == 1)
6661 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6662 else if (tgsi_usage_mask == 2)
6663 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6664 else
6665 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6666 }
6667
6668 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6669 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6670 if (procType == PIPE_SHADER_FRAGMENT) {
6671 assert(interpMode);
6672 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6673 (enum tgsi_interpolate_mode) interpMode[slot] :
6674 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6675
6676 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6677 }
6678
6679 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6680 (enum tgsi_semantic) inputSemanticName[slot],
6681 inputSemanticIndex[slot],
6682 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6683 decl->array_id, decl->size);
6684
6685 for (unsigned j = 0; j < decl->size; ++j) {
6686 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6687 /* The ArrayID is set up in dst_register */
6688 t->inputs[slot + j] = src;
6689 t->inputs[slot + j].ArrayID = 0;
6690 t->inputs[slot + j].Index += j;
6691 }
6692 }
6693 }
6694 break;
6695 case PIPE_SHADER_VERTEX:
6696 for (i = 0; i < numInputs; i++) {
6697 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6698 }
6699 break;
6700 case PIPE_SHADER_COMPUTE:
6701 break;
6702 default:
6703 assert(0);
6704 }
6705
6706 /*
6707 * Declare output attributes.
6708 */
6709 switch (procType) {
6710 case PIPE_SHADER_FRAGMENT:
6711 case PIPE_SHADER_COMPUTE:
6712 break;
6713 case PIPE_SHADER_GEOMETRY:
6714 case PIPE_SHADER_TESS_EVAL:
6715 case PIPE_SHADER_TESS_CTRL:
6716 case PIPE_SHADER_VERTEX:
6717 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6718
6719 for (i = 0; i < program->num_outputs; ++i) {
6720 struct inout_decl *decl = &program->outputs[i];
6721 unsigned slot = outputMapping[decl->mesa_index];
6722 struct ureg_dst dst;
6723 ubyte tgsi_usage_mask = decl->usage_mask;
6724
6725 if (glsl_base_type_is_64bit(decl->base_type)) {
6726 if (tgsi_usage_mask == 1)
6727 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6728 else if (tgsi_usage_mask == 2)
6729 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6730 else
6731 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6732 }
6733
6734 dst = ureg_DECL_output_layout(ureg,
6735 (enum tgsi_semantic) outputSemanticName[slot],
6736 outputSemanticIndex[slot],
6737 decl->gs_out_streams,
6738 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6739 dst.Invariant = decl->invariant;
6740 for (unsigned j = 0; j < decl->size; ++j) {
6741 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6742 /* The ArrayID is set up in dst_register */
6743 t->outputs[slot + j] = dst;
6744 t->outputs[slot + j].ArrayID = 0;
6745 t->outputs[slot + j].Index += j;
6746 t->outputs[slot + j].Invariant = decl->invariant;
6747 }
6748 }
6749 }
6750 break;
6751 default:
6752 assert(0);
6753 }
6754
6755 if (procType == PIPE_SHADER_FRAGMENT) {
6756 if (program->shader->Program->info.fs.early_fragment_tests ||
6757 program->shader->Program->info.fs.post_depth_coverage) {
6758 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6759
6760 if (program->shader->Program->info.fs.post_depth_coverage)
6761 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6762 }
6763
6764 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6765 /* Must do this after setting up t->inputs. */
6766 emit_wpos(st_context(ctx), t, proginfo, ureg,
6767 program->wpos_transform_const);
6768 }
6769
6770 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6771 emit_face_var(ctx, t);
6772
6773 for (i = 0; i < numOutputs; i++) {
6774 switch (outputSemanticName[i]) {
6775 case TGSI_SEMANTIC_POSITION:
6776 t->outputs[i] = ureg_DECL_output(ureg,
6777 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6778 outputSemanticIndex[i]);
6779 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6780 break;
6781 case TGSI_SEMANTIC_STENCIL:
6782 t->outputs[i] = ureg_DECL_output(ureg,
6783 TGSI_SEMANTIC_STENCIL, /* Stencil */
6784 outputSemanticIndex[i]);
6785 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6786 break;
6787 case TGSI_SEMANTIC_COLOR:
6788 t->outputs[i] = ureg_DECL_output(ureg,
6789 TGSI_SEMANTIC_COLOR,
6790 outputSemanticIndex[i]);
6791 break;
6792 case TGSI_SEMANTIC_SAMPLEMASK:
6793 t->outputs[i] = ureg_DECL_output(ureg,
6794 TGSI_SEMANTIC_SAMPLEMASK,
6795 outputSemanticIndex[i]);
6796 /* TODO: If we ever support more than 32 samples, this will have
6797 * to become an array.
6798 */
6799 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6800 break;
6801 default:
6802 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6803 ret = PIPE_ERROR_BAD_INPUT;
6804 goto out;
6805 }
6806 }
6807 }
6808 else if (procType == PIPE_SHADER_VERTEX) {
6809 for (i = 0; i < numOutputs; i++) {
6810 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6811 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6812 ureg_MOV(ureg,
6813 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6814 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6815 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6816 }
6817 }
6818 }
6819
6820 if (procType == PIPE_SHADER_COMPUTE) {
6821 emit_compute_block_size(proginfo, ureg);
6822 }
6823
6824 if (program->shader->Program->info.layer_viewport_relative)
6825 ureg_property(ureg, TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE, 1);
6826
6827 /* Declare address register.
6828 */
6829 if (program->num_address_regs > 0) {
6830 assert(program->num_address_regs <= 3);
6831 for (int i = 0; i < program->num_address_regs; i++)
6832 t->address[i] = ureg_DECL_address(ureg);
6833 }
6834
6835 /* Declare misc input registers
6836 */
6837 {
6838 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6839
6840 for (i = 0; sysInputs; i++) {
6841 if (sysInputs & (1ull << i)) {
6842 enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
6843
6844 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6845
6846 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6847 semName == TGSI_SEMANTIC_VERTEXID) {
6848 /* From Gallium perspective, these system values are always
6849 * integer, and require native integer support. However, if
6850 * native integer is supported on the vertex stage but not the
6851 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6852 * assumes these system values are floats. To resolve the
6853 * inconsistency, we insert a U2F.
6854 */
6855 struct st_context *st = st_context(ctx);
6856 struct pipe_screen *pscreen = st->pipe->screen;
6857 assert(procType == PIPE_SHADER_VERTEX);
6858 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6859 (void) pscreen;
6860 if (!ctx->Const.NativeIntegers) {
6861 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6862 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6863 t->systemValues[i]);
6864 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6865 }
6866 }
6867
6868 if (procType == PIPE_SHADER_FRAGMENT &&
6869 semName == TGSI_SEMANTIC_POSITION)
6870 emit_wpos(st_context(ctx), t, proginfo, ureg,
6871 program->wpos_transform_const);
6872
6873 if (procType == PIPE_SHADER_FRAGMENT &&
6874 semName == TGSI_SEMANTIC_SAMPLEPOS)
6875 emit_samplepos_adjustment(t, program->wpos_transform_const);
6876
6877 sysInputs &= ~(1ull << i);
6878 }
6879 }
6880 }
6881
6882 t->array_sizes = program->array_sizes;
6883 t->input_decls = program->inputs;
6884 t->num_input_decls = program->num_inputs;
6885 t->output_decls = program->outputs;
6886 t->num_output_decls = program->num_outputs;
6887
6888 /* Emit constants and uniforms. TGSI uses a single index space for these,
6889 * so we put all the translated regs in t->constants.
6890 */
6891 if (proginfo->Parameters) {
6892 t->constants = (struct ureg_src *)
6893 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6894 if (t->constants == NULL) {
6895 ret = PIPE_ERROR_OUT_OF_MEMORY;
6896 goto out;
6897 }
6898 t->num_constants = proginfo->Parameters->NumParameters;
6899
6900 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6901 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6902
6903 switch (proginfo->Parameters->Parameters[i].Type) {
6904 case PROGRAM_STATE_VAR:
6905 case PROGRAM_UNIFORM:
6906 t->constants[i] = ureg_DECL_constant(ureg, i);
6907 break;
6908
6909 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6910 * addressing of the const buffer.
6911 * FIXME: Be smarter and recognize param arrays:
6912 * indirect addressing is only valid within the referenced
6913 * array.
6914 */
6915 case PROGRAM_CONSTANT:
6916 if (program->indirect_addr_consts)
6917 t->constants[i] = ureg_DECL_constant(ureg, i);
6918 else
6919 t->constants[i] = emit_immediate(t,
6920 proginfo->Parameters->ParameterValues + pvo,
6921 proginfo->Parameters->Parameters[i].DataType,
6922 4);
6923 break;
6924 default:
6925 break;
6926 }
6927 }
6928 }
6929
6930 for (i = 0; i < proginfo->info.num_ubos; i++) {
6931 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6932 unsigned num_const_vecs = (size + 15) / 16;
6933 unsigned first, last;
6934 assert(num_const_vecs > 0);
6935 first = 0;
6936 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6937 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6938 }
6939
6940 /* Emit immediate values.
6941 */
6942 t->immediates = (struct ureg_src *)
6943 calloc(program->num_immediates, sizeof(struct ureg_src));
6944 if (t->immediates == NULL) {
6945 ret = PIPE_ERROR_OUT_OF_MEMORY;
6946 goto out;
6947 }
6948 t->num_immediates = program->num_immediates;
6949
6950 i = 0;
6951 foreach_in_list(immediate_storage, imm, &program->immediates) {
6952 assert(i < program->num_immediates);
6953 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6954 }
6955 assert(i == program->num_immediates);
6956
6957 /* texture samplers */
6958 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6959 if (program->samplers_used & (1u << i)) {
6960 enum tgsi_return_type type =
6961 st_translate_texture_type(program->sampler_types[i]);
6962
6963 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6964
6965 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6966 type, type, type, type);
6967 }
6968 }
6969
6970 /* Declare atomic and shader storage buffers. */
6971 {
6972 struct gl_program *prog = program->prog;
6973
6974 if (!st_context(ctx)->has_hw_atomics) {
6975 for (i = 0; i < prog->info.num_abos; i++) {
6976 unsigned index = (prog->info.num_ssbos +
6977 prog->sh.AtomicBuffers[i]->Binding);
6978 assert(prog->sh.AtomicBuffers[i]->Binding <
6979 frag_const->MaxAtomicBuffers);
6980 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6981 }
6982 } else {
6983 for (i = 0; i < program->num_atomics; i++) {
6984 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6985 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6986 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6987 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6988 ainfo->array_id);
6989 }
6990 }
6991
6992 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6993 for (i = 0; i < prog->info.num_ssbos; i++) {
6994 t->buffers[i] = ureg_DECL_buffer(ureg, i, false);
6995 }
6996 }
6997
6998 if (program->use_shared_memory)
6999 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
7000
7001 for (i = 0; i < program->shader->Program->info.num_images; i++) {
7002 if (program->images_used & (1 << i)) {
7003 t->images[i] = ureg_DECL_image(ureg, i,
7004 program->image_targets[i],
7005 program->image_formats[i],
7006 program->image_wr[i],
7007 false);
7008 }
7009 }
7010
7011 /* Emit each instruction in turn:
7012 */
7013 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
7014 compile_tgsi_instruction(t, inst);
7015
7016 /* Set the next shader stage hint for VS and TES. */
7017 switch (procType) {
7018 case PIPE_SHADER_VERTEX:
7019 case PIPE_SHADER_TESS_EVAL:
7020 if (program->shader_program->SeparateShader)
7021 break;
7022
7023 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
7024 if (program->shader_program->_LinkedShaders[i]) {
7025 ureg_set_next_shader_processor(
7026 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
7027 break;
7028 }
7029 }
7030 break;
7031 default:
7032 ; /* nothing - silence compiler warning */
7033 }
7034
7035 out:
7036 if (t) {
7037 free(t->arrays);
7038 free(t->temps);
7039 free(t->constants);
7040 t->num_constants = 0;
7041 free(t->immediates);
7042 t->num_immediates = 0;
7043 FREE(t);
7044 }
7045
7046 return ret;
7047 }
7048 /* ----------------------------- End TGSI code ------------------------------ */
7049
7050
7051 /**
7052 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7053 * generating Mesa IR.
7054 */
7055 static struct gl_program *
7056 get_mesa_program_tgsi(struct gl_context *ctx,
7057 struct gl_shader_program *shader_program,
7058 struct gl_linked_shader *shader)
7059 {
7060 glsl_to_tgsi_visitor* v;
7061 struct gl_program *prog;
7062 struct gl_shader_compiler_options *options =
7063 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7064 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7065 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7066 unsigned skip_merge_registers;
7067
7068 validate_ir_tree(shader->ir);
7069
7070 prog = shader->Program;
7071
7072 prog->Parameters = _mesa_new_parameter_list();
7073 v = new glsl_to_tgsi_visitor();
7074 v->ctx = ctx;
7075 v->prog = prog;
7076 v->shader_program = shader_program;
7077 v->shader = shader;
7078 v->options = options;
7079 v->native_integers = ctx->Const.NativeIntegers;
7080
7081 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7082 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7083 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7084 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7085 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7086 PIPE_CAP_TGSI_TEX_TXF_LZ);
7087 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7088
7089 v->tg4_component_in_swizzle = pscreen->get_param(pscreen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
7090 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7091 _mesa_key_pointer_equal);
7092 skip_merge_registers =
7093 pscreen->get_shader_param(pscreen, ptarget,
7094 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7095
7096 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7097 prog->Parameters);
7098
7099 /* Remove reads from output registers. */
7100 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7101 lower_output_reads(shader->Stage, shader->ir);
7102
7103 /* Emit intermediate IR for main(). */
7104 visit_exec_list(shader->ir, v);
7105
7106 #if 0
7107 /* Print out some information (for debugging purposes) used by the
7108 * optimization passes. */
7109 {
7110 int i;
7111 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7112 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7113 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7114 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7115
7116 for (i = 0; i < v->next_temp; i++) {
7117 first_writes[i] = -1;
7118 first_reads[i] = -1;
7119 last_writes[i] = -1;
7120 last_reads[i] = -1;
7121 }
7122 v->get_first_temp_read(first_reads);
7123 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7124 v->get_last_temp_write(last_writes);
7125 for (i = 0; i < v->next_temp; i++)
7126 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7127 first_writes[i],
7128 last_reads[i],
7129 last_writes[i]);
7130 ralloc_free(first_writes);
7131 ralloc_free(first_reads);
7132 ralloc_free(last_writes);
7133 ralloc_free(last_reads);
7134 }
7135 #endif
7136
7137 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7138 v->simplify_cmp();
7139 v->copy_propagate();
7140
7141 while (v->eliminate_dead_code());
7142
7143 v->merge_two_dsts();
7144
7145 if (!skip_merge_registers) {
7146 v->split_arrays();
7147 v->copy_propagate();
7148 while (v->eliminate_dead_code());
7149
7150 v->merge_registers();
7151 v->copy_propagate();
7152 while (v->eliminate_dead_code());
7153 }
7154
7155 v->renumber_registers();
7156
7157 /* Write the END instruction. */
7158 v->emit_asm(NULL, TGSI_OPCODE_END);
7159
7160 if (ctx->_Shader->Flags & GLSL_DUMP) {
7161 _mesa_log("\n");
7162 _mesa_log("GLSL IR for linked %s program %d:\n",
7163 _mesa_shader_stage_to_string(shader->Stage),
7164 shader_program->Name);
7165 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7166 _mesa_log("\n\n");
7167 }
7168
7169 do_set_program_inouts(shader->ir, prog, shader->Stage);
7170
7171 _mesa_copy_linked_program_data(shader_program, shader);
7172
7173 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS)) {
7174 mark_array_io(v->inputs, v->num_inputs,
7175 &prog->info.inputs_read,
7176 prog->DualSlotInputs,
7177 &prog->info.patch_inputs_read);
7178
7179 mark_array_io(v->outputs, v->num_outputs,
7180 &prog->info.outputs_written, 0ULL,
7181 &prog->info.patch_outputs_written);
7182 } else {
7183 shrink_array_declarations(v->inputs, v->num_inputs,
7184 &prog->info.inputs_read,
7185 prog->DualSlotInputs,
7186 &prog->info.patch_inputs_read);
7187 shrink_array_declarations(v->outputs, v->num_outputs,
7188 &prog->info.outputs_written, 0ULL,
7189 &prog->info.patch_outputs_written);
7190 }
7191
7192 count_resources(v, prog);
7193
7194 /* The GLSL IR won't be needed anymore. */
7195 ralloc_free(shader->ir);
7196 shader->ir = NULL;
7197
7198 /* This must be done before the uniform storage is associated. */
7199 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7200 (prog->info.inputs_read & VARYING_BIT_POS ||
7201 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
7202 prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
7203 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7204 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7205 };
7206
7207 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7208 wposTransformState);
7209 }
7210
7211 /* Avoid reallocation of the program parameter list, because the uniform
7212 * storage is only associated with the original parameter list.
7213 * This should be enough for Bitmap and DrawPixels constants.
7214 */
7215 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7216
7217 /* This has to be done last. Any operation the can cause
7218 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7219 * program constant) has to happen before creating this linkage.
7220 */
7221 _mesa_associate_uniform_storage(ctx, shader_program, prog);
7222 if (!shader_program->data->LinkStatus) {
7223 free_glsl_to_tgsi_visitor(v);
7224 _mesa_reference_program(ctx, &shader->Program, NULL);
7225 return NULL;
7226 }
7227
7228 st_program(prog)->glsl_to_tgsi = v;
7229
7230 PRINT_STATS(v->print_stats());
7231
7232 return prog;
7233 }
7234
7235 /* See if there are unsupported control flow statements. */
7236 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7237 private:
7238 const struct gl_shader_compiler_options *options;
7239 public:
7240 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7241 : options(options),
7242 unsupported(false)
7243 {
7244 }
7245
7246 virtual ir_visitor_status visit_enter(ir_function *ir)
7247 {
7248 /* Other functions are skipped (same as glsl_to_tgsi). */
7249 if (strcmp(ir->name, "main") == 0)
7250 return visit_continue;
7251
7252 return visit_continue_with_parent;
7253 }
7254
7255 virtual ir_visitor_status visit_enter(ir_call *ir)
7256 {
7257 if (!ir->callee->is_intrinsic()) {
7258 unsupported = true; /* it's a function call */
7259 return visit_stop;
7260 }
7261 return visit_continue;
7262 }
7263
7264 virtual ir_visitor_status visit_enter(ir_return *ir)
7265 {
7266 if (options->EmitNoMainReturn) {
7267 unsupported = true;
7268 return visit_stop;
7269 }
7270 return visit_continue;
7271 }
7272
7273 bool unsupported;
7274 };
7275
7276 static bool
7277 has_unsupported_control_flow(exec_list *ir,
7278 const struct gl_shader_compiler_options *options)
7279 {
7280 ir_control_flow_info_visitor visitor(options);
7281 visit_list_elements(&visitor, ir);
7282 return visitor.unsupported;
7283 }
7284
7285 /**
7286 * Link a shader.
7287 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7288 * with code lowering and other optimizations.
7289 */
7290 GLboolean
7291 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7292 {
7293 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7294
7295 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7296 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7297 if (shader == NULL)
7298 continue;
7299
7300 exec_list *ir = shader->ir;
7301 gl_shader_stage stage = shader->Stage;
7302 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7303 const struct gl_shader_compiler_options *options =
7304 &ctx->Const.ShaderCompilerOptions[stage];
7305
7306 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7307 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7308 if (ctx->Const.GLSLOptimizeConservatively) {
7309 /* Do it once and repeat only if there's unsupported control flow. */
7310 do {
7311 do_common_optimization(ir, true, true, options,
7312 ctx->Const.NativeIntegers);
7313 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7314 options->MaxIfDepth, if_threshold);
7315 } while (has_unsupported_control_flow(ir, options));
7316 } else {
7317 /* Repeat it until it stops making changes. */
7318 bool progress;
7319 do {
7320 progress = do_common_optimization(ir, true, true, options,
7321 ctx->Const.NativeIntegers);
7322 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7323 options->MaxIfDepth, if_threshold);
7324 } while (progress);
7325 }
7326
7327 /* Do this again to lower ir_binop_vector_extract introduced
7328 * by optimization passes.
7329 */
7330 do_vec_index_to_cond_assign(ir);
7331
7332 validate_ir_tree(ir);
7333
7334 struct gl_program *linked_prog =
7335 get_mesa_program_tgsi(ctx, prog, shader);
7336 st_set_prog_affected_state_flags(linked_prog);
7337
7338 if (linked_prog) {
7339 /* This is really conservative: */
7340 linked_prog->info.writes_memory =
7341 linked_prog->info.num_ssbos ||
7342 linked_prog->info.num_images ||
7343 ctx->Extensions.ARB_bindless_texture ||
7344 (linked_prog->sh.LinkedTransformFeedback &&
7345 linked_prog->sh.LinkedTransformFeedback->NumVarying);
7346
7347 if (!ctx->Driver.ProgramStringNotify(ctx,
7348 _mesa_shader_stage_to_program(i),
7349 linked_prog)) {
7350 _mesa_reference_program(ctx, &shader->Program, NULL);
7351 return GL_FALSE;
7352 }
7353 }
7354 }
7355
7356 return GL_TRUE;
7357 }