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glsl: Add IR conversion ops for 16-bit float types
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_to_tgsi_temprename.h"
56
57 #include "util/hash_table.h"
58 #include <algorithm>
59
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
63
64 #define MAX_GLSL_TEXTURE_OFFSET 4
65
66 #ifndef NDEBUG
67 #include "util/u_atomic.h"
68 #include "util/simple_mtx.h"
69 #include <fstream>
70 #include <ios>
71
72 /* Prepare to make it possible to specify log file */
73 static std::ofstream stats_log;
74
75 /* Helper function to check whether we want to write some statistics
76 * of the shader conversion.
77 */
78
79 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
80
81 static inline bool print_stats_enabled ()
82 {
83 static int stats_enabled = 0;
84
85 if (!stats_enabled) {
86 simple_mtx_lock(&print_stats_mutex);
87 if (!stats_enabled) {
88 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
89 if (stats_filename) {
90 bool write_header = std::ifstream(stats_filename).fail();
91 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
92 stats_enabled = stats_log.good() ? 1 : -1;
93 if (write_header)
94 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
95 } else {
96 stats_enabled = -1;
97 }
98 }
99 simple_mtx_unlock(&print_stats_mutex);
100 }
101 return stats_enabled > 0;
102 }
103 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
104 #else
105 #define PRINT_STATS(X)
106 #endif
107
108
109 static unsigned is_precise(const ir_variable *ir)
110 {
111 if (!ir)
112 return 0;
113 return ir->data.precise || ir->data.invariant;
114 }
115
116 class variable_storage {
117 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
118
119 public:
120 variable_storage(ir_variable *var, gl_register_file file, int index,
121 unsigned array_id = 0)
122 : file(file), index(index), component(0), var(var), array_id(array_id)
123 {
124 assert(file != PROGRAM_ARRAY || array_id != 0);
125 }
126
127 gl_register_file file;
128 int index;
129
130 /* Explicit component location. This is given in terms of the GLSL-style
131 * swizzles where each double is a single component, i.e. for 64-bit types
132 * it can only be 0 or 1.
133 */
134 int component;
135 ir_variable *var; /* variable that maps to this, if any */
136 unsigned array_id;
137 };
138
139 class immediate_storage : public exec_node {
140 public:
141 immediate_storage(gl_constant_value *values, int size32, GLenum type)
142 {
143 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
144 this->size32 = size32;
145 this->type = type;
146 }
147
148 /* doubles are stored across 2 gl_constant_values */
149 gl_constant_value values[4];
150 int size32; /**< Number of 32-bit components (1-4) */
151 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
152 };
153
154 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
155 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
156
157 struct inout_decl {
158 unsigned mesa_index;
159 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
160 unsigned size;
161 unsigned interp_loc;
162 unsigned gs_out_streams;
163 enum glsl_interp_mode interp;
164 enum glsl_base_type base_type;
165 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
166 bool invariant;
167 };
168
169 static struct inout_decl *
170 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
171 {
172 assert(array_id != 0);
173
174 for (unsigned i = 0; i < count; i++) {
175 struct inout_decl *decl = &decls[i];
176
177 if (array_id == decl->array_id) {
178 return decl;
179 }
180 }
181
182 return NULL;
183 }
184
185 static enum glsl_base_type
186 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
187 {
188 if (!array_id)
189 return GLSL_TYPE_ERROR;
190 struct inout_decl *decl = find_inout_array(decls, count, array_id);
191 if (decl)
192 return decl->base_type;
193 return GLSL_TYPE_ERROR;
194 }
195
196 struct hwatomic_decl {
197 unsigned location;
198 unsigned binding;
199 unsigned size;
200 unsigned array_id;
201 };
202
203 struct glsl_to_tgsi_visitor : public ir_visitor {
204 public:
205 glsl_to_tgsi_visitor();
206 ~glsl_to_tgsi_visitor();
207
208 struct gl_context *ctx;
209 struct gl_program *prog;
210 struct gl_shader_program *shader_program;
211 struct gl_linked_shader *shader;
212 struct gl_shader_compiler_options *options;
213
214 int next_temp;
215
216 unsigned *array_sizes;
217 unsigned max_num_arrays;
218 unsigned next_array;
219
220 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
221 unsigned num_inputs;
222 unsigned num_input_arrays;
223 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
224 unsigned num_outputs;
225 unsigned num_output_arrays;
226
227 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
228 unsigned num_atomics;
229 unsigned num_atomic_arrays;
230 int num_address_regs;
231 uint32_t samplers_used;
232 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
233 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
234 int images_used;
235 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
236 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
237 bool image_wr[PIPE_MAX_SHADER_IMAGES];
238 bool indirect_addr_consts;
239 int wpos_transform_const;
240
241 bool native_integers;
242 bool have_sqrt;
243 bool have_fma;
244 bool use_shared_memory;
245 bool has_tex_txf_lz;
246 bool precise;
247 bool need_uarl;
248 bool tg4_component_in_swizzle;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_demote *);
288 virtual void visit(ir_texture *);
289 virtual void visit(ir_if *);
290 virtual void visit(ir_emit_vertex *);
291 virtual void visit(ir_end_primitive *);
292 virtual void visit(ir_barrier *);
293 /*@}*/
294
295 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
296
297 void visit_atomic_counter_intrinsic(ir_call *);
298 void visit_ssbo_intrinsic(ir_call *);
299 void visit_membar_intrinsic(ir_call *);
300 void visit_shared_intrinsic(ir_call *);
301 void visit_image_intrinsic(ir_call *);
302 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
303
304 st_src_reg result;
305
306 /** List of variable_storage */
307 struct hash_table *variables;
308
309 /** List of immediate_storage */
310 exec_list immediates;
311 unsigned num_immediates;
312
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions;
315
316 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
317 st_dst_reg dst = undef_dst,
318 st_src_reg src0 = undef_src,
319 st_src_reg src1 = undef_src,
320 st_src_reg src2 = undef_src,
321 st_src_reg src3 = undef_src);
322
323 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
324 st_dst_reg dst, st_dst_reg dst1,
325 st_src_reg src0 = undef_src,
326 st_src_reg src1 = undef_src,
327 st_src_reg src2 = undef_src,
328 st_src_reg src3 = undef_src);
329
330 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
331 st_dst_reg dst,
332 st_src_reg src0, st_src_reg src1);
333
334 /**
335 * Emit the correct dot-product instruction for the type of arguments
336 */
337 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
338 st_dst_reg dst,
339 st_src_reg src0,
340 st_src_reg src1,
341 unsigned elements);
342
343 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
344 st_dst_reg dst, st_src_reg src0);
345
346 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
347 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
348
349 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
350
351 void get_deref_offsets(ir_dereference *ir,
352 unsigned *array_size,
353 unsigned *base,
354 uint16_t *index,
355 st_src_reg *reladdr,
356 bool opaque);
357 void calc_deref_offsets(ir_dereference *tail,
358 unsigned *array_elements,
359 uint16_t *index,
360 st_src_reg *indirect,
361 unsigned *location);
362 st_src_reg canonicalize_gather_offset(st_src_reg offset);
363 bool handle_bound_deref(ir_dereference *ir);
364
365 bool try_emit_mad(ir_expression *ir,
366 int mul_operand);
367 bool try_emit_mad_for_and_not(ir_expression *ir,
368 int mul_operand);
369
370 void emit_swz(ir_expression *ir);
371
372 bool process_move_condition(ir_rvalue *ir);
373
374 void simplify_cmp(void);
375
376 void rename_temp_registers(struct rename_reg_pair *renames);
377 void get_first_temp_read(int *first_reads);
378 void get_first_temp_write(int *first_writes);
379 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
380 void get_last_temp_write(int *last_writes);
381
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
384
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
389
390 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
391 st_dst_reg *l, st_src_reg *r,
392 st_src_reg *cond, bool cond_swap);
393
394 void print_stats();
395
396 void *mem_ctx;
397 };
398
399 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
400 GLSL_TYPE_FLOAT, 0);
401 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
402 GLSL_TYPE_FLOAT, 1);
403 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
404 GLSL_TYPE_FLOAT, 2);
405
406 static void
407 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
408 PRINTFLIKE(2, 3);
409
410 static void
411 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
412 {
413 va_list args;
414 va_start(args, fmt);
415 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
416 va_end(args);
417
418 prog->data->LinkStatus = LINKING_FAILURE;
419 }
420
421 int
422 swizzle_for_size(int size)
423 {
424 static const int size_swizzles[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
428 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
429 };
430
431 assert((size >= 1) && (size <= 4));
432 return size_swizzles[size - 1];
433 }
434
435
436 glsl_to_tgsi_instruction *
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
438 st_dst_reg dst, st_dst_reg dst1,
439 st_src_reg src0, st_src_reg src1,
440 st_src_reg src2, st_src_reg src3)
441 {
442 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
443 int num_reladdr = 0, i, j;
444 bool dst_is_64bit[2];
445
446 op = get_opcode(op, dst, src0, src1);
447
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
451 */
452 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
453 assert(!dst1.reladdr); /* should be lowered in earlier passes */
454 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
455 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
456 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
457 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
458
459 reladdr_to_temp(ir, &src3, &num_reladdr);
460 reladdr_to_temp(ir, &src2, &num_reladdr);
461 reladdr_to_temp(ir, &src1, &num_reladdr);
462 reladdr_to_temp(ir, &src0, &num_reladdr);
463
464 if (dst.reladdr || dst.reladdr2) {
465 if (dst.reladdr)
466 emit_arl(ir, address_reg, *dst.reladdr);
467 if (dst.reladdr2)
468 emit_arl(ir, address_reg2, *dst.reladdr2);
469 num_reladdr--;
470 }
471
472 assert(num_reladdr == 0);
473
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
476
477 inst->op = op;
478 inst->precise = this->precise;
479 inst->info = tgsi_get_opcode_info(op);
480 inst->dst[0] = dst;
481 inst->dst[1] = dst1;
482 inst->src[0] = src0;
483 inst->src[1] = src1;
484 inst->src[2] = src2;
485 inst->src[3] = src3;
486 inst->is_64bit_expanded = false;
487 inst->ir = ir;
488 inst->dead_mask = 0;
489 inst->tex_offsets = NULL;
490 inst->tex_offset_num_offset = 0;
491 inst->saturate = 0;
492 inst->tex_shadow = 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
495 */
496 inst->tex_type = GLSL_TYPE_FLOAT;
497
498 /* Update indirect addressing status used by TGSI */
499 if (dst.reladdr || dst.reladdr2) {
500 switch (dst.file) {
501 case PROGRAM_STATE_VAR:
502 case PROGRAM_CONSTANT:
503 case PROGRAM_UNIFORM:
504 this->indirect_addr_consts = true;
505 break;
506 case PROGRAM_IMMEDIATE:
507 assert(!"immediates should not have indirect addressing");
508 break;
509 default:
510 break;
511 }
512 }
513 else {
514 for (i = 0; i < 4; i++) {
515 if (inst->src[i].reladdr) {
516 switch (inst->src[i].file) {
517 case PROGRAM_STATE_VAR:
518 case PROGRAM_CONSTANT:
519 case PROGRAM_UNIFORM:
520 this->indirect_addr_consts = true;
521 break;
522 case PROGRAM_IMMEDIATE:
523 assert(!"immediates should not have indirect addressing");
524 break;
525 default:
526 break;
527 }
528 }
529 }
530 }
531
532 /*
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
536 *
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
541 *
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
544 *
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
549 */
550 for (j = 0; j < 2; j++) {
551 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
552 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
553 inst->dst[j].type == GLSL_TYPE_ARRAY) {
554 enum glsl_base_type type = find_array_type(this->outputs,
555 this->num_outputs,
556 inst->dst[j].array_id);
557 if (glsl_base_type_is_64bit(type))
558 dst_is_64bit[j] = true;
559 }
560 }
561
562 if (dst_is_64bit[0] || dst_is_64bit[1] ||
563 glsl_base_type_is_64bit(inst->src[0].type)) {
564 glsl_to_tgsi_instruction *dinst = NULL;
565 int initial_src_swz[4], initial_src_idx[4];
566 int initial_dst_idx[2], initial_dst_writemask[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
569 ? inst->dst[0].writemask : inst->dst[1].writemask;
570
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j = 0; j < 2; j++) {
573 initial_dst_writemask[j] = inst->dst[j].writemask;
574 initial_dst_idx[j] = inst->dst[j].index;
575 }
576
577 for (j = 0; j < 4; j++) {
578 initial_src_swz[j] = inst->src[j].swizzle;
579 initial_src_idx[j] = inst->src[j].index;
580 }
581
582 /*
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
585 */
586 st_src_reg addr;
587 while (writemask) {
588
589 int i = u_bit_scan(&writemask);
590
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
594 inst->op == TGSI_OPCODE_STORE) &&
595 addr.file == PROGRAM_UNDEFINED) {
596 /* We have to advance the buffer address by 16 */
597 addr = get_temp(glsl_type::uint_type);
598 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
599 inst->src[0], st_src_reg_for_int(16));
600 }
601
602 /* first time use previous instruction */
603 if (dinst == NULL) {
604 dinst = inst;
605 } else {
606 /* create a new instructions for subsequent attempts */
607 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
608 *dinst = *inst;
609 dinst->next = NULL;
610 dinst->prev = NULL;
611 }
612 this->instructions.push_tail(dinst);
613 dinst->is_64bit_expanded = true;
614
615 /* modify the destination if we are splitting */
616 for (j = 0; j < 2; j++) {
617 if (dst_is_64bit[j]) {
618 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
619 dinst->dst[j].index = initial_dst_idx[j];
620 if (i > 1) {
621 if (dinst->op == TGSI_OPCODE_LOAD ||
622 dinst->op == TGSI_OPCODE_STORE)
623 dinst->src[0] = addr;
624 if (dinst->op != TGSI_OPCODE_STORE)
625 dinst->dst[j].index++;
626 }
627 } else {
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
630 */
631 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
632 }
633 }
634
635 /* modify the src registers */
636 for (j = 0; j < 4; j++) {
637 int swz = GET_SWZ(initial_src_swz[j], i);
638
639 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
640 dinst->src[j].index = initial_src_idx[j];
641 if (swz > 1) {
642 dinst->src[j].double_reg2 = true;
643 dinst->src[j].index++;
644 }
645
646 if (swz & 1)
647 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
648 SWIZZLE_Z, SWIZZLE_W);
649 else
650 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
651 SWIZZLE_X, SWIZZLE_Y);
652
653 } else {
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
656 * integer src1
657 */
658 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
659 op == TGSI_OPCODE_I2D ||
660 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
661 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
662 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
663 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
664 }
665 }
666 }
667 }
668 inst = dinst;
669 } else {
670 this->instructions.push_tail(inst);
671 }
672
673
674 return inst;
675 }
676
677 glsl_to_tgsi_instruction *
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
679 st_dst_reg dst,
680 st_src_reg src0, st_src_reg src1,
681 st_src_reg src2, st_src_reg src3)
682 {
683 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
684 }
685
686 /**
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
689 */
690 enum tgsi_opcode
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
692 st_dst_reg dst,
693 st_src_reg src0, st_src_reg src1)
694 {
695 enum glsl_base_type type = GLSL_TYPE_FLOAT;
696
697 if (op == TGSI_OPCODE_MOV)
698 return op;
699
700 assert(src0.type != GLSL_TYPE_ARRAY);
701 assert(src0.type != GLSL_TYPE_STRUCT);
702 assert(src1.type != GLSL_TYPE_ARRAY);
703 assert(src1.type != GLSL_TYPE_STRUCT);
704
705 if (is_resource_instruction(op))
706 type = src1.type;
707 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
708 type = GLSL_TYPE_INT64;
709 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
710 type = GLSL_TYPE_UINT64;
711 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
712 type = GLSL_TYPE_DOUBLE;
713 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
714 type = GLSL_TYPE_FLOAT;
715 else if (native_integers)
716 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
717
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
730 else \
731 op = TGSI_OPCODE_##f; \
732 break;
733
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
748 else \
749 op = TGSI_OPCODE_##c; \
750 break;
751
752 switch (op) {
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
755 *
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
757 */
758 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
759 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
760 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
761 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
762 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
763 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
764 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
765 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
766 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
767 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
768 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
769 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
770 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
771 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
772 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
773 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
774
775 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
776 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
777 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
778 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
779 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
780 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
781 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
782 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
783 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
784
785 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
786 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
787 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
788 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
789
790 default:
791 break;
792 }
793
794 assert(op != TGSI_OPCODE_LAST);
795 return op;
796 }
797
798 glsl_to_tgsi_instruction *
799 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
800 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
801 unsigned elements)
802 {
803 static const enum tgsi_opcode dot_opcodes[] = {
804 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
805 };
806
807 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
808 }
809
810 /**
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
812 *
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
817 */
818 void
819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
820 st_dst_reg dst,
821 st_src_reg orig_src0, st_src_reg orig_src1)
822 {
823 int i, j;
824 int done_mask = ~dst.writemask;
825
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
828 * dst channels.
829 */
830 for (i = 0; i < 4; i++) {
831 GLuint this_mask = (1 << i);
832 st_src_reg src0 = orig_src0;
833 st_src_reg src1 = orig_src1;
834
835 if (done_mask & this_mask)
836 continue;
837
838 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
839 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
840 for (j = i + 1; j < 4; j++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
843 * well.
844 */
845 if (!(done_mask & (1 << j)) &&
846 GET_SWZ(src0.swizzle, j) == src0_swiz &&
847 GET_SWZ(src1.swizzle, j) == src1_swiz) {
848 this_mask |= (1 << j);
849 }
850 }
851 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
852 src0_swiz, src0_swiz);
853 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
854 src1_swiz, src1_swiz);
855
856 dst.writemask = this_mask;
857 emit_asm(ir, op, dst, src0, src1);
858 done_mask |= this_mask;
859 }
860 }
861
862 void
863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
864 st_dst_reg dst, st_src_reg src0)
865 {
866 st_src_reg undef = undef_src;
867
868 undef.swizzle = SWIZZLE_XXXX;
869
870 emit_scalar(ir, op, dst, src0, undef);
871 }
872
873 void
874 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
875 st_dst_reg dst, st_src_reg src0)
876 {
877 enum tgsi_opcode op = TGSI_OPCODE_ARL;
878
879 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
880 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
881 return;
882
883 op = TGSI_OPCODE_UARL;
884 }
885
886 assert(dst.file == PROGRAM_ADDRESS);
887 if (dst.index >= this->num_address_regs)
888 this->num_address_regs = dst.index + 1;
889
890 emit_asm(NULL, op, dst, src0);
891 }
892
893 int
894 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
895 gl_constant_value values[8], int size,
896 GLenum datatype,
897 uint16_t *swizzle_out)
898 {
899 if (file == PROGRAM_CONSTANT) {
900 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
901 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
902 values, size, datatype,
903 &swizzle);
904 if (swizzle_out)
905 *swizzle_out = swizzle;
906 return result;
907 }
908
909 assert(file == PROGRAM_IMMEDIATE);
910
911 int index = 0;
912 immediate_storage *entry;
913 int size32 = size * ((datatype == GL_DOUBLE ||
914 datatype == GL_INT64_ARB ||
915 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
916 int i;
917
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
920 */
921 foreach_in_list(immediate_storage, entry, &this->immediates) {
922 immediate_storage *tmp = entry;
923
924 for (i = 0; i * 4 < size32; i++) {
925 int slot_size = MIN2(size32 - (i * 4), 4);
926 if (tmp->type != datatype || tmp->size32 != slot_size)
927 break;
928 if (memcmp(tmp->values, &values[i * 4],
929 slot_size * sizeof(gl_constant_value)))
930 break;
931
932 /* Everything matches, keep going until the full size is matched */
933 tmp = (immediate_storage *)tmp->next;
934 }
935
936 /* The full value matched */
937 if (i * 4 >= size32)
938 return index;
939
940 index++;
941 }
942
943 for (i = 0; i * 4 < size32; i++) {
944 int slot_size = MIN2(size32 - (i * 4), 4);
945 /* Add this immediate to the list. */
946 entry = new(mem_ctx) immediate_storage(&values[i * 4],
947 slot_size, datatype);
948 this->immediates.push_tail(entry);
949 this->num_immediates++;
950 }
951 return index;
952 }
953
954 st_src_reg
955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
956 {
957 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
958 union gl_constant_value uval;
959
960 uval.f = val;
961 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
962
963 return src;
964 }
965
966 st_src_reg
967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
968 {
969 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
970 union gl_constant_value uval[2];
971
972 memcpy(uval, &val, sizeof(uval));
973 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
974 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
975 return src;
976 }
977
978 st_src_reg
979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
980 {
981 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
982 union gl_constant_value uval;
983
984 assert(native_integers);
985
986 uval.i = val;
987 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
988
989 return src;
990 }
991
992 st_src_reg
993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
994 {
995 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
996 union gl_constant_value uval[2];
997
998 memcpy(uval, &val, sizeof(uval));
999 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
1000 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1001
1002 return src;
1003 }
1004
1005 st_src_reg
1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1007 {
1008 if (native_integers)
1009 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1010 st_src_reg_for_int(val);
1011 else
1012 return st_src_reg_for_float(val);
1013 }
1014
1015 static int
1016 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1017 {
1018 return type->count_attribute_slots(is_vs_input);
1019 }
1020
1021 static int
1022 type_size(const struct glsl_type *type)
1023 {
1024 return type->count_attribute_slots(false);
1025 }
1026
1027 static void
1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1029 exec_list *instructions, ir_constant *access)
1030 {
1031 /**
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1034 */
1035 enum tgsi_opcode op = inst->op;
1036 do {
1037 inst->resource = *buf;
1038 if (access)
1039 inst->buffer_access = access->value.u[0];
1040
1041 if (inst == instructions->get_head_raw())
1042 break;
1043 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1044
1045 if (inst->op == TGSI_OPCODE_UADD) {
1046 if (inst == instructions->get_head_raw())
1047 break;
1048 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1049 }
1050 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1051 }
1052
1053 /**
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1056 *
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1061 */
1062 static bool
1063 type_has_array_or_matrix(const glsl_type *type)
1064 {
1065 if (type->is_array() || type->is_matrix())
1066 return true;
1067
1068 if (type->is_struct()) {
1069 for (unsigned i = 0; i < type->length; i++) {
1070 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1071 return true;
1072 }
1073 }
1074 }
1075
1076 return false;
1077 }
1078
1079
1080 /**
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1083 * storage).
1084 */
1085 st_src_reg
1086 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1087 {
1088 st_src_reg src;
1089
1090 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1091 src.reladdr = NULL;
1092 src.negate = 0;
1093 src.abs = 0;
1094
1095 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1096 if (next_array >= max_num_arrays) {
1097 max_num_arrays += 32;
1098 array_sizes = (unsigned*)
1099 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1100 }
1101
1102 src.file = PROGRAM_ARRAY;
1103 src.index = 0;
1104 src.array_id = next_array + 1;
1105 array_sizes[next_array] = type_size(type);
1106 ++next_array;
1107
1108 } else {
1109 src.file = PROGRAM_TEMPORARY;
1110 src.index = next_temp;
1111 next_temp += type_size(type);
1112 }
1113
1114 if (type->is_array() || type->is_struct()) {
1115 src.swizzle = SWIZZLE_NOOP;
1116 } else {
1117 src.swizzle = swizzle_for_size(type->vector_elements);
1118 }
1119
1120 return src;
1121 }
1122
1123 variable_storage *
1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1125 {
1126 struct hash_entry *entry;
1127
1128 entry = _mesa_hash_table_search(this->variables, var);
1129 if (!entry)
1130 return NULL;
1131
1132 return (variable_storage *)entry->data;
1133 }
1134
1135 void
1136 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1137 {
1138 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1139 unsigned int i;
1140 const ir_state_slot *const slots = ir->get_state_slots();
1141 assert(slots != NULL);
1142
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1147 * out.
1148 */
1149 for (i = 0; i < ir->get_num_state_slots(); i++) {
1150 if (slots[i].swizzle != SWIZZLE_XYZW) {
1151 break;
1152 }
1153 }
1154
1155 variable_storage *storage;
1156 st_dst_reg dst;
1157 if (i == ir->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1160
1161 _mesa_hash_table_insert(this->variables, ir, storage);
1162
1163 dst = undef_dst;
1164 } else {
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1168 */
1169 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1170
1171 dst = st_dst_reg(get_temp(ir->type));
1172
1173 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1174 dst.array_id);
1175
1176 _mesa_hash_table_insert(this->variables, ir, storage);
1177 }
1178
1179
1180 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1181 int index = _mesa_add_state_reference(this->prog->Parameters,
1182 slots[i].tokens);
1183
1184 if (storage->file == PROGRAM_STATE_VAR) {
1185 if (storage->index == -1) {
1186 storage->index = index;
1187 } else {
1188 assert(index == storage->index + (int)i);
1189 }
1190 } else {
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1195 */
1196 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1197 src.swizzle = slots[i].swizzle;
1198 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1200 dst.index++;
1201 }
1202 }
1203
1204 if (storage->file == PROGRAM_TEMPORARY &&
1205 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1206 fail_link(this->shader_program,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir->name, dst.index - storage->index,
1209 type_size(ir->type));
1210 }
1211 }
1212 }
1213
1214 void
1215 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1216 {
1217 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1218
1219 visit_exec_list(&ir->body_instructions, this);
1220
1221 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1222 }
1223
1224 void
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1226 {
1227 switch (ir->mode) {
1228 case ir_loop_jump::jump_break:
1229 emit_asm(NULL, TGSI_OPCODE_BRK);
1230 break;
1231 case ir_loop_jump::jump_continue:
1232 emit_asm(NULL, TGSI_OPCODE_CONT);
1233 break;
1234 }
1235 }
1236
1237
1238 void
1239 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1240 {
1241 assert(0);
1242 (void)ir;
1243 }
1244
1245 void
1246 glsl_to_tgsi_visitor::visit(ir_function *ir)
1247 {
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1250 */
1251 if (strcmp(ir->name, "main") == 0) {
1252 const ir_function_signature *sig;
1253 exec_list empty;
1254
1255 sig = ir->matching_signature(NULL, &empty, false);
1256
1257 assert(sig);
1258
1259 foreach_in_list(ir_instruction, ir, &sig->body) {
1260 ir->accept(this);
1261 }
1262 }
1263 }
1264
1265 bool
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1267 {
1268 int nonmul_operand = 1 - mul_operand;
1269 st_src_reg a, b, c;
1270 st_dst_reg result_dst;
1271
1272 // there is no TGSI opcode for this
1273 if (ir->type->is_integer_64())
1274 return false;
1275
1276 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1277 if (!expr || expr->operation != ir_binop_mul)
1278 return false;
1279
1280 expr->operands[0]->accept(this);
1281 a = this->result;
1282 expr->operands[1]->accept(this);
1283 b = this->result;
1284 ir->operands[nonmul_operand]->accept(this);
1285 c = this->result;
1286
1287 this->result = get_temp(ir->type);
1288 result_dst = st_dst_reg(this->result);
1289 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1290 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1291
1292 return true;
1293 }
1294
1295 /**
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1297 *
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1302 *
1303 * - a * !b
1304 * - a * (1 - b)
1305 * - (a * 1) - (a * b)
1306 * - a + -(a * b)
1307 * - a + (a * -b)
1308 *
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1310 * instruction.
1311 */
1312 bool
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1314 int try_operand)
1315 {
1316 const int other_operand = 1 - try_operand;
1317 st_src_reg a, b;
1318
1319 ir_expression *expr = ir->operands[try_operand]->as_expression();
1320 if (!expr || expr->operation != ir_unop_logic_not)
1321 return false;
1322
1323 ir->operands[other_operand]->accept(this);
1324 a = this->result;
1325 expr->operands[0]->accept(this);
1326 b = this->result;
1327
1328 b.negate = ~b.negate;
1329
1330 this->result = get_temp(ir->type);
1331 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1332
1333 return true;
1334 }
1335
1336 void
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1338 st_src_reg *reg, int *num_reladdr)
1339 {
1340 if (!reg->reladdr && !reg->reladdr2)
1341 return;
1342
1343 if (reg->reladdr)
1344 emit_arl(ir, address_reg, *reg->reladdr);
1345 if (reg->reladdr2)
1346 emit_arl(ir, address_reg2, *reg->reladdr2);
1347
1348 if (*num_reladdr != 1) {
1349 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1350
1351 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1352 *reg = temp;
1353 }
1354
1355 (*num_reladdr)--;
1356 }
1357
1358 void
1359 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1360 {
1361 st_src_reg op[ARRAY_SIZE(ir->operands)];
1362
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1364 */
1365 if (!this->precise && ir->operation == ir_binop_add) {
1366 if (try_emit_mad(ir, 1))
1367 return;
1368 if (try_emit_mad(ir, 0))
1369 return;
1370 }
1371
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1373 */
1374 if (!native_integers && ir->operation == ir_binop_logic_and) {
1375 if (try_emit_mad_for_and_not(ir, 1))
1376 return;
1377 if (try_emit_mad_for_and_not(ir, 0))
1378 return;
1379 }
1380
1381 if (ir->operation == ir_quadop_vector)
1382 assert(!"ir_quadop_vector should have been lowered");
1383
1384 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1385 this->result.file = PROGRAM_UNDEFINED;
1386 ir->operands[operand]->accept(this);
1387 if (this->result.file == PROGRAM_UNDEFINED) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir->operands[operand]->print();
1390 printf("\n");
1391 exit(1);
1392 }
1393 op[operand] = this->result;
1394
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1397 */
1398 assert(!ir->operands[operand]->type->is_matrix());
1399 }
1400
1401 visit_expression(ir, op);
1402 }
1403
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1407 */
1408 void
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1410 {
1411 st_src_reg result_src;
1412 st_dst_reg result_dst;
1413
1414 int vector_elements = ir->operands[0]->type->vector_elements;
1415 if (ir->operands[1] &&
1416 ir->operation != ir_binop_interpolate_at_offset &&
1417 ir->operation != ir_binop_interpolate_at_sample) {
1418 st_src_reg *swz_op = NULL;
1419 if (vector_elements > ir->operands[1]->type->vector_elements) {
1420 assert(ir->operands[1]->type->vector_elements == 1);
1421 swz_op = &op[1];
1422 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1423 assert(ir->operands[0]->type->vector_elements == 1);
1424 swz_op = &op[0];
1425 }
1426 if (swz_op) {
1427 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1428 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1429 swizzle_x, swizzle_x);
1430 }
1431 vector_elements = MAX2(vector_elements,
1432 ir->operands[1]->type->vector_elements);
1433 }
1434 if (ir->operands[2] &&
1435 ir->operands[2]->type->vector_elements != vector_elements) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir->operands[2]->type->vector_elements == 1);
1438 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1439 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1440 swizzle_x, swizzle_x);
1441 }
1442
1443 this->result.file = PROGRAM_UNDEFINED;
1444
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1447 */
1448 result_src = get_temp(ir->type);
1449 /* convenience for the emit functions below. */
1450 result_dst = st_dst_reg(result_src);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1453 * sequences.
1454 */
1455 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1456
1457 switch (ir->operation) {
1458 case ir_unop_logic_not:
1459 if (result_dst.type != GLSL_TYPE_FLOAT)
1460 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1461 else {
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1466 */
1467 op[0].negate = ~op[0].negate;
1468 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1469 st_src_reg_for_float(1.0));
1470 }
1471 break;
1472 case ir_unop_neg:
1473 if (result_dst.type == GLSL_TYPE_INT64 ||
1474 result_dst.type == GLSL_TYPE_UINT64)
1475 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1476 else if (result_dst.type == GLSL_TYPE_INT ||
1477 result_dst.type == GLSL_TYPE_UINT)
1478 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1479 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1480 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1481 else {
1482 op[0].negate = ~op[0].negate;
1483 result_src = op[0];
1484 }
1485 break;
1486 case ir_unop_subroutine_to_int:
1487 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1488 break;
1489 case ir_unop_abs:
1490 if (result_dst.type == GLSL_TYPE_FLOAT)
1491 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1492 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1493 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1494 else if (result_dst.type == GLSL_TYPE_INT64 ||
1495 result_dst.type == GLSL_TYPE_UINT64)
1496 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1497 else
1498 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1499 break;
1500 case ir_unop_sign:
1501 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1502 break;
1503 case ir_unop_rcp:
1504 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1505 break;
1506
1507 case ir_unop_exp2:
1508 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1509 break;
1510 case ir_unop_exp:
1511 assert(!"not reached: should be handled by exp_to_exp2");
1512 break;
1513 case ir_unop_log:
1514 assert(!"not reached: should be handled by log_to_log2");
1515 break;
1516 case ir_unop_log2:
1517 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1518 break;
1519 case ir_unop_sin:
1520 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1521 break;
1522 case ir_unop_cos:
1523 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1524 break;
1525 case ir_unop_saturate: {
1526 glsl_to_tgsi_instruction *inst;
1527 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1528 inst->saturate = true;
1529 break;
1530 }
1531
1532 case ir_unop_dFdx:
1533 case ir_unop_dFdx_coarse:
1534 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1535 break;
1536 case ir_unop_dFdx_fine:
1537 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1538 break;
1539 case ir_unop_dFdy:
1540 case ir_unop_dFdy_coarse:
1541 case ir_unop_dFdy_fine:
1542 {
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1546 */
1547 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1548 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1549
1550 unsigned transform_y_index =
1551 _mesa_add_state_reference(this->prog->Parameters,
1552 transform_y_state);
1553
1554 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1555 transform_y_index,
1556 glsl_type::vec4_type);
1557 transform_y.swizzle = SWIZZLE_XXXX;
1558
1559 st_src_reg temp = get_temp(glsl_type::vec4_type);
1560
1561 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1562 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1563 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1564 break;
1565 }
1566
1567 case ir_unop_frexp_sig:
1568 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1569 break;
1570
1571 case ir_unop_frexp_exp:
1572 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1573 break;
1574
1575 case ir_unop_noise: {
1576 /* At some point, a motivated person could add a better
1577 * implementation of noise. Currently not even the nvidia
1578 * binary drivers do anything more than this. In any case, the
1579 * place to do this is in the GL state tracker, not the poor
1580 * driver.
1581 */
1582 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1583 break;
1584 }
1585
1586 case ir_binop_add:
1587 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1588 break;
1589 case ir_binop_sub:
1590 op[1].negate = ~op[1].negate;
1591 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1592 break;
1593
1594 case ir_binop_mul:
1595 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1596 break;
1597 case ir_binop_div:
1598 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1599 break;
1600 case ir_binop_mod:
1601 if (result_dst.type == GLSL_TYPE_FLOAT)
1602 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1603 else
1604 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1605 break;
1606
1607 case ir_binop_less:
1608 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1609 break;
1610 case ir_binop_gequal:
1611 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1612 break;
1613 case ir_binop_equal:
1614 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1615 break;
1616 case ir_binop_nequal:
1617 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1618 break;
1619 case ir_binop_all_equal:
1620 /* "==" operator producing a scalar boolean. */
1621 if (ir->operands[0]->type->is_vector() ||
1622 ir->operands[1]->type->is_vector()) {
1623 st_src_reg temp = get_temp(native_integers ?
1624 glsl_type::uvec4_type :
1625 glsl_type::vec4_type);
1626
1627 if (native_integers) {
1628 st_dst_reg temp_dst = st_dst_reg(temp);
1629 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1630
1631 if (ir->operands[0]->type->is_boolean() &&
1632 ir->operands[1]->as_constant() &&
1633 ir->operands[1]->as_constant()->is_one()) {
1634 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1635 } else {
1636 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1637 }
1638
1639 /* Emit 1-3 AND operations to combine the SEQ results. */
1640 switch (ir->operands[0]->type->vector_elements) {
1641 case 2:
1642 break;
1643 case 3:
1644 temp_dst.writemask = WRITEMASK_Y;
1645 temp1.swizzle = SWIZZLE_YYYY;
1646 temp2.swizzle = SWIZZLE_ZZZZ;
1647 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1648 break;
1649 case 4:
1650 temp_dst.writemask = WRITEMASK_X;
1651 temp1.swizzle = SWIZZLE_XXXX;
1652 temp2.swizzle = SWIZZLE_YYYY;
1653 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1654 temp_dst.writemask = WRITEMASK_Y;
1655 temp1.swizzle = SWIZZLE_ZZZZ;
1656 temp2.swizzle = SWIZZLE_WWWW;
1657 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1658 }
1659
1660 temp1.swizzle = SWIZZLE_XXXX;
1661 temp2.swizzle = SWIZZLE_YYYY;
1662 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1663 } else {
1664 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1665
1666 /* After the dot-product, the value will be an integer on the
1667 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1668 */
1669 emit_dp(ir, result_dst, temp, temp, vector_elements);
1670
1671 /* Negating the result of the dot-product gives values on the range
1672 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1673 * This is achieved using SGE.
1674 */
1675 st_src_reg sge_src = result_src;
1676 sge_src.negate = ~sge_src.negate;
1677 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1678 st_src_reg_for_float(0.0));
1679 }
1680 } else {
1681 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1682 }
1683 break;
1684 case ir_binop_any_nequal:
1685 /* "!=" operator producing a scalar boolean. */
1686 if (ir->operands[0]->type->is_vector() ||
1687 ir->operands[1]->type->is_vector()) {
1688 st_src_reg temp = get_temp(native_integers ?
1689 glsl_type::uvec4_type :
1690 glsl_type::vec4_type);
1691 if (ir->operands[0]->type->is_boolean() &&
1692 ir->operands[1]->as_constant() &&
1693 ir->operands[1]->as_constant()->is_zero()) {
1694 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1695 } else {
1696 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1697 }
1698
1699 if (native_integers) {
1700 st_dst_reg temp_dst = st_dst_reg(temp);
1701 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1702
1703 /* Emit 1-3 OR operations to combine the SNE results. */
1704 switch (ir->operands[0]->type->vector_elements) {
1705 case 2:
1706 break;
1707 case 3:
1708 temp_dst.writemask = WRITEMASK_Y;
1709 temp1.swizzle = SWIZZLE_YYYY;
1710 temp2.swizzle = SWIZZLE_ZZZZ;
1711 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1712 break;
1713 case 4:
1714 temp_dst.writemask = WRITEMASK_X;
1715 temp1.swizzle = SWIZZLE_XXXX;
1716 temp2.swizzle = SWIZZLE_YYYY;
1717 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1718 temp_dst.writemask = WRITEMASK_Y;
1719 temp1.swizzle = SWIZZLE_ZZZZ;
1720 temp2.swizzle = SWIZZLE_WWWW;
1721 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1722 }
1723
1724 temp1.swizzle = SWIZZLE_XXXX;
1725 temp2.swizzle = SWIZZLE_YYYY;
1726 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1727 } else {
1728 /* After the dot-product, the value will be an integer on the
1729 * range [0,4]. Zero stays zero, and positive values become 1.0.
1730 */
1731 glsl_to_tgsi_instruction *const dp =
1732 emit_dp(ir, result_dst, temp, temp, vector_elements);
1733 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1734 /* The clamping to [0,1] can be done for free in the fragment
1735 * shader with a saturate.
1736 */
1737 dp->saturate = true;
1738 } else {
1739 /* Negating the result of the dot-product gives values on the
1740 * range [-4, 0]. Zero stays zero, and negative values become
1741 * 1.0. This achieved using SLT.
1742 */
1743 st_src_reg slt_src = result_src;
1744 slt_src.negate = ~slt_src.negate;
1745 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1746 st_src_reg_for_float(0.0));
1747 }
1748 }
1749 } else {
1750 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1751 }
1752 break;
1753
1754 case ir_binop_logic_xor:
1755 if (native_integers)
1756 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1757 else
1758 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1759 break;
1760
1761 case ir_binop_logic_or: {
1762 if (native_integers) {
1763 /* If integers are used as booleans, we can use an actual "or"
1764 * instruction.
1765 */
1766 assert(native_integers);
1767 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1768 } else {
1769 /* After the addition, the value will be an integer on the
1770 * range [0,2]. Zero stays zero, and positive values become 1.0.
1771 */
1772 glsl_to_tgsi_instruction *add =
1773 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1774 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1775 /* The clamping to [0,1] can be done for free in the fragment
1776 * shader with a saturate if floats are being used as boolean
1777 * values.
1778 */
1779 add->saturate = true;
1780 } else {
1781 /* Negating the result of the addition gives values on the range
1782 * [-2, 0]. Zero stays zero, and negative values become 1.0
1783 * This is achieved using SLT.
1784 */
1785 st_src_reg slt_src = result_src;
1786 slt_src.negate = ~slt_src.negate;
1787 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1788 st_src_reg_for_float(0.0));
1789 }
1790 }
1791 break;
1792 }
1793
1794 case ir_binop_logic_and:
1795 /* If native integers are disabled, the bool args are stored as float 0.0
1796 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1797 * actual AND opcode.
1798 */
1799 if (native_integers)
1800 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1801 else
1802 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1803 break;
1804
1805 case ir_binop_dot:
1806 assert(ir->operands[0]->type->is_vector());
1807 assert(ir->operands[0]->type == ir->operands[1]->type);
1808 emit_dp(ir, result_dst, op[0], op[1],
1809 ir->operands[0]->type->vector_elements);
1810 break;
1811
1812 case ir_unop_sqrt:
1813 if (have_sqrt) {
1814 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1815 } else {
1816 /* This is the only instruction sequence that makes the game "Risen"
1817 * render correctly. ABS is not required for the game, but since GLSL
1818 * declares negative values as "undefined", allowing us to do whatever
1819 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1820 * behavior.
1821 */
1822 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1823 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1824 }
1825 break;
1826 case ir_unop_rsq:
1827 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1828 break;
1829 case ir_unop_i2f:
1830 if (native_integers) {
1831 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1832 break;
1833 }
1834 /* fallthrough to next case otherwise */
1835 case ir_unop_b2f:
1836 if (native_integers) {
1837 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1838 st_src_reg_for_float(1.0));
1839 break;
1840 }
1841 /* fallthrough to next case otherwise */
1842 case ir_unop_i2u:
1843 case ir_unop_u2i:
1844 case ir_unop_i642u64:
1845 case ir_unop_u642i64:
1846 /* Converting between signed and unsigned integers is a no-op. */
1847 result_src = op[0];
1848 result_src.type = result_dst.type;
1849 break;
1850 case ir_unop_b2i:
1851 if (native_integers) {
1852 /* Booleans are stored as integers using ~0 for true and 0 for false.
1853 * GLSL requires that int(bool) return 1 for true and 0 for false.
1854 * This conversion is done with AND, but it could be done with NEG.
1855 */
1856 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1857 st_src_reg_for_int(1));
1858 } else {
1859 /* Booleans and integers are both stored as floats when native
1860 * integers are disabled.
1861 */
1862 result_src = op[0];
1863 }
1864 break;
1865 case ir_unop_f2i:
1866 if (native_integers)
1867 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1868 else
1869 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1870 break;
1871 case ir_unop_f2u:
1872 if (native_integers)
1873 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1874 else
1875 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1876 break;
1877 case ir_unop_bitcast_f2i:
1878 case ir_unop_bitcast_f2u:
1879 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1880 if (op[0].negate || op[0].abs)
1881 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1882 else
1883 result_src = op[0];
1884 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1885 GLSL_TYPE_UINT;
1886 break;
1887 case ir_unop_bitcast_i2f:
1888 case ir_unop_bitcast_u2f:
1889 result_src = op[0];
1890 result_src.type = GLSL_TYPE_FLOAT;
1891 break;
1892 case ir_unop_f2b:
1893 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1894 st_src_reg_for_float(0.0));
1895 break;
1896 case ir_unop_d2b:
1897 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1898 st_src_reg_for_double(0.0));
1899 break;
1900 case ir_unop_i2b:
1901 if (native_integers)
1902 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1903 st_src_reg_for_int(0));
1904 else
1905 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1906 st_src_reg_for_float(0.0));
1907 break;
1908 case ir_unop_bitcast_u642d:
1909 case ir_unop_bitcast_i642d:
1910 result_src = op[0];
1911 result_src.type = GLSL_TYPE_DOUBLE;
1912 break;
1913 case ir_unop_bitcast_d2i64:
1914 result_src = op[0];
1915 result_src.type = GLSL_TYPE_INT64;
1916 break;
1917 case ir_unop_bitcast_d2u64:
1918 result_src = op[0];
1919 result_src.type = GLSL_TYPE_UINT64;
1920 break;
1921 case ir_unop_trunc:
1922 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1923 break;
1924 case ir_unop_ceil:
1925 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1926 break;
1927 case ir_unop_floor:
1928 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1929 break;
1930 case ir_unop_round_even:
1931 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1932 break;
1933 case ir_unop_fract:
1934 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1935 break;
1936
1937 case ir_binop_min:
1938 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1939 break;
1940 case ir_binop_max:
1941 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1942 break;
1943 case ir_binop_pow:
1944 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1945 break;
1946
1947 case ir_unop_bit_not:
1948 if (native_integers) {
1949 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1950 break;
1951 }
1952 case ir_unop_u2f:
1953 if (native_integers) {
1954 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1955 break;
1956 }
1957 case ir_binop_lshift:
1958 case ir_binop_rshift:
1959 if (native_integers) {
1960 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1961 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1962 st_src_reg count;
1963
1964 if (glsl_base_type_is_64bit(op[0].type)) {
1965 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1966 * 64 bits.
1967 */
1968 count = get_temp(glsl_type::u64vec(ir->operands[1]
1969 ->type->components()));
1970 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1971 } else {
1972 count = op[1];
1973 }
1974
1975 emit_asm(ir, opcode, result_dst, op[0], count);
1976 break;
1977 }
1978 case ir_binop_bit_and:
1979 if (native_integers) {
1980 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1981 break;
1982 }
1983 case ir_binop_bit_xor:
1984 if (native_integers) {
1985 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1986 break;
1987 }
1988 case ir_binop_bit_or:
1989 if (native_integers) {
1990 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1991 break;
1992 }
1993
1994 assert(!"GLSL 1.30 features unsupported");
1995 break;
1996
1997 case ir_binop_ubo_load: {
1998 if (ctx->Const.UseSTD430AsDefaultPacking) {
1999 ir_rvalue *block = ir->operands[0];
2000 ir_rvalue *offset = ir->operands[1];
2001 ir_constant *const_block = block->as_constant();
2002
2003 st_src_reg cbuf(PROGRAM_CONSTANT,
2004 (const_block ? const_block->value.u[0] + 1 : 1),
2005 ir->type->base_type);
2006
2007 cbuf.has_index2 = true;
2008
2009 if (!const_block) {
2010 block->accept(this);
2011 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2012 *cbuf.reladdr = this->result;
2013 emit_arl(ir, sampler_reladdr, this->result);
2014 }
2015
2016 /* Calculate the surface offset */
2017 offset->accept(this);
2018 st_src_reg off = this->result;
2019
2020 glsl_to_tgsi_instruction *inst =
2021 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2022
2023 if (result_dst.type == GLSL_TYPE_BOOL)
2024 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2025 st_src_reg_for_int(0));
2026
2027 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2028 NULL);
2029 } else {
2030 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2031 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2032 unsigned const_offset = const_offset_ir ?
2033 const_offset_ir->value.u[0] : 0;
2034 unsigned const_block = const_uniform_block ?
2035 const_uniform_block->value.u[0] + 1 : 1;
2036 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2037 st_src_reg cbuf;
2038
2039 cbuf.type = ir->type->base_type;
2040 cbuf.file = PROGRAM_CONSTANT;
2041 cbuf.index = 0;
2042 cbuf.reladdr = NULL;
2043 cbuf.negate = 0;
2044 cbuf.abs = 0;
2045 cbuf.index2D = const_block;
2046
2047 assert(ir->type->is_vector() || ir->type->is_scalar());
2048
2049 if (const_offset_ir) {
2050 /* Constant index into constant buffer */
2051 cbuf.reladdr = NULL;
2052 cbuf.index = const_offset / 16;
2053 } else {
2054 ir_expression *offset_expr = ir->operands[1]->as_expression();
2055 st_src_reg offset = op[1];
2056
2057 /* The OpenGL spec is written in such a way that accesses with
2058 * non-constant offset are almost always vec4-aligned. The only
2059 * exception to this are members of structs in arrays of structs:
2060 * each struct in an array of structs is at least vec4-aligned,
2061 * but single-element and [ui]vec2 members of the struct may be at
2062 * an offset that is not a multiple of 16 bytes.
2063 *
2064 * Here, we extract that offset, relying on previous passes to
2065 * always generate offset expressions of the form
2066 * (+ expr constant_offset).
2067 *
2068 * Note that the std430 layout, which allows more cases of
2069 * alignment less than vec4 in arrays, is not supported for
2070 * uniform blocks, so we do not have to deal with it here.
2071 */
2072 if (offset_expr && offset_expr->operation == ir_binop_add) {
2073 const_offset_ir = offset_expr->operands[1]->as_constant();
2074 if (const_offset_ir) {
2075 const_offset = const_offset_ir->value.u[0];
2076 cbuf.index = const_offset / 16;
2077 offset_expr->operands[0]->accept(this);
2078 offset = this->result;
2079 }
2080 }
2081
2082 /* Relative/variable index into constant buffer */
2083 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2084 st_src_reg_for_int(4));
2085 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2086 *cbuf.reladdr = index_reg;
2087 }
2088
2089 if (const_uniform_block) {
2090 /* Constant constant buffer */
2091 cbuf.reladdr2 = NULL;
2092 } else {
2093 /* Relative/variable constant buffer */
2094 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2095 *cbuf.reladdr2 = op[0];
2096 }
2097 cbuf.has_index2 = true;
2098
2099 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2100 if (glsl_base_type_is_64bit(cbuf.type))
2101 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2102 const_offset % 16 / 8,
2103 const_offset % 16 / 8,
2104 const_offset % 16 / 8);
2105 else
2106 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2107 const_offset % 16 / 4,
2108 const_offset % 16 / 4,
2109 const_offset % 16 / 4);
2110
2111 if (ir->type->is_boolean()) {
2112 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2113 st_src_reg_for_int(0));
2114 } else {
2115 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2116 }
2117 }
2118 break;
2119 }
2120 case ir_triop_lrp:
2121 /* note: we have to reorder the three args here */
2122 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2123 break;
2124 case ir_triop_csel:
2125 if (this->ctx->Const.NativeIntegers)
2126 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2127 else {
2128 op[0].negate = ~op[0].negate;
2129 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2130 }
2131 break;
2132 case ir_triop_bitfield_extract:
2133 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2134 break;
2135 case ir_quadop_bitfield_insert:
2136 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2137 break;
2138 case ir_unop_bitfield_reverse:
2139 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2140 break;
2141 case ir_unop_bit_count:
2142 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2143 break;
2144 case ir_unop_find_msb:
2145 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2146 break;
2147 case ir_unop_find_lsb:
2148 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2149 break;
2150 case ir_binop_imul_high:
2151 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2152 break;
2153 case ir_triop_fma:
2154 /* In theory, MAD is incorrect here. */
2155 if (have_fma)
2156 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2157 else
2158 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2159 break;
2160 case ir_unop_interpolate_at_centroid:
2161 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2162 break;
2163 case ir_binop_interpolate_at_offset: {
2164 /* The y coordinate needs to be flipped for the default fb */
2165 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2166 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2167
2168 unsigned transform_y_index =
2169 _mesa_add_state_reference(this->prog->Parameters,
2170 transform_y_state);
2171
2172 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2173 transform_y_index,
2174 glsl_type::vec4_type);
2175 transform_y.swizzle = SWIZZLE_XXXX;
2176
2177 st_src_reg temp = get_temp(glsl_type::vec2_type);
2178 st_dst_reg temp_dst = st_dst_reg(temp);
2179
2180 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2181 temp_dst.writemask = WRITEMASK_Y;
2182 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2183 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2184 break;
2185 }
2186 case ir_binop_interpolate_at_sample:
2187 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2188 break;
2189
2190 case ir_unop_d2f:
2191 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2192 break;
2193 case ir_unop_f2d:
2194 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2195 break;
2196 case ir_unop_d2i:
2197 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2198 break;
2199 case ir_unop_i2d:
2200 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2201 break;
2202 case ir_unop_d2u:
2203 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2204 break;
2205 case ir_unop_u2d:
2206 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2207 break;
2208 case ir_unop_unpack_double_2x32:
2209 case ir_unop_pack_double_2x32:
2210 case ir_unop_unpack_int_2x32:
2211 case ir_unop_pack_int_2x32:
2212 case ir_unop_unpack_uint_2x32:
2213 case ir_unop_pack_uint_2x32:
2214 case ir_unop_unpack_sampler_2x32:
2215 case ir_unop_pack_sampler_2x32:
2216 case ir_unop_unpack_image_2x32:
2217 case ir_unop_pack_image_2x32:
2218 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2219 break;
2220
2221 case ir_binop_ldexp:
2222 if (ir->operands[0]->type->is_double()) {
2223 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2224 } else if (ir->operands[0]->type->is_float()) {
2225 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2226 } else {
2227 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2228 }
2229 break;
2230
2231 case ir_unop_pack_half_2x16:
2232 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2233 break;
2234 case ir_unop_unpack_half_2x16:
2235 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2236 break;
2237
2238 case ir_unop_get_buffer_size: {
2239 ir_constant *const_offset = ir->operands[0]->as_constant();
2240 st_src_reg buffer(
2241 PROGRAM_BUFFER,
2242 const_offset ? const_offset->value.u[0] : 0,
2243 GLSL_TYPE_UINT);
2244 if (!const_offset) {
2245 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2246 *buffer.reladdr = op[0];
2247 emit_arl(ir, sampler_reladdr, op[0]);
2248 }
2249 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2250 break;
2251 }
2252
2253 case ir_unop_u2i64:
2254 case ir_unop_u2u64:
2255 case ir_unop_b2i64: {
2256 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2257 st_dst_reg temp_dst = st_dst_reg(temp);
2258 unsigned orig_swz = op[0].swizzle;
2259 /*
2260 * To convert unsigned to 64-bit:
2261 * zero Y channel, copy X channel.
2262 */
2263 temp_dst.writemask = WRITEMASK_Y;
2264 if (vector_elements > 1)
2265 temp_dst.writemask |= WRITEMASK_W;
2266 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2267 temp_dst.writemask = WRITEMASK_X;
2268 if (vector_elements > 1)
2269 temp_dst.writemask |= WRITEMASK_Z;
2270 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2271 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2272 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2273 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2274 else
2275 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2276 result_src = temp;
2277 result_src.type = GLSL_TYPE_UINT64;
2278 if (vector_elements > 2) {
2279 /* Subtle: We rely on the fact that get_temp here returns the next
2280 * TGSI temporary register directly after the temp register used for
2281 * the first two components, so that the result gets picked up
2282 * automatically.
2283 */
2284 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2285 st_dst_reg temp_dst = st_dst_reg(temp);
2286 temp_dst.writemask = WRITEMASK_Y;
2287 if (vector_elements > 3)
2288 temp_dst.writemask |= WRITEMASK_W;
2289 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2290
2291 temp_dst.writemask = WRITEMASK_X;
2292 if (vector_elements > 3)
2293 temp_dst.writemask |= WRITEMASK_Z;
2294 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2295 GET_SWZ(orig_swz, 2),
2296 GET_SWZ(orig_swz, 3),
2297 GET_SWZ(orig_swz, 3));
2298 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2299 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2300 else
2301 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2302 st_src_reg_for_int(1));
2303 }
2304 break;
2305 }
2306 case ir_unop_i642i:
2307 case ir_unop_u642i:
2308 case ir_unop_u642u:
2309 case ir_unop_i642u: {
2310 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2311 st_dst_reg temp_dst = st_dst_reg(temp);
2312 unsigned orig_swz = op[0].swizzle;
2313 unsigned orig_idx = op[0].index;
2314 int el;
2315 temp_dst.writemask = WRITEMASK_X;
2316
2317 for (el = 0; el < vector_elements; el++) {
2318 unsigned swz = GET_SWZ(orig_swz, el);
2319 if (swz & 1)
2320 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2321 SWIZZLE_Z, SWIZZLE_Z);
2322 else
2323 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2324 SWIZZLE_X, SWIZZLE_X);
2325 if (swz > 2)
2326 op[0].index = orig_idx + 1;
2327 op[0].type = GLSL_TYPE_UINT;
2328 temp_dst.writemask = WRITEMASK_X << el;
2329 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2330 }
2331 result_src = temp;
2332 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2333 result_src.type = GLSL_TYPE_UINT;
2334 else
2335 result_src.type = GLSL_TYPE_INT;
2336 break;
2337 }
2338 case ir_unop_i642b:
2339 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2340 st_src_reg_for_int64(0));
2341 break;
2342 case ir_unop_i642f:
2343 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2344 break;
2345 case ir_unop_u642f:
2346 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2347 break;
2348 case ir_unop_i642d:
2349 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2350 break;
2351 case ir_unop_u642d:
2352 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2353 break;
2354 case ir_unop_i2i64:
2355 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2356 break;
2357 case ir_unop_f2i64:
2358 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2359 break;
2360 case ir_unop_d2i64:
2361 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2362 break;
2363 case ir_unop_i2u64:
2364 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2365 break;
2366 case ir_unop_f2u64:
2367 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2368 break;
2369 case ir_unop_d2u64:
2370 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2371 break;
2372 /* these might be needed */
2373 case ir_unop_pack_snorm_2x16:
2374 case ir_unop_pack_unorm_2x16:
2375 case ir_unop_pack_snorm_4x8:
2376 case ir_unop_pack_unorm_4x8:
2377
2378 case ir_unop_unpack_snorm_2x16:
2379 case ir_unop_unpack_unorm_2x16:
2380 case ir_unop_unpack_snorm_4x8:
2381 case ir_unop_unpack_unorm_4x8:
2382
2383 case ir_quadop_vector:
2384 case ir_binop_vector_extract:
2385 case ir_triop_vector_insert:
2386 case ir_binop_carry:
2387 case ir_binop_borrow:
2388 case ir_unop_ssbo_unsized_array_length:
2389 case ir_unop_atan:
2390 case ir_binop_atan2:
2391 case ir_unop_clz:
2392 case ir_binop_add_sat:
2393 case ir_binop_sub_sat:
2394 case ir_binop_abs_sub:
2395 case ir_binop_avg:
2396 case ir_binop_avg_round:
2397 case ir_binop_mul_32x16:
2398 case ir_unop_f162f:
2399 case ir_unop_f2f16:
2400 /* This operation is not supported, or should have already been handled.
2401 */
2402 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2403 break;
2404 }
2405
2406 this->result = result_src;
2407 }
2408
2409
2410 void
2411 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2412 {
2413 st_src_reg src;
2414 int i;
2415 int swizzle[4] = {0};
2416
2417 /* Note that this is only swizzles in expressions, not those on the left
2418 * hand side of an assignment, which do write masking. See ir_assignment
2419 * for that.
2420 */
2421
2422 ir->val->accept(this);
2423 src = this->result;
2424 assert(src.file != PROGRAM_UNDEFINED);
2425 assert(ir->type->vector_elements > 0);
2426
2427 for (i = 0; i < 4; i++) {
2428 if (i < ir->type->vector_elements) {
2429 switch (i) {
2430 case 0:
2431 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2432 break;
2433 case 1:
2434 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2435 break;
2436 case 2:
2437 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2438 break;
2439 case 3:
2440 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2441 break;
2442 }
2443 } else {
2444 /* If the type is smaller than a vec4, replicate the last
2445 * channel out.
2446 */
2447 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2448 }
2449 }
2450
2451 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2452
2453 this->result = src;
2454 }
2455
2456 /* Test if the variable is an array. Note that geometry and
2457 * tessellation shader inputs are outputs are always arrays (except
2458 * for patch inputs), so only the array element type is considered.
2459 */
2460 static bool
2461 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2462 {
2463 const glsl_type *type = var->type;
2464
2465 *remove_array = false;
2466
2467 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2468 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2469 return false;
2470
2471 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2472 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2473 stage == MESA_SHADER_TESS_CTRL) &&
2474 !var->data.patch) {
2475 if (!var->type->is_array())
2476 return false; /* a system value probably */
2477
2478 type = var->type->fields.array;
2479 *remove_array = true;
2480 }
2481
2482 return type->is_array() || type->is_matrix();
2483 }
2484
2485 static unsigned
2486 st_translate_interp_loc(ir_variable *var)
2487 {
2488 if (var->data.centroid)
2489 return TGSI_INTERPOLATE_LOC_CENTROID;
2490 else if (var->data.sample)
2491 return TGSI_INTERPOLATE_LOC_SAMPLE;
2492 else
2493 return TGSI_INTERPOLATE_LOC_CENTER;
2494 }
2495
2496 void
2497 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2498 {
2499 variable_storage *entry;
2500 ir_variable *var = ir->var;
2501 bool remove_array;
2502
2503 if (handle_bound_deref(ir->as_dereference()))
2504 return;
2505
2506 entry = find_variable_storage(ir->var);
2507
2508 if (!entry) {
2509 switch (var->data.mode) {
2510 case ir_var_uniform:
2511 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2512 var->data.param_index);
2513 _mesa_hash_table_insert(this->variables, var, entry);
2514 break;
2515 case ir_var_shader_in: {
2516 /* The linker assigns locations for varyings and attributes,
2517 * including deprecated builtins (like gl_Color), user-assign
2518 * generic attributes (glBindVertexLocation), and
2519 * user-defined varyings.
2520 */
2521 assert(var->data.location != -1);
2522
2523 const glsl_type *type_without_array = var->type->without_array();
2524 struct inout_decl *decl = &inputs[num_inputs];
2525 unsigned component = var->data.location_frac;
2526 unsigned num_components;
2527 num_inputs++;
2528
2529 if (type_without_array->is_64bit())
2530 component = component / 2;
2531 if (type_without_array->vector_elements)
2532 num_components = type_without_array->vector_elements;
2533 else
2534 num_components = 4;
2535
2536 decl->mesa_index = var->data.location;
2537 decl->interp = (glsl_interp_mode) var->data.interpolation;
2538 decl->interp_loc = st_translate_interp_loc(var);
2539 decl->base_type = type_without_array->base_type;
2540 decl->usage_mask = u_bit_consecutive(component, num_components);
2541
2542 if (is_inout_array(shader->Stage, var, &remove_array)) {
2543 decl->array_id = num_input_arrays + 1;
2544 num_input_arrays++;
2545 } else {
2546 decl->array_id = 0;
2547 }
2548
2549 if (remove_array)
2550 decl->size = type_size(var->type->fields.array);
2551 else
2552 decl->size = type_size(var->type);
2553
2554 entry = new(mem_ctx) variable_storage(var,
2555 PROGRAM_INPUT,
2556 decl->mesa_index,
2557 decl->array_id);
2558 entry->component = component;
2559
2560 _mesa_hash_table_insert(this->variables, var, entry);
2561
2562 break;
2563 }
2564 case ir_var_shader_out: {
2565 assert(var->data.location != -1);
2566
2567 const glsl_type *type_without_array = var->type->without_array();
2568 struct inout_decl *decl = &outputs[num_outputs];
2569 unsigned component = var->data.location_frac;
2570 unsigned num_components;
2571 num_outputs++;
2572
2573 decl->invariant = var->data.invariant;
2574
2575 if (type_without_array->is_64bit())
2576 component = component / 2;
2577 if (type_without_array->vector_elements)
2578 num_components = type_without_array->vector_elements;
2579 else
2580 num_components = 4;
2581
2582 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2583 decl->base_type = type_without_array->base_type;
2584 decl->usage_mask = u_bit_consecutive(component, num_components);
2585 if (var->data.stream & (1u << 31)) {
2586 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2587 } else {
2588 assert(var->data.stream < 4);
2589 decl->gs_out_streams = 0;
2590 for (unsigned i = 0; i < num_components; ++i)
2591 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2592 }
2593
2594 if (is_inout_array(shader->Stage, var, &remove_array)) {
2595 decl->array_id = num_output_arrays + 1;
2596 num_output_arrays++;
2597 } else {
2598 decl->array_id = 0;
2599 }
2600
2601 if (remove_array)
2602 decl->size = type_size(var->type->fields.array);
2603 else
2604 decl->size = type_size(var->type);
2605
2606 if (var->data.fb_fetch_output) {
2607 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2608 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2609 var->type, component, decl->array_id);
2610 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2611 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2612 dst.array_id);
2613 } else {
2614 entry = new(mem_ctx) variable_storage(var,
2615 PROGRAM_OUTPUT,
2616 decl->mesa_index,
2617 decl->array_id);
2618 }
2619 entry->component = component;
2620
2621 _mesa_hash_table_insert(this->variables, var, entry);
2622
2623 break;
2624 }
2625 case ir_var_system_value:
2626 entry = new(mem_ctx) variable_storage(var,
2627 PROGRAM_SYSTEM_VALUE,
2628 var->data.location);
2629 break;
2630 case ir_var_auto:
2631 case ir_var_temporary:
2632 st_src_reg src = get_temp(var->type);
2633
2634 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2635 src.array_id);
2636 _mesa_hash_table_insert(this->variables, var, entry);
2637
2638 break;
2639 }
2640
2641 if (!entry) {
2642 printf("Failed to make storage for %s\n", var->name);
2643 exit(1);
2644 }
2645 }
2646
2647 this->result = st_src_reg(entry->file, entry->index, var->type,
2648 entry->component, entry->array_id);
2649 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2650 var->data.mode == ir_var_shader_in &&
2651 var->type->without_array()->is_double())
2652 this->result.is_double_vertex_input = true;
2653 if (!native_integers)
2654 this->result.type = GLSL_TYPE_FLOAT;
2655 }
2656
2657 static void
2658 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2659 GLbitfield64* usage_mask,
2660 GLbitfield64 double_usage_mask,
2661 GLbitfield* patch_usage_mask)
2662 {
2663 unsigned i;
2664 int j;
2665
2666 /* Fix array declarations by removing unused array elements at both ends
2667 * of the arrays. For example, mat4[3] where only mat[1] is used.
2668 */
2669 for (i = 0; i < count; i++) {
2670 struct inout_decl *decl = &decls[i];
2671 if (!decl->array_id)
2672 continue;
2673
2674 /* Shrink the beginning. */
2675 for (j = 0; j < (int)decl->size; j++) {
2676 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2677 if (*patch_usage_mask &
2678 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2679 break;
2680 }
2681 else {
2682 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2683 break;
2684 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2685 break;
2686 }
2687
2688 decl->mesa_index++;
2689 decl->size--;
2690 j--;
2691 }
2692
2693 /* Shrink the end. */
2694 for (j = decl->size-1; j >= 0; j--) {
2695 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2696 if (*patch_usage_mask &
2697 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2698 break;
2699 }
2700 else {
2701 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2702 break;
2703 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2704 break;
2705 }
2706
2707 decl->size--;
2708 }
2709
2710 /* When not all entries of an array are accessed, we mark them as used
2711 * here anyway, to ensure that the input/output mapping logic doesn't get
2712 * confused.
2713 *
2714 * TODO This happens when an array isn't used via indirect access, which
2715 * some game ports do (at least eON-based). There is an optimization
2716 * opportunity here by replacing the array declaration with non-array
2717 * declarations of those slots that are actually used.
2718 */
2719 for (j = 1; j < (int)decl->size; ++j) {
2720 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2721 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2722 else
2723 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2724 }
2725 }
2726 }
2727
2728
2729 static void
2730 mark_array_io(struct inout_decl *decls, unsigned count,
2731 GLbitfield64* usage_mask,
2732 GLbitfield64 double_usage_mask,
2733 GLbitfield* patch_usage_mask)
2734 {
2735 unsigned i;
2736 int j;
2737
2738 /* Fix array declarations by removing unused array elements at both ends
2739 * of the arrays. For example, mat4[3] where only mat[1] is used.
2740 */
2741 for (i = 0; i < count; i++) {
2742 struct inout_decl *decl = &decls[i];
2743 if (!decl->array_id)
2744 continue;
2745
2746 /* When not all entries of an array are accessed, we mark them as used
2747 * here anyway, to ensure that the input/output mapping logic doesn't get
2748 * confused.
2749 *
2750 * TODO This happens when an array isn't used via indirect access, which
2751 * some game ports do (at least eON-based). There is an optimization
2752 * opportunity here by replacing the array declaration with non-array
2753 * declarations of those slots that are actually used.
2754 */
2755 for (j = 0; j < (int)decl->size; ++j) {
2756 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2757 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2758 else
2759 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2760 }
2761 }
2762 }
2763
2764 void
2765 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2766 {
2767 ir_constant *index;
2768 st_src_reg src;
2769 bool is_2D = false;
2770 ir_variable *var = ir->variable_referenced();
2771
2772 if (handle_bound_deref(ir->as_dereference()))
2773 return;
2774
2775 /* We only need the logic provided by count_vec4_slots()
2776 * for arrays of structs. Indirect sampler and image indexing is handled
2777 * elsewhere.
2778 */
2779 int element_size = ir->type->without_array()->is_struct() ?
2780 ir->type->count_vec4_slots(false, var->data.bindless) :
2781 type_size(ir->type);
2782
2783 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2784
2785 ir->array->accept(this);
2786 src = this->result;
2787
2788 if (!src.has_index2) {
2789 switch (this->prog->Target) {
2790 case GL_TESS_CONTROL_PROGRAM_NV:
2791 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2792 !ir->variable_referenced()->data.patch;
2793 break;
2794 case GL_TESS_EVALUATION_PROGRAM_NV:
2795 is_2D = src.file == PROGRAM_INPUT &&
2796 !ir->variable_referenced()->data.patch;
2797 break;
2798 case GL_GEOMETRY_PROGRAM_NV:
2799 is_2D = src.file == PROGRAM_INPUT;
2800 break;
2801 }
2802 }
2803
2804 if (is_2D)
2805 element_size = 1;
2806
2807 if (index) {
2808
2809 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2810 src.file == PROGRAM_INPUT)
2811 element_size = attrib_type_size(ir->type, true);
2812 if (is_2D) {
2813 src.index2D = index->value.i[0];
2814 src.has_index2 = true;
2815 } else
2816 src.index += index->value.i[0] * element_size;
2817 } else {
2818 /* Variable index array dereference. It eats the "vec4" of the
2819 * base of the array and an index that offsets the TGSI register
2820 * index.
2821 */
2822 ir->array_index->accept(this);
2823
2824 st_src_reg index_reg;
2825
2826 if (element_size == 1) {
2827 index_reg = this->result;
2828 } else {
2829 index_reg = get_temp(native_integers ?
2830 glsl_type::int_type : glsl_type::float_type);
2831
2832 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2833 this->result, st_src_reg_for_type(index_reg.type, element_size));
2834 }
2835
2836 /* If there was already a relative address register involved, add the
2837 * new and the old together to get the new offset.
2838 */
2839 if (!is_2D && src.reladdr != NULL) {
2840 st_src_reg accum_reg = get_temp(native_integers ?
2841 glsl_type::int_type : glsl_type::float_type);
2842
2843 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2844 index_reg, *src.reladdr);
2845
2846 index_reg = accum_reg;
2847 }
2848
2849 if (is_2D) {
2850 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2851 *src.reladdr2 = index_reg;
2852 src.index2D = 0;
2853 src.has_index2 = true;
2854 } else {
2855 src.reladdr = ralloc(mem_ctx, st_src_reg);
2856 *src.reladdr = index_reg;
2857 }
2858 }
2859
2860 /* Change the register type to the element type of the array. */
2861 src.type = ir->type->base_type;
2862
2863 this->result = src;
2864 }
2865
2866 void
2867 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2868 {
2869 unsigned int i;
2870 const glsl_type *struct_type = ir->record->type;
2871 ir_variable *var = ir->record->variable_referenced();
2872 int offset = 0;
2873
2874 if (handle_bound_deref(ir->as_dereference()))
2875 return;
2876
2877 ir->record->accept(this);
2878
2879 assert(ir->field_idx >= 0);
2880 assert(var);
2881 for (i = 0; i < struct_type->length; i++) {
2882 if (i == (unsigned) ir->field_idx)
2883 break;
2884 const glsl_type *member_type = struct_type->fields.structure[i].type;
2885 offset += member_type->count_vec4_slots(false, var->data.bindless);
2886 }
2887
2888 /* If the type is smaller than a vec4, replicate the last channel out. */
2889 if (ir->type->is_scalar() || ir->type->is_vector())
2890 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2891 else
2892 this->result.swizzle = SWIZZLE_NOOP;
2893
2894 this->result.index += offset;
2895 this->result.type = ir->type->base_type;
2896 }
2897
2898 /**
2899 * We want to be careful in assignment setup to hit the actual storage
2900 * instead of potentially using a temporary like we might with the
2901 * ir_dereference handler.
2902 */
2903 static st_dst_reg
2904 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2905 {
2906 /* The LHS must be a dereference. If the LHS is a variable indexed array
2907 * access of a vector, it must be separated into a series conditional moves
2908 * before reaching this point (see ir_vec_index_to_cond_assign).
2909 */
2910 assert(ir->as_dereference());
2911 ir_dereference_array *deref_array = ir->as_dereference_array();
2912 if (deref_array) {
2913 assert(!deref_array->array->type->is_vector());
2914 }
2915
2916 /* Use the rvalue deref handler for the most part. We write swizzles using
2917 * the writemask, but we do extract the base component for enhanced layouts
2918 * from the source swizzle.
2919 */
2920 ir->accept(v);
2921 *component = GET_SWZ(v->result.swizzle, 0);
2922 return st_dst_reg(v->result);
2923 }
2924
2925 /**
2926 * Process the condition of a conditional assignment
2927 *
2928 * Examines the condition of a conditional assignment to generate the optimal
2929 * first operand of a \c CMP instruction. If the condition is a relational
2930 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2931 * used as the source for the \c CMP instruction. Otherwise the comparison
2932 * is processed to a boolean result, and the boolean result is used as the
2933 * operand to the CMP instruction.
2934 */
2935 bool
2936 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2937 {
2938 ir_rvalue *src_ir = ir;
2939 bool negate = true;
2940 bool switch_order = false;
2941
2942 ir_expression *const expr = ir->as_expression();
2943
2944 if (native_integers) {
2945 if ((expr != NULL) && (expr->num_operands == 2)) {
2946 enum glsl_base_type type = expr->operands[0]->type->base_type;
2947 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2948 type == GLSL_TYPE_BOOL) {
2949 if (expr->operation == ir_binop_equal) {
2950 if (expr->operands[0]->is_zero()) {
2951 src_ir = expr->operands[1];
2952 switch_order = true;
2953 }
2954 else if (expr->operands[1]->is_zero()) {
2955 src_ir = expr->operands[0];
2956 switch_order = true;
2957 }
2958 }
2959 else if (expr->operation == ir_binop_nequal) {
2960 if (expr->operands[0]->is_zero()) {
2961 src_ir = expr->operands[1];
2962 }
2963 else if (expr->operands[1]->is_zero()) {
2964 src_ir = expr->operands[0];
2965 }
2966 }
2967 }
2968 }
2969
2970 src_ir->accept(this);
2971 return switch_order;
2972 }
2973
2974 if ((expr != NULL) && (expr->num_operands == 2)) {
2975 bool zero_on_left = false;
2976
2977 if (expr->operands[0]->is_zero()) {
2978 src_ir = expr->operands[1];
2979 zero_on_left = true;
2980 } else if (expr->operands[1]->is_zero()) {
2981 src_ir = expr->operands[0];
2982 zero_on_left = false;
2983 }
2984
2985 /* a is - 0 + - 0 +
2986 * (a < 0) T F F ( a < 0) T F F
2987 * (0 < a) F F T (-a < 0) F F T
2988 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2989 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2990 *
2991 * Note that exchanging the order of 0 and 'a' in the comparison simply
2992 * means that the value of 'a' should be negated.
2993 */
2994 if (src_ir != ir) {
2995 switch (expr->operation) {
2996 case ir_binop_less:
2997 switch_order = false;
2998 negate = zero_on_left;
2999 break;
3000
3001 case ir_binop_gequal:
3002 switch_order = true;
3003 negate = zero_on_left;
3004 break;
3005
3006 default:
3007 /* This isn't the right kind of comparison afterall, so make sure
3008 * the whole condition is visited.
3009 */
3010 src_ir = ir;
3011 break;
3012 }
3013 }
3014 }
3015
3016 src_ir->accept(this);
3017
3018 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3019 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3020 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3021 * computing the condition.
3022 */
3023 if (negate)
3024 this->result.negate = ~this->result.negate;
3025
3026 return switch_order;
3027 }
3028
3029 void
3030 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
3031 st_dst_reg *l, st_src_reg *r,
3032 st_src_reg *cond, bool cond_swap)
3033 {
3034 if (type->is_struct()) {
3035 for (unsigned int i = 0; i < type->length; i++) {
3036 emit_block_mov(ir, type->fields.structure[i].type, l, r,
3037 cond, cond_swap);
3038 }
3039 return;
3040 }
3041
3042 if (type->is_array()) {
3043 for (unsigned int i = 0; i < type->length; i++) {
3044 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
3045 }
3046 return;
3047 }
3048
3049 if (type->is_matrix()) {
3050 const struct glsl_type *vec_type;
3051
3052 vec_type = glsl_type::get_instance(type->is_double()
3053 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3054 type->vector_elements, 1);
3055
3056 for (int i = 0; i < type->matrix_columns; i++) {
3057 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3058 }
3059 return;
3060 }
3061
3062 assert(type->is_scalar() || type->is_vector());
3063
3064 l->type = type->base_type;
3065 r->type = type->base_type;
3066 if (cond) {
3067 st_src_reg l_src = st_src_reg(*l);
3068
3069 if (l_src.file == PROGRAM_OUTPUT &&
3070 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3071 (l_src.index == FRAG_RESULT_DEPTH ||
3072 l_src.index == FRAG_RESULT_STENCIL)) {
3073 /* This is a special case because the source swizzles will be shifted
3074 * later to account for the difference between GLSL (where they're
3075 * plain floats) and TGSI (where they're Z and Y components). */
3076 l_src.swizzle = SWIZZLE_XXXX;
3077 }
3078
3079 if (native_integers) {
3080 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3081 cond_swap ? l_src : *r,
3082 cond_swap ? *r : l_src);
3083 } else {
3084 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3085 cond_swap ? l_src : *r,
3086 cond_swap ? *r : l_src);
3087 }
3088 } else {
3089 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3090 }
3091 l->index++;
3092 r->index++;
3093 if (type->is_dual_slot()) {
3094 l->index++;
3095 if (r->is_double_vertex_input == false)
3096 r->index++;
3097 }
3098 }
3099
3100 void
3101 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3102 {
3103 int dst_component;
3104 st_dst_reg l;
3105 st_src_reg r;
3106
3107 /* all generated instructions need to be flaged as precise */
3108 this->precise = is_precise(ir->lhs->variable_referenced());
3109 ir->rhs->accept(this);
3110 r = this->result;
3111
3112 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3113
3114 {
3115 int swizzles[4];
3116 int first_enabled_chan = 0;
3117 int rhs_chan = 0;
3118 ir_variable *variable = ir->lhs->variable_referenced();
3119
3120 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3121 variable->data.mode == ir_var_shader_out &&
3122 (variable->data.location == FRAG_RESULT_DEPTH ||
3123 variable->data.location == FRAG_RESULT_STENCIL)) {
3124 assert(ir->lhs->type->is_scalar());
3125 assert(ir->write_mask == WRITEMASK_X);
3126
3127 if (variable->data.location == FRAG_RESULT_DEPTH)
3128 l.writemask = WRITEMASK_Z;
3129 else {
3130 assert(variable->data.location == FRAG_RESULT_STENCIL);
3131 l.writemask = WRITEMASK_Y;
3132 }
3133 } else if (ir->write_mask == 0) {
3134 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3135
3136 unsigned num_elements =
3137 ir->lhs->type->without_array()->vector_elements;
3138
3139 if (num_elements) {
3140 l.writemask = u_bit_consecutive(0, num_elements);
3141 } else {
3142 /* The type is a struct or an array of (array of) structs. */
3143 l.writemask = WRITEMASK_XYZW;
3144 }
3145 } else {
3146 l.writemask = ir->write_mask;
3147 }
3148
3149 for (int i = 0; i < 4; i++) {
3150 if (l.writemask & (1 << i)) {
3151 first_enabled_chan = GET_SWZ(r.swizzle, i);
3152 break;
3153 }
3154 }
3155
3156 l.writemask = l.writemask << dst_component;
3157
3158 /* Swizzle a small RHS vector into the channels being written.
3159 *
3160 * glsl ir treats write_mask as dictating how many channels are
3161 * present on the RHS while TGSI treats write_mask as just
3162 * showing which channels of the vec4 RHS get written.
3163 */
3164 for (int i = 0; i < 4; i++) {
3165 if (l.writemask & (1 << i))
3166 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3167 else
3168 swizzles[i] = first_enabled_chan;
3169 }
3170 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3171 swizzles[2], swizzles[3]);
3172 }
3173
3174 assert(l.file != PROGRAM_UNDEFINED);
3175 assert(r.file != PROGRAM_UNDEFINED);
3176
3177 if (ir->condition) {
3178 const bool switch_order = this->process_move_condition(ir->condition);
3179 st_src_reg condition = this->result;
3180
3181 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3182 } else if (ir->rhs->as_expression() &&
3183 this->instructions.get_tail() &&
3184 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3185 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3186 type_size(ir->lhs->type) == 1 &&
3187 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3188 /* To avoid emitting an extra MOV when assigning an expression to a
3189 * variable, emit the last instruction of the expression again, but
3190 * replace the destination register with the target of the assignment.
3191 * Dead code elimination will remove the original instruction.
3192 */
3193 glsl_to_tgsi_instruction *inst, *new_inst;
3194 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3195 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3196 new_inst->saturate = inst->saturate;
3197 new_inst->resource = inst->resource;
3198 inst->dead_mask = inst->dst[0].writemask;
3199 } else {
3200 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3201 }
3202 this->precise = 0;
3203 }
3204
3205
3206 void
3207 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3208 {
3209 st_src_reg src;
3210 GLdouble stack_vals[4] = { 0 };
3211 gl_constant_value *values = (gl_constant_value *) stack_vals;
3212 GLenum gl_type = GL_NONE;
3213 unsigned int i, elements;
3214 static int in_array = 0;
3215 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3216
3217 /* Unfortunately, 4 floats is all we can get into
3218 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3219 * aggregate constant and move each constant value into it. If we
3220 * get lucky, copy propagation will eliminate the extra moves.
3221 */
3222 if (ir->type->is_struct()) {
3223 st_src_reg temp_base = get_temp(ir->type);
3224 st_dst_reg temp = st_dst_reg(temp_base);
3225
3226 for (i = 0; i < ir->type->length; i++) {
3227 ir_constant *const field_value = ir->get_record_field(i);
3228 int size = type_size(field_value->type);
3229
3230 assert(size > 0);
3231
3232 field_value->accept(this);
3233 src = this->result;
3234
3235 for (unsigned j = 0; j < (unsigned int)size; j++) {
3236 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3237
3238 src.index++;
3239 temp.index++;
3240 }
3241 }
3242 this->result = temp_base;
3243 return;
3244 }
3245
3246 if (ir->type->is_array()) {
3247 st_src_reg temp_base = get_temp(ir->type);
3248 st_dst_reg temp = st_dst_reg(temp_base);
3249 int size = type_size(ir->type->fields.array);
3250
3251 assert(size > 0);
3252 in_array++;
3253
3254 for (i = 0; i < ir->type->length; i++) {
3255 ir->const_elements[i]->accept(this);
3256 src = this->result;
3257 for (int j = 0; j < size; j++) {
3258 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3259
3260 src.index++;
3261 temp.index++;
3262 }
3263 }
3264 this->result = temp_base;
3265 in_array--;
3266 return;
3267 }
3268
3269 if (ir->type->is_matrix()) {
3270 st_src_reg mat = get_temp(ir->type);
3271 st_dst_reg mat_column = st_dst_reg(mat);
3272
3273 for (i = 0; i < ir->type->matrix_columns; i++) {
3274 switch (ir->type->base_type) {
3275 case GLSL_TYPE_FLOAT:
3276 values = (gl_constant_value *)
3277 &ir->value.f[i * ir->type->vector_elements];
3278
3279 src = st_src_reg(file, -1, ir->type->base_type);
3280 src.index = add_constant(file,
3281 values,
3282 ir->type->vector_elements,
3283 GL_FLOAT,
3284 &src.swizzle);
3285 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3286 break;
3287 case GLSL_TYPE_DOUBLE:
3288 values = (gl_constant_value *)
3289 &ir->value.d[i * ir->type->vector_elements];
3290 src = st_src_reg(file, -1, ir->type->base_type);
3291 src.index = add_constant(file,
3292 values,
3293 ir->type->vector_elements,
3294 GL_DOUBLE,
3295 &src.swizzle);
3296 if (ir->type->vector_elements >= 2) {
3297 mat_column.writemask = WRITEMASK_XY;
3298 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3299 SWIZZLE_X, SWIZZLE_Y);
3300 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3301 } else {
3302 mat_column.writemask = WRITEMASK_X;
3303 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3304 SWIZZLE_X, SWIZZLE_X);
3305 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3306 }
3307 src.index++;
3308 if (ir->type->vector_elements > 2) {
3309 if (ir->type->vector_elements == 4) {
3310 mat_column.writemask = WRITEMASK_ZW;
3311 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3312 SWIZZLE_X, SWIZZLE_Y);
3313 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3314 } else {
3315 mat_column.writemask = WRITEMASK_Z;
3316 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3317 SWIZZLE_Y, SWIZZLE_Y);
3318 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3319 mat_column.writemask = WRITEMASK_XYZW;
3320 src.swizzle = SWIZZLE_XYZW;
3321 }
3322 mat_column.index++;
3323 }
3324 break;
3325 default:
3326 unreachable("Illegal matrix constant type.\n");
3327 break;
3328 }
3329 mat_column.index++;
3330 }
3331 this->result = mat;
3332 return;
3333 }
3334
3335 elements = ir->type->vector_elements;
3336 switch (ir->type->base_type) {
3337 case GLSL_TYPE_FLOAT:
3338 gl_type = GL_FLOAT;
3339 for (i = 0; i < ir->type->vector_elements; i++) {
3340 values[i].f = ir->value.f[i];
3341 }
3342 break;
3343 case GLSL_TYPE_DOUBLE:
3344 gl_type = GL_DOUBLE;
3345 for (i = 0; i < ir->type->vector_elements; i++) {
3346 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3347 }
3348 break;
3349 case GLSL_TYPE_INT64:
3350 gl_type = GL_INT64_ARB;
3351 for (i = 0; i < ir->type->vector_elements; i++) {
3352 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3353 }
3354 break;
3355 case GLSL_TYPE_UINT64:
3356 gl_type = GL_UNSIGNED_INT64_ARB;
3357 for (i = 0; i < ir->type->vector_elements; i++) {
3358 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3359 }
3360 break;
3361 case GLSL_TYPE_UINT:
3362 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3363 for (i = 0; i < ir->type->vector_elements; i++) {
3364 if (native_integers)
3365 values[i].u = ir->value.u[i];
3366 else
3367 values[i].f = ir->value.u[i];
3368 }
3369 break;
3370 case GLSL_TYPE_INT:
3371 gl_type = native_integers ? GL_INT : GL_FLOAT;
3372 for (i = 0; i < ir->type->vector_elements; i++) {
3373 if (native_integers)
3374 values[i].i = ir->value.i[i];
3375 else
3376 values[i].f = ir->value.i[i];
3377 }
3378 break;
3379 case GLSL_TYPE_BOOL:
3380 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3381 for (i = 0; i < ir->type->vector_elements; i++) {
3382 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3383 }
3384 break;
3385 case GLSL_TYPE_SAMPLER:
3386 case GLSL_TYPE_IMAGE:
3387 gl_type = GL_UNSIGNED_INT;
3388 elements = 2;
3389 values[0].u = ir->value.u64[0] & 0xffffffff;
3390 values[1].u = ir->value.u64[0] >> 32;
3391 break;
3392 default:
3393 assert(!"Non-float/uint/int/bool/sampler/image constant");
3394 }
3395
3396 this->result = st_src_reg(file, -1, ir->type);
3397 this->result.index = add_constant(file,
3398 values,
3399 elements,
3400 gl_type,
3401 &this->result.swizzle);
3402 }
3403
3404 void
3405 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3406 {
3407 exec_node *param = ir->actual_parameters.get_head();
3408 ir_dereference *deref = static_cast<ir_dereference *>(param);
3409 ir_variable *location = deref->variable_referenced();
3410 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3411 /* Calculate the surface offset */
3412 st_src_reg offset;
3413 unsigned array_size = 0, base = 0;
3414 uint16_t index = 0;
3415 st_src_reg resource;
3416
3417 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3418
3419 if (has_hw_atomics) {
3420 variable_storage *entry = find_variable_storage(location);
3421 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3422 location->data.binding);
3423
3424 if (!entry) {
3425 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3426 num_atomics);
3427 _mesa_hash_table_insert(this->variables, location, entry);
3428
3429 atomic_info[num_atomics].location = location->data.location;
3430 atomic_info[num_atomics].binding = location->data.binding;
3431 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3432 if (atomic_info[num_atomics].size == 0)
3433 atomic_info[num_atomics].size = 1;
3434 atomic_info[num_atomics].array_id = 0;
3435 num_atomics++;
3436 }
3437
3438 if (offset.file != PROGRAM_UNDEFINED) {
3439 if (atomic_info[entry->index].array_id == 0) {
3440 num_atomic_arrays++;
3441 atomic_info[entry->index].array_id = num_atomic_arrays;
3442 }
3443 buffer.array_id = atomic_info[entry->index].array_id;
3444 }
3445
3446 buffer.index = index;
3447 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3448 buffer.has_index2 = true;
3449
3450 if (offset.file != PROGRAM_UNDEFINED) {
3451 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3452 *buffer.reladdr = offset;
3453 emit_arl(ir, sampler_reladdr, offset);
3454 }
3455 offset = st_src_reg_for_int(0);
3456
3457 resource = buffer;
3458 } else {
3459 st_src_reg buffer(PROGRAM_BUFFER,
3460 prog->info.num_ssbos +
3461 location->data.binding,
3462 GLSL_TYPE_ATOMIC_UINT);
3463
3464 if (offset.file != PROGRAM_UNDEFINED) {
3465 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3466 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3467 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3468 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3469 } else {
3470 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3471 }
3472 resource = buffer;
3473 }
3474
3475 ir->return_deref->accept(this);
3476 st_dst_reg dst(this->result);
3477 dst.writemask = WRITEMASK_X;
3478
3479 glsl_to_tgsi_instruction *inst;
3480
3481 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3482 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3483 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3484 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3485 st_src_reg_for_int(1));
3486 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3487 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3488 st_src_reg_for_int(-1));
3489 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3490 } else {
3491 param = param->get_next();
3492 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3493 val->accept(this);
3494
3495 st_src_reg data = this->result, data2 = undef_src;
3496 enum tgsi_opcode opcode;
3497 switch (ir->callee->intrinsic_id) {
3498 case ir_intrinsic_atomic_counter_add:
3499 opcode = TGSI_OPCODE_ATOMUADD;
3500 break;
3501 case ir_intrinsic_atomic_counter_min:
3502 opcode = TGSI_OPCODE_ATOMIMIN;
3503 break;
3504 case ir_intrinsic_atomic_counter_max:
3505 opcode = TGSI_OPCODE_ATOMIMAX;
3506 break;
3507 case ir_intrinsic_atomic_counter_and:
3508 opcode = TGSI_OPCODE_ATOMAND;
3509 break;
3510 case ir_intrinsic_atomic_counter_or:
3511 opcode = TGSI_OPCODE_ATOMOR;
3512 break;
3513 case ir_intrinsic_atomic_counter_xor:
3514 opcode = TGSI_OPCODE_ATOMXOR;
3515 break;
3516 case ir_intrinsic_atomic_counter_exchange:
3517 opcode = TGSI_OPCODE_ATOMXCHG;
3518 break;
3519 case ir_intrinsic_atomic_counter_comp_swap: {
3520 opcode = TGSI_OPCODE_ATOMCAS;
3521 param = param->get_next();
3522 val = ((ir_instruction *)param)->as_rvalue();
3523 val->accept(this);
3524 data2 = this->result;
3525 break;
3526 }
3527 default:
3528 assert(!"Unexpected intrinsic");
3529 return;
3530 }
3531
3532 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3533 }
3534
3535 inst->resource = resource;
3536 }
3537
3538 void
3539 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3540 {
3541 exec_node *param = ir->actual_parameters.get_head();
3542
3543 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3544
3545 param = param->get_next();
3546 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3547
3548 ir_constant *const_block = block->as_constant();
3549 st_src_reg buffer(
3550 PROGRAM_BUFFER,
3551 const_block ? const_block->value.u[0] : 0,
3552 GLSL_TYPE_UINT);
3553
3554 if (!const_block) {
3555 block->accept(this);
3556 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3557 *buffer.reladdr = this->result;
3558 emit_arl(ir, sampler_reladdr, this->result);
3559 }
3560
3561 /* Calculate the surface offset */
3562 offset->accept(this);
3563 st_src_reg off = this->result;
3564
3565 st_dst_reg dst = undef_dst;
3566 if (ir->return_deref) {
3567 ir->return_deref->accept(this);
3568 dst = st_dst_reg(this->result);
3569 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3570 }
3571
3572 glsl_to_tgsi_instruction *inst;
3573
3574 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3575 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3576 if (dst.type == GLSL_TYPE_BOOL)
3577 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3578 st_src_reg_for_int(0));
3579 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3580 param = param->get_next();
3581 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3582 val->accept(this);
3583
3584 param = param->get_next();
3585 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3586 assert(write_mask);
3587 dst.writemask = write_mask->value.u[0];
3588
3589 dst.type = this->result.type;
3590 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3591 } else {
3592 param = param->get_next();
3593 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3594 val->accept(this);
3595
3596 st_src_reg data = this->result, data2 = undef_src;
3597 enum tgsi_opcode opcode;
3598 switch (ir->callee->intrinsic_id) {
3599 case ir_intrinsic_ssbo_atomic_add:
3600 opcode = TGSI_OPCODE_ATOMUADD;
3601 break;
3602 case ir_intrinsic_ssbo_atomic_min:
3603 opcode = TGSI_OPCODE_ATOMIMIN;
3604 break;
3605 case ir_intrinsic_ssbo_atomic_max:
3606 opcode = TGSI_OPCODE_ATOMIMAX;
3607 break;
3608 case ir_intrinsic_ssbo_atomic_and:
3609 opcode = TGSI_OPCODE_ATOMAND;
3610 break;
3611 case ir_intrinsic_ssbo_atomic_or:
3612 opcode = TGSI_OPCODE_ATOMOR;
3613 break;
3614 case ir_intrinsic_ssbo_atomic_xor:
3615 opcode = TGSI_OPCODE_ATOMXOR;
3616 break;
3617 case ir_intrinsic_ssbo_atomic_exchange:
3618 opcode = TGSI_OPCODE_ATOMXCHG;
3619 break;
3620 case ir_intrinsic_ssbo_atomic_comp_swap:
3621 opcode = TGSI_OPCODE_ATOMCAS;
3622 param = param->get_next();
3623 val = ((ir_instruction *)param)->as_rvalue();
3624 val->accept(this);
3625 data2 = this->result;
3626 break;
3627 default:
3628 assert(!"Unexpected intrinsic");
3629 return;
3630 }
3631
3632 inst = emit_asm(ir, opcode, dst, off, data, data2);
3633 }
3634
3635 param = param->get_next();
3636 ir_constant *access = NULL;
3637 if (!param->is_tail_sentinel()) {
3638 access = ((ir_instruction *)param)->as_constant();
3639 assert(access);
3640 }
3641
3642 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3643 }
3644
3645 void
3646 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3647 {
3648 switch (ir->callee->intrinsic_id) {
3649 case ir_intrinsic_memory_barrier:
3650 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3651 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3652 TGSI_MEMBAR_ATOMIC_BUFFER |
3653 TGSI_MEMBAR_SHADER_IMAGE |
3654 TGSI_MEMBAR_SHARED));
3655 break;
3656 case ir_intrinsic_memory_barrier_atomic_counter:
3657 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3658 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3659 break;
3660 case ir_intrinsic_memory_barrier_buffer:
3661 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3662 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3663 break;
3664 case ir_intrinsic_memory_barrier_image:
3665 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3666 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3667 break;
3668 case ir_intrinsic_memory_barrier_shared:
3669 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3670 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3671 break;
3672 case ir_intrinsic_group_memory_barrier:
3673 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3674 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3675 TGSI_MEMBAR_ATOMIC_BUFFER |
3676 TGSI_MEMBAR_SHADER_IMAGE |
3677 TGSI_MEMBAR_SHARED |
3678 TGSI_MEMBAR_THREAD_GROUP));
3679 break;
3680 default:
3681 assert(!"Unexpected memory barrier intrinsic");
3682 }
3683 }
3684
3685 void
3686 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3687 {
3688 exec_node *param = ir->actual_parameters.get_head();
3689
3690 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3691
3692 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3693
3694 /* Calculate the surface offset */
3695 offset->accept(this);
3696 st_src_reg off = this->result;
3697
3698 st_dst_reg dst = undef_dst;
3699 if (ir->return_deref) {
3700 ir->return_deref->accept(this);
3701 dst = st_dst_reg(this->result);
3702 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3703 }
3704
3705 glsl_to_tgsi_instruction *inst;
3706
3707 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3708 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3709 inst->resource = buffer;
3710 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3711 param = param->get_next();
3712 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3713 val->accept(this);
3714
3715 param = param->get_next();
3716 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3717 assert(write_mask);
3718 dst.writemask = write_mask->value.u[0];
3719
3720 dst.type = this->result.type;
3721 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3722 inst->resource = buffer;
3723 } else {
3724 param = param->get_next();
3725 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3726 val->accept(this);
3727
3728 st_src_reg data = this->result, data2 = undef_src;
3729 enum tgsi_opcode opcode;
3730 switch (ir->callee->intrinsic_id) {
3731 case ir_intrinsic_shared_atomic_add:
3732 opcode = TGSI_OPCODE_ATOMUADD;
3733 break;
3734 case ir_intrinsic_shared_atomic_min:
3735 opcode = TGSI_OPCODE_ATOMIMIN;
3736 break;
3737 case ir_intrinsic_shared_atomic_max:
3738 opcode = TGSI_OPCODE_ATOMIMAX;
3739 break;
3740 case ir_intrinsic_shared_atomic_and:
3741 opcode = TGSI_OPCODE_ATOMAND;
3742 break;
3743 case ir_intrinsic_shared_atomic_or:
3744 opcode = TGSI_OPCODE_ATOMOR;
3745 break;
3746 case ir_intrinsic_shared_atomic_xor:
3747 opcode = TGSI_OPCODE_ATOMXOR;
3748 break;
3749 case ir_intrinsic_shared_atomic_exchange:
3750 opcode = TGSI_OPCODE_ATOMXCHG;
3751 break;
3752 case ir_intrinsic_shared_atomic_comp_swap:
3753 opcode = TGSI_OPCODE_ATOMCAS;
3754 param = param->get_next();
3755 val = ((ir_instruction *)param)->as_rvalue();
3756 val->accept(this);
3757 data2 = this->result;
3758 break;
3759 default:
3760 assert(!"Unexpected intrinsic");
3761 return;
3762 }
3763
3764 inst = emit_asm(ir, opcode, dst, off, data, data2);
3765 inst->resource = buffer;
3766 }
3767 }
3768
3769 static void
3770 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3771 bool *memory_coherent, bool *memory_volatile,
3772 bool *memory_restrict, bool *memory_read_only,
3773 enum pipe_format *image_format)
3774 {
3775
3776 switch (ir->ir_type) {
3777 case ir_type_dereference_record: {
3778 ir_dereference_record *deref_record = ir->as_dereference_record();
3779 const glsl_type *struct_type = deref_record->record->type;
3780 int fild_idx = deref_record->field_idx;
3781
3782 *type = struct_type->fields.structure[fild_idx].type->without_array();
3783 *memory_coherent =
3784 struct_type->fields.structure[fild_idx].memory_coherent;
3785 *memory_volatile =
3786 struct_type->fields.structure[fild_idx].memory_volatile;
3787 *memory_restrict =
3788 struct_type->fields.structure[fild_idx].memory_restrict;
3789 *memory_read_only =
3790 struct_type->fields.structure[fild_idx].memory_read_only;
3791 *image_format =
3792 struct_type->fields.structure[fild_idx].image_format;
3793 break;
3794 }
3795
3796 case ir_type_dereference_array: {
3797 ir_dereference_array *deref_arr = ir->as_dereference_array();
3798 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3799 memory_coherent, memory_volatile, memory_restrict,
3800 memory_read_only, image_format);
3801 break;
3802 }
3803
3804 case ir_type_dereference_variable: {
3805 ir_variable *var = ir->variable_referenced();
3806
3807 *type = var->type->without_array();
3808 *memory_coherent = var->data.memory_coherent;
3809 *memory_volatile = var->data.memory_volatile;
3810 *memory_restrict = var->data.memory_restrict;
3811 *memory_read_only = var->data.memory_read_only;
3812 *image_format = var->data.image_format;
3813 break;
3814 }
3815
3816 default:
3817 break;
3818 }
3819 }
3820
3821 void
3822 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3823 {
3824 exec_node *param = ir->actual_parameters.get_head();
3825
3826 ir_dereference *img = (ir_dereference *)param;
3827 const ir_variable *imgvar = img->variable_referenced();
3828 unsigned sampler_array_size = 1, sampler_base = 0;
3829 bool memory_coherent = false, memory_volatile = false,
3830 memory_restrict = false, memory_read_only = false;
3831 enum pipe_format image_format = PIPE_FORMAT_NONE;
3832 const glsl_type *type = NULL;
3833
3834 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3835 &memory_restrict, &memory_read_only, &image_format);
3836
3837 st_src_reg reladdr;
3838 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3839 uint16_t index = 0;
3840 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3841 &index, &reladdr, !imgvar->contains_bindless());
3842
3843 image.index = index;
3844 if (reladdr.file != PROGRAM_UNDEFINED) {
3845 image.reladdr = ralloc(mem_ctx, st_src_reg);
3846 *image.reladdr = reladdr;
3847 emit_arl(ir, sampler_reladdr, reladdr);
3848 }
3849
3850 st_dst_reg dst = undef_dst;
3851 if (ir->return_deref) {
3852 ir->return_deref->accept(this);
3853 dst = st_dst_reg(this->result);
3854 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3855 }
3856
3857 glsl_to_tgsi_instruction *inst;
3858
3859 st_src_reg bindless;
3860 if (imgvar->contains_bindless()) {
3861 img->accept(this);
3862 bindless = this->result;
3863 }
3864
3865 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3866 dst.writemask = WRITEMASK_XYZ;
3867 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3868 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3869 st_src_reg res = get_temp(glsl_type::ivec4_type);
3870 st_dst_reg dstres = st_dst_reg(res);
3871 dstres.writemask = WRITEMASK_W;
3872 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3873 res.swizzle = SWIZZLE_WWWW;
3874 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3875 } else {
3876 st_src_reg arg1 = undef_src, arg2 = undef_src;
3877 st_src_reg coord;
3878 st_dst_reg coord_dst;
3879 coord = get_temp(glsl_type::ivec4_type);
3880 coord_dst = st_dst_reg(coord);
3881 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3882 param = param->get_next();
3883 ((ir_dereference *)param)->accept(this);
3884 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3885 coord.swizzle = SWIZZLE_XXXX;
3886 switch (type->coordinate_components()) {
3887 case 4: assert(!"unexpected coord count");
3888 /* fallthrough */
3889 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3890 /* fallthrough */
3891 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3892 }
3893
3894 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3895 param = param->get_next();
3896 ((ir_dereference *)param)->accept(this);
3897 st_src_reg sample = this->result;
3898 sample.swizzle = SWIZZLE_XXXX;
3899 coord_dst.writemask = WRITEMASK_W;
3900 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3901 coord.swizzle |= SWIZZLE_W << 9;
3902 }
3903
3904 param = param->get_next();
3905 if (!param->is_tail_sentinel()) {
3906 ((ir_dereference *)param)->accept(this);
3907 arg1 = this->result;
3908 param = param->get_next();
3909 }
3910
3911 if (!param->is_tail_sentinel()) {
3912 ((ir_dereference *)param)->accept(this);
3913 arg2 = this->result;
3914 param = param->get_next();
3915 }
3916
3917 assert(param->is_tail_sentinel());
3918
3919 enum tgsi_opcode opcode;
3920 switch (ir->callee->intrinsic_id) {
3921 case ir_intrinsic_image_load:
3922 opcode = TGSI_OPCODE_LOAD;
3923 break;
3924 case ir_intrinsic_image_store:
3925 opcode = TGSI_OPCODE_STORE;
3926 break;
3927 case ir_intrinsic_image_atomic_add:
3928 opcode = TGSI_OPCODE_ATOMUADD;
3929 break;
3930 case ir_intrinsic_image_atomic_min:
3931 opcode = TGSI_OPCODE_ATOMIMIN;
3932 break;
3933 case ir_intrinsic_image_atomic_max:
3934 opcode = TGSI_OPCODE_ATOMIMAX;
3935 break;
3936 case ir_intrinsic_image_atomic_and:
3937 opcode = TGSI_OPCODE_ATOMAND;
3938 break;
3939 case ir_intrinsic_image_atomic_or:
3940 opcode = TGSI_OPCODE_ATOMOR;
3941 break;
3942 case ir_intrinsic_image_atomic_xor:
3943 opcode = TGSI_OPCODE_ATOMXOR;
3944 break;
3945 case ir_intrinsic_image_atomic_exchange:
3946 opcode = TGSI_OPCODE_ATOMXCHG;
3947 break;
3948 case ir_intrinsic_image_atomic_comp_swap:
3949 opcode = TGSI_OPCODE_ATOMCAS;
3950 break;
3951 case ir_intrinsic_image_atomic_inc_wrap: {
3952 /* There's a bit of disagreement between GLSL and the hardware. The
3953 * hardware wants to wrap after the given wrap value, while GLSL
3954 * wants to wrap at the value. Subtract 1 to make up the difference.
3955 */
3956 st_src_reg wrap = get_temp(glsl_type::uint_type);
3957 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(wrap),
3958 arg1, st_src_reg_for_int(-1));
3959 arg1 = wrap;
3960 opcode = TGSI_OPCODE_ATOMINC_WRAP;
3961 break;
3962 }
3963 case ir_intrinsic_image_atomic_dec_wrap:
3964 opcode = TGSI_OPCODE_ATOMDEC_WRAP;
3965 break;
3966 default:
3967 assert(!"Unexpected intrinsic");
3968 return;
3969 }
3970
3971 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3972 if (opcode == TGSI_OPCODE_STORE)
3973 inst->dst[0].writemask = WRITEMASK_XYZW;
3974 }
3975
3976 if (imgvar->contains_bindless()) {
3977 inst->resource = bindless;
3978 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3979 SWIZZLE_X, SWIZZLE_Y);
3980 } else {
3981 inst->resource = image;
3982 inst->sampler_array_size = sampler_array_size;
3983 inst->sampler_base = sampler_base;
3984 }
3985
3986 inst->tex_target = type->sampler_index();
3987 inst->image_format = image_format;
3988 inst->read_only = memory_read_only;
3989
3990 if (memory_coherent)
3991 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3992 if (memory_restrict)
3993 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3994 if (memory_volatile)
3995 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3996 }
3997
3998 void
3999 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
4000 {
4001 ir->return_deref->accept(this);
4002 st_dst_reg dst = st_dst_reg(this->result);
4003
4004 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
4005
4006 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
4007 unsigned num_src = 0;
4008 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
4009 assert(num_src < ARRAY_SIZE(src));
4010
4011 this->result.file = PROGRAM_UNDEFINED;
4012 param->accept(this);
4013 assert(this->result.file != PROGRAM_UNDEFINED);
4014
4015 src[num_src] = this->result;
4016 num_src++;
4017 }
4018
4019 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
4020 }
4021
4022 void
4023 glsl_to_tgsi_visitor::visit(ir_call *ir)
4024 {
4025 ir_function_signature *sig = ir->callee;
4026
4027 /* Filter out intrinsics */
4028 switch (sig->intrinsic_id) {
4029 case ir_intrinsic_atomic_counter_read:
4030 case ir_intrinsic_atomic_counter_increment:
4031 case ir_intrinsic_atomic_counter_predecrement:
4032 case ir_intrinsic_atomic_counter_add:
4033 case ir_intrinsic_atomic_counter_min:
4034 case ir_intrinsic_atomic_counter_max:
4035 case ir_intrinsic_atomic_counter_and:
4036 case ir_intrinsic_atomic_counter_or:
4037 case ir_intrinsic_atomic_counter_xor:
4038 case ir_intrinsic_atomic_counter_exchange:
4039 case ir_intrinsic_atomic_counter_comp_swap:
4040 visit_atomic_counter_intrinsic(ir);
4041 return;
4042
4043 case ir_intrinsic_ssbo_load:
4044 case ir_intrinsic_ssbo_store:
4045 case ir_intrinsic_ssbo_atomic_add:
4046 case ir_intrinsic_ssbo_atomic_min:
4047 case ir_intrinsic_ssbo_atomic_max:
4048 case ir_intrinsic_ssbo_atomic_and:
4049 case ir_intrinsic_ssbo_atomic_or:
4050 case ir_intrinsic_ssbo_atomic_xor:
4051 case ir_intrinsic_ssbo_atomic_exchange:
4052 case ir_intrinsic_ssbo_atomic_comp_swap:
4053 visit_ssbo_intrinsic(ir);
4054 return;
4055
4056 case ir_intrinsic_memory_barrier:
4057 case ir_intrinsic_memory_barrier_atomic_counter:
4058 case ir_intrinsic_memory_barrier_buffer:
4059 case ir_intrinsic_memory_barrier_image:
4060 case ir_intrinsic_memory_barrier_shared:
4061 case ir_intrinsic_group_memory_barrier:
4062 visit_membar_intrinsic(ir);
4063 return;
4064
4065 case ir_intrinsic_shared_load:
4066 case ir_intrinsic_shared_store:
4067 case ir_intrinsic_shared_atomic_add:
4068 case ir_intrinsic_shared_atomic_min:
4069 case ir_intrinsic_shared_atomic_max:
4070 case ir_intrinsic_shared_atomic_and:
4071 case ir_intrinsic_shared_atomic_or:
4072 case ir_intrinsic_shared_atomic_xor:
4073 case ir_intrinsic_shared_atomic_exchange:
4074 case ir_intrinsic_shared_atomic_comp_swap:
4075 visit_shared_intrinsic(ir);
4076 return;
4077
4078 case ir_intrinsic_image_load:
4079 case ir_intrinsic_image_store:
4080 case ir_intrinsic_image_atomic_add:
4081 case ir_intrinsic_image_atomic_min:
4082 case ir_intrinsic_image_atomic_max:
4083 case ir_intrinsic_image_atomic_and:
4084 case ir_intrinsic_image_atomic_or:
4085 case ir_intrinsic_image_atomic_xor:
4086 case ir_intrinsic_image_atomic_exchange:
4087 case ir_intrinsic_image_atomic_comp_swap:
4088 case ir_intrinsic_image_size:
4089 case ir_intrinsic_image_samples:
4090 case ir_intrinsic_image_atomic_inc_wrap:
4091 case ir_intrinsic_image_atomic_dec_wrap:
4092 visit_image_intrinsic(ir);
4093 return;
4094
4095 case ir_intrinsic_shader_clock:
4096 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4097 return;
4098
4099 case ir_intrinsic_vote_all:
4100 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4101 return;
4102 case ir_intrinsic_vote_any:
4103 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4104 return;
4105 case ir_intrinsic_vote_eq:
4106 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4107 return;
4108 case ir_intrinsic_ballot:
4109 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4110 return;
4111 case ir_intrinsic_read_first_invocation:
4112 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4113 return;
4114 case ir_intrinsic_read_invocation:
4115 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4116 return;
4117
4118 case ir_intrinsic_helper_invocation:
4119 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_HELPER);
4120 return;
4121
4122 case ir_intrinsic_invalid:
4123 case ir_intrinsic_generic_load:
4124 case ir_intrinsic_generic_store:
4125 case ir_intrinsic_generic_atomic_add:
4126 case ir_intrinsic_generic_atomic_and:
4127 case ir_intrinsic_generic_atomic_or:
4128 case ir_intrinsic_generic_atomic_xor:
4129 case ir_intrinsic_generic_atomic_min:
4130 case ir_intrinsic_generic_atomic_max:
4131 case ir_intrinsic_generic_atomic_exchange:
4132 case ir_intrinsic_generic_atomic_comp_swap:
4133 case ir_intrinsic_begin_invocation_interlock:
4134 case ir_intrinsic_end_invocation_interlock:
4135 unreachable("Invalid intrinsic");
4136 }
4137 }
4138
4139 void
4140 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4141 unsigned *array_elements,
4142 uint16_t *index,
4143 st_src_reg *indirect,
4144 unsigned *location)
4145 {
4146 switch (tail->ir_type) {
4147 case ir_type_dereference_record: {
4148 ir_dereference_record *deref_record = tail->as_dereference_record();
4149 const glsl_type *struct_type = deref_record->record->type;
4150 int field_index = deref_record->field_idx;
4151
4152 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4153
4154 assert(field_index >= 0);
4155 *location += struct_type->struct_location_offset(field_index);
4156 break;
4157 }
4158
4159 case ir_type_dereference_array: {
4160 ir_dereference_array *deref_arr = tail->as_dereference_array();
4161
4162 void *mem_ctx = ralloc_parent(deref_arr);
4163 ir_constant *array_index =
4164 deref_arr->array_index->constant_expression_value(mem_ctx);
4165
4166 if (!array_index) {
4167 st_src_reg temp_reg;
4168 st_dst_reg temp_dst;
4169
4170 temp_reg = get_temp(glsl_type::uint_type);
4171 temp_dst = st_dst_reg(temp_reg);
4172 temp_dst.writemask = 1;
4173
4174 deref_arr->array_index->accept(this);
4175 if (*array_elements != 1)
4176 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4177 else
4178 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4179
4180 if (indirect->file == PROGRAM_UNDEFINED)
4181 *indirect = temp_reg;
4182 else {
4183 temp_dst = st_dst_reg(*indirect);
4184 temp_dst.writemask = 1;
4185 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4186 }
4187 } else
4188 *index += array_index->value.u[0] * *array_elements;
4189
4190 *array_elements *= deref_arr->array->type->length;
4191
4192 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4193 break;
4194 }
4195 default:
4196 break;
4197 }
4198 }
4199
4200 void
4201 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4202 unsigned *array_size,
4203 unsigned *base,
4204 uint16_t *index,
4205 st_src_reg *reladdr,
4206 bool opaque)
4207 {
4208 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4209 unsigned location = 0;
4210 ir_variable *var = ir->variable_referenced();
4211
4212 reladdr->reset();
4213
4214 *base = 0;
4215 *array_size = 1;
4216
4217 assert(var);
4218 location = var->data.location;
4219 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4220
4221 /*
4222 * If we end up with no indirect then adjust the base to the index,
4223 * and set the array size to 1.
4224 */
4225 if (reladdr->file == PROGRAM_UNDEFINED) {
4226 *base = *index;
4227 *array_size = 1;
4228 }
4229
4230 if (opaque) {
4231 assert(location != 0xffffffff);
4232 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4233 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4234 }
4235 }
4236
4237 st_src_reg
4238 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4239 {
4240 if (offset.reladdr || offset.reladdr2 ||
4241 offset.has_index2 ||
4242 offset.file == PROGRAM_UNIFORM ||
4243 offset.file == PROGRAM_CONSTANT ||
4244 offset.file == PROGRAM_STATE_VAR) {
4245 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4246 st_dst_reg tmp_dst = st_dst_reg(tmp);
4247 tmp_dst.writemask = WRITEMASK_XY;
4248 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4249 return tmp;
4250 }
4251
4252 return offset;
4253 }
4254
4255 bool
4256 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4257 {
4258 ir_variable *var = ir->variable_referenced();
4259
4260 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4261 !(ir->type->is_image() || ir->type->is_sampler()))
4262 return false;
4263
4264 /* Convert from bound sampler/image to bindless handle. */
4265 bool is_image = ir->type->is_image();
4266 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4267 uint16_t index = 0;
4268 unsigned array_size = 1, base = 0;
4269 st_src_reg reladdr;
4270 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4271
4272 resource.index = index;
4273 if (reladdr.file != PROGRAM_UNDEFINED) {
4274 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4275 *resource.reladdr = reladdr;
4276 emit_arl(ir, sampler_reladdr, reladdr);
4277 }
4278
4279 this->result = get_temp(glsl_type::uvec2_type);
4280 st_dst_reg dst(this->result);
4281 dst.writemask = WRITEMASK_XY;
4282
4283 glsl_to_tgsi_instruction *inst = emit_asm(
4284 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4285
4286 inst->tex_target = ir->type->sampler_index();
4287 inst->resource = resource;
4288 inst->sampler_array_size = array_size;
4289 inst->sampler_base = base;
4290
4291 return true;
4292 }
4293
4294 void
4295 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4296 {
4297 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4298 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4299 st_src_reg levels_src, reladdr;
4300 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4301 glsl_to_tgsi_instruction *inst = NULL;
4302 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4303 const glsl_type *sampler_type = ir->sampler->type;
4304 unsigned sampler_array_size = 1, sampler_base = 0;
4305 bool is_cube_array = false;
4306 ir_variable *var = ir->sampler->variable_referenced();
4307 unsigned i;
4308
4309 /* if we are a cube array sampler or a cube shadow */
4310 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4311 is_cube_array = sampler_type->sampler_array;
4312 }
4313
4314 if (ir->coordinate) {
4315 ir->coordinate->accept(this);
4316
4317 /* Put our coords in a temp. We'll need to modify them for shadow,
4318 * projection, or LOD, so the only case we'd use it as-is is if
4319 * we're doing plain old texturing. The optimization passes on
4320 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4321 */
4322 coord = get_temp(glsl_type::vec4_type);
4323 coord_dst = st_dst_reg(coord);
4324 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4325 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4326 }
4327
4328 if (ir->projector) {
4329 ir->projector->accept(this);
4330 projector = this->result;
4331 }
4332
4333 /* Storage for our result. Ideally for an assignment we'd be using
4334 * the actual storage for the result here, instead.
4335 */
4336 result_src = get_temp(ir->type);
4337 result_dst = st_dst_reg(result_src);
4338 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4339
4340 switch (ir->op) {
4341 case ir_tex:
4342 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4343 if (ir->offset) {
4344 ir->offset->accept(this);
4345 offset[0] = this->result;
4346 }
4347 break;
4348 case ir_txb:
4349 if (is_cube_array ||
4350 (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) {
4351 opcode = TGSI_OPCODE_TXB2;
4352 }
4353 else {
4354 opcode = TGSI_OPCODE_TXB;
4355 }
4356 ir->lod_info.bias->accept(this);
4357 lod_info = this->result;
4358 if (ir->offset) {
4359 ir->offset->accept(this);
4360 offset[0] = this->result;
4361 }
4362 break;
4363 case ir_txl:
4364 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4365 opcode = TGSI_OPCODE_TEX_LZ;
4366 } else {
4367 opcode = (is_cube_array || (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4368 ir->lod_info.lod->accept(this);
4369 lod_info = this->result;
4370 }
4371 if (ir->offset) {
4372 ir->offset->accept(this);
4373 offset[0] = this->result;
4374 }
4375 break;
4376 case ir_txd:
4377 opcode = TGSI_OPCODE_TXD;
4378 ir->lod_info.grad.dPdx->accept(this);
4379 dx = this->result;
4380 ir->lod_info.grad.dPdy->accept(this);
4381 dy = this->result;
4382 if (ir->offset) {
4383 ir->offset->accept(this);
4384 offset[0] = this->result;
4385 }
4386 break;
4387 case ir_txs:
4388 opcode = TGSI_OPCODE_TXQ;
4389 ir->lod_info.lod->accept(this);
4390 lod_info = this->result;
4391 break;
4392 case ir_query_levels:
4393 opcode = TGSI_OPCODE_TXQ;
4394 lod_info = undef_src;
4395 levels_src = get_temp(ir->type);
4396 break;
4397 case ir_txf:
4398 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4399 opcode = TGSI_OPCODE_TXF_LZ;
4400 } else {
4401 opcode = TGSI_OPCODE_TXF;
4402 ir->lod_info.lod->accept(this);
4403 lod_info = this->result;
4404 }
4405 if (ir->offset) {
4406 ir->offset->accept(this);
4407 offset[0] = this->result;
4408 }
4409 break;
4410 case ir_txf_ms:
4411 opcode = TGSI_OPCODE_TXF;
4412 ir->lod_info.sample_index->accept(this);
4413 sample_index = this->result;
4414 break;
4415 case ir_tg4:
4416 opcode = TGSI_OPCODE_TG4;
4417 ir->lod_info.component->accept(this);
4418 component = this->result;
4419 if (ir->offset) {
4420 ir->offset->accept(this);
4421 if (ir->offset->type->is_array()) {
4422 const glsl_type *elt_type = ir->offset->type->fields.array;
4423 for (i = 0; i < ir->offset->type->length; i++) {
4424 offset[i] = this->result;
4425 offset[i].index += i * type_size(elt_type);
4426 offset[i].type = elt_type->base_type;
4427 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4428 offset[i] = canonicalize_gather_offset(offset[i]);
4429 }
4430 } else {
4431 offset[0] = canonicalize_gather_offset(this->result);
4432 }
4433 }
4434 break;
4435 case ir_lod:
4436 opcode = TGSI_OPCODE_LODQ;
4437 break;
4438 case ir_texture_samples:
4439 opcode = TGSI_OPCODE_TXQS;
4440 break;
4441 case ir_samples_identical:
4442 unreachable("Unexpected ir_samples_identical opcode");
4443 }
4444
4445 if (ir->projector) {
4446 if (opcode == TGSI_OPCODE_TEX) {
4447 /* Slot the projector in as the last component of the coord. */
4448 coord_dst.writemask = WRITEMASK_W;
4449 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4450 coord_dst.writemask = WRITEMASK_XYZW;
4451 opcode = TGSI_OPCODE_TXP;
4452 } else {
4453 st_src_reg coord_w = coord;
4454 coord_w.swizzle = SWIZZLE_WWWW;
4455
4456 /* For the other TEX opcodes there's no projective version
4457 * since the last slot is taken up by LOD info. Do the
4458 * projective divide now.
4459 */
4460 coord_dst.writemask = WRITEMASK_W;
4461 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4462
4463 /* In the case where we have to project the coordinates "by hand,"
4464 * the shadow comparator value must also be projected.
4465 */
4466 st_src_reg tmp_src = coord;
4467 if (ir->shadow_comparator) {
4468 /* Slot the shadow value in as the second to last component of the
4469 * coord.
4470 */
4471 ir->shadow_comparator->accept(this);
4472
4473 tmp_src = get_temp(glsl_type::vec4_type);
4474 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4475
4476 /* Projective division not allowed for array samplers. */
4477 assert(!sampler_type->sampler_array);
4478
4479 tmp_dst.writemask = WRITEMASK_Z;
4480 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4481
4482 tmp_dst.writemask = WRITEMASK_XY;
4483 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4484 }
4485
4486 coord_dst.writemask = WRITEMASK_XYZ;
4487 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4488
4489 coord_dst.writemask = WRITEMASK_XYZW;
4490 coord.swizzle = SWIZZLE_XYZW;
4491 }
4492 }
4493
4494 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4495 * shadow comparator was put in the correct place (and projected) by the
4496 * code, above, that handles by-hand projection.
4497 */
4498 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4499 /* Slot the shadow value in as the second to last component of the
4500 * coord.
4501 */
4502 ir->shadow_comparator->accept(this);
4503
4504 if (is_cube_array) {
4505 if (lod_info.file != PROGRAM_UNDEFINED) {
4506 // If we have both a cube array *and* a bias/lod, stick the
4507 // comparator into the .Y of the second argument.
4508 st_src_reg tmp = get_temp(glsl_type::vec2_type);
4509 cube_sc_dst = st_dst_reg(tmp);
4510 cube_sc_dst.writemask = WRITEMASK_X;
4511 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, lod_info);
4512 lod_info = tmp;
4513 cube_sc_dst.writemask = WRITEMASK_Y;
4514 } else {
4515 cube_sc = get_temp(glsl_type::float_type);
4516 cube_sc_dst = st_dst_reg(cube_sc);
4517 cube_sc_dst.writemask = WRITEMASK_X;
4518 }
4519 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4520 }
4521 else {
4522 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4523 sampler_type->sampler_array) ||
4524 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4525 coord_dst.writemask = WRITEMASK_W;
4526 } else {
4527 coord_dst.writemask = WRITEMASK_Z;
4528 }
4529 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4530 coord_dst.writemask = WRITEMASK_XYZW;
4531 }
4532 }
4533
4534 if (ir->op == ir_txf_ms) {
4535 coord_dst.writemask = WRITEMASK_W;
4536 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4537 coord_dst.writemask = WRITEMASK_XYZW;
4538 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4539 opcode == TGSI_OPCODE_TXF) {
4540 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4541 coord_dst.writemask = WRITEMASK_W;
4542 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4543 coord_dst.writemask = WRITEMASK_XYZW;
4544 }
4545
4546 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4547
4548 uint16_t index = 0;
4549 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4550 &index, &reladdr, !var->contains_bindless());
4551
4552 sampler.index = index;
4553 if (reladdr.file != PROGRAM_UNDEFINED) {
4554 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4555 *sampler.reladdr = reladdr;
4556 emit_arl(ir, sampler_reladdr, reladdr);
4557 }
4558
4559 st_src_reg bindless;
4560 if (var->contains_bindless()) {
4561 ir->sampler->accept(this);
4562 bindless = this->result;
4563 }
4564
4565 if (opcode == TGSI_OPCODE_TXD)
4566 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4567 else if (opcode == TGSI_OPCODE_TXQ) {
4568 if (ir->op == ir_query_levels) {
4569 /* the level is stored in W */
4570 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4571 result_dst.writemask = WRITEMASK_X;
4572 levels_src.swizzle = SWIZZLE_WWWW;
4573 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4574 } else
4575 inst = emit_asm(ir, opcode, result_dst, lod_info);
4576 } else if (opcode == TGSI_OPCODE_TXQS) {
4577 inst = emit_asm(ir, opcode, result_dst);
4578 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4579 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4580 } else if (opcode == TGSI_OPCODE_TEX2) {
4581 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4582 } else if (opcode == TGSI_OPCODE_TG4) {
4583 if (is_cube_array && ir->shadow_comparator) {
4584 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4585 } else {
4586 if (this->tg4_component_in_swizzle) {
4587 inst = emit_asm(ir, opcode, result_dst, coord);
4588 int idx = 0;
4589 foreach_in_list(immediate_storage, entry, &this->immediates) {
4590 if (component.index == idx) {
4591 gl_constant_value value = entry->values[component.swizzle];
4592 inst->gather_component = value.i;
4593 break;
4594 }
4595 idx++;
4596 }
4597 } else {
4598 inst = emit_asm(ir, opcode, result_dst, coord, component);
4599 }
4600 }
4601 } else
4602 inst = emit_asm(ir, opcode, result_dst, coord);
4603
4604 if (ir->shadow_comparator)
4605 inst->tex_shadow = GL_TRUE;
4606
4607 if (var->contains_bindless()) {
4608 inst->resource = bindless;
4609 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4610 SWIZZLE_X, SWIZZLE_Y);
4611 } else {
4612 inst->resource = sampler;
4613 inst->sampler_array_size = sampler_array_size;
4614 inst->sampler_base = sampler_base;
4615 }
4616
4617 if (ir->offset) {
4618 if (!inst->tex_offsets)
4619 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4620 MAX_GLSL_TEXTURE_OFFSET);
4621
4622 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4623 offset[i].file != PROGRAM_UNDEFINED; i++)
4624 inst->tex_offsets[i] = offset[i];
4625 inst->tex_offset_num_offset = i;
4626 }
4627
4628 inst->tex_target = sampler_type->sampler_index();
4629 inst->tex_type = ir->type->base_type;
4630
4631 this->result = result_src;
4632 }
4633
4634 void
4635 glsl_to_tgsi_visitor::visit(ir_return *ir)
4636 {
4637 assert(!ir->get_value());
4638
4639 emit_asm(ir, TGSI_OPCODE_RET);
4640 }
4641
4642 void
4643 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4644 {
4645 if (ir->condition) {
4646 ir->condition->accept(this);
4647 st_src_reg condition = this->result;
4648
4649 /* Convert the bool condition to a float so we can negate. */
4650 if (native_integers) {
4651 st_src_reg temp = get_temp(ir->condition->type);
4652 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4653 condition, st_src_reg_for_float(1.0));
4654 condition = temp;
4655 }
4656
4657 condition.negate = ~condition.negate;
4658 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4659 } else {
4660 /* unconditional kil */
4661 emit_asm(ir, TGSI_OPCODE_KILL);
4662 }
4663 }
4664
4665 void
4666 glsl_to_tgsi_visitor::visit(ir_demote *ir)
4667 {
4668 emit_asm(ir, TGSI_OPCODE_DEMOTE);
4669 }
4670
4671 void
4672 glsl_to_tgsi_visitor::visit(ir_if *ir)
4673 {
4674 enum tgsi_opcode if_opcode;
4675 glsl_to_tgsi_instruction *if_inst;
4676
4677 ir->condition->accept(this);
4678 assert(this->result.file != PROGRAM_UNDEFINED);
4679
4680 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4681
4682 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4683
4684 this->instructions.push_tail(if_inst);
4685
4686 visit_exec_list(&ir->then_instructions, this);
4687
4688 if (!ir->else_instructions.is_empty()) {
4689 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4690 visit_exec_list(&ir->else_instructions, this);
4691 }
4692
4693 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4694 }
4695
4696
4697 void
4698 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4699 {
4700 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4701
4702 ir->stream->accept(this);
4703 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4704 }
4705
4706 void
4707 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4708 {
4709 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4710
4711 ir->stream->accept(this);
4712 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4713 }
4714
4715 void
4716 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4717 {
4718 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4719 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4720
4721 emit_asm(ir, TGSI_OPCODE_BARRIER);
4722 }
4723
4724 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4725 {
4726 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4727
4728 result.file = PROGRAM_UNDEFINED;
4729 next_temp = 1;
4730 array_sizes = NULL;
4731 max_num_arrays = 0;
4732 next_array = 0;
4733 num_inputs = 0;
4734 num_outputs = 0;
4735 num_input_arrays = 0;
4736 num_output_arrays = 0;
4737 num_atomics = 0;
4738 num_atomic_arrays = 0;
4739 num_immediates = 0;
4740 num_address_regs = 0;
4741 samplers_used = 0;
4742 images_used = 0;
4743 indirect_addr_consts = false;
4744 wpos_transform_const = -1;
4745 native_integers = false;
4746 mem_ctx = ralloc_context(NULL);
4747 ctx = NULL;
4748 prog = NULL;
4749 precise = 0;
4750 need_uarl = false;
4751 tg4_component_in_swizzle = false;
4752 shader_program = NULL;
4753 shader = NULL;
4754 options = NULL;
4755 have_sqrt = false;
4756 have_fma = false;
4757 use_shared_memory = false;
4758 has_tex_txf_lz = false;
4759 variables = NULL;
4760 }
4761
4762 static void var_destroy(struct hash_entry *entry)
4763 {
4764 variable_storage *storage = (variable_storage *)entry->data;
4765
4766 delete storage;
4767 }
4768
4769 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4770 {
4771 _mesa_hash_table_destroy(variables, var_destroy);
4772 free(array_sizes);
4773 ralloc_free(mem_ctx);
4774 }
4775
4776 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4777 {
4778 delete v;
4779 }
4780
4781
4782 /**
4783 * Count resources used by the given gpu program (number of texture
4784 * samplers, etc).
4785 */
4786 static void
4787 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4788 {
4789 v->samplers_used = 0;
4790 v->images_used = 0;
4791 prog->info.textures_used_by_txf = 0;
4792
4793 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4794 if (inst->info->is_tex) {
4795 for (int i = 0; i < inst->sampler_array_size; i++) {
4796 unsigned idx = inst->sampler_base + i;
4797 v->samplers_used |= 1u << idx;
4798
4799 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4800 v->sampler_types[idx] = inst->tex_type;
4801 v->sampler_targets[idx] =
4802 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4803
4804 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4805 prog->info.textures_used_by_txf |= 1u << idx;
4806 }
4807 }
4808 }
4809
4810 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4811 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4812
4813 if (inst->resource.file != PROGRAM_UNDEFINED && (
4814 is_resource_instruction(inst->op) ||
4815 inst->op == TGSI_OPCODE_STORE)) {
4816 if (inst->resource.file == PROGRAM_MEMORY) {
4817 v->use_shared_memory = true;
4818 } else if (inst->resource.file == PROGRAM_IMAGE) {
4819 for (int i = 0; i < inst->sampler_array_size; i++) {
4820 unsigned idx = inst->sampler_base + i;
4821 v->images_used |= 1 << idx;
4822 v->image_targets[idx] =
4823 st_translate_texture_target(inst->tex_target, false);
4824 v->image_formats[idx] = inst->image_format;
4825 v->image_wr[idx] = !inst->read_only;
4826 }
4827 }
4828 }
4829 }
4830 prog->SamplersUsed = v->samplers_used;
4831
4832 if (v->shader_program != NULL)
4833 _mesa_update_shader_textures_used(v->shader_program, prog);
4834 }
4835
4836 /**
4837 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4838 * are read from the given src in this instruction
4839 */
4840 static int
4841 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4842 {
4843 int read_mask = 0, comp;
4844
4845 /* Now, given the src swizzle and the written channels, find which
4846 * components are actually read
4847 */
4848 for (comp = 0; comp < 4; ++comp) {
4849 const unsigned coord = GET_SWZ(src.swizzle, comp);
4850 assert(coord < 4);
4851 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4852 read_mask |= 1 << coord;
4853 }
4854
4855 return read_mask;
4856 }
4857
4858 /**
4859 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4860 * instruction is the first instruction to write to register T0. There are
4861 * several lowering passes done in GLSL IR (e.g. branches and
4862 * relative addressing) that create a large number of conditional assignments
4863 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4864 *
4865 * Here is why this conversion is safe:
4866 * CMP T0, T1 T2 T0 can be expanded to:
4867 * if (T1 < 0.0)
4868 * MOV T0, T2;
4869 * else
4870 * MOV T0, T0;
4871 *
4872 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4873 * as the original program. If (T1 < 0.0) evaluates to false, executing
4874 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4875 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4876 * because any instruction that was going to read from T0 after this was going
4877 * to read a garbage value anyway.
4878 */
4879 void
4880 glsl_to_tgsi_visitor::simplify_cmp(void)
4881 {
4882 int tempWritesSize = 0;
4883 unsigned *tempWrites = NULL;
4884 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4885
4886 memset(outputWrites, 0, sizeof(outputWrites));
4887
4888 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4889 unsigned prevWriteMask = 0;
4890
4891 /* Give up if we encounter relative addressing or flow control. */
4892 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4893 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4894 inst->info->is_branch ||
4895 inst->op == TGSI_OPCODE_CONT ||
4896 inst->op == TGSI_OPCODE_END ||
4897 inst->op == TGSI_OPCODE_RET) {
4898 break;
4899 }
4900
4901 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4902 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4903 prevWriteMask = outputWrites[inst->dst[0].index];
4904 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4905 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4906 if (inst->dst[0].index >= tempWritesSize) {
4907 const int inc = 4096;
4908
4909 tempWrites = (unsigned*)
4910 realloc(tempWrites,
4911 (tempWritesSize + inc) * sizeof(unsigned));
4912 if (!tempWrites)
4913 return;
4914
4915 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4916 tempWritesSize += inc;
4917 }
4918
4919 prevWriteMask = tempWrites[inst->dst[0].index];
4920 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4921 } else
4922 continue;
4923
4924 /* For a CMP to be considered a conditional write, the destination
4925 * register and source register two must be the same. */
4926 if (inst->op == TGSI_OPCODE_CMP
4927 && !(inst->dst[0].writemask & prevWriteMask)
4928 && inst->src[2].file == inst->dst[0].file
4929 && inst->src[2].index == inst->dst[0].index
4930 && inst->dst[0].writemask ==
4931 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4932
4933 inst->op = TGSI_OPCODE_MOV;
4934 inst->info = tgsi_get_opcode_info(inst->op);
4935 inst->src[0] = inst->src[1];
4936 }
4937 }
4938
4939 free(tempWrites);
4940 }
4941
4942 static void
4943 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4944 {
4945 if (src && src->file == PROGRAM_TEMPORARY) {
4946 int old_idx = src->index;
4947 if (renames[old_idx].valid)
4948 src->index = renames[old_idx].new_reg;
4949 }
4950 }
4951
4952 /* Replaces all references to a temporary register index with another index. */
4953 void
4954 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4955 {
4956 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4957 unsigned j;
4958 for (j = 0; j < num_inst_src_regs(inst); j++) {
4959 rename_temp_handle_src(renames, &inst->src[j]);
4960 rename_temp_handle_src(renames, inst->src[j].reladdr);
4961 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4962 }
4963
4964 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4965 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4966 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4967 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4968 }
4969
4970 rename_temp_handle_src(renames, &inst->resource);
4971 rename_temp_handle_src(renames, inst->resource.reladdr);
4972 rename_temp_handle_src(renames, inst->resource.reladdr2);
4973
4974 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4975 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4976 int old_idx = inst->dst[j].index;
4977 if (renames[old_idx].valid)
4978 inst->dst[j].index = renames[old_idx].new_reg;
4979 }
4980 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4981 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4982 }
4983 }
4984 }
4985
4986 void
4987 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4988 {
4989 int depth = 0; /* loop depth */
4990 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4991 unsigned i = 0, j;
4992
4993 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4994 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4995 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4996 if (first_writes[inst->dst[j].index] == -1)
4997 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4998 }
4999 }
5000
5001 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5002 if (depth++ == 0)
5003 loop_start = i;
5004 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5005 if (--depth == 0)
5006 loop_start = -1;
5007 }
5008 assert(depth >= 0);
5009 i++;
5010 }
5011 }
5012
5013 void
5014 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
5015 {
5016 int depth = 0; /* loop depth */
5017 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5018 unsigned i = 0, j;
5019
5020 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5021 for (j = 0; j < num_inst_src_regs(inst); j++) {
5022 if (inst->src[j].file == PROGRAM_TEMPORARY) {
5023 if (first_reads[inst->src[j].index] == -1)
5024 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
5025 }
5026 }
5027 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5028 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
5029 if (first_reads[inst->tex_offsets[j].index] == -1)
5030 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
5031 }
5032 }
5033 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5034 if (depth++ == 0)
5035 loop_start = i;
5036 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5037 if (--depth == 0)
5038 loop_start = -1;
5039 }
5040 assert(depth >= 0);
5041 i++;
5042 }
5043 }
5044
5045 void
5046 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
5047 {
5048 int depth = 0; /* loop depth */
5049 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5050 unsigned i = 0, j;
5051 int k;
5052 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5053 for (j = 0; j < num_inst_src_regs(inst); j++) {
5054 if (inst->src[j].file == PROGRAM_TEMPORARY)
5055 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
5056 }
5057 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5058 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
5059 if (first_writes[inst->dst[j].index] == -1)
5060 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5061 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
5062 }
5063 }
5064 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5065 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
5066 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
5067 }
5068 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5069 if (depth++ == 0)
5070 loop_start = i;
5071 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5072 if (--depth == 0) {
5073 loop_start = -1;
5074 for (k = 0; k < this->next_temp; k++) {
5075 if (last_reads[k] == -2) {
5076 last_reads[k] = i;
5077 }
5078 }
5079 }
5080 }
5081 assert(depth >= 0);
5082 i++;
5083 }
5084 }
5085
5086 void
5087 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
5088 {
5089 int depth = 0; /* loop depth */
5090 int i = 0, k;
5091 unsigned j;
5092
5093 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5094 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5095 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5096 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5097 }
5098
5099 if (inst->op == TGSI_OPCODE_BGNLOOP)
5100 depth++;
5101 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5102 if (--depth == 0) {
5103 for (k = 0; k < this->next_temp; k++) {
5104 if (last_writes[k] == -2) {
5105 last_writes[k] = i;
5106 }
5107 }
5108 }
5109 assert(depth >= 0);
5110 i++;
5111 }
5112 }
5113
5114 /*
5115 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5116 * channels for copy propagation and updates following instructions to
5117 * use the original versions.
5118 *
5119 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5120 * will occur. As an example, a TXP production before this pass:
5121 *
5122 * 0: MOV TEMP[1], INPUT[4].xyyy;
5123 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5124 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5125 *
5126 * and after:
5127 *
5128 * 0: MOV TEMP[1], INPUT[4].xyyy;
5129 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5130 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5131 *
5132 * which allows for dead code elimination on TEMP[1]'s writes.
5133 */
5134 void
5135 glsl_to_tgsi_visitor::copy_propagate(void)
5136 {
5137 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5138 glsl_to_tgsi_instruction *,
5139 this->next_temp * 4);
5140 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5141 int level = 0;
5142
5143 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5144 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5145 || inst->dst[0].index < this->next_temp);
5146
5147 /* First, do any copy propagation possible into the src regs. */
5148 for (int r = 0; r < 3; r++) {
5149 glsl_to_tgsi_instruction *first = NULL;
5150 bool good = true;
5151 int acp_base = inst->src[r].index * 4;
5152
5153 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5154 inst->src[r].reladdr ||
5155 inst->src[r].reladdr2)
5156 continue;
5157
5158 /* See if we can find entries in the ACP consisting of MOVs
5159 * from the same src register for all the swizzled channels
5160 * of this src register reference.
5161 */
5162 for (int i = 0; i < 4; i++) {
5163 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5164 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5165
5166 if (!copy_chan) {
5167 good = false;
5168 break;
5169 }
5170
5171 assert(acp_level[acp_base + src_chan] <= level);
5172
5173 if (!first) {
5174 first = copy_chan;
5175 } else {
5176 if (first->src[0].file != copy_chan->src[0].file ||
5177 first->src[0].index != copy_chan->src[0].index ||
5178 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5179 first->src[0].index2D != copy_chan->src[0].index2D) {
5180 good = false;
5181 break;
5182 }
5183 }
5184 }
5185
5186 if (good) {
5187 /* We've now validated that we can copy-propagate to
5188 * replace this src register reference. Do it.
5189 */
5190 inst->src[r].file = first->src[0].file;
5191 inst->src[r].index = first->src[0].index;
5192 inst->src[r].index2D = first->src[0].index2D;
5193 inst->src[r].has_index2 = first->src[0].has_index2;
5194 inst->src[r].double_reg2 = first->src[0].double_reg2;
5195 inst->src[r].array_id = first->src[0].array_id;
5196
5197 int swizzle = 0;
5198 for (int i = 0; i < 4; i++) {
5199 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5200 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5201 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5202 }
5203 inst->src[r].swizzle = swizzle;
5204 }
5205 }
5206
5207 switch (inst->op) {
5208 case TGSI_OPCODE_BGNLOOP:
5209 case TGSI_OPCODE_ENDLOOP:
5210 /* End of a basic block, clear the ACP entirely. */
5211 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5212 break;
5213
5214 case TGSI_OPCODE_IF:
5215 case TGSI_OPCODE_UIF:
5216 ++level;
5217 break;
5218
5219 case TGSI_OPCODE_ENDIF:
5220 case TGSI_OPCODE_ELSE:
5221 /* Clear all channels written inside the block from the ACP, but
5222 * leaving those that were not touched.
5223 */
5224 for (int r = 0; r < this->next_temp; r++) {
5225 for (int c = 0; c < 4; c++) {
5226 if (!acp[4 * r + c])
5227 continue;
5228
5229 if (acp_level[4 * r + c] >= level)
5230 acp[4 * r + c] = NULL;
5231 }
5232 }
5233 if (inst->op == TGSI_OPCODE_ENDIF)
5234 --level;
5235 break;
5236
5237 default:
5238 /* Continuing the block, clear any written channels from
5239 * the ACP.
5240 */
5241 for (int d = 0; d < 2; d++) {
5242 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5243 /* Any temporary might be written, so no copy propagation
5244 * across this instruction.
5245 */
5246 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5247 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5248 inst->dst[d].reladdr) {
5249 /* Any output might be written, so no copy propagation
5250 * from outputs across this instruction.
5251 */
5252 for (int r = 0; r < this->next_temp; r++) {
5253 for (int c = 0; c < 4; c++) {
5254 if (!acp[4 * r + c])
5255 continue;
5256
5257 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5258 acp[4 * r + c] = NULL;
5259 }
5260 }
5261 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5262 inst->dst[d].file == PROGRAM_OUTPUT) {
5263 /* Clear where it's used as dst. */
5264 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5265 for (int c = 0; c < 4; c++) {
5266 if (inst->dst[d].writemask & (1 << c))
5267 acp[4 * inst->dst[d].index + c] = NULL;
5268 }
5269 }
5270
5271 /* Clear where it's used as src. */
5272 for (int r = 0; r < this->next_temp; r++) {
5273 for (int c = 0; c < 4; c++) {
5274 if (!acp[4 * r + c])
5275 continue;
5276
5277 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5278
5279 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5280 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5281 inst->dst[d].writemask & (1 << src_chan)) {
5282 acp[4 * r + c] = NULL;
5283 }
5284 }
5285 }
5286 }
5287 }
5288 break;
5289 }
5290
5291 /* If this is a copy, add it to the ACP. */
5292 if (inst->op == TGSI_OPCODE_MOV &&
5293 inst->dst[0].file == PROGRAM_TEMPORARY &&
5294 !(inst->dst[0].file == inst->src[0].file &&
5295 inst->dst[0].index == inst->src[0].index) &&
5296 !inst->dst[0].reladdr &&
5297 !inst->dst[0].reladdr2 &&
5298 !inst->saturate &&
5299 inst->src[0].file != PROGRAM_ARRAY &&
5300 (inst->src[0].file != PROGRAM_OUTPUT ||
5301 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5302 !inst->src[0].reladdr &&
5303 !inst->src[0].reladdr2 &&
5304 !inst->src[0].negate &&
5305 !inst->src[0].abs) {
5306 for (int i = 0; i < 4; i++) {
5307 if (inst->dst[0].writemask & (1 << i)) {
5308 acp[4 * inst->dst[0].index + i] = inst;
5309 acp_level[4 * inst->dst[0].index + i] = level;
5310 }
5311 }
5312 }
5313 }
5314
5315 ralloc_free(acp_level);
5316 ralloc_free(acp);
5317 }
5318
5319 static void
5320 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5321 {
5322 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5323 /* Clear where it's used as src. */
5324 int swz = GET_SWZ(reladdr->swizzle, 0);
5325 writes[4 * reladdr->index + swz] = NULL;
5326 }
5327 }
5328
5329 /*
5330 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5331 * code elimination.
5332 *
5333 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5334 * will occur. As an example, a TXP production after copy propagation but
5335 * before this pass:
5336 *
5337 * 0: MOV TEMP[1], INPUT[4].xyyy;
5338 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5339 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5340 *
5341 * and after this pass:
5342 *
5343 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5344 */
5345 int
5346 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5347 {
5348 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5349 glsl_to_tgsi_instruction *,
5350 this->next_temp * 4);
5351 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5352 int level = 0;
5353 int removed = 0;
5354
5355 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5356 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5357 || inst->dst[0].index < this->next_temp);
5358
5359 switch (inst->op) {
5360 case TGSI_OPCODE_BGNLOOP:
5361 case TGSI_OPCODE_ENDLOOP:
5362 case TGSI_OPCODE_CONT:
5363 case TGSI_OPCODE_BRK:
5364 /* End of a basic block, clear the write array entirely.
5365 *
5366 * This keeps us from killing dead code when the writes are
5367 * on either side of a loop, even when the register isn't touched
5368 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5369 * dead code of this type, so it shouldn't make a difference as long as
5370 * the dead code elimination pass in the GLSL compiler does its job.
5371 */
5372 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5373 break;
5374
5375 case TGSI_OPCODE_ENDIF:
5376 case TGSI_OPCODE_ELSE:
5377 /* Promote the recorded level of all channels written inside the
5378 * preceding if or else block to the level above the if/else block.
5379 */
5380 for (int r = 0; r < this->next_temp; r++) {
5381 for (int c = 0; c < 4; c++) {
5382 if (!writes[4 * r + c])
5383 continue;
5384
5385 if (write_level[4 * r + c] == level)
5386 write_level[4 * r + c] = level-1;
5387 }
5388 }
5389 if (inst->op == TGSI_OPCODE_ENDIF)
5390 --level;
5391 break;
5392
5393 case TGSI_OPCODE_IF:
5394 case TGSI_OPCODE_UIF:
5395 ++level;
5396 /* fallthrough to default case to mark the condition as read */
5397 default:
5398 /* Continuing the block, clear any channels from the write array that
5399 * are read by this instruction.
5400 */
5401 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5402 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5403 /* Any temporary might be read, so no dead code elimination
5404 * across this instruction.
5405 */
5406 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5407 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5408 /* Clear where it's used as src. */
5409 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5410 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5411 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5412 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5413
5414 for (int c = 0; c < 4; c++) {
5415 if (src_chans & (1 << c))
5416 writes[4 * inst->src[i].index + c] = NULL;
5417 }
5418 }
5419 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5420 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5421 }
5422 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5423 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5424 /* Any temporary might be read, so no dead code elimination
5425 * across this instruction.
5426 */
5427 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5428 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5429 /* Clear where it's used as src. */
5430 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5431 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5432 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5433 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5434
5435 for (int c = 0; c < 4; c++) {
5436 if (src_chans & (1 << c))
5437 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5438 }
5439 }
5440 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5441 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5442 }
5443
5444 if (inst->resource.file == PROGRAM_TEMPORARY) {
5445 int src_chans;
5446
5447 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5448 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5449 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5450 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5451
5452 for (int c = 0; c < 4; c++) {
5453 if (src_chans & (1 << c))
5454 writes[4 * inst->resource.index + c] = NULL;
5455 }
5456 }
5457 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5458 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5459
5460 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5461 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5462 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5463 }
5464 break;
5465 }
5466
5467 /* If this instruction writes to a temporary, add it to the write array.
5468 * If there is already an instruction in the write array for one or more
5469 * of the channels, flag that channel write as dead.
5470 */
5471 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5472 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5473 !inst->dst[i].reladdr) {
5474 for (int c = 0; c < 4; c++) {
5475 if (inst->dst[i].writemask & (1 << c)) {
5476 if (writes[4 * inst->dst[i].index + c]) {
5477 if (write_level[4 * inst->dst[i].index + c] < level)
5478 continue;
5479 else
5480 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5481 }
5482 writes[4 * inst->dst[i].index + c] = inst;
5483 write_level[4 * inst->dst[i].index + c] = level;
5484 }
5485 }
5486 }
5487 }
5488 }
5489
5490 /* Anything still in the write array at this point is dead code. */
5491 for (int r = 0; r < this->next_temp; r++) {
5492 for (int c = 0; c < 4; c++) {
5493 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5494 if (inst)
5495 inst->dead_mask |= (1 << c);
5496 }
5497 }
5498
5499 /* Now actually remove the instructions that are completely dead and update
5500 * the writemask of other instructions with dead channels.
5501 */
5502 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5503 if (!inst->dead_mask || !inst->dst[0].writemask)
5504 continue;
5505 /* No amount of dead masks should remove memory stores */
5506 if (inst->info->is_store)
5507 continue;
5508
5509 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5510 inst->remove();
5511 delete inst;
5512 removed++;
5513 } else {
5514 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5515 if (inst->dead_mask == WRITEMASK_XY ||
5516 inst->dead_mask == WRITEMASK_ZW)
5517 inst->dst[0].writemask &= ~(inst->dead_mask);
5518 } else
5519 inst->dst[0].writemask &= ~(inst->dead_mask);
5520 }
5521 }
5522
5523 ralloc_free(write_level);
5524 ralloc_free(writes);
5525
5526 return removed;
5527 }
5528
5529 /* merge DFRACEXP instructions into one. */
5530 void
5531 glsl_to_tgsi_visitor::merge_two_dsts(void)
5532 {
5533 /* We never delete inst, but we may delete its successor. */
5534 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5535 glsl_to_tgsi_instruction *inst2;
5536 unsigned defined;
5537
5538 if (num_inst_dst_regs(inst) != 2)
5539 continue;
5540
5541 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5542 inst->dst[1].file != PROGRAM_UNDEFINED)
5543 continue;
5544
5545 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5546 inst->dst[1].file != PROGRAM_UNDEFINED);
5547
5548 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5549 defined = 1;
5550 else
5551 defined = 0;
5552
5553 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5554 while (!inst2->is_tail_sentinel()) {
5555 if (inst->op == inst2->op &&
5556 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5557 inst->src[0].file == inst2->src[0].file &&
5558 inst->src[0].index == inst2->src[0].index &&
5559 inst->src[0].type == inst2->src[0].type &&
5560 inst->src[0].swizzle == inst2->src[0].swizzle)
5561 break;
5562 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5563 }
5564
5565 if (inst2->is_tail_sentinel()) {
5566 /* Undefined destinations are not allowed, substitute with an unused
5567 * temporary register.
5568 */
5569 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5570 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5571 inst->dst[defined ^ 1].writemask = 0;
5572 continue;
5573 }
5574
5575 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5576 inst2->remove();
5577 delete inst2;
5578 }
5579 }
5580
5581 template <typename st_reg>
5582 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5583 {
5584 if (reg.file == PROGRAM_ARRAY) {
5585 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5586 has_indirect_access[reg.array_id] = true;
5587 if (reg.reladdr)
5588 test_indirect_access(*reg.reladdr, has_indirect_access);
5589 if (reg.reladdr2)
5590 test_indirect_access(*reg.reladdr2, has_indirect_access);
5591 }
5592 }
5593 }
5594
5595 template <typename st_reg>
5596 void remap_array(st_reg& reg, const int *array_remap_info,
5597 const bool *has_indirect_access)
5598 {
5599 if (reg.file == PROGRAM_ARRAY) {
5600 if (!has_indirect_access[reg.array_id]) {
5601 reg.file = PROGRAM_TEMPORARY;
5602 reg.index = reg.index + array_remap_info[reg.array_id];
5603 reg.array_id = 0;
5604 } else {
5605 reg.array_id = array_remap_info[reg.array_id];
5606 }
5607
5608 if (reg.reladdr)
5609 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5610
5611 if (reg.reladdr2)
5612 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5613 }
5614 }
5615
5616 /* One-dimensional arrays whose elements are only accessed directly are
5617 * replaced by an according set of temporary registers that then can become
5618 * subject to further optimization steps like copy propagation and
5619 * register merging.
5620 */
5621 void
5622 glsl_to_tgsi_visitor::split_arrays(void)
5623 {
5624 if (!next_array)
5625 return;
5626
5627 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5628
5629 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5630 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5631 test_indirect_access(inst->src[j], has_indirect_access);
5632
5633 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5634 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5635
5636 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5637 test_indirect_access(inst->dst[j], has_indirect_access);
5638
5639 test_indirect_access(inst->resource, has_indirect_access);
5640 }
5641
5642 unsigned array_offset = 0;
5643 unsigned n_remaining_arrays = 0;
5644
5645 /* Double use: For arrays that get split this value will contain
5646 * the base index of the temporary registers this array is replaced
5647 * with. For arrays that remain it contains the new array ID.
5648 */
5649 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5650 next_array + 1);
5651
5652 for (unsigned i = 1; i <= next_array; ++i) {
5653 if (!has_indirect_access[i]) {
5654 array_remap_info[i] = this->next_temp + array_offset;
5655 array_offset += array_sizes[i - 1];
5656 } else {
5657 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5658 array_remap_info[i] = ++n_remaining_arrays;
5659 }
5660 }
5661
5662 if (next_array != n_remaining_arrays) {
5663 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5664 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5665 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5666
5667 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5668 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5669
5670 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5671 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5672 }
5673 remap_array(inst->resource, array_remap_info, has_indirect_access);
5674 }
5675 }
5676
5677 ralloc_free(has_indirect_access);
5678 this->next_temp += array_offset;
5679 next_array = n_remaining_arrays;
5680 }
5681
5682 /* Merges temporary registers together where possible to reduce the number of
5683 * registers needed to run a program.
5684 *
5685 * Produces optimal code only after copy propagation and dead code elimination
5686 * have been run. */
5687 void
5688 glsl_to_tgsi_visitor::merge_registers(void)
5689 {
5690 class array_live_range *arr_live_ranges = NULL;
5691
5692 struct register_live_range *reg_live_ranges =
5693 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5694
5695 if (this->next_array > 0) {
5696 arr_live_ranges = new array_live_range[this->next_array];
5697 for (unsigned i = 0; i < this->next_array; ++i)
5698 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5699 }
5700
5701
5702 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5703 this->next_temp, reg_live_ranges,
5704 this->next_array, arr_live_ranges)) {
5705 struct rename_reg_pair *renames =
5706 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5707 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5708 reg_live_ranges, renames);
5709 rename_temp_registers(renames);
5710
5711 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5712 &this->instructions, arr_live_ranges);
5713 }
5714
5715 if (arr_live_ranges)
5716 delete[] arr_live_ranges;
5717
5718 ralloc_free(reg_live_ranges);
5719 }
5720
5721 /* Reassign indices to temporary registers by reusing unused indices created
5722 * by optimization passes. */
5723 void
5724 glsl_to_tgsi_visitor::renumber_registers(void)
5725 {
5726 int i = 0;
5727 int new_index = 0;
5728 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5729 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5730
5731 for (i = 0; i < this->next_temp; i++) {
5732 first_writes[i] = -1;
5733 }
5734 get_first_temp_write(first_writes);
5735
5736 for (i = 0; i < this->next_temp; i++) {
5737 if (first_writes[i] < 0) continue;
5738 if (i != new_index) {
5739 renames[i].new_reg = new_index;
5740 renames[i].valid = true;
5741 }
5742 new_index++;
5743 }
5744
5745 rename_temp_registers(renames);
5746 this->next_temp = new_index;
5747 ralloc_free(renames);
5748 ralloc_free(first_writes);
5749 }
5750
5751 #ifndef NDEBUG
5752 void glsl_to_tgsi_visitor::print_stats()
5753 {
5754 int narray_registers = 0;
5755 for (unsigned i = 0; i < this->next_array; ++i)
5756 narray_registers += this->array_sizes[i];
5757
5758 int ninstructions = 0;
5759 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5760 ++ninstructions;
5761 }
5762
5763 simple_mtx_lock(&print_stats_mutex);
5764 stats_log << next_array << ", "
5765 << next_temp << ", "
5766 << narray_registers << ", "
5767 << next_temp + narray_registers << ", "
5768 << ninstructions << "\n";
5769 simple_mtx_unlock(&print_stats_mutex);
5770 }
5771 #endif
5772 /* ------------------------- TGSI conversion stuff -------------------------- */
5773
5774 /**
5775 * Intermediate state used during shader translation.
5776 */
5777 struct st_translate {
5778 struct ureg_program *ureg;
5779
5780 unsigned temps_size;
5781 struct ureg_dst *temps;
5782
5783 struct ureg_dst *arrays;
5784 unsigned num_temp_arrays;
5785 struct ureg_src *constants;
5786 int num_constants;
5787 struct ureg_src *immediates;
5788 int num_immediates;
5789 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5790 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5791 struct ureg_dst address[3];
5792 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5793 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5794 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5795 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5796 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5797 struct ureg_src shared_memory;
5798 unsigned *array_sizes;
5799 struct inout_decl *input_decls;
5800 unsigned num_input_decls;
5801 struct inout_decl *output_decls;
5802 unsigned num_output_decls;
5803
5804 const ubyte *inputMapping;
5805 const ubyte *outputMapping;
5806
5807 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5808 bool need_uarl;
5809 bool tg4_component_in_swizzle;
5810 };
5811
5812 /**
5813 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5814 */
5815 static struct ureg_src
5816 emit_immediate(struct st_translate *t,
5817 gl_constant_value values[4],
5818 GLenum type, int size)
5819 {
5820 struct ureg_program *ureg = t->ureg;
5821
5822 switch (type) {
5823 case GL_FLOAT:
5824 return ureg_DECL_immediate(ureg, &values[0].f, size);
5825 case GL_DOUBLE:
5826 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5827 case GL_INT64_ARB:
5828 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5829 case GL_UNSIGNED_INT64_ARB:
5830 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5831 case GL_INT:
5832 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5833 case GL_UNSIGNED_INT:
5834 case GL_BOOL:
5835 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5836 default:
5837 assert(!"should not get here - type must be float, int, uint, or bool");
5838 return ureg_src_undef();
5839 }
5840 }
5841
5842 /**
5843 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5844 */
5845 static struct ureg_dst
5846 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5847 unsigned array_id)
5848 {
5849 unsigned array;
5850
5851 switch (file) {
5852 case PROGRAM_UNDEFINED:
5853 return ureg_dst_undef();
5854
5855 case PROGRAM_TEMPORARY:
5856 /* Allocate space for temporaries on demand. */
5857 if (index >= t->temps_size) {
5858 const int inc = align(index - t->temps_size + 1, 4096);
5859
5860 t->temps = (struct ureg_dst*)
5861 realloc(t->temps,
5862 (t->temps_size + inc) * sizeof(struct ureg_dst));
5863 if (!t->temps)
5864 return ureg_dst_undef();
5865
5866 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5867 t->temps_size += inc;
5868 }
5869
5870 if (ureg_dst_is_undef(t->temps[index]))
5871 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5872
5873 return t->temps[index];
5874
5875 case PROGRAM_ARRAY:
5876 assert(array_id && array_id <= t->num_temp_arrays);
5877 array = array_id - 1;
5878
5879 if (ureg_dst_is_undef(t->arrays[array]))
5880 t->arrays[array] = ureg_DECL_array_temporary(
5881 t->ureg, t->array_sizes[array], TRUE);
5882
5883 return ureg_dst_array_offset(t->arrays[array], index);
5884
5885 case PROGRAM_OUTPUT:
5886 if (!array_id) {
5887 if (t->procType == PIPE_SHADER_FRAGMENT)
5888 assert(index < 2 * FRAG_RESULT_MAX);
5889 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5890 t->procType == PIPE_SHADER_TESS_EVAL)
5891 assert(index < VARYING_SLOT_TESS_MAX);
5892 else
5893 assert(index < VARYING_SLOT_MAX);
5894
5895 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5896 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5897 return t->outputs[t->outputMapping[index]];
5898 }
5899 else {
5900 struct inout_decl *decl =
5901 find_inout_array(t->output_decls,
5902 t->num_output_decls, array_id);
5903 unsigned mesa_index = decl->mesa_index;
5904 int slot = t->outputMapping[mesa_index];
5905
5906 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5907
5908 struct ureg_dst dst = t->outputs[slot];
5909 dst.ArrayID = array_id;
5910 return ureg_dst_array_offset(dst, index - mesa_index);
5911 }
5912
5913 case PROGRAM_ADDRESS:
5914 return t->address[index];
5915
5916 default:
5917 assert(!"unknown dst register file");
5918 return ureg_dst_undef();
5919 }
5920 }
5921
5922 static struct ureg_src
5923 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5924
5925 static struct ureg_src
5926 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5927 unsigned addr_index)
5928 {
5929 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5930 return ureg_src(t->address[addr_index]);
5931
5932 return translate_src(t, reladdr);
5933 }
5934
5935 /**
5936 * Create a TGSI ureg_dst register from an st_dst_reg.
5937 */
5938 static struct ureg_dst
5939 translate_dst(struct st_translate *t,
5940 const st_dst_reg *dst_reg,
5941 bool saturate)
5942 {
5943 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5944 dst_reg->array_id);
5945
5946 if (dst.File == TGSI_FILE_NULL)
5947 return dst;
5948
5949 dst = ureg_writemask(dst, dst_reg->writemask);
5950
5951 if (saturate)
5952 dst = ureg_saturate(dst);
5953
5954 if (dst_reg->reladdr != NULL) {
5955 assert(dst_reg->file != PROGRAM_TEMPORARY);
5956 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5957 }
5958
5959 if (dst_reg->has_index2) {
5960 if (dst_reg->reladdr2)
5961 dst = ureg_dst_dimension_indirect(dst,
5962 translate_addr(t, dst_reg->reladdr2, 1),
5963 dst_reg->index2D);
5964 else
5965 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5966 }
5967
5968 return dst;
5969 }
5970
5971 /**
5972 * Create a TGSI ureg_src register from an st_src_reg.
5973 */
5974 static struct ureg_src
5975 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5976 {
5977 struct ureg_src src;
5978 int index = src_reg->index;
5979 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5980
5981 switch (src_reg->file) {
5982 case PROGRAM_UNDEFINED:
5983 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5984 break;
5985
5986 case PROGRAM_TEMPORARY:
5987 case PROGRAM_ARRAY:
5988 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5989 src_reg->array_id));
5990 break;
5991
5992 case PROGRAM_OUTPUT: {
5993 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5994 src_reg->array_id);
5995 assert(dst.WriteMask != 0);
5996 unsigned shift = ffs(dst.WriteMask) - 1;
5997 src = ureg_swizzle(ureg_src(dst),
5998 shift,
5999 MIN2(shift + 1, 3),
6000 MIN2(shift + 2, 3),
6001 MIN2(shift + 3, 3));
6002 break;
6003 }
6004
6005 case PROGRAM_UNIFORM:
6006 assert(src_reg->index >= 0);
6007 src = src_reg->index < t->num_constants ?
6008 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6009 break;
6010 case PROGRAM_STATE_VAR:
6011 case PROGRAM_CONSTANT: /* ie, immediate */
6012 if (src_reg->has_index2)
6013 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6014 else
6015 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6016 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6017 break;
6018
6019 case PROGRAM_IMMEDIATE:
6020 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6021 src = t->immediates[src_reg->index];
6022 break;
6023
6024 case PROGRAM_INPUT:
6025 /* GLSL inputs are 64-bit containers, so we have to
6026 * map back to the original index and add the offset after
6027 * mapping. */
6028 index -= double_reg2;
6029 if (!src_reg->array_id) {
6030 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6031 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6032 src = t->inputs[t->inputMapping[index] + double_reg2];
6033 }
6034 else {
6035 struct inout_decl *decl = find_inout_array(t->input_decls,
6036 t->num_input_decls,
6037 src_reg->array_id);
6038 unsigned mesa_index = decl->mesa_index;
6039 int slot = t->inputMapping[mesa_index];
6040
6041 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6042
6043 src = t->inputs[slot];
6044 src.ArrayID = src_reg->array_id;
6045 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6046 }
6047 break;
6048
6049 case PROGRAM_ADDRESS:
6050 src = ureg_src(t->address[src_reg->index]);
6051 break;
6052
6053 case PROGRAM_SYSTEM_VALUE:
6054 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6055 src = t->systemValues[src_reg->index];
6056 break;
6057
6058 case PROGRAM_HW_ATOMIC:
6059 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6060 src_reg->array_id);
6061 break;
6062
6063 default:
6064 assert(!"unknown src register file");
6065 return ureg_src_undef();
6066 }
6067
6068 if (src_reg->has_index2) {
6069 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6070 * and UBO constant buffers (buffer, position).
6071 */
6072 if (src_reg->reladdr2)
6073 src = ureg_src_dimension_indirect(src,
6074 translate_addr(t, src_reg->reladdr2, 1),
6075 src_reg->index2D);
6076 else
6077 src = ureg_src_dimension(src, src_reg->index2D);
6078 }
6079
6080 src = ureg_swizzle(src,
6081 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6082 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6083 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6084 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6085
6086 if (src_reg->abs)
6087 src = ureg_abs(src);
6088
6089 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6090 src = ureg_negate(src);
6091
6092 if (src_reg->reladdr != NULL) {
6093 assert(src_reg->file != PROGRAM_TEMPORARY);
6094 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6095 }
6096
6097 return src;
6098 }
6099
6100 static struct tgsi_texture_offset
6101 translate_tex_offset(struct st_translate *t,
6102 const st_src_reg *in_offset)
6103 {
6104 struct tgsi_texture_offset offset;
6105 struct ureg_src src = translate_src(t, in_offset);
6106
6107 offset.File = src.File;
6108 offset.Index = src.Index;
6109 offset.SwizzleX = src.SwizzleX;
6110 offset.SwizzleY = src.SwizzleY;
6111 offset.SwizzleZ = src.SwizzleZ;
6112 offset.Padding = 0;
6113
6114 assert(!src.Indirect);
6115 assert(!src.DimIndirect);
6116 assert(!src.Dimension);
6117 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6118 assert(!src.Negate);
6119
6120 return offset;
6121 }
6122
6123 static void
6124 compile_tgsi_instruction(struct st_translate *t,
6125 const glsl_to_tgsi_instruction *inst)
6126 {
6127 struct ureg_program *ureg = t->ureg;
6128 int i;
6129 struct ureg_dst dst[2];
6130 struct ureg_src src[4];
6131 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6132
6133 int num_dst;
6134 int num_src;
6135 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6136
6137 num_dst = num_inst_dst_regs(inst);
6138 num_src = num_inst_src_regs(inst);
6139
6140 for (i = 0; i < num_dst; i++)
6141 dst[i] = translate_dst(t,
6142 &inst->dst[i],
6143 inst->saturate);
6144
6145 for (i = 0; i < num_src; i++)
6146 src[i] = translate_src(t, &inst->src[i]);
6147
6148 switch (inst->op) {
6149 case TGSI_OPCODE_BGNLOOP:
6150 case TGSI_OPCODE_ELSE:
6151 case TGSI_OPCODE_ENDLOOP:
6152 case TGSI_OPCODE_IF:
6153 case TGSI_OPCODE_UIF:
6154 assert(num_dst == 0);
6155 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6156 return;
6157
6158 case TGSI_OPCODE_TEX:
6159 case TGSI_OPCODE_TEX_LZ:
6160 case TGSI_OPCODE_TXB:
6161 case TGSI_OPCODE_TXD:
6162 case TGSI_OPCODE_TXL:
6163 case TGSI_OPCODE_TXP:
6164 case TGSI_OPCODE_TXQ:
6165 case TGSI_OPCODE_TXQS:
6166 case TGSI_OPCODE_TXF:
6167 case TGSI_OPCODE_TXF_LZ:
6168 case TGSI_OPCODE_TEX2:
6169 case TGSI_OPCODE_TXB2:
6170 case TGSI_OPCODE_TXL2:
6171 case TGSI_OPCODE_TG4:
6172 case TGSI_OPCODE_LODQ:
6173 case TGSI_OPCODE_SAMP2HND:
6174 if (inst->resource.file == PROGRAM_SAMPLER) {
6175 src[num_src] = t->samplers[inst->resource.index];
6176 if (t->tg4_component_in_swizzle && inst->op == TGSI_OPCODE_TG4)
6177 src[num_src].SwizzleX = inst->gather_component;
6178 } else {
6179 /* Bindless samplers. */
6180 src[num_src] = translate_src(t, &inst->resource);
6181 }
6182 assert(src[num_src].File != TGSI_FILE_NULL);
6183 if (inst->resource.reladdr)
6184 src[num_src] =
6185 ureg_src_indirect(src[num_src],
6186 translate_addr(t, inst->resource.reladdr, 2));
6187 num_src++;
6188 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6189 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6190 }
6191 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6192
6193 ureg_tex_insn(ureg,
6194 inst->op,
6195 dst, num_dst,
6196 tex_target,
6197 st_translate_texture_type(inst->tex_type),
6198 texoffsets, inst->tex_offset_num_offset,
6199 src, num_src);
6200 return;
6201
6202 case TGSI_OPCODE_RESQ:
6203 case TGSI_OPCODE_LOAD:
6204 case TGSI_OPCODE_ATOMUADD:
6205 case TGSI_OPCODE_ATOMXCHG:
6206 case TGSI_OPCODE_ATOMCAS:
6207 case TGSI_OPCODE_ATOMAND:
6208 case TGSI_OPCODE_ATOMOR:
6209 case TGSI_OPCODE_ATOMXOR:
6210 case TGSI_OPCODE_ATOMUMIN:
6211 case TGSI_OPCODE_ATOMUMAX:
6212 case TGSI_OPCODE_ATOMIMIN:
6213 case TGSI_OPCODE_ATOMIMAX:
6214 case TGSI_OPCODE_ATOMFADD:
6215 case TGSI_OPCODE_IMG2HND:
6216 case TGSI_OPCODE_ATOMINC_WRAP:
6217 case TGSI_OPCODE_ATOMDEC_WRAP:
6218 for (i = num_src - 1; i >= 0; i--)
6219 src[i + 1] = src[i];
6220 num_src++;
6221 if (inst->resource.file == PROGRAM_MEMORY) {
6222 src[0] = t->shared_memory;
6223 } else if (inst->resource.file == PROGRAM_BUFFER) {
6224 src[0] = t->buffers[inst->resource.index];
6225 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6226 src[0] = translate_src(t, &inst->resource);
6227 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6228 assert(inst->resource.has_index2);
6229 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6230 } else {
6231 assert(inst->resource.file != PROGRAM_UNDEFINED);
6232 if (inst->resource.file == PROGRAM_IMAGE) {
6233 src[0] = t->images[inst->resource.index];
6234 } else {
6235 /* Bindless images. */
6236 src[0] = translate_src(t, &inst->resource);
6237 }
6238 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6239 }
6240 if (inst->resource.reladdr)
6241 src[0] = ureg_src_indirect(src[0],
6242 translate_addr(t, inst->resource.reladdr, 2));
6243 assert(src[0].File != TGSI_FILE_NULL);
6244 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6245 inst->buffer_access,
6246 tex_target, inst->image_format);
6247 break;
6248
6249 case TGSI_OPCODE_STORE:
6250 if (inst->resource.file == PROGRAM_MEMORY) {
6251 dst[0] = ureg_dst(t->shared_memory);
6252 } else if (inst->resource.file == PROGRAM_BUFFER) {
6253 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6254 } else {
6255 if (inst->resource.file == PROGRAM_IMAGE) {
6256 dst[0] = ureg_dst(t->images[inst->resource.index]);
6257 } else {
6258 /* Bindless images. */
6259 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6260 }
6261 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6262 }
6263 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6264 if (inst->resource.reladdr)
6265 dst[0] = ureg_dst_indirect(dst[0],
6266 translate_addr(t, inst->resource.reladdr, 2));
6267 assert(dst[0].File != TGSI_FILE_NULL);
6268 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6269 inst->buffer_access,
6270 tex_target, inst->image_format);
6271 break;
6272
6273 default:
6274 ureg_insn(ureg,
6275 inst->op,
6276 dst, num_dst,
6277 src, num_src, inst->precise);
6278 break;
6279 }
6280 }
6281
6282 /* Invert SamplePos.y when rendering to the default framebuffer. */
6283 static void
6284 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6285 {
6286 struct ureg_program *ureg = t->ureg;
6287
6288 assert(wpos_y_transform >= 0);
6289 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6290 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6291 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6292 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6293
6294 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6295 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6296
6297 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6298 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6299 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6300 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6301 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6302 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6303 samplepos_sysval);
6304
6305 /* Use the result in place of the system value. */
6306 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6307 }
6308
6309
6310 /**
6311 * Emit the TGSI instructions for inverting and adjusting WPOS.
6312 * This code is unavoidable because it also depends on whether
6313 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6314 */
6315 static void
6316 emit_wpos_adjustment(struct gl_context *ctx,
6317 struct st_translate *t,
6318 int wpos_transform_const,
6319 boolean invert,
6320 GLfloat adjX, GLfloat adjY[2])
6321 {
6322 struct ureg_program *ureg = t->ureg;
6323
6324 assert(wpos_transform_const >= 0);
6325
6326 /* Fragment program uses fragment position input.
6327 * Need to replace instances of INPUT[WPOS] with temp T
6328 * where T = INPUT[WPOS] is inverted by Y.
6329 */
6330 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6331 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6332 struct ureg_src *wpos =
6333 ctx->Const.GLSLFragCoordIsSysVal ?
6334 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6335 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6336 struct ureg_src wpos_input = *wpos;
6337
6338 /* First, apply the coordinate shift: */
6339 if (adjX || adjY[0] || adjY[1]) {
6340 if (adjY[0] != adjY[1]) {
6341 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6342 * depending on whether inversion is actually going to be applied
6343 * or not, which is determined by testing against the inversion
6344 * state variable used below, which will be either +1 or -1.
6345 */
6346 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6347
6348 ureg_CMP(ureg, adj_temp,
6349 ureg_scalar(wpostrans, invert ? 2 : 0),
6350 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6351 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6352 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6353 } else {
6354 ureg_ADD(ureg, wpos_temp, wpos_input,
6355 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6356 }
6357 wpos_input = ureg_src(wpos_temp);
6358 } else {
6359 /* MOV wpos_temp, input[wpos]
6360 */
6361 ureg_MOV(ureg, wpos_temp, wpos_input);
6362 }
6363
6364 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6365 * inversion/identity, or the other way around if we're drawing to an FBO.
6366 */
6367 if (invert) {
6368 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6369 */
6370 ureg_MAD(ureg,
6371 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6372 wpos_input,
6373 ureg_scalar(wpostrans, 0),
6374 ureg_scalar(wpostrans, 1));
6375 } else {
6376 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6377 */
6378 ureg_MAD(ureg,
6379 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6380 wpos_input,
6381 ureg_scalar(wpostrans, 2),
6382 ureg_scalar(wpostrans, 3));
6383 }
6384
6385 /* Use wpos_temp as position input from here on:
6386 */
6387 *wpos = ureg_src(wpos_temp);
6388 }
6389
6390
6391 /**
6392 * Emit fragment position/ooordinate code.
6393 */
6394 static void
6395 emit_wpos(struct st_context *st,
6396 struct st_translate *t,
6397 const struct gl_program *program,
6398 struct ureg_program *ureg,
6399 int wpos_transform_const)
6400 {
6401 struct pipe_screen *pscreen = st->pipe->screen;
6402 GLfloat adjX = 0.0f;
6403 GLfloat adjY[2] = { 0.0f, 0.0f };
6404 boolean invert = FALSE;
6405
6406 /* Query the pixel center conventions supported by the pipe driver and set
6407 * adjX, adjY to help out if it cannot handle the requested one internally.
6408 *
6409 * The bias of the y-coordinate depends on whether y-inversion takes place
6410 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6411 * drawing to an FBO (causes additional inversion), and whether the pipe
6412 * driver origin and the requested origin differ (the latter condition is
6413 * stored in the 'invert' variable).
6414 *
6415 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6416 *
6417 * center shift only:
6418 * i -> h: +0.5
6419 * h -> i: -0.5
6420 *
6421 * inversion only:
6422 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6423 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6424 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6425 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6426 *
6427 * inversion and center shift:
6428 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6429 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6430 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6431 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6432 */
6433 if (program->info.fs.origin_upper_left) {
6434 /* Fragment shader wants origin in upper-left */
6435 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6436 /* the driver supports upper-left origin */
6437 }
6438 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6439 /* the driver supports lower-left origin, need to invert Y */
6440 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6441 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6442 invert = TRUE;
6443 }
6444 else
6445 assert(0);
6446 }
6447 else {
6448 /* Fragment shader wants origin in lower-left */
6449 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6450 /* the driver supports lower-left origin */
6451 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6452 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6453 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6454 /* the driver supports upper-left origin, need to invert Y */
6455 invert = TRUE;
6456 else
6457 assert(0);
6458 }
6459
6460 if (program->info.fs.pixel_center_integer) {
6461 /* Fragment shader wants pixel center integer */
6462 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6463 /* the driver supports pixel center integer */
6464 adjY[1] = 1.0f;
6465 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6466 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6467 }
6468 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6469 /* the driver supports pixel center half integer, need to bias X,Y */
6470 adjX = -0.5f;
6471 adjY[0] = -0.5f;
6472 adjY[1] = 0.5f;
6473 }
6474 else
6475 assert(0);
6476 }
6477 else {
6478 /* Fragment shader wants pixel center half integer */
6479 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6480 /* the driver supports pixel center half integer */
6481 }
6482 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6483 /* the driver supports pixel center integer, need to bias X,Y */
6484 adjX = adjY[0] = adjY[1] = 0.5f;
6485 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6486 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6487 }
6488 else
6489 assert(0);
6490 }
6491
6492 /* we invert after adjustment so that we avoid the MOV to temporary,
6493 * and reuse the adjustment ADD instead */
6494 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6495 }
6496
6497 /**
6498 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6499 * TGSI uses +1 for front, -1 for back.
6500 * This function converts the TGSI value to the GL value. Simply clamping/
6501 * saturating the value to [0,1] does the job.
6502 */
6503 static void
6504 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6505 {
6506 struct ureg_program *ureg = t->ureg;
6507 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6508 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6509
6510 if (ctx->Const.NativeIntegers) {
6511 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6512 }
6513 else {
6514 /* MOV_SAT face_temp, input[face] */
6515 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6516 }
6517
6518 /* Use face_temp as face input from here on: */
6519 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6520 }
6521
6522 static void
6523 emit_compute_block_size(const struct gl_program *prog,
6524 struct ureg_program *ureg) {
6525 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6526 prog->info.cs.local_size[0]);
6527 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6528 prog->info.cs.local_size[1]);
6529 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6530 prog->info.cs.local_size[2]);
6531 }
6532
6533 struct sort_inout_decls {
6534 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6535 return mapping[a.mesa_index] < mapping[b.mesa_index];
6536 }
6537
6538 const ubyte *mapping;
6539 };
6540
6541 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6542 *
6543 * This is for the benefit of older drivers which are broken when the
6544 * declarations aren't sorted in this way.
6545 */
6546 static void
6547 sort_inout_decls_by_slot(struct inout_decl *decls,
6548 unsigned count,
6549 const ubyte mapping[])
6550 {
6551 sort_inout_decls sorter;
6552 sorter.mapping = mapping;
6553 std::sort(decls, decls + count, sorter);
6554 }
6555
6556 static enum tgsi_interpolate_mode
6557 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6558 {
6559 switch (glsl_qual) {
6560 case INTERP_MODE_NONE:
6561 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6562 return TGSI_INTERPOLATE_COLOR;
6563 return TGSI_INTERPOLATE_PERSPECTIVE;
6564 case INTERP_MODE_SMOOTH:
6565 return TGSI_INTERPOLATE_PERSPECTIVE;
6566 case INTERP_MODE_FLAT:
6567 return TGSI_INTERPOLATE_CONSTANT;
6568 case INTERP_MODE_NOPERSPECTIVE:
6569 return TGSI_INTERPOLATE_LINEAR;
6570 default:
6571 assert(0 && "unexpected interp mode in st_translate_interp()");
6572 return TGSI_INTERPOLATE_PERSPECTIVE;
6573 }
6574 }
6575
6576 /**
6577 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6578 * \param program the program to translate
6579 * \param numInputs number of input registers used
6580 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6581 * input indexes
6582 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6583 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6584 * each input
6585 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6586 * \param numOutputs number of output registers used
6587 * \param outputMapping maps Mesa fragment program outputs to TGSI
6588 * generic outputs
6589 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6590 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6591 * each output
6592 *
6593 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6594 */
6595 extern "C" enum pipe_error
6596 st_translate_program(
6597 struct gl_context *ctx,
6598 enum pipe_shader_type procType,
6599 struct ureg_program *ureg,
6600 glsl_to_tgsi_visitor *program,
6601 const struct gl_program *proginfo,
6602 GLuint numInputs,
6603 const ubyte inputMapping[],
6604 const ubyte inputSlotToAttr[],
6605 const ubyte inputSemanticName[],
6606 const ubyte inputSemanticIndex[],
6607 const ubyte interpMode[],
6608 GLuint numOutputs,
6609 const ubyte outputMapping[],
6610 const ubyte outputSemanticName[],
6611 const ubyte outputSemanticIndex[])
6612 {
6613 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6614 struct st_translate *t;
6615 unsigned i;
6616 struct gl_program_constants *frag_const =
6617 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6618 enum pipe_error ret = PIPE_OK;
6619
6620 assert(numInputs <= ARRAY_SIZE(t->inputs));
6621 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6622
6623 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6624 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6625 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6626 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6627 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6628 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6629 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6630 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6631 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6632 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6633
6634 t = CALLOC_STRUCT(st_translate);
6635 if (!t) {
6636 ret = PIPE_ERROR_OUT_OF_MEMORY;
6637 goto out;
6638 }
6639
6640 t->procType = procType;
6641 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6642 t->tg4_component_in_swizzle = screen->get_param(screen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
6643 t->inputMapping = inputMapping;
6644 t->outputMapping = outputMapping;
6645 t->ureg = ureg;
6646 t->num_temp_arrays = program->next_array;
6647 if (t->num_temp_arrays)
6648 t->arrays = (struct ureg_dst*)
6649 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6650
6651 /*
6652 * Declare input attributes.
6653 */
6654 switch (procType) {
6655 case PIPE_SHADER_FRAGMENT:
6656 case PIPE_SHADER_GEOMETRY:
6657 case PIPE_SHADER_TESS_EVAL:
6658 case PIPE_SHADER_TESS_CTRL:
6659 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6660
6661 for (i = 0; i < program->num_inputs; ++i) {
6662 struct inout_decl *decl = &program->inputs[i];
6663 unsigned slot = inputMapping[decl->mesa_index];
6664 struct ureg_src src;
6665 ubyte tgsi_usage_mask = decl->usage_mask;
6666
6667 if (glsl_base_type_is_64bit(decl->base_type)) {
6668 if (tgsi_usage_mask == 1)
6669 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6670 else if (tgsi_usage_mask == 2)
6671 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6672 else
6673 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6674 }
6675
6676 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6677 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6678 if (procType == PIPE_SHADER_FRAGMENT) {
6679 assert(interpMode);
6680 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6681 (enum tgsi_interpolate_mode) interpMode[slot] :
6682 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6683
6684 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6685 }
6686
6687 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6688 (enum tgsi_semantic) inputSemanticName[slot],
6689 inputSemanticIndex[slot],
6690 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6691 decl->array_id, decl->size);
6692
6693 for (unsigned j = 0; j < decl->size; ++j) {
6694 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6695 /* The ArrayID is set up in dst_register */
6696 t->inputs[slot + j] = src;
6697 t->inputs[slot + j].ArrayID = 0;
6698 t->inputs[slot + j].Index += j;
6699 }
6700 }
6701 }
6702 break;
6703 case PIPE_SHADER_VERTEX:
6704 for (i = 0; i < numInputs; i++) {
6705 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6706 }
6707 break;
6708 case PIPE_SHADER_COMPUTE:
6709 break;
6710 default:
6711 assert(0);
6712 }
6713
6714 /*
6715 * Declare output attributes.
6716 */
6717 switch (procType) {
6718 case PIPE_SHADER_FRAGMENT:
6719 case PIPE_SHADER_COMPUTE:
6720 break;
6721 case PIPE_SHADER_GEOMETRY:
6722 case PIPE_SHADER_TESS_EVAL:
6723 case PIPE_SHADER_TESS_CTRL:
6724 case PIPE_SHADER_VERTEX:
6725 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6726
6727 for (i = 0; i < program->num_outputs; ++i) {
6728 struct inout_decl *decl = &program->outputs[i];
6729 unsigned slot = outputMapping[decl->mesa_index];
6730 struct ureg_dst dst;
6731 ubyte tgsi_usage_mask = decl->usage_mask;
6732
6733 if (glsl_base_type_is_64bit(decl->base_type)) {
6734 if (tgsi_usage_mask == 1)
6735 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6736 else if (tgsi_usage_mask == 2)
6737 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6738 else
6739 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6740 }
6741
6742 dst = ureg_DECL_output_layout(ureg,
6743 (enum tgsi_semantic) outputSemanticName[slot],
6744 outputSemanticIndex[slot],
6745 decl->gs_out_streams,
6746 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6747 dst.Invariant = decl->invariant;
6748 for (unsigned j = 0; j < decl->size; ++j) {
6749 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6750 /* The ArrayID is set up in dst_register */
6751 t->outputs[slot + j] = dst;
6752 t->outputs[slot + j].ArrayID = 0;
6753 t->outputs[slot + j].Index += j;
6754 t->outputs[slot + j].Invariant = decl->invariant;
6755 }
6756 }
6757 }
6758 break;
6759 default:
6760 assert(0);
6761 }
6762
6763 if (procType == PIPE_SHADER_FRAGMENT) {
6764 if (program->shader->Program->info.fs.early_fragment_tests ||
6765 program->shader->Program->info.fs.post_depth_coverage) {
6766 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6767
6768 if (program->shader->Program->info.fs.post_depth_coverage)
6769 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6770 }
6771
6772 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6773 /* Must do this after setting up t->inputs. */
6774 emit_wpos(st_context(ctx), t, proginfo, ureg,
6775 program->wpos_transform_const);
6776 }
6777
6778 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6779 emit_face_var(ctx, t);
6780
6781 for (i = 0; i < numOutputs; i++) {
6782 switch (outputSemanticName[i]) {
6783 case TGSI_SEMANTIC_POSITION:
6784 t->outputs[i] = ureg_DECL_output(ureg,
6785 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6786 outputSemanticIndex[i]);
6787 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6788 break;
6789 case TGSI_SEMANTIC_STENCIL:
6790 t->outputs[i] = ureg_DECL_output(ureg,
6791 TGSI_SEMANTIC_STENCIL, /* Stencil */
6792 outputSemanticIndex[i]);
6793 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6794 break;
6795 case TGSI_SEMANTIC_COLOR:
6796 t->outputs[i] = ureg_DECL_output(ureg,
6797 TGSI_SEMANTIC_COLOR,
6798 outputSemanticIndex[i]);
6799 break;
6800 case TGSI_SEMANTIC_SAMPLEMASK:
6801 t->outputs[i] = ureg_DECL_output(ureg,
6802 TGSI_SEMANTIC_SAMPLEMASK,
6803 outputSemanticIndex[i]);
6804 /* TODO: If we ever support more than 32 samples, this will have
6805 * to become an array.
6806 */
6807 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6808 break;
6809 default:
6810 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6811 ret = PIPE_ERROR_BAD_INPUT;
6812 goto out;
6813 }
6814 }
6815 }
6816 else if (procType == PIPE_SHADER_VERTEX) {
6817 for (i = 0; i < numOutputs; i++) {
6818 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6819 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6820 ureg_MOV(ureg,
6821 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6822 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6823 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6824 }
6825 }
6826 }
6827
6828 if (procType == PIPE_SHADER_COMPUTE) {
6829 emit_compute_block_size(proginfo, ureg);
6830 }
6831
6832 /* Declare address register.
6833 */
6834 if (program->num_address_regs > 0) {
6835 assert(program->num_address_regs <= 3);
6836 for (int i = 0; i < program->num_address_regs; i++)
6837 t->address[i] = ureg_DECL_address(ureg);
6838 }
6839
6840 /* Declare misc input registers
6841 */
6842 {
6843 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6844
6845 for (i = 0; sysInputs; i++) {
6846 if (sysInputs & (1ull << i)) {
6847 enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
6848
6849 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6850
6851 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6852 semName == TGSI_SEMANTIC_VERTEXID) {
6853 /* From Gallium perspective, these system values are always
6854 * integer, and require native integer support. However, if
6855 * native integer is supported on the vertex stage but not the
6856 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6857 * assumes these system values are floats. To resolve the
6858 * inconsistency, we insert a U2F.
6859 */
6860 struct st_context *st = st_context(ctx);
6861 struct pipe_screen *pscreen = st->pipe->screen;
6862 assert(procType == PIPE_SHADER_VERTEX);
6863 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6864 (void) pscreen;
6865 if (!ctx->Const.NativeIntegers) {
6866 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6867 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6868 t->systemValues[i]);
6869 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6870 }
6871 }
6872
6873 if (procType == PIPE_SHADER_FRAGMENT &&
6874 semName == TGSI_SEMANTIC_POSITION)
6875 emit_wpos(st_context(ctx), t, proginfo, ureg,
6876 program->wpos_transform_const);
6877
6878 if (procType == PIPE_SHADER_FRAGMENT &&
6879 semName == TGSI_SEMANTIC_SAMPLEPOS)
6880 emit_samplepos_adjustment(t, program->wpos_transform_const);
6881
6882 sysInputs &= ~(1ull << i);
6883 }
6884 }
6885 }
6886
6887 t->array_sizes = program->array_sizes;
6888 t->input_decls = program->inputs;
6889 t->num_input_decls = program->num_inputs;
6890 t->output_decls = program->outputs;
6891 t->num_output_decls = program->num_outputs;
6892
6893 /* Emit constants and uniforms. TGSI uses a single index space for these,
6894 * so we put all the translated regs in t->constants.
6895 */
6896 if (proginfo->Parameters) {
6897 t->constants = (struct ureg_src *)
6898 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6899 if (t->constants == NULL) {
6900 ret = PIPE_ERROR_OUT_OF_MEMORY;
6901 goto out;
6902 }
6903 t->num_constants = proginfo->Parameters->NumParameters;
6904
6905 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6906 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6907
6908 switch (proginfo->Parameters->Parameters[i].Type) {
6909 case PROGRAM_STATE_VAR:
6910 case PROGRAM_UNIFORM:
6911 t->constants[i] = ureg_DECL_constant(ureg, i);
6912 break;
6913
6914 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6915 * addressing of the const buffer.
6916 * FIXME: Be smarter and recognize param arrays:
6917 * indirect addressing is only valid within the referenced
6918 * array.
6919 */
6920 case PROGRAM_CONSTANT:
6921 if (program->indirect_addr_consts)
6922 t->constants[i] = ureg_DECL_constant(ureg, i);
6923 else
6924 t->constants[i] = emit_immediate(t,
6925 proginfo->Parameters->ParameterValues + pvo,
6926 proginfo->Parameters->Parameters[i].DataType,
6927 4);
6928 break;
6929 default:
6930 break;
6931 }
6932 }
6933 }
6934
6935 for (i = 0; i < proginfo->info.num_ubos; i++) {
6936 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6937 unsigned num_const_vecs = (size + 15) / 16;
6938 unsigned first, last;
6939 assert(num_const_vecs > 0);
6940 first = 0;
6941 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6942 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6943 }
6944
6945 /* Emit immediate values.
6946 */
6947 t->immediates = (struct ureg_src *)
6948 calloc(program->num_immediates, sizeof(struct ureg_src));
6949 if (t->immediates == NULL) {
6950 ret = PIPE_ERROR_OUT_OF_MEMORY;
6951 goto out;
6952 }
6953 t->num_immediates = program->num_immediates;
6954
6955 i = 0;
6956 foreach_in_list(immediate_storage, imm, &program->immediates) {
6957 assert(i < program->num_immediates);
6958 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6959 }
6960 assert(i == program->num_immediates);
6961
6962 /* texture samplers */
6963 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6964 if (program->samplers_used & (1u << i)) {
6965 enum tgsi_return_type type =
6966 st_translate_texture_type(program->sampler_types[i]);
6967
6968 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6969
6970 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6971 type, type, type, type);
6972 }
6973 }
6974
6975 /* Declare atomic and shader storage buffers. */
6976 {
6977 struct gl_program *prog = program->prog;
6978
6979 if (!st_context(ctx)->has_hw_atomics) {
6980 for (i = 0; i < prog->info.num_abos; i++) {
6981 unsigned index = (prog->info.num_ssbos +
6982 prog->sh.AtomicBuffers[i]->Binding);
6983 assert(prog->sh.AtomicBuffers[i]->Binding <
6984 frag_const->MaxAtomicBuffers);
6985 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6986 }
6987 } else {
6988 for (i = 0; i < program->num_atomics; i++) {
6989 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6990 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6991 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6992 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6993 ainfo->array_id);
6994 }
6995 }
6996
6997 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6998 for (i = 0; i < prog->info.num_ssbos; i++) {
6999 t->buffers[i] = ureg_DECL_buffer(ureg, i, false);
7000 }
7001 }
7002
7003 if (program->use_shared_memory)
7004 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
7005
7006 for (i = 0; i < program->shader->Program->info.num_images; i++) {
7007 if (program->images_used & (1 << i)) {
7008 t->images[i] = ureg_DECL_image(ureg, i,
7009 program->image_targets[i],
7010 program->image_formats[i],
7011 program->image_wr[i],
7012 false);
7013 }
7014 }
7015
7016 /* Emit each instruction in turn:
7017 */
7018 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
7019 compile_tgsi_instruction(t, inst);
7020
7021 /* Set the next shader stage hint for VS and TES. */
7022 switch (procType) {
7023 case PIPE_SHADER_VERTEX:
7024 case PIPE_SHADER_TESS_EVAL:
7025 if (program->shader_program->SeparateShader)
7026 break;
7027
7028 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
7029 if (program->shader_program->_LinkedShaders[i]) {
7030 ureg_set_next_shader_processor(
7031 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
7032 break;
7033 }
7034 }
7035 break;
7036 default:
7037 ; /* nothing - silence compiler warning */
7038 }
7039
7040 out:
7041 if (t) {
7042 free(t->arrays);
7043 free(t->temps);
7044 free(t->constants);
7045 t->num_constants = 0;
7046 free(t->immediates);
7047 t->num_immediates = 0;
7048 FREE(t);
7049 }
7050
7051 return ret;
7052 }
7053 /* ----------------------------- End TGSI code ------------------------------ */
7054
7055
7056 /**
7057 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7058 * generating Mesa IR.
7059 */
7060 static struct gl_program *
7061 get_mesa_program_tgsi(struct gl_context *ctx,
7062 struct gl_shader_program *shader_program,
7063 struct gl_linked_shader *shader)
7064 {
7065 glsl_to_tgsi_visitor* v;
7066 struct gl_program *prog;
7067 struct gl_shader_compiler_options *options =
7068 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7069 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7070 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7071 unsigned skip_merge_registers;
7072
7073 validate_ir_tree(shader->ir);
7074
7075 prog = shader->Program;
7076
7077 prog->Parameters = _mesa_new_parameter_list();
7078 v = new glsl_to_tgsi_visitor();
7079 v->ctx = ctx;
7080 v->prog = prog;
7081 v->shader_program = shader_program;
7082 v->shader = shader;
7083 v->options = options;
7084 v->native_integers = ctx->Const.NativeIntegers;
7085
7086 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7087 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7088 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7089 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7090 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7091 PIPE_CAP_TGSI_TEX_TXF_LZ);
7092 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7093
7094 v->tg4_component_in_swizzle = pscreen->get_param(pscreen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
7095 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7096 _mesa_key_pointer_equal);
7097 skip_merge_registers =
7098 pscreen->get_shader_param(pscreen, ptarget,
7099 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7100
7101 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7102 prog->Parameters);
7103
7104 /* Remove reads from output registers. */
7105 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7106 lower_output_reads(shader->Stage, shader->ir);
7107
7108 /* Emit intermediate IR for main(). */
7109 visit_exec_list(shader->ir, v);
7110
7111 #if 0
7112 /* Print out some information (for debugging purposes) used by the
7113 * optimization passes. */
7114 {
7115 int i;
7116 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7117 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7118 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7119 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7120
7121 for (i = 0; i < v->next_temp; i++) {
7122 first_writes[i] = -1;
7123 first_reads[i] = -1;
7124 last_writes[i] = -1;
7125 last_reads[i] = -1;
7126 }
7127 v->get_first_temp_read(first_reads);
7128 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7129 v->get_last_temp_write(last_writes);
7130 for (i = 0; i < v->next_temp; i++)
7131 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7132 first_writes[i],
7133 last_reads[i],
7134 last_writes[i]);
7135 ralloc_free(first_writes);
7136 ralloc_free(first_reads);
7137 ralloc_free(last_writes);
7138 ralloc_free(last_reads);
7139 }
7140 #endif
7141
7142 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7143 v->simplify_cmp();
7144 v->copy_propagate();
7145
7146 while (v->eliminate_dead_code());
7147
7148 v->merge_two_dsts();
7149
7150 if (!skip_merge_registers) {
7151 v->split_arrays();
7152 v->copy_propagate();
7153 while (v->eliminate_dead_code());
7154
7155 v->merge_registers();
7156 v->copy_propagate();
7157 while (v->eliminate_dead_code());
7158 }
7159
7160 v->renumber_registers();
7161
7162 /* Write the END instruction. */
7163 v->emit_asm(NULL, TGSI_OPCODE_END);
7164
7165 if (ctx->_Shader->Flags & GLSL_DUMP) {
7166 _mesa_log("\n");
7167 _mesa_log("GLSL IR for linked %s program %d:\n",
7168 _mesa_shader_stage_to_string(shader->Stage),
7169 shader_program->Name);
7170 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7171 _mesa_log("\n\n");
7172 }
7173
7174 do_set_program_inouts(shader->ir, prog, shader->Stage);
7175
7176 _mesa_copy_linked_program_data(shader_program, shader);
7177
7178 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS)) {
7179 mark_array_io(v->inputs, v->num_inputs,
7180 &prog->info.inputs_read,
7181 prog->DualSlotInputs,
7182 &prog->info.patch_inputs_read);
7183
7184 mark_array_io(v->outputs, v->num_outputs,
7185 &prog->info.outputs_written, 0ULL,
7186 &prog->info.patch_outputs_written);
7187 } else {
7188 shrink_array_declarations(v->inputs, v->num_inputs,
7189 &prog->info.inputs_read,
7190 prog->DualSlotInputs,
7191 &prog->info.patch_inputs_read);
7192 shrink_array_declarations(v->outputs, v->num_outputs,
7193 &prog->info.outputs_written, 0ULL,
7194 &prog->info.patch_outputs_written);
7195 }
7196
7197 count_resources(v, prog);
7198
7199 /* The GLSL IR won't be needed anymore. */
7200 ralloc_free(shader->ir);
7201 shader->ir = NULL;
7202
7203 /* This must be done before the uniform storage is associated. */
7204 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7205 (prog->info.inputs_read & VARYING_BIT_POS ||
7206 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
7207 prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
7208 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7209 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7210 };
7211
7212 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7213 wposTransformState);
7214 }
7215
7216 /* Avoid reallocation of the program parameter list, because the uniform
7217 * storage is only associated with the original parameter list.
7218 * This should be enough for Bitmap and DrawPixels constants.
7219 */
7220 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7221
7222 /* This has to be done last. Any operation the can cause
7223 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7224 * program constant) has to happen before creating this linkage.
7225 */
7226 _mesa_associate_uniform_storage(ctx, shader_program, prog);
7227 if (!shader_program->data->LinkStatus) {
7228 free_glsl_to_tgsi_visitor(v);
7229 _mesa_reference_program(ctx, &shader->Program, NULL);
7230 return NULL;
7231 }
7232
7233 st_program(prog)->glsl_to_tgsi = v;
7234
7235 PRINT_STATS(v->print_stats());
7236
7237 return prog;
7238 }
7239
7240 /* See if there are unsupported control flow statements. */
7241 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7242 private:
7243 const struct gl_shader_compiler_options *options;
7244 public:
7245 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7246 : options(options),
7247 unsupported(false)
7248 {
7249 }
7250
7251 virtual ir_visitor_status visit_enter(ir_function *ir)
7252 {
7253 /* Other functions are skipped (same as glsl_to_tgsi). */
7254 if (strcmp(ir->name, "main") == 0)
7255 return visit_continue;
7256
7257 return visit_continue_with_parent;
7258 }
7259
7260 virtual ir_visitor_status visit_enter(ir_call *ir)
7261 {
7262 if (!ir->callee->is_intrinsic()) {
7263 unsupported = true; /* it's a function call */
7264 return visit_stop;
7265 }
7266 return visit_continue;
7267 }
7268
7269 virtual ir_visitor_status visit_enter(ir_return *ir)
7270 {
7271 if (options->EmitNoMainReturn) {
7272 unsupported = true;
7273 return visit_stop;
7274 }
7275 return visit_continue;
7276 }
7277
7278 bool unsupported;
7279 };
7280
7281 static bool
7282 has_unsupported_control_flow(exec_list *ir,
7283 const struct gl_shader_compiler_options *options)
7284 {
7285 ir_control_flow_info_visitor visitor(options);
7286 visit_list_elements(&visitor, ir);
7287 return visitor.unsupported;
7288 }
7289
7290 /**
7291 * Link a shader.
7292 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7293 * with code lowering and other optimizations.
7294 */
7295 GLboolean
7296 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7297 {
7298 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7299
7300 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7301 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7302 if (shader == NULL)
7303 continue;
7304
7305 exec_list *ir = shader->ir;
7306 gl_shader_stage stage = shader->Stage;
7307 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7308 const struct gl_shader_compiler_options *options =
7309 &ctx->Const.ShaderCompilerOptions[stage];
7310
7311 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7312 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7313 if (ctx->Const.GLSLOptimizeConservatively) {
7314 /* Do it once and repeat only if there's unsupported control flow. */
7315 do {
7316 do_common_optimization(ir, true, true, options,
7317 ctx->Const.NativeIntegers);
7318 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7319 options->MaxIfDepth, if_threshold);
7320 } while (has_unsupported_control_flow(ir, options));
7321 } else {
7322 /* Repeat it until it stops making changes. */
7323 bool progress;
7324 do {
7325 progress = do_common_optimization(ir, true, true, options,
7326 ctx->Const.NativeIntegers);
7327 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7328 options->MaxIfDepth, if_threshold);
7329 } while (progress);
7330 }
7331
7332 /* Do this again to lower ir_binop_vector_extract introduced
7333 * by optimization passes.
7334 */
7335 do_vec_index_to_cond_assign(ir);
7336
7337 validate_ir_tree(ir);
7338
7339 struct gl_program *linked_prog =
7340 get_mesa_program_tgsi(ctx, prog, shader);
7341 st_set_prog_affected_state_flags(linked_prog);
7342
7343 if (linked_prog) {
7344 if (!ctx->Driver.ProgramStringNotify(ctx,
7345 _mesa_shader_stage_to_program(i),
7346 linked_prog)) {
7347 _mesa_reference_program(ctx, &shader->Program, NULL);
7348 return GL_FALSE;
7349 }
7350 }
7351 }
7352
7353 return GL_TRUE;
7354 }