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tgsi: add ATOMICINC_WRAP/ATOMICDEC_WRAP opcode
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
56 #include "st_glsl_to_tgsi_temprename.h"
57
58 #include "util/hash_table.h"
59 #include <algorithm>
60
61 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
62 (1 << PROGRAM_CONSTANT) | \
63 (1 << PROGRAM_UNIFORM))
64
65 #define MAX_GLSL_TEXTURE_OFFSET 4
66
67 #ifndef NDEBUG
68 #include "util/u_atomic.h"
69 #include "util/simple_mtx.h"
70 #include <fstream>
71 #include <ios>
72
73 /* Prepare to make it possible to specify log file */
74 static std::ofstream stats_log;
75
76 /* Helper function to check whether we want to write some statistics
77 * of the shader conversion.
78 */
79
80 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
81
82 static inline bool print_stats_enabled ()
83 {
84 static int stats_enabled = 0;
85
86 if (!stats_enabled) {
87 simple_mtx_lock(&print_stats_mutex);
88 if (!stats_enabled) {
89 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
90 if (stats_filename) {
91 bool write_header = std::ifstream(stats_filename).fail();
92 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
93 stats_enabled = stats_log.good() ? 1 : -1;
94 if (write_header)
95 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
96 } else {
97 stats_enabled = -1;
98 }
99 }
100 simple_mtx_unlock(&print_stats_mutex);
101 }
102 return stats_enabled > 0;
103 }
104 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
105 #else
106 #define PRINT_STATS(X)
107 #endif
108
109
110 static unsigned is_precise(const ir_variable *ir)
111 {
112 if (!ir)
113 return 0;
114 return ir->data.precise || ir->data.invariant;
115 }
116
117 class variable_storage {
118 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
119
120 public:
121 variable_storage(ir_variable *var, gl_register_file file, int index,
122 unsigned array_id = 0)
123 : file(file), index(index), component(0), var(var), array_id(array_id)
124 {
125 assert(file != PROGRAM_ARRAY || array_id != 0);
126 }
127
128 gl_register_file file;
129 int index;
130
131 /* Explicit component location. This is given in terms of the GLSL-style
132 * swizzles where each double is a single component, i.e. for 64-bit types
133 * it can only be 0 or 1.
134 */
135 int component;
136 ir_variable *var; /* variable that maps to this, if any */
137 unsigned array_id;
138 };
139
140 class immediate_storage : public exec_node {
141 public:
142 immediate_storage(gl_constant_value *values, int size32, GLenum type)
143 {
144 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
145 this->size32 = size32;
146 this->type = type;
147 }
148
149 /* doubles are stored across 2 gl_constant_values */
150 gl_constant_value values[4];
151 int size32; /**< Number of 32-bit components (1-4) */
152 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
153 };
154
155 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
156 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
157
158 struct inout_decl {
159 unsigned mesa_index;
160 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
161 unsigned size;
162 unsigned interp_loc;
163 unsigned gs_out_streams;
164 enum glsl_interp_mode interp;
165 enum glsl_base_type base_type;
166 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
167 bool invariant;
168 };
169
170 static struct inout_decl *
171 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
172 {
173 assert(array_id != 0);
174
175 for (unsigned i = 0; i < count; i++) {
176 struct inout_decl *decl = &decls[i];
177
178 if (array_id == decl->array_id) {
179 return decl;
180 }
181 }
182
183 return NULL;
184 }
185
186 static enum glsl_base_type
187 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
188 {
189 if (!array_id)
190 return GLSL_TYPE_ERROR;
191 struct inout_decl *decl = find_inout_array(decls, count, array_id);
192 if (decl)
193 return decl->base_type;
194 return GLSL_TYPE_ERROR;
195 }
196
197 struct hwatomic_decl {
198 unsigned location;
199 unsigned binding;
200 unsigned size;
201 unsigned array_id;
202 };
203
204 struct glsl_to_tgsi_visitor : public ir_visitor {
205 public:
206 glsl_to_tgsi_visitor();
207 ~glsl_to_tgsi_visitor();
208
209 struct gl_context *ctx;
210 struct gl_program *prog;
211 struct gl_shader_program *shader_program;
212 struct gl_linked_shader *shader;
213 struct gl_shader_compiler_options *options;
214
215 int next_temp;
216
217 unsigned *array_sizes;
218 unsigned max_num_arrays;
219 unsigned next_array;
220
221 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
222 unsigned num_inputs;
223 unsigned num_input_arrays;
224 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
225 unsigned num_outputs;
226 unsigned num_output_arrays;
227
228 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
229 unsigned num_atomics;
230 unsigned num_atomic_arrays;
231 int num_address_regs;
232 uint32_t samplers_used;
233 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
234 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
235 int images_used;
236 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
237 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
238 bool image_wr[PIPE_MAX_SHADER_IMAGES];
239 bool indirect_addr_consts;
240 int wpos_transform_const;
241
242 bool native_integers;
243 bool have_sqrt;
244 bool have_fma;
245 bool use_shared_memory;
246 bool has_tex_txf_lz;
247 bool precise;
248 bool need_uarl;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_texture *);
288 virtual void visit(ir_if *);
289 virtual void visit(ir_emit_vertex *);
290 virtual void visit(ir_end_primitive *);
291 virtual void visit(ir_barrier *);
292 /*@}*/
293
294 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
295
296 void visit_atomic_counter_intrinsic(ir_call *);
297 void visit_ssbo_intrinsic(ir_call *);
298 void visit_membar_intrinsic(ir_call *);
299 void visit_shared_intrinsic(ir_call *);
300 void visit_image_intrinsic(ir_call *);
301 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
302
303 st_src_reg result;
304
305 /** List of variable_storage */
306 struct hash_table *variables;
307
308 /** List of immediate_storage */
309 exec_list immediates;
310 unsigned num_immediates;
311
312 /** List of glsl_to_tgsi_instruction */
313 exec_list instructions;
314
315 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
316 st_dst_reg dst = undef_dst,
317 st_src_reg src0 = undef_src,
318 st_src_reg src1 = undef_src,
319 st_src_reg src2 = undef_src,
320 st_src_reg src3 = undef_src);
321
322 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
323 st_dst_reg dst, st_dst_reg dst1,
324 st_src_reg src0 = undef_src,
325 st_src_reg src1 = undef_src,
326 st_src_reg src2 = undef_src,
327 st_src_reg src3 = undef_src);
328
329 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
330 st_dst_reg dst,
331 st_src_reg src0, st_src_reg src1);
332
333 /**
334 * Emit the correct dot-product instruction for the type of arguments
335 */
336 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
337 st_dst_reg dst,
338 st_src_reg src0,
339 st_src_reg src1,
340 unsigned elements);
341
342 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
343 st_dst_reg dst, st_src_reg src0);
344
345 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
346 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
347
348 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
349
350 void get_deref_offsets(ir_dereference *ir,
351 unsigned *array_size,
352 unsigned *base,
353 uint16_t *index,
354 st_src_reg *reladdr,
355 bool opaque);
356 void calc_deref_offsets(ir_dereference *tail,
357 unsigned *array_elements,
358 uint16_t *index,
359 st_src_reg *indirect,
360 unsigned *location);
361 st_src_reg canonicalize_gather_offset(st_src_reg offset);
362 bool handle_bound_deref(ir_dereference *ir);
363
364 bool try_emit_mad(ir_expression *ir,
365 int mul_operand);
366 bool try_emit_mad_for_and_not(ir_expression *ir,
367 int mul_operand);
368
369 void emit_swz(ir_expression *ir);
370
371 bool process_move_condition(ir_rvalue *ir);
372
373 void simplify_cmp(void);
374
375 void rename_temp_registers(struct rename_reg_pair *renames);
376 void get_first_temp_read(int *first_reads);
377 void get_first_temp_write(int *first_writes);
378 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
379 void get_last_temp_write(int *last_writes);
380
381 void copy_propagate(void);
382 int eliminate_dead_code(void);
383
384 void split_arrays(void);
385 void merge_two_dsts(void);
386 void merge_registers(void);
387 void renumber_registers(void);
388
389 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
390 st_dst_reg *l, st_src_reg *r,
391 st_src_reg *cond, bool cond_swap);
392
393 void print_stats();
394
395 void *mem_ctx;
396 };
397
398 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
399 GLSL_TYPE_FLOAT, 0);
400 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
401 GLSL_TYPE_FLOAT, 1);
402 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
403 GLSL_TYPE_FLOAT, 2);
404
405 static void
406 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
407 PRINTFLIKE(2, 3);
408
409 static void
410 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
411 {
412 va_list args;
413 va_start(args, fmt);
414 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
415 va_end(args);
416
417 prog->data->LinkStatus = LINKING_FAILURE;
418 }
419
420 int
421 swizzle_for_size(int size)
422 {
423 static const int size_swizzles[4] = {
424 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
428 };
429
430 assert((size >= 1) && (size <= 4));
431 return size_swizzles[size - 1];
432 }
433
434
435 glsl_to_tgsi_instruction *
436 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
437 st_dst_reg dst, st_dst_reg dst1,
438 st_src_reg src0, st_src_reg src1,
439 st_src_reg src2, st_src_reg src3)
440 {
441 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
442 int num_reladdr = 0, i, j;
443 bool dst_is_64bit[2];
444
445 op = get_opcode(op, dst, src0, src1);
446
447 /* If we have to do relative addressing, we want to load the ARL
448 * reg directly for one of the regs, and preload the other reladdr
449 * sources into temps.
450 */
451 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
452 assert(!dst1.reladdr); /* should be lowered in earlier passes */
453 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
454 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
455 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
456 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
457
458 reladdr_to_temp(ir, &src3, &num_reladdr);
459 reladdr_to_temp(ir, &src2, &num_reladdr);
460 reladdr_to_temp(ir, &src1, &num_reladdr);
461 reladdr_to_temp(ir, &src0, &num_reladdr);
462
463 if (dst.reladdr || dst.reladdr2) {
464 if (dst.reladdr)
465 emit_arl(ir, address_reg, *dst.reladdr);
466 if (dst.reladdr2)
467 emit_arl(ir, address_reg2, *dst.reladdr2);
468 num_reladdr--;
469 }
470
471 assert(num_reladdr == 0);
472
473 /* inst->op has only 8 bits. */
474 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
475
476 inst->op = op;
477 inst->precise = this->precise;
478 inst->info = tgsi_get_opcode_info(op);
479 inst->dst[0] = dst;
480 inst->dst[1] = dst1;
481 inst->src[0] = src0;
482 inst->src[1] = src1;
483 inst->src[2] = src2;
484 inst->src[3] = src3;
485 inst->is_64bit_expanded = false;
486 inst->ir = ir;
487 inst->dead_mask = 0;
488 inst->tex_offsets = NULL;
489 inst->tex_offset_num_offset = 0;
490 inst->saturate = 0;
491 inst->tex_shadow = 0;
492 /* default to float, for paths where this is not initialized
493 * (since 0==UINT which is likely wrong):
494 */
495 inst->tex_type = GLSL_TYPE_FLOAT;
496
497 /* Update indirect addressing status used by TGSI */
498 if (dst.reladdr || dst.reladdr2) {
499 switch (dst.file) {
500 case PROGRAM_STATE_VAR:
501 case PROGRAM_CONSTANT:
502 case PROGRAM_UNIFORM:
503 this->indirect_addr_consts = true;
504 break;
505 case PROGRAM_IMMEDIATE:
506 assert(!"immediates should not have indirect addressing");
507 break;
508 default:
509 break;
510 }
511 }
512 else {
513 for (i = 0; i < 4; i++) {
514 if (inst->src[i].reladdr) {
515 switch (inst->src[i].file) {
516 case PROGRAM_STATE_VAR:
517 case PROGRAM_CONSTANT:
518 case PROGRAM_UNIFORM:
519 this->indirect_addr_consts = true;
520 break;
521 case PROGRAM_IMMEDIATE:
522 assert(!"immediates should not have indirect addressing");
523 break;
524 default:
525 break;
526 }
527 }
528 }
529 }
530
531 /*
532 * This section contains the double processing.
533 * GLSL just represents doubles as single channel values,
534 * however most HW and TGSI represent doubles as pairs of register channels.
535 *
536 * so we have to fixup destination writemask/index and src swizzle/indexes.
537 * dest writemasks need to translate from single channel write mask
538 * to a dual-channel writemask, but also need to modify the index,
539 * if we are touching the Z,W fields in the pre-translated writemask.
540 *
541 * src channels have similiar index modifications along with swizzle
542 * changes to we pick the XY, ZW pairs from the correct index.
543 *
544 * GLSL [0].x -> TGSI [0].xy
545 * GLSL [0].y -> TGSI [0].zw
546 * GLSL [0].z -> TGSI [1].xy
547 * GLSL [0].w -> TGSI [1].zw
548 */
549 for (j = 0; j < 2; j++) {
550 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
551 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
552 inst->dst[j].type == GLSL_TYPE_ARRAY) {
553 enum glsl_base_type type = find_array_type(this->outputs,
554 this->num_outputs,
555 inst->dst[j].array_id);
556 if (glsl_base_type_is_64bit(type))
557 dst_is_64bit[j] = true;
558 }
559 }
560
561 if (dst_is_64bit[0] || dst_is_64bit[1] ||
562 glsl_base_type_is_64bit(inst->src[0].type)) {
563 glsl_to_tgsi_instruction *dinst = NULL;
564 int initial_src_swz[4], initial_src_idx[4];
565 int initial_dst_idx[2], initial_dst_writemask[2];
566 /* select the writemask for dst0 or dst1 */
567 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
568 ? inst->dst[0].writemask : inst->dst[1].writemask;
569
570 /* copy out the writemask, index and swizzles for all src/dsts. */
571 for (j = 0; j < 2; j++) {
572 initial_dst_writemask[j] = inst->dst[j].writemask;
573 initial_dst_idx[j] = inst->dst[j].index;
574 }
575
576 for (j = 0; j < 4; j++) {
577 initial_src_swz[j] = inst->src[j].swizzle;
578 initial_src_idx[j] = inst->src[j].index;
579 }
580
581 /*
582 * scan all the components in the dst writemask
583 * generate an instruction for each of them if required.
584 */
585 st_src_reg addr;
586 while (writemask) {
587
588 int i = u_bit_scan(&writemask);
589
590 /* before emitting the instruction, see if we have to adjust
591 * load / store address */
592 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
593 inst->op == TGSI_OPCODE_STORE) &&
594 addr.file == PROGRAM_UNDEFINED) {
595 /* We have to advance the buffer address by 16 */
596 addr = get_temp(glsl_type::uint_type);
597 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
598 inst->src[0], st_src_reg_for_int(16));
599 }
600
601 /* first time use previous instruction */
602 if (dinst == NULL) {
603 dinst = inst;
604 } else {
605 /* create a new instructions for subsequent attempts */
606 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
607 *dinst = *inst;
608 dinst->next = NULL;
609 dinst->prev = NULL;
610 }
611 this->instructions.push_tail(dinst);
612 dinst->is_64bit_expanded = true;
613
614 /* modify the destination if we are splitting */
615 for (j = 0; j < 2; j++) {
616 if (dst_is_64bit[j]) {
617 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
618 dinst->dst[j].index = initial_dst_idx[j];
619 if (i > 1) {
620 if (dinst->op == TGSI_OPCODE_LOAD ||
621 dinst->op == TGSI_OPCODE_STORE)
622 dinst->src[0] = addr;
623 if (dinst->op != TGSI_OPCODE_STORE)
624 dinst->dst[j].index++;
625 }
626 } else {
627 /* if we aren't writing to a double, just get the bit of the
628 * initial writemask for this channel
629 */
630 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
631 }
632 }
633
634 /* modify the src registers */
635 for (j = 0; j < 4; j++) {
636 int swz = GET_SWZ(initial_src_swz[j], i);
637
638 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
639 dinst->src[j].index = initial_src_idx[j];
640 if (swz > 1) {
641 dinst->src[j].double_reg2 = true;
642 dinst->src[j].index++;
643 }
644
645 if (swz & 1)
646 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
647 SWIZZLE_Z, SWIZZLE_W);
648 else
649 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
650 SWIZZLE_X, SWIZZLE_Y);
651
652 } else {
653 /* some opcodes are special case in what they use as sources
654 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
655 * integer src1
656 */
657 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
658 op == TGSI_OPCODE_I2D ||
659 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
660 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
661 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
662 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
663 }
664 }
665 }
666 }
667 inst = dinst;
668 } else {
669 this->instructions.push_tail(inst);
670 }
671
672
673 return inst;
674 }
675
676 glsl_to_tgsi_instruction *
677 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
678 st_dst_reg dst,
679 st_src_reg src0, st_src_reg src1,
680 st_src_reg src2, st_src_reg src3)
681 {
682 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
683 }
684
685 /**
686 * Determines whether to use an integer, unsigned integer, or float opcode
687 * based on the operands and input opcode, then emits the result.
688 */
689 enum tgsi_opcode
690 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
691 st_dst_reg dst,
692 st_src_reg src0, st_src_reg src1)
693 {
694 enum glsl_base_type type = GLSL_TYPE_FLOAT;
695
696 if (op == TGSI_OPCODE_MOV)
697 return op;
698
699 assert(src0.type != GLSL_TYPE_ARRAY);
700 assert(src0.type != GLSL_TYPE_STRUCT);
701 assert(src1.type != GLSL_TYPE_ARRAY);
702 assert(src1.type != GLSL_TYPE_STRUCT);
703
704 if (is_resource_instruction(op))
705 type = src1.type;
706 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
707 type = GLSL_TYPE_INT64;
708 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
709 type = GLSL_TYPE_UINT64;
710 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
711 type = GLSL_TYPE_DOUBLE;
712 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
713 type = GLSL_TYPE_FLOAT;
714 else if (native_integers)
715 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
716
717 #define case7(c, f, i, u, d, i64, ui64) \
718 case TGSI_OPCODE_##c: \
719 if (type == GLSL_TYPE_UINT64) \
720 op = TGSI_OPCODE_##ui64; \
721 else if (type == GLSL_TYPE_INT64) \
722 op = TGSI_OPCODE_##i64; \
723 else if (type == GLSL_TYPE_DOUBLE) \
724 op = TGSI_OPCODE_##d; \
725 else if (type == GLSL_TYPE_INT) \
726 op = TGSI_OPCODE_##i; \
727 else if (type == GLSL_TYPE_UINT) \
728 op = TGSI_OPCODE_##u; \
729 else \
730 op = TGSI_OPCODE_##f; \
731 break;
732
733 #define casecomp(c, f, i, u, d, i64, ui64) \
734 case TGSI_OPCODE_##c: \
735 if (type == GLSL_TYPE_INT64) \
736 op = TGSI_OPCODE_##i64; \
737 else if (type == GLSL_TYPE_UINT64) \
738 op = TGSI_OPCODE_##ui64; \
739 else if (type == GLSL_TYPE_DOUBLE) \
740 op = TGSI_OPCODE_##d; \
741 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
742 op = TGSI_OPCODE_##i; \
743 else if (type == GLSL_TYPE_UINT) \
744 op = TGSI_OPCODE_##u; \
745 else if (native_integers) \
746 op = TGSI_OPCODE_##f; \
747 else \
748 op = TGSI_OPCODE_##c; \
749 break;
750
751 switch (op) {
752 /* Some instructions are initially selected without considering the type.
753 * This fixes the type:
754 *
755 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
756 */
757 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
758 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
759 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
760 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
761 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
762 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
763 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
764 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
765 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
766 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
767 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
768 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
769 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
770 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
771 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
772 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
773
774 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
775 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
776 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
777 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
778 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
779 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
780 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
781 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
782 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
783
784 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
785 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
786 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
787 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
788
789 default:
790 break;
791 }
792
793 assert(op != TGSI_OPCODE_LAST);
794 return op;
795 }
796
797 glsl_to_tgsi_instruction *
798 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
799 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
800 unsigned elements)
801 {
802 static const enum tgsi_opcode dot_opcodes[] = {
803 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
804 };
805
806 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
807 }
808
809 /**
810 * Emits TGSI scalar opcodes to produce unique answers across channels.
811 *
812 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
813 * channel determines the result across all channels. So to do a vec4
814 * of this operation, we want to emit a scalar per source channel used
815 * to produce dest channels.
816 */
817 void
818 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
819 st_dst_reg dst,
820 st_src_reg orig_src0, st_src_reg orig_src1)
821 {
822 int i, j;
823 int done_mask = ~dst.writemask;
824
825 /* TGSI RCP is a scalar operation splatting results to all channels,
826 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
827 * dst channels.
828 */
829 for (i = 0; i < 4; i++) {
830 GLuint this_mask = (1 << i);
831 st_src_reg src0 = orig_src0;
832 st_src_reg src1 = orig_src1;
833
834 if (done_mask & this_mask)
835 continue;
836
837 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
838 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
839 for (j = i + 1; j < 4; j++) {
840 /* If there is another enabled component in the destination that is
841 * derived from the same inputs, generate its value on this pass as
842 * well.
843 */
844 if (!(done_mask & (1 << j)) &&
845 GET_SWZ(src0.swizzle, j) == src0_swiz &&
846 GET_SWZ(src1.swizzle, j) == src1_swiz) {
847 this_mask |= (1 << j);
848 }
849 }
850 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
851 src0_swiz, src0_swiz);
852 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
853 src1_swiz, src1_swiz);
854
855 dst.writemask = this_mask;
856 emit_asm(ir, op, dst, src0, src1);
857 done_mask |= this_mask;
858 }
859 }
860
861 void
862 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
863 st_dst_reg dst, st_src_reg src0)
864 {
865 st_src_reg undef = undef_src;
866
867 undef.swizzle = SWIZZLE_XXXX;
868
869 emit_scalar(ir, op, dst, src0, undef);
870 }
871
872 void
873 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
874 st_dst_reg dst, st_src_reg src0)
875 {
876 enum tgsi_opcode op = TGSI_OPCODE_ARL;
877
878 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
879 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
880 return;
881
882 op = TGSI_OPCODE_UARL;
883 }
884
885 assert(dst.file == PROGRAM_ADDRESS);
886 if (dst.index >= this->num_address_regs)
887 this->num_address_regs = dst.index + 1;
888
889 emit_asm(NULL, op, dst, src0);
890 }
891
892 int
893 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
894 gl_constant_value values[8], int size,
895 GLenum datatype,
896 uint16_t *swizzle_out)
897 {
898 if (file == PROGRAM_CONSTANT) {
899 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
900 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
901 values, size, datatype,
902 &swizzle);
903 if (swizzle_out)
904 *swizzle_out = swizzle;
905 return result;
906 }
907
908 assert(file == PROGRAM_IMMEDIATE);
909
910 int index = 0;
911 immediate_storage *entry;
912 int size32 = size * ((datatype == GL_DOUBLE ||
913 datatype == GL_INT64_ARB ||
914 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
915 int i;
916
917 /* Search immediate storage to see if we already have an identical
918 * immediate that we can use instead of adding a duplicate entry.
919 */
920 foreach_in_list(immediate_storage, entry, &this->immediates) {
921 immediate_storage *tmp = entry;
922
923 for (i = 0; i * 4 < size32; i++) {
924 int slot_size = MIN2(size32 - (i * 4), 4);
925 if (tmp->type != datatype || tmp->size32 != slot_size)
926 break;
927 if (memcmp(tmp->values, &values[i * 4],
928 slot_size * sizeof(gl_constant_value)))
929 break;
930
931 /* Everything matches, keep going until the full size is matched */
932 tmp = (immediate_storage *)tmp->next;
933 }
934
935 /* The full value matched */
936 if (i * 4 >= size32)
937 return index;
938
939 index++;
940 }
941
942 for (i = 0; i * 4 < size32; i++) {
943 int slot_size = MIN2(size32 - (i * 4), 4);
944 /* Add this immediate to the list. */
945 entry = new(mem_ctx) immediate_storage(&values[i * 4],
946 slot_size, datatype);
947 this->immediates.push_tail(entry);
948 this->num_immediates++;
949 }
950 return index;
951 }
952
953 st_src_reg
954 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
955 {
956 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
957 union gl_constant_value uval;
958
959 uval.f = val;
960 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
961
962 return src;
963 }
964
965 st_src_reg
966 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
967 {
968 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
969 union gl_constant_value uval[2];
970
971 memcpy(uval, &val, sizeof(uval));
972 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
973 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
974 return src;
975 }
976
977 st_src_reg
978 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
979 {
980 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
981 union gl_constant_value uval;
982
983 assert(native_integers);
984
985 uval.i = val;
986 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
987
988 return src;
989 }
990
991 st_src_reg
992 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
993 {
994 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
995 union gl_constant_value uval[2];
996
997 memcpy(uval, &val, sizeof(uval));
998 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
999 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1000
1001 return src;
1002 }
1003
1004 st_src_reg
1005 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1006 {
1007 if (native_integers)
1008 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1009 st_src_reg_for_int(val);
1010 else
1011 return st_src_reg_for_float(val);
1012 }
1013
1014 static int
1015 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1016 {
1017 return type->count_attribute_slots(is_vs_input);
1018 }
1019
1020 static int
1021 type_size(const struct glsl_type *type)
1022 {
1023 return type->count_attribute_slots(false);
1024 }
1025
1026 static void
1027 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1028 exec_list *instructions, ir_constant *access)
1029 {
1030 /**
1031 * emit_asm() might have actually split the op into pieces, e.g. for
1032 * double stores. We have to go back and fix up all the generated ops.
1033 */
1034 enum tgsi_opcode op = inst->op;
1035 do {
1036 inst->resource = *buf;
1037 if (access)
1038 inst->buffer_access = access->value.u[0];
1039
1040 if (inst == instructions->get_head_raw())
1041 break;
1042 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1043
1044 if (inst->op == TGSI_OPCODE_UADD) {
1045 if (inst == instructions->get_head_raw())
1046 break;
1047 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1048 }
1049 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1050 }
1051
1052 /**
1053 * If the given GLSL type is an array or matrix or a structure containing
1054 * an array/matrix member, return true. Else return false.
1055 *
1056 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1057 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1058 * we have an array that might be indexed with a variable, we need to use
1059 * the later storage type.
1060 */
1061 static bool
1062 type_has_array_or_matrix(const glsl_type *type)
1063 {
1064 if (type->is_array() || type->is_matrix())
1065 return true;
1066
1067 if (type->is_struct()) {
1068 for (unsigned i = 0; i < type->length; i++) {
1069 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1070 return true;
1071 }
1072 }
1073 }
1074
1075 return false;
1076 }
1077
1078
1079 /**
1080 * In the initial pass of codegen, we assign temporary numbers to
1081 * intermediate results. (not SSA -- variable assignments will reuse
1082 * storage).
1083 */
1084 st_src_reg
1085 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1086 {
1087 st_src_reg src;
1088
1089 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1090 src.reladdr = NULL;
1091 src.negate = 0;
1092 src.abs = 0;
1093
1094 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1095 if (next_array >= max_num_arrays) {
1096 max_num_arrays += 32;
1097 array_sizes = (unsigned*)
1098 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1099 }
1100
1101 src.file = PROGRAM_ARRAY;
1102 src.index = 0;
1103 src.array_id = next_array + 1;
1104 array_sizes[next_array] = type_size(type);
1105 ++next_array;
1106
1107 } else {
1108 src.file = PROGRAM_TEMPORARY;
1109 src.index = next_temp;
1110 next_temp += type_size(type);
1111 }
1112
1113 if (type->is_array() || type->is_struct()) {
1114 src.swizzle = SWIZZLE_NOOP;
1115 } else {
1116 src.swizzle = swizzle_for_size(type->vector_elements);
1117 }
1118
1119 return src;
1120 }
1121
1122 variable_storage *
1123 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1124 {
1125 struct hash_entry *entry;
1126
1127 entry = _mesa_hash_table_search(this->variables, var);
1128 if (!entry)
1129 return NULL;
1130
1131 return (variable_storage *)entry->data;
1132 }
1133
1134 void
1135 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1136 {
1137 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1138 unsigned int i;
1139 const ir_state_slot *const slots = ir->get_state_slots();
1140 assert(slots != NULL);
1141
1142 /* Check if this statevar's setup in the STATE file exactly
1143 * matches how we'll want to reference it as a
1144 * struct/array/whatever. If not, then we need to move it into
1145 * temporary storage and hope that it'll get copy-propagated
1146 * out.
1147 */
1148 for (i = 0; i < ir->get_num_state_slots(); i++) {
1149 if (slots[i].swizzle != SWIZZLE_XYZW) {
1150 break;
1151 }
1152 }
1153
1154 variable_storage *storage;
1155 st_dst_reg dst;
1156 if (i == ir->get_num_state_slots()) {
1157 /* We'll set the index later. */
1158 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1159
1160 _mesa_hash_table_insert(this->variables, ir, storage);
1161
1162 dst = undef_dst;
1163 } else {
1164 /* The variable_storage constructor allocates slots based on the size
1165 * of the type. However, this had better match the number of state
1166 * elements that we're going to copy into the new temporary.
1167 */
1168 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1169
1170 dst = st_dst_reg(get_temp(ir->type));
1171
1172 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1173 dst.array_id);
1174
1175 _mesa_hash_table_insert(this->variables, ir, storage);
1176 }
1177
1178
1179 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1180 int index = _mesa_add_state_reference(this->prog->Parameters,
1181 slots[i].tokens);
1182
1183 if (storage->file == PROGRAM_STATE_VAR) {
1184 if (storage->index == -1) {
1185 storage->index = index;
1186 } else {
1187 assert(index == storage->index + (int)i);
1188 }
1189 } else {
1190 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1191 * the data being moved since MOV does not care about the type of
1192 * data it is moving, and we don't want to declare registers with
1193 * array or struct types.
1194 */
1195 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1196 src.swizzle = slots[i].swizzle;
1197 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1198 /* even a float takes up a whole vec4 reg in a struct/array. */
1199 dst.index++;
1200 }
1201 }
1202
1203 if (storage->file == PROGRAM_TEMPORARY &&
1204 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1205 fail_link(this->shader_program,
1206 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1207 ir->name, dst.index - storage->index,
1208 type_size(ir->type));
1209 }
1210 }
1211 }
1212
1213 void
1214 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1215 {
1216 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1217
1218 visit_exec_list(&ir->body_instructions, this);
1219
1220 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1221 }
1222
1223 void
1224 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1225 {
1226 switch (ir->mode) {
1227 case ir_loop_jump::jump_break:
1228 emit_asm(NULL, TGSI_OPCODE_BRK);
1229 break;
1230 case ir_loop_jump::jump_continue:
1231 emit_asm(NULL, TGSI_OPCODE_CONT);
1232 break;
1233 }
1234 }
1235
1236
1237 void
1238 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1239 {
1240 assert(0);
1241 (void)ir;
1242 }
1243
1244 void
1245 glsl_to_tgsi_visitor::visit(ir_function *ir)
1246 {
1247 /* Ignore function bodies other than main() -- we shouldn't see calls to
1248 * them since they should all be inlined before we get to glsl_to_tgsi.
1249 */
1250 if (strcmp(ir->name, "main") == 0) {
1251 const ir_function_signature *sig;
1252 exec_list empty;
1253
1254 sig = ir->matching_signature(NULL, &empty, false);
1255
1256 assert(sig);
1257
1258 foreach_in_list(ir_instruction, ir, &sig->body) {
1259 ir->accept(this);
1260 }
1261 }
1262 }
1263
1264 bool
1265 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1266 {
1267 int nonmul_operand = 1 - mul_operand;
1268 st_src_reg a, b, c;
1269 st_dst_reg result_dst;
1270
1271 // there is no TGSI opcode for this
1272 if (ir->type->is_integer_64())
1273 return false;
1274
1275 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1276 if (!expr || expr->operation != ir_binop_mul)
1277 return false;
1278
1279 expr->operands[0]->accept(this);
1280 a = this->result;
1281 expr->operands[1]->accept(this);
1282 b = this->result;
1283 ir->operands[nonmul_operand]->accept(this);
1284 c = this->result;
1285
1286 this->result = get_temp(ir->type);
1287 result_dst = st_dst_reg(this->result);
1288 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1289 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1290
1291 return true;
1292 }
1293
1294 /**
1295 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1296 *
1297 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1298 * implemented using multiplication, and logical-or is implemented using
1299 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1300 * As result, the logical expression (a & !b) can be rewritten as:
1301 *
1302 * - a * !b
1303 * - a * (1 - b)
1304 * - (a * 1) - (a * b)
1305 * - a + -(a * b)
1306 * - a + (a * -b)
1307 *
1308 * This final expression can be implemented as a single MAD(a, -b, a)
1309 * instruction.
1310 */
1311 bool
1312 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1313 int try_operand)
1314 {
1315 const int other_operand = 1 - try_operand;
1316 st_src_reg a, b;
1317
1318 ir_expression *expr = ir->operands[try_operand]->as_expression();
1319 if (!expr || expr->operation != ir_unop_logic_not)
1320 return false;
1321
1322 ir->operands[other_operand]->accept(this);
1323 a = this->result;
1324 expr->operands[0]->accept(this);
1325 b = this->result;
1326
1327 b.negate = ~b.negate;
1328
1329 this->result = get_temp(ir->type);
1330 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1331
1332 return true;
1333 }
1334
1335 void
1336 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1337 st_src_reg *reg, int *num_reladdr)
1338 {
1339 if (!reg->reladdr && !reg->reladdr2)
1340 return;
1341
1342 if (reg->reladdr)
1343 emit_arl(ir, address_reg, *reg->reladdr);
1344 if (reg->reladdr2)
1345 emit_arl(ir, address_reg2, *reg->reladdr2);
1346
1347 if (*num_reladdr != 1) {
1348 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1349
1350 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1351 *reg = temp;
1352 }
1353
1354 (*num_reladdr)--;
1355 }
1356
1357 void
1358 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1359 {
1360 st_src_reg op[ARRAY_SIZE(ir->operands)];
1361
1362 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1363 */
1364 if (!this->precise && ir->operation == ir_binop_add) {
1365 if (try_emit_mad(ir, 1))
1366 return;
1367 if (try_emit_mad(ir, 0))
1368 return;
1369 }
1370
1371 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1372 */
1373 if (!native_integers && ir->operation == ir_binop_logic_and) {
1374 if (try_emit_mad_for_and_not(ir, 1))
1375 return;
1376 if (try_emit_mad_for_and_not(ir, 0))
1377 return;
1378 }
1379
1380 if (ir->operation == ir_quadop_vector)
1381 assert(!"ir_quadop_vector should have been lowered");
1382
1383 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1384 this->result.file = PROGRAM_UNDEFINED;
1385 ir->operands[operand]->accept(this);
1386 if (this->result.file == PROGRAM_UNDEFINED) {
1387 printf("Failed to get tree for expression operand:\n");
1388 ir->operands[operand]->print();
1389 printf("\n");
1390 exit(1);
1391 }
1392 op[operand] = this->result;
1393
1394 /* Matrix expression operands should have been broken down to vector
1395 * operations already.
1396 */
1397 assert(!ir->operands[operand]->type->is_matrix());
1398 }
1399
1400 visit_expression(ir, op);
1401 }
1402
1403 /* The non-recursive part of the expression visitor lives in a separate
1404 * function and should be prevented from being inlined, to avoid a stack
1405 * explosion when deeply nested expressions are visited.
1406 */
1407 void
1408 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1409 {
1410 st_src_reg result_src;
1411 st_dst_reg result_dst;
1412
1413 int vector_elements = ir->operands[0]->type->vector_elements;
1414 if (ir->operands[1] &&
1415 ir->operation != ir_binop_interpolate_at_offset &&
1416 ir->operation != ir_binop_interpolate_at_sample) {
1417 st_src_reg *swz_op = NULL;
1418 if (vector_elements > ir->operands[1]->type->vector_elements) {
1419 assert(ir->operands[1]->type->vector_elements == 1);
1420 swz_op = &op[1];
1421 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1422 assert(ir->operands[0]->type->vector_elements == 1);
1423 swz_op = &op[0];
1424 }
1425 if (swz_op) {
1426 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1427 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1428 swizzle_x, swizzle_x);
1429 }
1430 vector_elements = MAX2(vector_elements,
1431 ir->operands[1]->type->vector_elements);
1432 }
1433 if (ir->operands[2] &&
1434 ir->operands[2]->type->vector_elements != vector_elements) {
1435 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1436 assert(ir->operands[2]->type->vector_elements == 1);
1437 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1438 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1439 swizzle_x, swizzle_x);
1440 }
1441
1442 this->result.file = PROGRAM_UNDEFINED;
1443
1444 /* Storage for our result. Ideally for an assignment we'd be using
1445 * the actual storage for the result here, instead.
1446 */
1447 result_src = get_temp(ir->type);
1448 /* convenience for the emit functions below. */
1449 result_dst = st_dst_reg(result_src);
1450 /* Limit writes to the channels that will be used by result_src later.
1451 * This does limit this temp's use as a temporary for multi-instruction
1452 * sequences.
1453 */
1454 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1455
1456 switch (ir->operation) {
1457 case ir_unop_logic_not:
1458 if (result_dst.type != GLSL_TYPE_FLOAT)
1459 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1460 else {
1461 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1462 * older GPUs implement SEQ using multiple instructions (i915 uses two
1463 * SGE instructions and a MUL instruction). Since our logic values are
1464 * 0.0 and 1.0, 1-x also implements !x.
1465 */
1466 op[0].negate = ~op[0].negate;
1467 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1468 st_src_reg_for_float(1.0));
1469 }
1470 break;
1471 case ir_unop_neg:
1472 if (result_dst.type == GLSL_TYPE_INT64 ||
1473 result_dst.type == GLSL_TYPE_UINT64)
1474 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1475 else if (result_dst.type == GLSL_TYPE_INT ||
1476 result_dst.type == GLSL_TYPE_UINT)
1477 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1478 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1479 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1480 else {
1481 op[0].negate = ~op[0].negate;
1482 result_src = op[0];
1483 }
1484 break;
1485 case ir_unop_subroutine_to_int:
1486 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1487 break;
1488 case ir_unop_abs:
1489 if (result_dst.type == GLSL_TYPE_FLOAT)
1490 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1491 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1492 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1493 else if (result_dst.type == GLSL_TYPE_INT64 ||
1494 result_dst.type == GLSL_TYPE_UINT64)
1495 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1496 else
1497 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1498 break;
1499 case ir_unop_sign:
1500 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1501 break;
1502 case ir_unop_rcp:
1503 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1504 break;
1505
1506 case ir_unop_exp2:
1507 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1508 break;
1509 case ir_unop_exp:
1510 assert(!"not reached: should be handled by exp_to_exp2");
1511 break;
1512 case ir_unop_log:
1513 assert(!"not reached: should be handled by log_to_log2");
1514 break;
1515 case ir_unop_log2:
1516 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1517 break;
1518 case ir_unop_sin:
1519 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1520 break;
1521 case ir_unop_cos:
1522 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1523 break;
1524 case ir_unop_saturate: {
1525 glsl_to_tgsi_instruction *inst;
1526 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1527 inst->saturate = true;
1528 break;
1529 }
1530
1531 case ir_unop_dFdx:
1532 case ir_unop_dFdx_coarse:
1533 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1534 break;
1535 case ir_unop_dFdx_fine:
1536 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1537 break;
1538 case ir_unop_dFdy:
1539 case ir_unop_dFdy_coarse:
1540 case ir_unop_dFdy_fine:
1541 {
1542 /* The X component contains 1 or -1 depending on whether the framebuffer
1543 * is a FBO or the window system buffer, respectively.
1544 * It is then multiplied with the source operand of DDY.
1545 */
1546 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1547 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1548
1549 unsigned transform_y_index =
1550 _mesa_add_state_reference(this->prog->Parameters,
1551 transform_y_state);
1552
1553 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1554 transform_y_index,
1555 glsl_type::vec4_type);
1556 transform_y.swizzle = SWIZZLE_XXXX;
1557
1558 st_src_reg temp = get_temp(glsl_type::vec4_type);
1559
1560 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1561 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1562 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1563 break;
1564 }
1565
1566 case ir_unop_frexp_sig:
1567 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1568 break;
1569
1570 case ir_unop_frexp_exp:
1571 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1572 break;
1573
1574 case ir_unop_noise: {
1575 /* At some point, a motivated person could add a better
1576 * implementation of noise. Currently not even the nvidia
1577 * binary drivers do anything more than this. In any case, the
1578 * place to do this is in the GL state tracker, not the poor
1579 * driver.
1580 */
1581 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1582 break;
1583 }
1584
1585 case ir_binop_add:
1586 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1587 break;
1588 case ir_binop_sub:
1589 op[1].negate = ~op[1].negate;
1590 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1591 break;
1592
1593 case ir_binop_mul:
1594 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1595 break;
1596 case ir_binop_div:
1597 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1598 break;
1599 case ir_binop_mod:
1600 if (result_dst.type == GLSL_TYPE_FLOAT)
1601 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1602 else
1603 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1604 break;
1605
1606 case ir_binop_less:
1607 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1608 break;
1609 case ir_binop_gequal:
1610 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1611 break;
1612 case ir_binop_equal:
1613 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1614 break;
1615 case ir_binop_nequal:
1616 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1617 break;
1618 case ir_binop_all_equal:
1619 /* "==" operator producing a scalar boolean. */
1620 if (ir->operands[0]->type->is_vector() ||
1621 ir->operands[1]->type->is_vector()) {
1622 st_src_reg temp = get_temp(native_integers ?
1623 glsl_type::uvec4_type :
1624 glsl_type::vec4_type);
1625
1626 if (native_integers) {
1627 st_dst_reg temp_dst = st_dst_reg(temp);
1628 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1629
1630 if (ir->operands[0]->type->is_boolean() &&
1631 ir->operands[1]->as_constant() &&
1632 ir->operands[1]->as_constant()->is_one()) {
1633 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1634 } else {
1635 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1636 }
1637
1638 /* Emit 1-3 AND operations to combine the SEQ results. */
1639 switch (ir->operands[0]->type->vector_elements) {
1640 case 2:
1641 break;
1642 case 3:
1643 temp_dst.writemask = WRITEMASK_Y;
1644 temp1.swizzle = SWIZZLE_YYYY;
1645 temp2.swizzle = SWIZZLE_ZZZZ;
1646 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1647 break;
1648 case 4:
1649 temp_dst.writemask = WRITEMASK_X;
1650 temp1.swizzle = SWIZZLE_XXXX;
1651 temp2.swizzle = SWIZZLE_YYYY;
1652 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1653 temp_dst.writemask = WRITEMASK_Y;
1654 temp1.swizzle = SWIZZLE_ZZZZ;
1655 temp2.swizzle = SWIZZLE_WWWW;
1656 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1657 }
1658
1659 temp1.swizzle = SWIZZLE_XXXX;
1660 temp2.swizzle = SWIZZLE_YYYY;
1661 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1662 } else {
1663 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1664
1665 /* After the dot-product, the value will be an integer on the
1666 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1667 */
1668 emit_dp(ir, result_dst, temp, temp, vector_elements);
1669
1670 /* Negating the result of the dot-product gives values on the range
1671 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1672 * This is achieved using SGE.
1673 */
1674 st_src_reg sge_src = result_src;
1675 sge_src.negate = ~sge_src.negate;
1676 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1677 st_src_reg_for_float(0.0));
1678 }
1679 } else {
1680 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1681 }
1682 break;
1683 case ir_binop_any_nequal:
1684 /* "!=" operator producing a scalar boolean. */
1685 if (ir->operands[0]->type->is_vector() ||
1686 ir->operands[1]->type->is_vector()) {
1687 st_src_reg temp = get_temp(native_integers ?
1688 glsl_type::uvec4_type :
1689 glsl_type::vec4_type);
1690 if (ir->operands[0]->type->is_boolean() &&
1691 ir->operands[1]->as_constant() &&
1692 ir->operands[1]->as_constant()->is_zero()) {
1693 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1694 } else {
1695 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1696 }
1697
1698 if (native_integers) {
1699 st_dst_reg temp_dst = st_dst_reg(temp);
1700 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1701
1702 /* Emit 1-3 OR operations to combine the SNE results. */
1703 switch (ir->operands[0]->type->vector_elements) {
1704 case 2:
1705 break;
1706 case 3:
1707 temp_dst.writemask = WRITEMASK_Y;
1708 temp1.swizzle = SWIZZLE_YYYY;
1709 temp2.swizzle = SWIZZLE_ZZZZ;
1710 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1711 break;
1712 case 4:
1713 temp_dst.writemask = WRITEMASK_X;
1714 temp1.swizzle = SWIZZLE_XXXX;
1715 temp2.swizzle = SWIZZLE_YYYY;
1716 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1717 temp_dst.writemask = WRITEMASK_Y;
1718 temp1.swizzle = SWIZZLE_ZZZZ;
1719 temp2.swizzle = SWIZZLE_WWWW;
1720 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1721 }
1722
1723 temp1.swizzle = SWIZZLE_XXXX;
1724 temp2.swizzle = SWIZZLE_YYYY;
1725 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1726 } else {
1727 /* After the dot-product, the value will be an integer on the
1728 * range [0,4]. Zero stays zero, and positive values become 1.0.
1729 */
1730 glsl_to_tgsi_instruction *const dp =
1731 emit_dp(ir, result_dst, temp, temp, vector_elements);
1732 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1733 /* The clamping to [0,1] can be done for free in the fragment
1734 * shader with a saturate.
1735 */
1736 dp->saturate = true;
1737 } else {
1738 /* Negating the result of the dot-product gives values on the
1739 * range [-4, 0]. Zero stays zero, and negative values become
1740 * 1.0. This achieved using SLT.
1741 */
1742 st_src_reg slt_src = result_src;
1743 slt_src.negate = ~slt_src.negate;
1744 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1745 st_src_reg_for_float(0.0));
1746 }
1747 }
1748 } else {
1749 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1750 }
1751 break;
1752
1753 case ir_binop_logic_xor:
1754 if (native_integers)
1755 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1756 else
1757 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1758 break;
1759
1760 case ir_binop_logic_or: {
1761 if (native_integers) {
1762 /* If integers are used as booleans, we can use an actual "or"
1763 * instruction.
1764 */
1765 assert(native_integers);
1766 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1767 } else {
1768 /* After the addition, the value will be an integer on the
1769 * range [0,2]. Zero stays zero, and positive values become 1.0.
1770 */
1771 glsl_to_tgsi_instruction *add =
1772 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1773 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1774 /* The clamping to [0,1] can be done for free in the fragment
1775 * shader with a saturate if floats are being used as boolean
1776 * values.
1777 */
1778 add->saturate = true;
1779 } else {
1780 /* Negating the result of the addition gives values on the range
1781 * [-2, 0]. Zero stays zero, and negative values become 1.0
1782 * This is achieved using SLT.
1783 */
1784 st_src_reg slt_src = result_src;
1785 slt_src.negate = ~slt_src.negate;
1786 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1787 st_src_reg_for_float(0.0));
1788 }
1789 }
1790 break;
1791 }
1792
1793 case ir_binop_logic_and:
1794 /* If native integers are disabled, the bool args are stored as float 0.0
1795 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1796 * actual AND opcode.
1797 */
1798 if (native_integers)
1799 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1800 else
1801 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1802 break;
1803
1804 case ir_binop_dot:
1805 assert(ir->operands[0]->type->is_vector());
1806 assert(ir->operands[0]->type == ir->operands[1]->type);
1807 emit_dp(ir, result_dst, op[0], op[1],
1808 ir->operands[0]->type->vector_elements);
1809 break;
1810
1811 case ir_unop_sqrt:
1812 if (have_sqrt) {
1813 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1814 } else {
1815 /* This is the only instruction sequence that makes the game "Risen"
1816 * render correctly. ABS is not required for the game, but since GLSL
1817 * declares negative values as "undefined", allowing us to do whatever
1818 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1819 * behavior.
1820 */
1821 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1822 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1823 }
1824 break;
1825 case ir_unop_rsq:
1826 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1827 break;
1828 case ir_unop_i2f:
1829 if (native_integers) {
1830 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1831 break;
1832 }
1833 /* fallthrough to next case otherwise */
1834 case ir_unop_b2f:
1835 if (native_integers) {
1836 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1837 st_src_reg_for_float(1.0));
1838 break;
1839 }
1840 /* fallthrough to next case otherwise */
1841 case ir_unop_i2u:
1842 case ir_unop_u2i:
1843 case ir_unop_i642u64:
1844 case ir_unop_u642i64:
1845 /* Converting between signed and unsigned integers is a no-op. */
1846 result_src = op[0];
1847 result_src.type = result_dst.type;
1848 break;
1849 case ir_unop_b2i:
1850 if (native_integers) {
1851 /* Booleans are stored as integers using ~0 for true and 0 for false.
1852 * GLSL requires that int(bool) return 1 for true and 0 for false.
1853 * This conversion is done with AND, but it could be done with NEG.
1854 */
1855 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1856 st_src_reg_for_int(1));
1857 } else {
1858 /* Booleans and integers are both stored as floats when native
1859 * integers are disabled.
1860 */
1861 result_src = op[0];
1862 }
1863 break;
1864 case ir_unop_f2i:
1865 if (native_integers)
1866 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1867 else
1868 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1869 break;
1870 case ir_unop_f2u:
1871 if (native_integers)
1872 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1873 else
1874 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1875 break;
1876 case ir_unop_bitcast_f2i:
1877 case ir_unop_bitcast_f2u:
1878 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1879 if (op[0].negate || op[0].abs)
1880 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1881 else
1882 result_src = op[0];
1883 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1884 GLSL_TYPE_UINT;
1885 break;
1886 case ir_unop_bitcast_i2f:
1887 case ir_unop_bitcast_u2f:
1888 result_src = op[0];
1889 result_src.type = GLSL_TYPE_FLOAT;
1890 break;
1891 case ir_unop_f2b:
1892 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1893 st_src_reg_for_float(0.0));
1894 break;
1895 case ir_unop_d2b:
1896 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1897 st_src_reg_for_double(0.0));
1898 break;
1899 case ir_unop_i2b:
1900 if (native_integers)
1901 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1902 st_src_reg_for_int(0));
1903 else
1904 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1905 st_src_reg_for_float(0.0));
1906 break;
1907 case ir_unop_bitcast_u642d:
1908 case ir_unop_bitcast_i642d:
1909 result_src = op[0];
1910 result_src.type = GLSL_TYPE_DOUBLE;
1911 break;
1912 case ir_unop_bitcast_d2i64:
1913 result_src = op[0];
1914 result_src.type = GLSL_TYPE_INT64;
1915 break;
1916 case ir_unop_bitcast_d2u64:
1917 result_src = op[0];
1918 result_src.type = GLSL_TYPE_UINT64;
1919 break;
1920 case ir_unop_trunc:
1921 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1922 break;
1923 case ir_unop_ceil:
1924 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1925 break;
1926 case ir_unop_floor:
1927 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1928 break;
1929 case ir_unop_round_even:
1930 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1931 break;
1932 case ir_unop_fract:
1933 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1934 break;
1935
1936 case ir_binop_min:
1937 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1938 break;
1939 case ir_binop_max:
1940 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1941 break;
1942 case ir_binop_pow:
1943 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1944 break;
1945
1946 case ir_unop_bit_not:
1947 if (native_integers) {
1948 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1949 break;
1950 }
1951 case ir_unop_u2f:
1952 if (native_integers) {
1953 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1954 break;
1955 }
1956 case ir_binop_lshift:
1957 case ir_binop_rshift:
1958 if (native_integers) {
1959 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1960 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1961 st_src_reg count;
1962
1963 if (glsl_base_type_is_64bit(op[0].type)) {
1964 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1965 * 64 bits.
1966 */
1967 count = get_temp(glsl_type::u64vec(ir->operands[1]
1968 ->type->components()));
1969 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1970 } else {
1971 count = op[1];
1972 }
1973
1974 emit_asm(ir, opcode, result_dst, op[0], count);
1975 break;
1976 }
1977 case ir_binop_bit_and:
1978 if (native_integers) {
1979 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1980 break;
1981 }
1982 case ir_binop_bit_xor:
1983 if (native_integers) {
1984 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1985 break;
1986 }
1987 case ir_binop_bit_or:
1988 if (native_integers) {
1989 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1990 break;
1991 }
1992
1993 assert(!"GLSL 1.30 features unsupported");
1994 break;
1995
1996 case ir_binop_ubo_load: {
1997 if (ctx->Const.UseSTD430AsDefaultPacking) {
1998 ir_rvalue *block = ir->operands[0];
1999 ir_rvalue *offset = ir->operands[1];
2000 ir_constant *const_block = block->as_constant();
2001
2002 st_src_reg cbuf(PROGRAM_CONSTANT,
2003 (const_block ? const_block->value.u[0] + 1 : 1),
2004 ir->type->base_type);
2005
2006 cbuf.has_index2 = true;
2007
2008 if (!const_block) {
2009 block->accept(this);
2010 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2011 *cbuf.reladdr = this->result;
2012 emit_arl(ir, sampler_reladdr, this->result);
2013 }
2014
2015 /* Calculate the surface offset */
2016 offset->accept(this);
2017 st_src_reg off = this->result;
2018
2019 glsl_to_tgsi_instruction *inst =
2020 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2021
2022 if (result_dst.type == GLSL_TYPE_BOOL)
2023 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2024 st_src_reg_for_int(0));
2025
2026 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2027 NULL);
2028 } else {
2029 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2030 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2031 unsigned const_offset = const_offset_ir ?
2032 const_offset_ir->value.u[0] : 0;
2033 unsigned const_block = const_uniform_block ?
2034 const_uniform_block->value.u[0] + 1 : 1;
2035 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2036 st_src_reg cbuf;
2037
2038 cbuf.type = ir->type->base_type;
2039 cbuf.file = PROGRAM_CONSTANT;
2040 cbuf.index = 0;
2041 cbuf.reladdr = NULL;
2042 cbuf.negate = 0;
2043 cbuf.abs = 0;
2044 cbuf.index2D = const_block;
2045
2046 assert(ir->type->is_vector() || ir->type->is_scalar());
2047
2048 if (const_offset_ir) {
2049 /* Constant index into constant buffer */
2050 cbuf.reladdr = NULL;
2051 cbuf.index = const_offset / 16;
2052 } else {
2053 ir_expression *offset_expr = ir->operands[1]->as_expression();
2054 st_src_reg offset = op[1];
2055
2056 /* The OpenGL spec is written in such a way that accesses with
2057 * non-constant offset are almost always vec4-aligned. The only
2058 * exception to this are members of structs in arrays of structs:
2059 * each struct in an array of structs is at least vec4-aligned,
2060 * but single-element and [ui]vec2 members of the struct may be at
2061 * an offset that is not a multiple of 16 bytes.
2062 *
2063 * Here, we extract that offset, relying on previous passes to
2064 * always generate offset expressions of the form
2065 * (+ expr constant_offset).
2066 *
2067 * Note that the std430 layout, which allows more cases of
2068 * alignment less than vec4 in arrays, is not supported for
2069 * uniform blocks, so we do not have to deal with it here.
2070 */
2071 if (offset_expr && offset_expr->operation == ir_binop_add) {
2072 const_offset_ir = offset_expr->operands[1]->as_constant();
2073 if (const_offset_ir) {
2074 const_offset = const_offset_ir->value.u[0];
2075 cbuf.index = const_offset / 16;
2076 offset_expr->operands[0]->accept(this);
2077 offset = this->result;
2078 }
2079 }
2080
2081 /* Relative/variable index into constant buffer */
2082 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2083 st_src_reg_for_int(4));
2084 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2085 *cbuf.reladdr = index_reg;
2086 }
2087
2088 if (const_uniform_block) {
2089 /* Constant constant buffer */
2090 cbuf.reladdr2 = NULL;
2091 } else {
2092 /* Relative/variable constant buffer */
2093 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2094 *cbuf.reladdr2 = op[0];
2095 }
2096 cbuf.has_index2 = true;
2097
2098 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2099 if (glsl_base_type_is_64bit(cbuf.type))
2100 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2101 const_offset % 16 / 8,
2102 const_offset % 16 / 8,
2103 const_offset % 16 / 8);
2104 else
2105 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2106 const_offset % 16 / 4,
2107 const_offset % 16 / 4,
2108 const_offset % 16 / 4);
2109
2110 if (ir->type->is_boolean()) {
2111 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2112 st_src_reg_for_int(0));
2113 } else {
2114 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2115 }
2116 }
2117 break;
2118 }
2119 case ir_triop_lrp:
2120 /* note: we have to reorder the three args here */
2121 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2122 break;
2123 case ir_triop_csel:
2124 if (this->ctx->Const.NativeIntegers)
2125 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2126 else {
2127 op[0].negate = ~op[0].negate;
2128 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2129 }
2130 break;
2131 case ir_triop_bitfield_extract:
2132 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2133 break;
2134 case ir_quadop_bitfield_insert:
2135 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2136 break;
2137 case ir_unop_bitfield_reverse:
2138 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2139 break;
2140 case ir_unop_bit_count:
2141 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2142 break;
2143 case ir_unop_find_msb:
2144 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2145 break;
2146 case ir_unop_find_lsb:
2147 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2148 break;
2149 case ir_binop_imul_high:
2150 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2151 break;
2152 case ir_triop_fma:
2153 /* In theory, MAD is incorrect here. */
2154 if (have_fma)
2155 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2156 else
2157 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2158 break;
2159 case ir_unop_interpolate_at_centroid:
2160 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2161 break;
2162 case ir_binop_interpolate_at_offset: {
2163 /* The y coordinate needs to be flipped for the default fb */
2164 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2165 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2166
2167 unsigned transform_y_index =
2168 _mesa_add_state_reference(this->prog->Parameters,
2169 transform_y_state);
2170
2171 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2172 transform_y_index,
2173 glsl_type::vec4_type);
2174 transform_y.swizzle = SWIZZLE_XXXX;
2175
2176 st_src_reg temp = get_temp(glsl_type::vec2_type);
2177 st_dst_reg temp_dst = st_dst_reg(temp);
2178
2179 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2180 temp_dst.writemask = WRITEMASK_Y;
2181 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2182 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2183 break;
2184 }
2185 case ir_binop_interpolate_at_sample:
2186 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2187 break;
2188
2189 case ir_unop_d2f:
2190 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2191 break;
2192 case ir_unop_f2d:
2193 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2194 break;
2195 case ir_unop_d2i:
2196 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2197 break;
2198 case ir_unop_i2d:
2199 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2200 break;
2201 case ir_unop_d2u:
2202 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2203 break;
2204 case ir_unop_u2d:
2205 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2206 break;
2207 case ir_unop_unpack_double_2x32:
2208 case ir_unop_pack_double_2x32:
2209 case ir_unop_unpack_int_2x32:
2210 case ir_unop_pack_int_2x32:
2211 case ir_unop_unpack_uint_2x32:
2212 case ir_unop_pack_uint_2x32:
2213 case ir_unop_unpack_sampler_2x32:
2214 case ir_unop_pack_sampler_2x32:
2215 case ir_unop_unpack_image_2x32:
2216 case ir_unop_pack_image_2x32:
2217 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2218 break;
2219
2220 case ir_binop_ldexp:
2221 if (ir->operands[0]->type->is_double()) {
2222 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2223 } else if (ir->operands[0]->type->is_float()) {
2224 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2225 } else {
2226 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2227 }
2228 break;
2229
2230 case ir_unop_pack_half_2x16:
2231 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2232 break;
2233 case ir_unop_unpack_half_2x16:
2234 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2235 break;
2236
2237 case ir_unop_get_buffer_size: {
2238 ir_constant *const_offset = ir->operands[0]->as_constant();
2239 int buf_base = ctx->st->has_hw_atomics
2240 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
2241 st_src_reg buffer(
2242 PROGRAM_BUFFER,
2243 buf_base + (const_offset ? const_offset->value.u[0] : 0),
2244 GLSL_TYPE_UINT);
2245 if (!const_offset) {
2246 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2247 *buffer.reladdr = op[0];
2248 emit_arl(ir, sampler_reladdr, op[0]);
2249 }
2250 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2251 break;
2252 }
2253
2254 case ir_unop_u2i64:
2255 case ir_unop_u2u64:
2256 case ir_unop_b2i64: {
2257 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2258 st_dst_reg temp_dst = st_dst_reg(temp);
2259 unsigned orig_swz = op[0].swizzle;
2260 /*
2261 * To convert unsigned to 64-bit:
2262 * zero Y channel, copy X channel.
2263 */
2264 temp_dst.writemask = WRITEMASK_Y;
2265 if (vector_elements > 1)
2266 temp_dst.writemask |= WRITEMASK_W;
2267 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2268 temp_dst.writemask = WRITEMASK_X;
2269 if (vector_elements > 1)
2270 temp_dst.writemask |= WRITEMASK_Z;
2271 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2272 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2273 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2274 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2275 else
2276 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2277 result_src = temp;
2278 result_src.type = GLSL_TYPE_UINT64;
2279 if (vector_elements > 2) {
2280 /* Subtle: We rely on the fact that get_temp here returns the next
2281 * TGSI temporary register directly after the temp register used for
2282 * the first two components, so that the result gets picked up
2283 * automatically.
2284 */
2285 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2286 st_dst_reg temp_dst = st_dst_reg(temp);
2287 temp_dst.writemask = WRITEMASK_Y;
2288 if (vector_elements > 3)
2289 temp_dst.writemask |= WRITEMASK_W;
2290 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2291
2292 temp_dst.writemask = WRITEMASK_X;
2293 if (vector_elements > 3)
2294 temp_dst.writemask |= WRITEMASK_Z;
2295 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2296 GET_SWZ(orig_swz, 2),
2297 GET_SWZ(orig_swz, 3),
2298 GET_SWZ(orig_swz, 3));
2299 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2300 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2301 else
2302 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2303 st_src_reg_for_int(1));
2304 }
2305 break;
2306 }
2307 case ir_unop_i642i:
2308 case ir_unop_u642i:
2309 case ir_unop_u642u:
2310 case ir_unop_i642u: {
2311 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2312 st_dst_reg temp_dst = st_dst_reg(temp);
2313 unsigned orig_swz = op[0].swizzle;
2314 unsigned orig_idx = op[0].index;
2315 int el;
2316 temp_dst.writemask = WRITEMASK_X;
2317
2318 for (el = 0; el < vector_elements; el++) {
2319 unsigned swz = GET_SWZ(orig_swz, el);
2320 if (swz & 1)
2321 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2322 SWIZZLE_Z, SWIZZLE_Z);
2323 else
2324 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2325 SWIZZLE_X, SWIZZLE_X);
2326 if (swz > 2)
2327 op[0].index = orig_idx + 1;
2328 op[0].type = GLSL_TYPE_UINT;
2329 temp_dst.writemask = WRITEMASK_X << el;
2330 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2331 }
2332 result_src = temp;
2333 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2334 result_src.type = GLSL_TYPE_UINT;
2335 else
2336 result_src.type = GLSL_TYPE_INT;
2337 break;
2338 }
2339 case ir_unop_i642b:
2340 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2341 st_src_reg_for_int64(0));
2342 break;
2343 case ir_unop_i642f:
2344 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2345 break;
2346 case ir_unop_u642f:
2347 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2348 break;
2349 case ir_unop_i642d:
2350 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2351 break;
2352 case ir_unop_u642d:
2353 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2354 break;
2355 case ir_unop_i2i64:
2356 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2357 break;
2358 case ir_unop_f2i64:
2359 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2360 break;
2361 case ir_unop_d2i64:
2362 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2363 break;
2364 case ir_unop_i2u64:
2365 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2366 break;
2367 case ir_unop_f2u64:
2368 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2369 break;
2370 case ir_unop_d2u64:
2371 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2372 break;
2373 /* these might be needed */
2374 case ir_unop_pack_snorm_2x16:
2375 case ir_unop_pack_unorm_2x16:
2376 case ir_unop_pack_snorm_4x8:
2377 case ir_unop_pack_unorm_4x8:
2378
2379 case ir_unop_unpack_snorm_2x16:
2380 case ir_unop_unpack_unorm_2x16:
2381 case ir_unop_unpack_snorm_4x8:
2382 case ir_unop_unpack_unorm_4x8:
2383
2384 case ir_quadop_vector:
2385 case ir_binop_vector_extract:
2386 case ir_triop_vector_insert:
2387 case ir_binop_carry:
2388 case ir_binop_borrow:
2389 case ir_unop_ssbo_unsized_array_length:
2390 /* This operation is not supported, or should have already been handled.
2391 */
2392 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2393 break;
2394 }
2395
2396 this->result = result_src;
2397 }
2398
2399
2400 void
2401 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2402 {
2403 st_src_reg src;
2404 int i;
2405 int swizzle[4];
2406
2407 /* Note that this is only swizzles in expressions, not those on the left
2408 * hand side of an assignment, which do write masking. See ir_assignment
2409 * for that.
2410 */
2411
2412 ir->val->accept(this);
2413 src = this->result;
2414 assert(src.file != PROGRAM_UNDEFINED);
2415 assert(ir->type->vector_elements > 0);
2416
2417 for (i = 0; i < 4; i++) {
2418 if (i < ir->type->vector_elements) {
2419 switch (i) {
2420 case 0:
2421 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2422 break;
2423 case 1:
2424 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2425 break;
2426 case 2:
2427 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2428 break;
2429 case 3:
2430 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2431 break;
2432 }
2433 } else {
2434 /* If the type is smaller than a vec4, replicate the last
2435 * channel out.
2436 */
2437 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2438 }
2439 }
2440
2441 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2442
2443 this->result = src;
2444 }
2445
2446 /* Test if the variable is an array. Note that geometry and
2447 * tessellation shader inputs are outputs are always arrays (except
2448 * for patch inputs), so only the array element type is considered.
2449 */
2450 static bool
2451 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2452 {
2453 const glsl_type *type = var->type;
2454
2455 *remove_array = false;
2456
2457 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2458 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2459 return false;
2460
2461 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2462 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2463 stage == MESA_SHADER_TESS_CTRL) &&
2464 !var->data.patch) {
2465 if (!var->type->is_array())
2466 return false; /* a system value probably */
2467
2468 type = var->type->fields.array;
2469 *remove_array = true;
2470 }
2471
2472 return type->is_array() || type->is_matrix();
2473 }
2474
2475 static unsigned
2476 st_translate_interp_loc(ir_variable *var)
2477 {
2478 if (var->data.centroid)
2479 return TGSI_INTERPOLATE_LOC_CENTROID;
2480 else if (var->data.sample)
2481 return TGSI_INTERPOLATE_LOC_SAMPLE;
2482 else
2483 return TGSI_INTERPOLATE_LOC_CENTER;
2484 }
2485
2486 void
2487 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2488 {
2489 variable_storage *entry;
2490 ir_variable *var = ir->var;
2491 bool remove_array;
2492
2493 if (handle_bound_deref(ir->as_dereference()))
2494 return;
2495
2496 entry = find_variable_storage(ir->var);
2497
2498 if (!entry) {
2499 switch (var->data.mode) {
2500 case ir_var_uniform:
2501 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2502 var->data.param_index);
2503 _mesa_hash_table_insert(this->variables, var, entry);
2504 break;
2505 case ir_var_shader_in: {
2506 /* The linker assigns locations for varyings and attributes,
2507 * including deprecated builtins (like gl_Color), user-assign
2508 * generic attributes (glBindVertexLocation), and
2509 * user-defined varyings.
2510 */
2511 assert(var->data.location != -1);
2512
2513 const glsl_type *type_without_array = var->type->without_array();
2514 struct inout_decl *decl = &inputs[num_inputs];
2515 unsigned component = var->data.location_frac;
2516 unsigned num_components;
2517 num_inputs++;
2518
2519 if (type_without_array->is_64bit())
2520 component = component / 2;
2521 if (type_without_array->vector_elements)
2522 num_components = type_without_array->vector_elements;
2523 else
2524 num_components = 4;
2525
2526 decl->mesa_index = var->data.location;
2527 decl->interp = (glsl_interp_mode) var->data.interpolation;
2528 decl->interp_loc = st_translate_interp_loc(var);
2529 decl->base_type = type_without_array->base_type;
2530 decl->usage_mask = u_bit_consecutive(component, num_components);
2531
2532 if (is_inout_array(shader->Stage, var, &remove_array)) {
2533 decl->array_id = num_input_arrays + 1;
2534 num_input_arrays++;
2535 } else {
2536 decl->array_id = 0;
2537 }
2538
2539 if (remove_array)
2540 decl->size = type_size(var->type->fields.array);
2541 else
2542 decl->size = type_size(var->type);
2543
2544 entry = new(mem_ctx) variable_storage(var,
2545 PROGRAM_INPUT,
2546 decl->mesa_index,
2547 decl->array_id);
2548 entry->component = component;
2549
2550 _mesa_hash_table_insert(this->variables, var, entry);
2551
2552 break;
2553 }
2554 case ir_var_shader_out: {
2555 assert(var->data.location != -1);
2556
2557 const glsl_type *type_without_array = var->type->without_array();
2558 struct inout_decl *decl = &outputs[num_outputs];
2559 unsigned component = var->data.location_frac;
2560 unsigned num_components;
2561 num_outputs++;
2562
2563 decl->invariant = var->data.invariant;
2564
2565 if (type_without_array->is_64bit())
2566 component = component / 2;
2567 if (type_without_array->vector_elements)
2568 num_components = type_without_array->vector_elements;
2569 else
2570 num_components = 4;
2571
2572 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2573 decl->base_type = type_without_array->base_type;
2574 decl->usage_mask = u_bit_consecutive(component, num_components);
2575 if (var->data.stream & (1u << 31)) {
2576 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2577 } else {
2578 assert(var->data.stream < 4);
2579 decl->gs_out_streams = 0;
2580 for (unsigned i = 0; i < num_components; ++i)
2581 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2582 }
2583
2584 if (is_inout_array(shader->Stage, var, &remove_array)) {
2585 decl->array_id = num_output_arrays + 1;
2586 num_output_arrays++;
2587 } else {
2588 decl->array_id = 0;
2589 }
2590
2591 if (remove_array)
2592 decl->size = type_size(var->type->fields.array);
2593 else
2594 decl->size = type_size(var->type);
2595
2596 if (var->data.fb_fetch_output) {
2597 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2598 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2599 var->type, component, decl->array_id);
2600 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2601 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2602 dst.array_id);
2603 } else {
2604 entry = new(mem_ctx) variable_storage(var,
2605 PROGRAM_OUTPUT,
2606 decl->mesa_index,
2607 decl->array_id);
2608 }
2609 entry->component = component;
2610
2611 _mesa_hash_table_insert(this->variables, var, entry);
2612
2613 break;
2614 }
2615 case ir_var_system_value:
2616 entry = new(mem_ctx) variable_storage(var,
2617 PROGRAM_SYSTEM_VALUE,
2618 var->data.location);
2619 break;
2620 case ir_var_auto:
2621 case ir_var_temporary:
2622 st_src_reg src = get_temp(var->type);
2623
2624 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2625 src.array_id);
2626 _mesa_hash_table_insert(this->variables, var, entry);
2627
2628 break;
2629 }
2630
2631 if (!entry) {
2632 printf("Failed to make storage for %s\n", var->name);
2633 exit(1);
2634 }
2635 }
2636
2637 this->result = st_src_reg(entry->file, entry->index, var->type,
2638 entry->component, entry->array_id);
2639 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2640 var->data.mode == ir_var_shader_in &&
2641 var->type->without_array()->is_double())
2642 this->result.is_double_vertex_input = true;
2643 if (!native_integers)
2644 this->result.type = GLSL_TYPE_FLOAT;
2645 }
2646
2647 static void
2648 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2649 GLbitfield64* usage_mask,
2650 GLbitfield64 double_usage_mask,
2651 GLbitfield* patch_usage_mask)
2652 {
2653 unsigned i;
2654 int j;
2655
2656 /* Fix array declarations by removing unused array elements at both ends
2657 * of the arrays. For example, mat4[3] where only mat[1] is used.
2658 */
2659 for (i = 0; i < count; i++) {
2660 struct inout_decl *decl = &decls[i];
2661 if (!decl->array_id)
2662 continue;
2663
2664 /* Shrink the beginning. */
2665 for (j = 0; j < (int)decl->size; j++) {
2666 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2667 if (*patch_usage_mask &
2668 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2669 break;
2670 }
2671 else {
2672 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2673 break;
2674 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2675 break;
2676 }
2677
2678 decl->mesa_index++;
2679 decl->size--;
2680 j--;
2681 }
2682
2683 /* Shrink the end. */
2684 for (j = decl->size-1; j >= 0; j--) {
2685 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2686 if (*patch_usage_mask &
2687 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2688 break;
2689 }
2690 else {
2691 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2692 break;
2693 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2694 break;
2695 }
2696
2697 decl->size--;
2698 }
2699
2700 /* When not all entries of an array are accessed, we mark them as used
2701 * here anyway, to ensure that the input/output mapping logic doesn't get
2702 * confused.
2703 *
2704 * TODO This happens when an array isn't used via indirect access, which
2705 * some game ports do (at least eON-based). There is an optimization
2706 * opportunity here by replacing the array declaration with non-array
2707 * declarations of those slots that are actually used.
2708 */
2709 for (j = 1; j < (int)decl->size; ++j) {
2710 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2711 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2712 else
2713 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2714 }
2715 }
2716 }
2717
2718
2719 static void
2720 mark_array_io(struct inout_decl *decls, unsigned count,
2721 GLbitfield64* usage_mask,
2722 GLbitfield64 double_usage_mask,
2723 GLbitfield* patch_usage_mask)
2724 {
2725 unsigned i;
2726 int j;
2727
2728 /* Fix array declarations by removing unused array elements at both ends
2729 * of the arrays. For example, mat4[3] where only mat[1] is used.
2730 */
2731 for (i = 0; i < count; i++) {
2732 struct inout_decl *decl = &decls[i];
2733 if (!decl->array_id)
2734 continue;
2735
2736 /* When not all entries of an array are accessed, we mark them as used
2737 * here anyway, to ensure that the input/output mapping logic doesn't get
2738 * confused.
2739 *
2740 * TODO This happens when an array isn't used via indirect access, which
2741 * some game ports do (at least eON-based). There is an optimization
2742 * opportunity here by replacing the array declaration with non-array
2743 * declarations of those slots that are actually used.
2744 */
2745 for (j = 0; j < (int)decl->size; ++j) {
2746 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2747 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2748 else
2749 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2750 }
2751 }
2752 }
2753
2754 void
2755 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2756 {
2757 ir_constant *index;
2758 st_src_reg src;
2759 bool is_2D = false;
2760 ir_variable *var = ir->variable_referenced();
2761
2762 if (handle_bound_deref(ir->as_dereference()))
2763 return;
2764
2765 /* We only need the logic provided by st_glsl_storage_type_size()
2766 * for arrays of structs. Indirect sampler and image indexing is handled
2767 * elsewhere.
2768 */
2769 int element_size = ir->type->without_array()->is_struct() ?
2770 st_glsl_storage_type_size(ir->type, var->data.bindless) :
2771 type_size(ir->type);
2772
2773 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2774
2775 ir->array->accept(this);
2776 src = this->result;
2777
2778 if (!src.has_index2) {
2779 switch (this->prog->Target) {
2780 case GL_TESS_CONTROL_PROGRAM_NV:
2781 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2782 !ir->variable_referenced()->data.patch;
2783 break;
2784 case GL_TESS_EVALUATION_PROGRAM_NV:
2785 is_2D = src.file == PROGRAM_INPUT &&
2786 !ir->variable_referenced()->data.patch;
2787 break;
2788 case GL_GEOMETRY_PROGRAM_NV:
2789 is_2D = src.file == PROGRAM_INPUT;
2790 break;
2791 }
2792 }
2793
2794 if (is_2D)
2795 element_size = 1;
2796
2797 if (index) {
2798
2799 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2800 src.file == PROGRAM_INPUT)
2801 element_size = attrib_type_size(ir->type, true);
2802 if (is_2D) {
2803 src.index2D = index->value.i[0];
2804 src.has_index2 = true;
2805 } else
2806 src.index += index->value.i[0] * element_size;
2807 } else {
2808 /* Variable index array dereference. It eats the "vec4" of the
2809 * base of the array and an index that offsets the TGSI register
2810 * index.
2811 */
2812 ir->array_index->accept(this);
2813
2814 st_src_reg index_reg;
2815
2816 if (element_size == 1) {
2817 index_reg = this->result;
2818 } else {
2819 index_reg = get_temp(native_integers ?
2820 glsl_type::int_type : glsl_type::float_type);
2821
2822 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2823 this->result, st_src_reg_for_type(index_reg.type, element_size));
2824 }
2825
2826 /* If there was already a relative address register involved, add the
2827 * new and the old together to get the new offset.
2828 */
2829 if (!is_2D && src.reladdr != NULL) {
2830 st_src_reg accum_reg = get_temp(native_integers ?
2831 glsl_type::int_type : glsl_type::float_type);
2832
2833 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2834 index_reg, *src.reladdr);
2835
2836 index_reg = accum_reg;
2837 }
2838
2839 if (is_2D) {
2840 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2841 *src.reladdr2 = index_reg;
2842 src.index2D = 0;
2843 src.has_index2 = true;
2844 } else {
2845 src.reladdr = ralloc(mem_ctx, st_src_reg);
2846 *src.reladdr = index_reg;
2847 }
2848 }
2849
2850 /* Change the register type to the element type of the array. */
2851 src.type = ir->type->base_type;
2852
2853 this->result = src;
2854 }
2855
2856 void
2857 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2858 {
2859 unsigned int i;
2860 const glsl_type *struct_type = ir->record->type;
2861 ir_variable *var = ir->record->variable_referenced();
2862 int offset = 0;
2863
2864 if (handle_bound_deref(ir->as_dereference()))
2865 return;
2866
2867 ir->record->accept(this);
2868
2869 assert(ir->field_idx >= 0);
2870 assert(var);
2871 for (i = 0; i < struct_type->length; i++) {
2872 if (i == (unsigned) ir->field_idx)
2873 break;
2874 const glsl_type *member_type = struct_type->fields.structure[i].type;
2875 offset += st_glsl_storage_type_size(member_type, var->data.bindless);
2876 }
2877
2878 /* If the type is smaller than a vec4, replicate the last channel out. */
2879 if (ir->type->is_scalar() || ir->type->is_vector())
2880 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2881 else
2882 this->result.swizzle = SWIZZLE_NOOP;
2883
2884 this->result.index += offset;
2885 this->result.type = ir->type->base_type;
2886 }
2887
2888 /**
2889 * We want to be careful in assignment setup to hit the actual storage
2890 * instead of potentially using a temporary like we might with the
2891 * ir_dereference handler.
2892 */
2893 static st_dst_reg
2894 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2895 {
2896 /* The LHS must be a dereference. If the LHS is a variable indexed array
2897 * access of a vector, it must be separated into a series conditional moves
2898 * before reaching this point (see ir_vec_index_to_cond_assign).
2899 */
2900 assert(ir->as_dereference());
2901 ir_dereference_array *deref_array = ir->as_dereference_array();
2902 if (deref_array) {
2903 assert(!deref_array->array->type->is_vector());
2904 }
2905
2906 /* Use the rvalue deref handler for the most part. We write swizzles using
2907 * the writemask, but we do extract the base component for enhanced layouts
2908 * from the source swizzle.
2909 */
2910 ir->accept(v);
2911 *component = GET_SWZ(v->result.swizzle, 0);
2912 return st_dst_reg(v->result);
2913 }
2914
2915 /**
2916 * Process the condition of a conditional assignment
2917 *
2918 * Examines the condition of a conditional assignment to generate the optimal
2919 * first operand of a \c CMP instruction. If the condition is a relational
2920 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2921 * used as the source for the \c CMP instruction. Otherwise the comparison
2922 * is processed to a boolean result, and the boolean result is used as the
2923 * operand to the CMP instruction.
2924 */
2925 bool
2926 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2927 {
2928 ir_rvalue *src_ir = ir;
2929 bool negate = true;
2930 bool switch_order = false;
2931
2932 ir_expression *const expr = ir->as_expression();
2933
2934 if (native_integers) {
2935 if ((expr != NULL) && (expr->num_operands == 2)) {
2936 enum glsl_base_type type = expr->operands[0]->type->base_type;
2937 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2938 type == GLSL_TYPE_BOOL) {
2939 if (expr->operation == ir_binop_equal) {
2940 if (expr->operands[0]->is_zero()) {
2941 src_ir = expr->operands[1];
2942 switch_order = true;
2943 }
2944 else if (expr->operands[1]->is_zero()) {
2945 src_ir = expr->operands[0];
2946 switch_order = true;
2947 }
2948 }
2949 else if (expr->operation == ir_binop_nequal) {
2950 if (expr->operands[0]->is_zero()) {
2951 src_ir = expr->operands[1];
2952 }
2953 else if (expr->operands[1]->is_zero()) {
2954 src_ir = expr->operands[0];
2955 }
2956 }
2957 }
2958 }
2959
2960 src_ir->accept(this);
2961 return switch_order;
2962 }
2963
2964 if ((expr != NULL) && (expr->num_operands == 2)) {
2965 bool zero_on_left = false;
2966
2967 if (expr->operands[0]->is_zero()) {
2968 src_ir = expr->operands[1];
2969 zero_on_left = true;
2970 } else if (expr->operands[1]->is_zero()) {
2971 src_ir = expr->operands[0];
2972 zero_on_left = false;
2973 }
2974
2975 /* a is - 0 + - 0 +
2976 * (a < 0) T F F ( a < 0) T F F
2977 * (0 < a) F F T (-a < 0) F F T
2978 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2979 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2980 *
2981 * Note that exchanging the order of 0 and 'a' in the comparison simply
2982 * means that the value of 'a' should be negated.
2983 */
2984 if (src_ir != ir) {
2985 switch (expr->operation) {
2986 case ir_binop_less:
2987 switch_order = false;
2988 negate = zero_on_left;
2989 break;
2990
2991 case ir_binop_gequal:
2992 switch_order = true;
2993 negate = zero_on_left;
2994 break;
2995
2996 default:
2997 /* This isn't the right kind of comparison afterall, so make sure
2998 * the whole condition is visited.
2999 */
3000 src_ir = ir;
3001 break;
3002 }
3003 }
3004 }
3005
3006 src_ir->accept(this);
3007
3008 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3009 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3010 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3011 * computing the condition.
3012 */
3013 if (negate)
3014 this->result.negate = ~this->result.negate;
3015
3016 return switch_order;
3017 }
3018
3019 void
3020 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
3021 st_dst_reg *l, st_src_reg *r,
3022 st_src_reg *cond, bool cond_swap)
3023 {
3024 if (type->is_struct()) {
3025 for (unsigned int i = 0; i < type->length; i++) {
3026 emit_block_mov(ir, type->fields.structure[i].type, l, r,
3027 cond, cond_swap);
3028 }
3029 return;
3030 }
3031
3032 if (type->is_array()) {
3033 for (unsigned int i = 0; i < type->length; i++) {
3034 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
3035 }
3036 return;
3037 }
3038
3039 if (type->is_matrix()) {
3040 const struct glsl_type *vec_type;
3041
3042 vec_type = glsl_type::get_instance(type->is_double()
3043 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3044 type->vector_elements, 1);
3045
3046 for (int i = 0; i < type->matrix_columns; i++) {
3047 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3048 }
3049 return;
3050 }
3051
3052 assert(type->is_scalar() || type->is_vector());
3053
3054 l->type = type->base_type;
3055 r->type = type->base_type;
3056 if (cond) {
3057 st_src_reg l_src = st_src_reg(*l);
3058
3059 if (l_src.file == PROGRAM_OUTPUT &&
3060 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3061 (l_src.index == FRAG_RESULT_DEPTH ||
3062 l_src.index == FRAG_RESULT_STENCIL)) {
3063 /* This is a special case because the source swizzles will be shifted
3064 * later to account for the difference between GLSL (where they're
3065 * plain floats) and TGSI (where they're Z and Y components). */
3066 l_src.swizzle = SWIZZLE_XXXX;
3067 }
3068
3069 if (native_integers) {
3070 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3071 cond_swap ? l_src : *r,
3072 cond_swap ? *r : l_src);
3073 } else {
3074 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3075 cond_swap ? l_src : *r,
3076 cond_swap ? *r : l_src);
3077 }
3078 } else {
3079 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3080 }
3081 l->index++;
3082 r->index++;
3083 if (type->is_dual_slot()) {
3084 l->index++;
3085 if (r->is_double_vertex_input == false)
3086 r->index++;
3087 }
3088 }
3089
3090 void
3091 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3092 {
3093 int dst_component;
3094 st_dst_reg l;
3095 st_src_reg r;
3096
3097 /* all generated instructions need to be flaged as precise */
3098 this->precise = is_precise(ir->lhs->variable_referenced());
3099 ir->rhs->accept(this);
3100 r = this->result;
3101
3102 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3103
3104 {
3105 int swizzles[4];
3106 int first_enabled_chan = 0;
3107 int rhs_chan = 0;
3108 ir_variable *variable = ir->lhs->variable_referenced();
3109
3110 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3111 variable->data.mode == ir_var_shader_out &&
3112 (variable->data.location == FRAG_RESULT_DEPTH ||
3113 variable->data.location == FRAG_RESULT_STENCIL)) {
3114 assert(ir->lhs->type->is_scalar());
3115 assert(ir->write_mask == WRITEMASK_X);
3116
3117 if (variable->data.location == FRAG_RESULT_DEPTH)
3118 l.writemask = WRITEMASK_Z;
3119 else {
3120 assert(variable->data.location == FRAG_RESULT_STENCIL);
3121 l.writemask = WRITEMASK_Y;
3122 }
3123 } else if (ir->write_mask == 0) {
3124 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3125
3126 unsigned num_elements =
3127 ir->lhs->type->without_array()->vector_elements;
3128
3129 if (num_elements) {
3130 l.writemask = u_bit_consecutive(0, num_elements);
3131 } else {
3132 /* The type is a struct or an array of (array of) structs. */
3133 l.writemask = WRITEMASK_XYZW;
3134 }
3135 } else {
3136 l.writemask = ir->write_mask;
3137 }
3138
3139 for (int i = 0; i < 4; i++) {
3140 if (l.writemask & (1 << i)) {
3141 first_enabled_chan = GET_SWZ(r.swizzle, i);
3142 break;
3143 }
3144 }
3145
3146 l.writemask = l.writemask << dst_component;
3147
3148 /* Swizzle a small RHS vector into the channels being written.
3149 *
3150 * glsl ir treats write_mask as dictating how many channels are
3151 * present on the RHS while TGSI treats write_mask as just
3152 * showing which channels of the vec4 RHS get written.
3153 */
3154 for (int i = 0; i < 4; i++) {
3155 if (l.writemask & (1 << i))
3156 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3157 else
3158 swizzles[i] = first_enabled_chan;
3159 }
3160 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3161 swizzles[2], swizzles[3]);
3162 }
3163
3164 assert(l.file != PROGRAM_UNDEFINED);
3165 assert(r.file != PROGRAM_UNDEFINED);
3166
3167 if (ir->condition) {
3168 const bool switch_order = this->process_move_condition(ir->condition);
3169 st_src_reg condition = this->result;
3170
3171 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3172 } else if (ir->rhs->as_expression() &&
3173 this->instructions.get_tail() &&
3174 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3175 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3176 type_size(ir->lhs->type) == 1 &&
3177 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3178 /* To avoid emitting an extra MOV when assigning an expression to a
3179 * variable, emit the last instruction of the expression again, but
3180 * replace the destination register with the target of the assignment.
3181 * Dead code elimination will remove the original instruction.
3182 */
3183 glsl_to_tgsi_instruction *inst, *new_inst;
3184 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3185 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3186 new_inst->saturate = inst->saturate;
3187 new_inst->resource = inst->resource;
3188 inst->dead_mask = inst->dst[0].writemask;
3189 } else {
3190 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3191 }
3192 this->precise = 0;
3193 }
3194
3195
3196 void
3197 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3198 {
3199 st_src_reg src;
3200 GLdouble stack_vals[4] = { 0 };
3201 gl_constant_value *values = (gl_constant_value *) stack_vals;
3202 GLenum gl_type = GL_NONE;
3203 unsigned int i, elements;
3204 static int in_array = 0;
3205 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3206
3207 /* Unfortunately, 4 floats is all we can get into
3208 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3209 * aggregate constant and move each constant value into it. If we
3210 * get lucky, copy propagation will eliminate the extra moves.
3211 */
3212 if (ir->type->is_struct()) {
3213 st_src_reg temp_base = get_temp(ir->type);
3214 st_dst_reg temp = st_dst_reg(temp_base);
3215
3216 for (i = 0; i < ir->type->length; i++) {
3217 ir_constant *const field_value = ir->get_record_field(i);
3218 int size = type_size(field_value->type);
3219
3220 assert(size > 0);
3221
3222 field_value->accept(this);
3223 src = this->result;
3224
3225 for (unsigned j = 0; j < (unsigned int)size; j++) {
3226 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3227
3228 src.index++;
3229 temp.index++;
3230 }
3231 }
3232 this->result = temp_base;
3233 return;
3234 }
3235
3236 if (ir->type->is_array()) {
3237 st_src_reg temp_base = get_temp(ir->type);
3238 st_dst_reg temp = st_dst_reg(temp_base);
3239 int size = type_size(ir->type->fields.array);
3240
3241 assert(size > 0);
3242 in_array++;
3243
3244 for (i = 0; i < ir->type->length; i++) {
3245 ir->const_elements[i]->accept(this);
3246 src = this->result;
3247 for (int j = 0; j < size; j++) {
3248 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3249
3250 src.index++;
3251 temp.index++;
3252 }
3253 }
3254 this->result = temp_base;
3255 in_array--;
3256 return;
3257 }
3258
3259 if (ir->type->is_matrix()) {
3260 st_src_reg mat = get_temp(ir->type);
3261 st_dst_reg mat_column = st_dst_reg(mat);
3262
3263 for (i = 0; i < ir->type->matrix_columns; i++) {
3264 switch (ir->type->base_type) {
3265 case GLSL_TYPE_FLOAT:
3266 values = (gl_constant_value *)
3267 &ir->value.f[i * ir->type->vector_elements];
3268
3269 src = st_src_reg(file, -1, ir->type->base_type);
3270 src.index = add_constant(file,
3271 values,
3272 ir->type->vector_elements,
3273 GL_FLOAT,
3274 &src.swizzle);
3275 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3276 break;
3277 case GLSL_TYPE_DOUBLE:
3278 values = (gl_constant_value *)
3279 &ir->value.d[i * ir->type->vector_elements];
3280 src = st_src_reg(file, -1, ir->type->base_type);
3281 src.index = add_constant(file,
3282 values,
3283 ir->type->vector_elements,
3284 GL_DOUBLE,
3285 &src.swizzle);
3286 if (ir->type->vector_elements >= 2) {
3287 mat_column.writemask = WRITEMASK_XY;
3288 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3289 SWIZZLE_X, SWIZZLE_Y);
3290 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3291 } else {
3292 mat_column.writemask = WRITEMASK_X;
3293 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3294 SWIZZLE_X, SWIZZLE_X);
3295 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3296 }
3297 src.index++;
3298 if (ir->type->vector_elements > 2) {
3299 if (ir->type->vector_elements == 4) {
3300 mat_column.writemask = WRITEMASK_ZW;
3301 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3302 SWIZZLE_X, SWIZZLE_Y);
3303 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3304 } else {
3305 mat_column.writemask = WRITEMASK_Z;
3306 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3307 SWIZZLE_Y, SWIZZLE_Y);
3308 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3309 mat_column.writemask = WRITEMASK_XYZW;
3310 src.swizzle = SWIZZLE_XYZW;
3311 }
3312 mat_column.index++;
3313 }
3314 break;
3315 default:
3316 unreachable("Illegal matrix constant type.\n");
3317 break;
3318 }
3319 mat_column.index++;
3320 }
3321 this->result = mat;
3322 return;
3323 }
3324
3325 elements = ir->type->vector_elements;
3326 switch (ir->type->base_type) {
3327 case GLSL_TYPE_FLOAT:
3328 gl_type = GL_FLOAT;
3329 for (i = 0; i < ir->type->vector_elements; i++) {
3330 values[i].f = ir->value.f[i];
3331 }
3332 break;
3333 case GLSL_TYPE_DOUBLE:
3334 gl_type = GL_DOUBLE;
3335 for (i = 0; i < ir->type->vector_elements; i++) {
3336 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3337 }
3338 break;
3339 case GLSL_TYPE_INT64:
3340 gl_type = GL_INT64_ARB;
3341 for (i = 0; i < ir->type->vector_elements; i++) {
3342 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3343 }
3344 break;
3345 case GLSL_TYPE_UINT64:
3346 gl_type = GL_UNSIGNED_INT64_ARB;
3347 for (i = 0; i < ir->type->vector_elements; i++) {
3348 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3349 }
3350 break;
3351 case GLSL_TYPE_UINT:
3352 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3353 for (i = 0; i < ir->type->vector_elements; i++) {
3354 if (native_integers)
3355 values[i].u = ir->value.u[i];
3356 else
3357 values[i].f = ir->value.u[i];
3358 }
3359 break;
3360 case GLSL_TYPE_INT:
3361 gl_type = native_integers ? GL_INT : GL_FLOAT;
3362 for (i = 0; i < ir->type->vector_elements; i++) {
3363 if (native_integers)
3364 values[i].i = ir->value.i[i];
3365 else
3366 values[i].f = ir->value.i[i];
3367 }
3368 break;
3369 case GLSL_TYPE_BOOL:
3370 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3371 for (i = 0; i < ir->type->vector_elements; i++) {
3372 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3373 }
3374 break;
3375 case GLSL_TYPE_SAMPLER:
3376 case GLSL_TYPE_IMAGE:
3377 gl_type = GL_UNSIGNED_INT;
3378 elements = 2;
3379 values[0].u = ir->value.u64[0] & 0xffffffff;
3380 values[1].u = ir->value.u64[0] >> 32;
3381 break;
3382 default:
3383 assert(!"Non-float/uint/int/bool/sampler/image constant");
3384 }
3385
3386 this->result = st_src_reg(file, -1, ir->type);
3387 this->result.index = add_constant(file,
3388 values,
3389 elements,
3390 gl_type,
3391 &this->result.swizzle);
3392 }
3393
3394 void
3395 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3396 {
3397 exec_node *param = ir->actual_parameters.get_head();
3398 ir_dereference *deref = static_cast<ir_dereference *>(param);
3399 ir_variable *location = deref->variable_referenced();
3400 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3401 /* Calculate the surface offset */
3402 st_src_reg offset;
3403 unsigned array_size = 0, base = 0;
3404 uint16_t index = 0;
3405 st_src_reg resource;
3406
3407 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3408
3409 if (has_hw_atomics) {
3410 variable_storage *entry = find_variable_storage(location);
3411 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3412 location->data.binding);
3413
3414 if (!entry) {
3415 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3416 num_atomics);
3417 _mesa_hash_table_insert(this->variables, location, entry);
3418
3419 atomic_info[num_atomics].location = location->data.location;
3420 atomic_info[num_atomics].binding = location->data.binding;
3421 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3422 if (atomic_info[num_atomics].size == 0)
3423 atomic_info[num_atomics].size = 1;
3424 atomic_info[num_atomics].array_id = 0;
3425 num_atomics++;
3426 }
3427
3428 if (offset.file != PROGRAM_UNDEFINED) {
3429 if (atomic_info[entry->index].array_id == 0) {
3430 num_atomic_arrays++;
3431 atomic_info[entry->index].array_id = num_atomic_arrays;
3432 }
3433 buffer.array_id = atomic_info[entry->index].array_id;
3434 }
3435
3436 buffer.index = index;
3437 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3438 buffer.has_index2 = true;
3439
3440 if (offset.file != PROGRAM_UNDEFINED) {
3441 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3442 *buffer.reladdr = offset;
3443 emit_arl(ir, sampler_reladdr, offset);
3444 }
3445 offset = st_src_reg_for_int(0);
3446
3447 resource = buffer;
3448 } else {
3449 st_src_reg buffer(PROGRAM_BUFFER, location->data.binding,
3450 GLSL_TYPE_ATOMIC_UINT);
3451
3452 if (offset.file != PROGRAM_UNDEFINED) {
3453 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3454 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3455 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3456 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3457 } else {
3458 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3459 }
3460 resource = buffer;
3461 }
3462
3463 ir->return_deref->accept(this);
3464 st_dst_reg dst(this->result);
3465 dst.writemask = WRITEMASK_X;
3466
3467 glsl_to_tgsi_instruction *inst;
3468
3469 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3470 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3471 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3472 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3473 st_src_reg_for_int(1));
3474 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3475 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3476 st_src_reg_for_int(-1));
3477 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3478 } else {
3479 param = param->get_next();
3480 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3481 val->accept(this);
3482
3483 st_src_reg data = this->result, data2 = undef_src;
3484 enum tgsi_opcode opcode;
3485 switch (ir->callee->intrinsic_id) {
3486 case ir_intrinsic_atomic_counter_add:
3487 opcode = TGSI_OPCODE_ATOMUADD;
3488 break;
3489 case ir_intrinsic_atomic_counter_min:
3490 opcode = TGSI_OPCODE_ATOMIMIN;
3491 break;
3492 case ir_intrinsic_atomic_counter_max:
3493 opcode = TGSI_OPCODE_ATOMIMAX;
3494 break;
3495 case ir_intrinsic_atomic_counter_and:
3496 opcode = TGSI_OPCODE_ATOMAND;
3497 break;
3498 case ir_intrinsic_atomic_counter_or:
3499 opcode = TGSI_OPCODE_ATOMOR;
3500 break;
3501 case ir_intrinsic_atomic_counter_xor:
3502 opcode = TGSI_OPCODE_ATOMXOR;
3503 break;
3504 case ir_intrinsic_atomic_counter_exchange:
3505 opcode = TGSI_OPCODE_ATOMXCHG;
3506 break;
3507 case ir_intrinsic_atomic_counter_comp_swap: {
3508 opcode = TGSI_OPCODE_ATOMCAS;
3509 param = param->get_next();
3510 val = ((ir_instruction *)param)->as_rvalue();
3511 val->accept(this);
3512 data2 = this->result;
3513 break;
3514 }
3515 default:
3516 assert(!"Unexpected intrinsic");
3517 return;
3518 }
3519
3520 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3521 }
3522
3523 inst->resource = resource;
3524 }
3525
3526 void
3527 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3528 {
3529 exec_node *param = ir->actual_parameters.get_head();
3530
3531 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3532
3533 param = param->get_next();
3534 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3535
3536 ir_constant *const_block = block->as_constant();
3537 int buf_base = st_context(ctx)->has_hw_atomics
3538 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
3539 st_src_reg buffer(
3540 PROGRAM_BUFFER,
3541 buf_base + (const_block ? const_block->value.u[0] : 0),
3542 GLSL_TYPE_UINT);
3543
3544 if (!const_block) {
3545 block->accept(this);
3546 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3547 *buffer.reladdr = this->result;
3548 emit_arl(ir, sampler_reladdr, this->result);
3549 }
3550
3551 /* Calculate the surface offset */
3552 offset->accept(this);
3553 st_src_reg off = this->result;
3554
3555 st_dst_reg dst = undef_dst;
3556 if (ir->return_deref) {
3557 ir->return_deref->accept(this);
3558 dst = st_dst_reg(this->result);
3559 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3560 }
3561
3562 glsl_to_tgsi_instruction *inst;
3563
3564 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3565 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3566 if (dst.type == GLSL_TYPE_BOOL)
3567 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3568 st_src_reg_for_int(0));
3569 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3570 param = param->get_next();
3571 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3572 val->accept(this);
3573
3574 param = param->get_next();
3575 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3576 assert(write_mask);
3577 dst.writemask = write_mask->value.u[0];
3578
3579 dst.type = this->result.type;
3580 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3581 } else {
3582 param = param->get_next();
3583 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3584 val->accept(this);
3585
3586 st_src_reg data = this->result, data2 = undef_src;
3587 enum tgsi_opcode opcode;
3588 switch (ir->callee->intrinsic_id) {
3589 case ir_intrinsic_ssbo_atomic_add:
3590 opcode = TGSI_OPCODE_ATOMUADD;
3591 break;
3592 case ir_intrinsic_ssbo_atomic_min:
3593 opcode = TGSI_OPCODE_ATOMIMIN;
3594 break;
3595 case ir_intrinsic_ssbo_atomic_max:
3596 opcode = TGSI_OPCODE_ATOMIMAX;
3597 break;
3598 case ir_intrinsic_ssbo_atomic_and:
3599 opcode = TGSI_OPCODE_ATOMAND;
3600 break;
3601 case ir_intrinsic_ssbo_atomic_or:
3602 opcode = TGSI_OPCODE_ATOMOR;
3603 break;
3604 case ir_intrinsic_ssbo_atomic_xor:
3605 opcode = TGSI_OPCODE_ATOMXOR;
3606 break;
3607 case ir_intrinsic_ssbo_atomic_exchange:
3608 opcode = TGSI_OPCODE_ATOMXCHG;
3609 break;
3610 case ir_intrinsic_ssbo_atomic_comp_swap:
3611 opcode = TGSI_OPCODE_ATOMCAS;
3612 param = param->get_next();
3613 val = ((ir_instruction *)param)->as_rvalue();
3614 val->accept(this);
3615 data2 = this->result;
3616 break;
3617 default:
3618 assert(!"Unexpected intrinsic");
3619 return;
3620 }
3621
3622 inst = emit_asm(ir, opcode, dst, off, data, data2);
3623 }
3624
3625 param = param->get_next();
3626 ir_constant *access = NULL;
3627 if (!param->is_tail_sentinel()) {
3628 access = ((ir_instruction *)param)->as_constant();
3629 assert(access);
3630 }
3631
3632 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3633 }
3634
3635 void
3636 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3637 {
3638 switch (ir->callee->intrinsic_id) {
3639 case ir_intrinsic_memory_barrier:
3640 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3641 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3642 TGSI_MEMBAR_ATOMIC_BUFFER |
3643 TGSI_MEMBAR_SHADER_IMAGE |
3644 TGSI_MEMBAR_SHARED));
3645 break;
3646 case ir_intrinsic_memory_barrier_atomic_counter:
3647 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3648 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3649 break;
3650 case ir_intrinsic_memory_barrier_buffer:
3651 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3652 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3653 break;
3654 case ir_intrinsic_memory_barrier_image:
3655 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3656 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3657 break;
3658 case ir_intrinsic_memory_barrier_shared:
3659 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3660 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3661 break;
3662 case ir_intrinsic_group_memory_barrier:
3663 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3664 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3665 TGSI_MEMBAR_ATOMIC_BUFFER |
3666 TGSI_MEMBAR_SHADER_IMAGE |
3667 TGSI_MEMBAR_SHARED |
3668 TGSI_MEMBAR_THREAD_GROUP));
3669 break;
3670 default:
3671 assert(!"Unexpected memory barrier intrinsic");
3672 }
3673 }
3674
3675 void
3676 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3677 {
3678 exec_node *param = ir->actual_parameters.get_head();
3679
3680 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3681
3682 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3683
3684 /* Calculate the surface offset */
3685 offset->accept(this);
3686 st_src_reg off = this->result;
3687
3688 st_dst_reg dst = undef_dst;
3689 if (ir->return_deref) {
3690 ir->return_deref->accept(this);
3691 dst = st_dst_reg(this->result);
3692 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3693 }
3694
3695 glsl_to_tgsi_instruction *inst;
3696
3697 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3698 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3699 inst->resource = buffer;
3700 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3701 param = param->get_next();
3702 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3703 val->accept(this);
3704
3705 param = param->get_next();
3706 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3707 assert(write_mask);
3708 dst.writemask = write_mask->value.u[0];
3709
3710 dst.type = this->result.type;
3711 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3712 inst->resource = buffer;
3713 } else {
3714 param = param->get_next();
3715 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3716 val->accept(this);
3717
3718 st_src_reg data = this->result, data2 = undef_src;
3719 enum tgsi_opcode opcode;
3720 switch (ir->callee->intrinsic_id) {
3721 case ir_intrinsic_shared_atomic_add:
3722 opcode = TGSI_OPCODE_ATOMUADD;
3723 break;
3724 case ir_intrinsic_shared_atomic_min:
3725 opcode = TGSI_OPCODE_ATOMIMIN;
3726 break;
3727 case ir_intrinsic_shared_atomic_max:
3728 opcode = TGSI_OPCODE_ATOMIMAX;
3729 break;
3730 case ir_intrinsic_shared_atomic_and:
3731 opcode = TGSI_OPCODE_ATOMAND;
3732 break;
3733 case ir_intrinsic_shared_atomic_or:
3734 opcode = TGSI_OPCODE_ATOMOR;
3735 break;
3736 case ir_intrinsic_shared_atomic_xor:
3737 opcode = TGSI_OPCODE_ATOMXOR;
3738 break;
3739 case ir_intrinsic_shared_atomic_exchange:
3740 opcode = TGSI_OPCODE_ATOMXCHG;
3741 break;
3742 case ir_intrinsic_shared_atomic_comp_swap:
3743 opcode = TGSI_OPCODE_ATOMCAS;
3744 param = param->get_next();
3745 val = ((ir_instruction *)param)->as_rvalue();
3746 val->accept(this);
3747 data2 = this->result;
3748 break;
3749 default:
3750 assert(!"Unexpected intrinsic");
3751 return;
3752 }
3753
3754 inst = emit_asm(ir, opcode, dst, off, data, data2);
3755 inst->resource = buffer;
3756 }
3757 }
3758
3759 static void
3760 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3761 bool *memory_coherent, bool *memory_volatile,
3762 bool *memory_restrict, bool *memory_read_only,
3763 unsigned *image_format)
3764 {
3765
3766 switch (ir->ir_type) {
3767 case ir_type_dereference_record: {
3768 ir_dereference_record *deref_record = ir->as_dereference_record();
3769 const glsl_type *struct_type = deref_record->record->type;
3770 int fild_idx = deref_record->field_idx;
3771
3772 *type = struct_type->fields.structure[fild_idx].type->without_array();
3773 *memory_coherent =
3774 struct_type->fields.structure[fild_idx].memory_coherent;
3775 *memory_volatile =
3776 struct_type->fields.structure[fild_idx].memory_volatile;
3777 *memory_restrict =
3778 struct_type->fields.structure[fild_idx].memory_restrict;
3779 *memory_read_only =
3780 struct_type->fields.structure[fild_idx].memory_read_only;
3781 *image_format =
3782 struct_type->fields.structure[fild_idx].image_format;
3783 break;
3784 }
3785
3786 case ir_type_dereference_array: {
3787 ir_dereference_array *deref_arr = ir->as_dereference_array();
3788 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3789 memory_coherent, memory_volatile, memory_restrict,
3790 memory_read_only, image_format);
3791 break;
3792 }
3793
3794 case ir_type_dereference_variable: {
3795 ir_variable *var = ir->variable_referenced();
3796
3797 *type = var->type->without_array();
3798 *memory_coherent = var->data.memory_coherent;
3799 *memory_volatile = var->data.memory_volatile;
3800 *memory_restrict = var->data.memory_restrict;
3801 *memory_read_only = var->data.memory_read_only;
3802 *image_format = var->data.image_format;
3803 break;
3804 }
3805
3806 default:
3807 break;
3808 }
3809 }
3810
3811 void
3812 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3813 {
3814 exec_node *param = ir->actual_parameters.get_head();
3815
3816 ir_dereference *img = (ir_dereference *)param;
3817 const ir_variable *imgvar = img->variable_referenced();
3818 unsigned sampler_array_size = 1, sampler_base = 0;
3819 bool memory_coherent = false, memory_volatile = false,
3820 memory_restrict = false, memory_read_only = false;
3821 unsigned image_format = 0;
3822 const glsl_type *type = NULL;
3823
3824 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3825 &memory_restrict, &memory_read_only, &image_format);
3826
3827 st_src_reg reladdr;
3828 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3829 uint16_t index = 0;
3830 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3831 &index, &reladdr, !imgvar->contains_bindless());
3832
3833 image.index = index;
3834 if (reladdr.file != PROGRAM_UNDEFINED) {
3835 image.reladdr = ralloc(mem_ctx, st_src_reg);
3836 *image.reladdr = reladdr;
3837 emit_arl(ir, sampler_reladdr, reladdr);
3838 }
3839
3840 st_dst_reg dst = undef_dst;
3841 if (ir->return_deref) {
3842 ir->return_deref->accept(this);
3843 dst = st_dst_reg(this->result);
3844 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3845 }
3846
3847 glsl_to_tgsi_instruction *inst;
3848
3849 st_src_reg bindless;
3850 if (imgvar->contains_bindless()) {
3851 img->accept(this);
3852 bindless = this->result;
3853 }
3854
3855 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3856 dst.writemask = WRITEMASK_XYZ;
3857 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3858 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3859 st_src_reg res = get_temp(glsl_type::ivec4_type);
3860 st_dst_reg dstres = st_dst_reg(res);
3861 dstres.writemask = WRITEMASK_W;
3862 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3863 res.swizzle = SWIZZLE_WWWW;
3864 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3865 } else {
3866 st_src_reg arg1 = undef_src, arg2 = undef_src;
3867 st_src_reg coord;
3868 st_dst_reg coord_dst;
3869 coord = get_temp(glsl_type::ivec4_type);
3870 coord_dst = st_dst_reg(coord);
3871 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3872 param = param->get_next();
3873 ((ir_dereference *)param)->accept(this);
3874 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3875 coord.swizzle = SWIZZLE_XXXX;
3876 switch (type->coordinate_components()) {
3877 case 4: assert(!"unexpected coord count");
3878 /* fallthrough */
3879 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3880 /* fallthrough */
3881 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3882 }
3883
3884 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3885 param = param->get_next();
3886 ((ir_dereference *)param)->accept(this);
3887 st_src_reg sample = this->result;
3888 sample.swizzle = SWIZZLE_XXXX;
3889 coord_dst.writemask = WRITEMASK_W;
3890 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3891 coord.swizzle |= SWIZZLE_W << 9;
3892 }
3893
3894 param = param->get_next();
3895 if (!param->is_tail_sentinel()) {
3896 ((ir_dereference *)param)->accept(this);
3897 arg1 = this->result;
3898 param = param->get_next();
3899 }
3900
3901 if (!param->is_tail_sentinel()) {
3902 ((ir_dereference *)param)->accept(this);
3903 arg2 = this->result;
3904 param = param->get_next();
3905 }
3906
3907 assert(param->is_tail_sentinel());
3908
3909 enum tgsi_opcode opcode;
3910 switch (ir->callee->intrinsic_id) {
3911 case ir_intrinsic_image_load:
3912 opcode = TGSI_OPCODE_LOAD;
3913 break;
3914 case ir_intrinsic_image_store:
3915 opcode = TGSI_OPCODE_STORE;
3916 break;
3917 case ir_intrinsic_image_atomic_add:
3918 opcode = TGSI_OPCODE_ATOMUADD;
3919 break;
3920 case ir_intrinsic_image_atomic_min:
3921 opcode = TGSI_OPCODE_ATOMIMIN;
3922 break;
3923 case ir_intrinsic_image_atomic_max:
3924 opcode = TGSI_OPCODE_ATOMIMAX;
3925 break;
3926 case ir_intrinsic_image_atomic_and:
3927 opcode = TGSI_OPCODE_ATOMAND;
3928 break;
3929 case ir_intrinsic_image_atomic_or:
3930 opcode = TGSI_OPCODE_ATOMOR;
3931 break;
3932 case ir_intrinsic_image_atomic_xor:
3933 opcode = TGSI_OPCODE_ATOMXOR;
3934 break;
3935 case ir_intrinsic_image_atomic_exchange:
3936 opcode = TGSI_OPCODE_ATOMXCHG;
3937 break;
3938 case ir_intrinsic_image_atomic_comp_swap:
3939 opcode = TGSI_OPCODE_ATOMCAS;
3940 break;
3941 default:
3942 assert(!"Unexpected intrinsic");
3943 return;
3944 }
3945
3946 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3947 if (opcode == TGSI_OPCODE_STORE)
3948 inst->dst[0].writemask = WRITEMASK_XYZW;
3949 }
3950
3951 if (imgvar->contains_bindless()) {
3952 inst->resource = bindless;
3953 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3954 SWIZZLE_X, SWIZZLE_Y);
3955 } else {
3956 inst->resource = image;
3957 inst->sampler_array_size = sampler_array_size;
3958 inst->sampler_base = sampler_base;
3959 }
3960
3961 inst->tex_target = type->sampler_index();
3962 inst->image_format = st_mesa_format_to_pipe_format(st_context(ctx),
3963 _mesa_get_shader_image_format(image_format));
3964 inst->read_only = memory_read_only;
3965
3966 if (memory_coherent)
3967 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3968 if (memory_restrict)
3969 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3970 if (memory_volatile)
3971 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3972 }
3973
3974 void
3975 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
3976 {
3977 ir->return_deref->accept(this);
3978 st_dst_reg dst = st_dst_reg(this->result);
3979
3980 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
3981
3982 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
3983 unsigned num_src = 0;
3984 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
3985 assert(num_src < ARRAY_SIZE(src));
3986
3987 this->result.file = PROGRAM_UNDEFINED;
3988 param->accept(this);
3989 assert(this->result.file != PROGRAM_UNDEFINED);
3990
3991 src[num_src] = this->result;
3992 num_src++;
3993 }
3994
3995 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
3996 }
3997
3998 void
3999 glsl_to_tgsi_visitor::visit(ir_call *ir)
4000 {
4001 ir_function_signature *sig = ir->callee;
4002
4003 /* Filter out intrinsics */
4004 switch (sig->intrinsic_id) {
4005 case ir_intrinsic_atomic_counter_read:
4006 case ir_intrinsic_atomic_counter_increment:
4007 case ir_intrinsic_atomic_counter_predecrement:
4008 case ir_intrinsic_atomic_counter_add:
4009 case ir_intrinsic_atomic_counter_min:
4010 case ir_intrinsic_atomic_counter_max:
4011 case ir_intrinsic_atomic_counter_and:
4012 case ir_intrinsic_atomic_counter_or:
4013 case ir_intrinsic_atomic_counter_xor:
4014 case ir_intrinsic_atomic_counter_exchange:
4015 case ir_intrinsic_atomic_counter_comp_swap:
4016 visit_atomic_counter_intrinsic(ir);
4017 return;
4018
4019 case ir_intrinsic_ssbo_load:
4020 case ir_intrinsic_ssbo_store:
4021 case ir_intrinsic_ssbo_atomic_add:
4022 case ir_intrinsic_ssbo_atomic_min:
4023 case ir_intrinsic_ssbo_atomic_max:
4024 case ir_intrinsic_ssbo_atomic_and:
4025 case ir_intrinsic_ssbo_atomic_or:
4026 case ir_intrinsic_ssbo_atomic_xor:
4027 case ir_intrinsic_ssbo_atomic_exchange:
4028 case ir_intrinsic_ssbo_atomic_comp_swap:
4029 visit_ssbo_intrinsic(ir);
4030 return;
4031
4032 case ir_intrinsic_memory_barrier:
4033 case ir_intrinsic_memory_barrier_atomic_counter:
4034 case ir_intrinsic_memory_barrier_buffer:
4035 case ir_intrinsic_memory_barrier_image:
4036 case ir_intrinsic_memory_barrier_shared:
4037 case ir_intrinsic_group_memory_barrier:
4038 visit_membar_intrinsic(ir);
4039 return;
4040
4041 case ir_intrinsic_shared_load:
4042 case ir_intrinsic_shared_store:
4043 case ir_intrinsic_shared_atomic_add:
4044 case ir_intrinsic_shared_atomic_min:
4045 case ir_intrinsic_shared_atomic_max:
4046 case ir_intrinsic_shared_atomic_and:
4047 case ir_intrinsic_shared_atomic_or:
4048 case ir_intrinsic_shared_atomic_xor:
4049 case ir_intrinsic_shared_atomic_exchange:
4050 case ir_intrinsic_shared_atomic_comp_swap:
4051 visit_shared_intrinsic(ir);
4052 return;
4053
4054 case ir_intrinsic_image_load:
4055 case ir_intrinsic_image_store:
4056 case ir_intrinsic_image_atomic_add:
4057 case ir_intrinsic_image_atomic_min:
4058 case ir_intrinsic_image_atomic_max:
4059 case ir_intrinsic_image_atomic_and:
4060 case ir_intrinsic_image_atomic_or:
4061 case ir_intrinsic_image_atomic_xor:
4062 case ir_intrinsic_image_atomic_exchange:
4063 case ir_intrinsic_image_atomic_comp_swap:
4064 case ir_intrinsic_image_size:
4065 case ir_intrinsic_image_samples:
4066 visit_image_intrinsic(ir);
4067 return;
4068
4069 case ir_intrinsic_shader_clock:
4070 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4071 return;
4072
4073 case ir_intrinsic_vote_all:
4074 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4075 return;
4076 case ir_intrinsic_vote_any:
4077 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4078 return;
4079 case ir_intrinsic_vote_eq:
4080 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4081 return;
4082 case ir_intrinsic_ballot:
4083 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4084 return;
4085 case ir_intrinsic_read_first_invocation:
4086 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4087 return;
4088 case ir_intrinsic_read_invocation:
4089 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4090 return;
4091
4092 case ir_intrinsic_invalid:
4093 case ir_intrinsic_generic_load:
4094 case ir_intrinsic_generic_store:
4095 case ir_intrinsic_generic_atomic_add:
4096 case ir_intrinsic_generic_atomic_and:
4097 case ir_intrinsic_generic_atomic_or:
4098 case ir_intrinsic_generic_atomic_xor:
4099 case ir_intrinsic_generic_atomic_min:
4100 case ir_intrinsic_generic_atomic_max:
4101 case ir_intrinsic_generic_atomic_exchange:
4102 case ir_intrinsic_generic_atomic_comp_swap:
4103 case ir_intrinsic_begin_invocation_interlock:
4104 case ir_intrinsic_end_invocation_interlock:
4105 unreachable("Invalid intrinsic");
4106 }
4107 }
4108
4109 void
4110 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4111 unsigned *array_elements,
4112 uint16_t *index,
4113 st_src_reg *indirect,
4114 unsigned *location)
4115 {
4116 switch (tail->ir_type) {
4117 case ir_type_dereference_record: {
4118 ir_dereference_record *deref_record = tail->as_dereference_record();
4119 const glsl_type *struct_type = deref_record->record->type;
4120 int field_index = deref_record->field_idx;
4121
4122 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4123
4124 assert(field_index >= 0);
4125 *location += struct_type->struct_location_offset(field_index);
4126 break;
4127 }
4128
4129 case ir_type_dereference_array: {
4130 ir_dereference_array *deref_arr = tail->as_dereference_array();
4131
4132 void *mem_ctx = ralloc_parent(deref_arr);
4133 ir_constant *array_index =
4134 deref_arr->array_index->constant_expression_value(mem_ctx);
4135
4136 if (!array_index) {
4137 st_src_reg temp_reg;
4138 st_dst_reg temp_dst;
4139
4140 temp_reg = get_temp(glsl_type::uint_type);
4141 temp_dst = st_dst_reg(temp_reg);
4142 temp_dst.writemask = 1;
4143
4144 deref_arr->array_index->accept(this);
4145 if (*array_elements != 1)
4146 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4147 else
4148 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4149
4150 if (indirect->file == PROGRAM_UNDEFINED)
4151 *indirect = temp_reg;
4152 else {
4153 temp_dst = st_dst_reg(*indirect);
4154 temp_dst.writemask = 1;
4155 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4156 }
4157 } else
4158 *index += array_index->value.u[0] * *array_elements;
4159
4160 *array_elements *= deref_arr->array->type->length;
4161
4162 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4163 break;
4164 }
4165 default:
4166 break;
4167 }
4168 }
4169
4170 void
4171 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4172 unsigned *array_size,
4173 unsigned *base,
4174 uint16_t *index,
4175 st_src_reg *reladdr,
4176 bool opaque)
4177 {
4178 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4179 unsigned location = 0;
4180 ir_variable *var = ir->variable_referenced();
4181
4182 reladdr->reset();
4183
4184 *base = 0;
4185 *array_size = 1;
4186
4187 assert(var);
4188 location = var->data.location;
4189 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4190
4191 /*
4192 * If we end up with no indirect then adjust the base to the index,
4193 * and set the array size to 1.
4194 */
4195 if (reladdr->file == PROGRAM_UNDEFINED) {
4196 *base = *index;
4197 *array_size = 1;
4198 }
4199
4200 if (opaque) {
4201 assert(location != 0xffffffff);
4202 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4203 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4204 }
4205 }
4206
4207 st_src_reg
4208 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4209 {
4210 if (offset.reladdr || offset.reladdr2 ||
4211 offset.has_index2 ||
4212 offset.file == PROGRAM_UNIFORM ||
4213 offset.file == PROGRAM_CONSTANT ||
4214 offset.file == PROGRAM_STATE_VAR) {
4215 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4216 st_dst_reg tmp_dst = st_dst_reg(tmp);
4217 tmp_dst.writemask = WRITEMASK_XY;
4218 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4219 return tmp;
4220 }
4221
4222 return offset;
4223 }
4224
4225 bool
4226 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4227 {
4228 ir_variable *var = ir->variable_referenced();
4229
4230 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4231 !(ir->type->is_image() || ir->type->is_sampler()))
4232 return false;
4233
4234 /* Convert from bound sampler/image to bindless handle. */
4235 bool is_image = ir->type->is_image();
4236 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4237 uint16_t index = 0;
4238 unsigned array_size = 1, base = 0;
4239 st_src_reg reladdr;
4240 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4241
4242 resource.index = index;
4243 if (reladdr.file != PROGRAM_UNDEFINED) {
4244 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4245 *resource.reladdr = reladdr;
4246 emit_arl(ir, sampler_reladdr, reladdr);
4247 }
4248
4249 this->result = get_temp(glsl_type::uvec2_type);
4250 st_dst_reg dst(this->result);
4251 dst.writemask = WRITEMASK_XY;
4252
4253 glsl_to_tgsi_instruction *inst = emit_asm(
4254 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4255
4256 inst->tex_target = ir->type->sampler_index();
4257 inst->resource = resource;
4258 inst->sampler_array_size = array_size;
4259 inst->sampler_base = base;
4260
4261 return true;
4262 }
4263
4264 void
4265 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4266 {
4267 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4268 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4269 st_src_reg levels_src, reladdr;
4270 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4271 glsl_to_tgsi_instruction *inst = NULL;
4272 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4273 const glsl_type *sampler_type = ir->sampler->type;
4274 unsigned sampler_array_size = 1, sampler_base = 0;
4275 bool is_cube_array = false, is_cube_shadow = false;
4276 ir_variable *var = ir->sampler->variable_referenced();
4277 unsigned i;
4278
4279 /* if we are a cube array sampler or a cube shadow */
4280 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4281 is_cube_array = sampler_type->sampler_array;
4282 is_cube_shadow = sampler_type->sampler_shadow;
4283 }
4284
4285 if (ir->coordinate) {
4286 ir->coordinate->accept(this);
4287
4288 /* Put our coords in a temp. We'll need to modify them for shadow,
4289 * projection, or LOD, so the only case we'd use it as-is is if
4290 * we're doing plain old texturing. The optimization passes on
4291 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4292 */
4293 coord = get_temp(glsl_type::vec4_type);
4294 coord_dst = st_dst_reg(coord);
4295 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4296 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4297 }
4298
4299 if (ir->projector) {
4300 ir->projector->accept(this);
4301 projector = this->result;
4302 }
4303
4304 /* Storage for our result. Ideally for an assignment we'd be using
4305 * the actual storage for the result here, instead.
4306 */
4307 result_src = get_temp(ir->type);
4308 result_dst = st_dst_reg(result_src);
4309 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4310
4311 switch (ir->op) {
4312 case ir_tex:
4313 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4314 if (ir->offset) {
4315 ir->offset->accept(this);
4316 offset[0] = this->result;
4317 }
4318 break;
4319 case ir_txb:
4320 if (is_cube_array || is_cube_shadow) {
4321 opcode = TGSI_OPCODE_TXB2;
4322 }
4323 else {
4324 opcode = TGSI_OPCODE_TXB;
4325 }
4326 ir->lod_info.bias->accept(this);
4327 lod_info = this->result;
4328 if (ir->offset) {
4329 ir->offset->accept(this);
4330 offset[0] = this->result;
4331 }
4332 break;
4333 case ir_txl:
4334 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4335 opcode = TGSI_OPCODE_TEX_LZ;
4336 } else {
4337 opcode = is_cube_array ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4338 ir->lod_info.lod->accept(this);
4339 lod_info = this->result;
4340 }
4341 if (ir->offset) {
4342 ir->offset->accept(this);
4343 offset[0] = this->result;
4344 }
4345 break;
4346 case ir_txd:
4347 opcode = TGSI_OPCODE_TXD;
4348 ir->lod_info.grad.dPdx->accept(this);
4349 dx = this->result;
4350 ir->lod_info.grad.dPdy->accept(this);
4351 dy = this->result;
4352 if (ir->offset) {
4353 ir->offset->accept(this);
4354 offset[0] = this->result;
4355 }
4356 break;
4357 case ir_txs:
4358 opcode = TGSI_OPCODE_TXQ;
4359 ir->lod_info.lod->accept(this);
4360 lod_info = this->result;
4361 break;
4362 case ir_query_levels:
4363 opcode = TGSI_OPCODE_TXQ;
4364 lod_info = undef_src;
4365 levels_src = get_temp(ir->type);
4366 break;
4367 case ir_txf:
4368 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4369 opcode = TGSI_OPCODE_TXF_LZ;
4370 } else {
4371 opcode = TGSI_OPCODE_TXF;
4372 ir->lod_info.lod->accept(this);
4373 lod_info = this->result;
4374 }
4375 if (ir->offset) {
4376 ir->offset->accept(this);
4377 offset[0] = this->result;
4378 }
4379 break;
4380 case ir_txf_ms:
4381 opcode = TGSI_OPCODE_TXF;
4382 ir->lod_info.sample_index->accept(this);
4383 sample_index = this->result;
4384 break;
4385 case ir_tg4:
4386 opcode = TGSI_OPCODE_TG4;
4387 ir->lod_info.component->accept(this);
4388 component = this->result;
4389 if (ir->offset) {
4390 ir->offset->accept(this);
4391 if (ir->offset->type->is_array()) {
4392 const glsl_type *elt_type = ir->offset->type->fields.array;
4393 for (i = 0; i < ir->offset->type->length; i++) {
4394 offset[i] = this->result;
4395 offset[i].index += i * type_size(elt_type);
4396 offset[i].type = elt_type->base_type;
4397 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4398 offset[i] = canonicalize_gather_offset(offset[i]);
4399 }
4400 } else {
4401 offset[0] = canonicalize_gather_offset(this->result);
4402 }
4403 }
4404 break;
4405 case ir_lod:
4406 opcode = TGSI_OPCODE_LODQ;
4407 break;
4408 case ir_texture_samples:
4409 opcode = TGSI_OPCODE_TXQS;
4410 break;
4411 case ir_samples_identical:
4412 unreachable("Unexpected ir_samples_identical opcode");
4413 }
4414
4415 if (ir->projector) {
4416 if (opcode == TGSI_OPCODE_TEX) {
4417 /* Slot the projector in as the last component of the coord. */
4418 coord_dst.writemask = WRITEMASK_W;
4419 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4420 coord_dst.writemask = WRITEMASK_XYZW;
4421 opcode = TGSI_OPCODE_TXP;
4422 } else {
4423 st_src_reg coord_w = coord;
4424 coord_w.swizzle = SWIZZLE_WWWW;
4425
4426 /* For the other TEX opcodes there's no projective version
4427 * since the last slot is taken up by LOD info. Do the
4428 * projective divide now.
4429 */
4430 coord_dst.writemask = WRITEMASK_W;
4431 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4432
4433 /* In the case where we have to project the coordinates "by hand,"
4434 * the shadow comparator value must also be projected.
4435 */
4436 st_src_reg tmp_src = coord;
4437 if (ir->shadow_comparator) {
4438 /* Slot the shadow value in as the second to last component of the
4439 * coord.
4440 */
4441 ir->shadow_comparator->accept(this);
4442
4443 tmp_src = get_temp(glsl_type::vec4_type);
4444 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4445
4446 /* Projective division not allowed for array samplers. */
4447 assert(!sampler_type->sampler_array);
4448
4449 tmp_dst.writemask = WRITEMASK_Z;
4450 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4451
4452 tmp_dst.writemask = WRITEMASK_XY;
4453 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4454 }
4455
4456 coord_dst.writemask = WRITEMASK_XYZ;
4457 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4458
4459 coord_dst.writemask = WRITEMASK_XYZW;
4460 coord.swizzle = SWIZZLE_XYZW;
4461 }
4462 }
4463
4464 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4465 * shadow comparator was put in the correct place (and projected) by the
4466 * code, above, that handles by-hand projection.
4467 */
4468 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4469 /* Slot the shadow value in as the second to last component of the
4470 * coord.
4471 */
4472 ir->shadow_comparator->accept(this);
4473
4474 if (is_cube_array) {
4475 cube_sc = get_temp(glsl_type::float_type);
4476 cube_sc_dst = st_dst_reg(cube_sc);
4477 cube_sc_dst.writemask = WRITEMASK_X;
4478 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4479 cube_sc_dst.writemask = WRITEMASK_X;
4480 }
4481 else {
4482 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4483 sampler_type->sampler_array) ||
4484 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4485 coord_dst.writemask = WRITEMASK_W;
4486 } else {
4487 coord_dst.writemask = WRITEMASK_Z;
4488 }
4489 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4490 coord_dst.writemask = WRITEMASK_XYZW;
4491 }
4492 }
4493
4494 if (ir->op == ir_txf_ms) {
4495 coord_dst.writemask = WRITEMASK_W;
4496 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4497 coord_dst.writemask = WRITEMASK_XYZW;
4498 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4499 opcode == TGSI_OPCODE_TXF) {
4500 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4501 coord_dst.writemask = WRITEMASK_W;
4502 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4503 coord_dst.writemask = WRITEMASK_XYZW;
4504 }
4505
4506 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4507
4508 uint16_t index = 0;
4509 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4510 &index, &reladdr, !var->contains_bindless());
4511
4512 sampler.index = index;
4513 if (reladdr.file != PROGRAM_UNDEFINED) {
4514 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4515 *sampler.reladdr = reladdr;
4516 emit_arl(ir, sampler_reladdr, reladdr);
4517 }
4518
4519 st_src_reg bindless;
4520 if (var->contains_bindless()) {
4521 ir->sampler->accept(this);
4522 bindless = this->result;
4523 }
4524
4525 if (opcode == TGSI_OPCODE_TXD)
4526 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4527 else if (opcode == TGSI_OPCODE_TXQ) {
4528 if (ir->op == ir_query_levels) {
4529 /* the level is stored in W */
4530 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4531 result_dst.writemask = WRITEMASK_X;
4532 levels_src.swizzle = SWIZZLE_WWWW;
4533 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4534 } else
4535 inst = emit_asm(ir, opcode, result_dst, lod_info);
4536 } else if (opcode == TGSI_OPCODE_TXQS) {
4537 inst = emit_asm(ir, opcode, result_dst);
4538 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4539 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4540 } else if (opcode == TGSI_OPCODE_TEX2) {
4541 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4542 } else if (opcode == TGSI_OPCODE_TG4) {
4543 if (is_cube_array && ir->shadow_comparator) {
4544 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4545 } else {
4546 inst = emit_asm(ir, opcode, result_dst, coord, component);
4547 }
4548 } else
4549 inst = emit_asm(ir, opcode, result_dst, coord);
4550
4551 if (ir->shadow_comparator)
4552 inst->tex_shadow = GL_TRUE;
4553
4554 if (var->contains_bindless()) {
4555 inst->resource = bindless;
4556 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4557 SWIZZLE_X, SWIZZLE_Y);
4558 } else {
4559 inst->resource = sampler;
4560 inst->sampler_array_size = sampler_array_size;
4561 inst->sampler_base = sampler_base;
4562 }
4563
4564 if (ir->offset) {
4565 if (!inst->tex_offsets)
4566 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4567 MAX_GLSL_TEXTURE_OFFSET);
4568
4569 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4570 offset[i].file != PROGRAM_UNDEFINED; i++)
4571 inst->tex_offsets[i] = offset[i];
4572 inst->tex_offset_num_offset = i;
4573 }
4574
4575 inst->tex_target = sampler_type->sampler_index();
4576 inst->tex_type = ir->type->base_type;
4577
4578 this->result = result_src;
4579 }
4580
4581 void
4582 glsl_to_tgsi_visitor::visit(ir_return *ir)
4583 {
4584 assert(!ir->get_value());
4585
4586 emit_asm(ir, TGSI_OPCODE_RET);
4587 }
4588
4589 void
4590 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4591 {
4592 if (ir->condition) {
4593 ir->condition->accept(this);
4594 st_src_reg condition = this->result;
4595
4596 /* Convert the bool condition to a float so we can negate. */
4597 if (native_integers) {
4598 st_src_reg temp = get_temp(ir->condition->type);
4599 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4600 condition, st_src_reg_for_float(1.0));
4601 condition = temp;
4602 }
4603
4604 condition.negate = ~condition.negate;
4605 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4606 } else {
4607 /* unconditional kil */
4608 emit_asm(ir, TGSI_OPCODE_KILL);
4609 }
4610 }
4611
4612 void
4613 glsl_to_tgsi_visitor::visit(ir_if *ir)
4614 {
4615 enum tgsi_opcode if_opcode;
4616 glsl_to_tgsi_instruction *if_inst;
4617
4618 ir->condition->accept(this);
4619 assert(this->result.file != PROGRAM_UNDEFINED);
4620
4621 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4622
4623 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4624
4625 this->instructions.push_tail(if_inst);
4626
4627 visit_exec_list(&ir->then_instructions, this);
4628
4629 if (!ir->else_instructions.is_empty()) {
4630 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4631 visit_exec_list(&ir->else_instructions, this);
4632 }
4633
4634 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4635 }
4636
4637
4638 void
4639 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4640 {
4641 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4642
4643 ir->stream->accept(this);
4644 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4645 }
4646
4647 void
4648 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4649 {
4650 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4651
4652 ir->stream->accept(this);
4653 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4654 }
4655
4656 void
4657 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4658 {
4659 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4660 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4661
4662 emit_asm(ir, TGSI_OPCODE_BARRIER);
4663 }
4664
4665 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4666 {
4667 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4668
4669 result.file = PROGRAM_UNDEFINED;
4670 next_temp = 1;
4671 array_sizes = NULL;
4672 max_num_arrays = 0;
4673 next_array = 0;
4674 num_inputs = 0;
4675 num_outputs = 0;
4676 num_input_arrays = 0;
4677 num_output_arrays = 0;
4678 num_atomics = 0;
4679 num_atomic_arrays = 0;
4680 num_immediates = 0;
4681 num_address_regs = 0;
4682 samplers_used = 0;
4683 images_used = 0;
4684 indirect_addr_consts = false;
4685 wpos_transform_const = -1;
4686 native_integers = false;
4687 mem_ctx = ralloc_context(NULL);
4688 ctx = NULL;
4689 prog = NULL;
4690 precise = 0;
4691 need_uarl = false;
4692 shader_program = NULL;
4693 shader = NULL;
4694 options = NULL;
4695 have_sqrt = false;
4696 have_fma = false;
4697 use_shared_memory = false;
4698 has_tex_txf_lz = false;
4699 variables = NULL;
4700 }
4701
4702 static void var_destroy(struct hash_entry *entry)
4703 {
4704 variable_storage *storage = (variable_storage *)entry->data;
4705
4706 delete storage;
4707 }
4708
4709 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4710 {
4711 _mesa_hash_table_destroy(variables, var_destroy);
4712 free(array_sizes);
4713 ralloc_free(mem_ctx);
4714 }
4715
4716 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4717 {
4718 delete v;
4719 }
4720
4721
4722 /**
4723 * Count resources used by the given gpu program (number of texture
4724 * samplers, etc).
4725 */
4726 static void
4727 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4728 {
4729 v->samplers_used = 0;
4730 v->images_used = 0;
4731 prog->info.textures_used_by_txf = 0;
4732
4733 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4734 if (inst->info->is_tex) {
4735 for (int i = 0; i < inst->sampler_array_size; i++) {
4736 unsigned idx = inst->sampler_base + i;
4737 v->samplers_used |= 1u << idx;
4738
4739 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4740 v->sampler_types[idx] = inst->tex_type;
4741 v->sampler_targets[idx] =
4742 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4743
4744 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4745 prog->info.textures_used_by_txf |= 1u << idx;
4746 }
4747 }
4748 }
4749
4750 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4751 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4752
4753 if (inst->resource.file != PROGRAM_UNDEFINED && (
4754 is_resource_instruction(inst->op) ||
4755 inst->op == TGSI_OPCODE_STORE)) {
4756 if (inst->resource.file == PROGRAM_MEMORY) {
4757 v->use_shared_memory = true;
4758 } else if (inst->resource.file == PROGRAM_IMAGE) {
4759 for (int i = 0; i < inst->sampler_array_size; i++) {
4760 unsigned idx = inst->sampler_base + i;
4761 v->images_used |= 1 << idx;
4762 v->image_targets[idx] =
4763 st_translate_texture_target(inst->tex_target, false);
4764 v->image_formats[idx] = inst->image_format;
4765 v->image_wr[idx] = !inst->read_only;
4766 }
4767 }
4768 }
4769 }
4770 prog->SamplersUsed = v->samplers_used;
4771
4772 if (v->shader_program != NULL)
4773 _mesa_update_shader_textures_used(v->shader_program, prog);
4774 }
4775
4776 /**
4777 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4778 * are read from the given src in this instruction
4779 */
4780 static int
4781 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4782 {
4783 int read_mask = 0, comp;
4784
4785 /* Now, given the src swizzle and the written channels, find which
4786 * components are actually read
4787 */
4788 for (comp = 0; comp < 4; ++comp) {
4789 const unsigned coord = GET_SWZ(src.swizzle, comp);
4790 assert(coord < 4);
4791 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4792 read_mask |= 1 << coord;
4793 }
4794
4795 return read_mask;
4796 }
4797
4798 /**
4799 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4800 * instruction is the first instruction to write to register T0. There are
4801 * several lowering passes done in GLSL IR (e.g. branches and
4802 * relative addressing) that create a large number of conditional assignments
4803 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4804 *
4805 * Here is why this conversion is safe:
4806 * CMP T0, T1 T2 T0 can be expanded to:
4807 * if (T1 < 0.0)
4808 * MOV T0, T2;
4809 * else
4810 * MOV T0, T0;
4811 *
4812 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4813 * as the original program. If (T1 < 0.0) evaluates to false, executing
4814 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4815 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4816 * because any instruction that was going to read from T0 after this was going
4817 * to read a garbage value anyway.
4818 */
4819 void
4820 glsl_to_tgsi_visitor::simplify_cmp(void)
4821 {
4822 int tempWritesSize = 0;
4823 unsigned *tempWrites = NULL;
4824 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4825
4826 memset(outputWrites, 0, sizeof(outputWrites));
4827
4828 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4829 unsigned prevWriteMask = 0;
4830
4831 /* Give up if we encounter relative addressing or flow control. */
4832 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4833 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4834 inst->info->is_branch ||
4835 inst->op == TGSI_OPCODE_CONT ||
4836 inst->op == TGSI_OPCODE_END ||
4837 inst->op == TGSI_OPCODE_RET) {
4838 break;
4839 }
4840
4841 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4842 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4843 prevWriteMask = outputWrites[inst->dst[0].index];
4844 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4845 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4846 if (inst->dst[0].index >= tempWritesSize) {
4847 const int inc = 4096;
4848
4849 tempWrites = (unsigned*)
4850 realloc(tempWrites,
4851 (tempWritesSize + inc) * sizeof(unsigned));
4852 if (!tempWrites)
4853 return;
4854
4855 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4856 tempWritesSize += inc;
4857 }
4858
4859 prevWriteMask = tempWrites[inst->dst[0].index];
4860 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4861 } else
4862 continue;
4863
4864 /* For a CMP to be considered a conditional write, the destination
4865 * register and source register two must be the same. */
4866 if (inst->op == TGSI_OPCODE_CMP
4867 && !(inst->dst[0].writemask & prevWriteMask)
4868 && inst->src[2].file == inst->dst[0].file
4869 && inst->src[2].index == inst->dst[0].index
4870 && inst->dst[0].writemask ==
4871 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4872
4873 inst->op = TGSI_OPCODE_MOV;
4874 inst->info = tgsi_get_opcode_info(inst->op);
4875 inst->src[0] = inst->src[1];
4876 }
4877 }
4878
4879 free(tempWrites);
4880 }
4881
4882 static void
4883 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4884 {
4885 if (src && src->file == PROGRAM_TEMPORARY) {
4886 int old_idx = src->index;
4887 if (renames[old_idx].valid)
4888 src->index = renames[old_idx].new_reg;
4889 }
4890 }
4891
4892 /* Replaces all references to a temporary register index with another index. */
4893 void
4894 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4895 {
4896 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4897 unsigned j;
4898 for (j = 0; j < num_inst_src_regs(inst); j++) {
4899 rename_temp_handle_src(renames, &inst->src[j]);
4900 rename_temp_handle_src(renames, inst->src[j].reladdr);
4901 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4902 }
4903
4904 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4905 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4906 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4907 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4908 }
4909
4910 rename_temp_handle_src(renames, &inst->resource);
4911 rename_temp_handle_src(renames, inst->resource.reladdr);
4912 rename_temp_handle_src(renames, inst->resource.reladdr2);
4913
4914 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4915 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4916 int old_idx = inst->dst[j].index;
4917 if (renames[old_idx].valid)
4918 inst->dst[j].index = renames[old_idx].new_reg;
4919 }
4920 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4921 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4922 }
4923 }
4924 }
4925
4926 void
4927 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4928 {
4929 int depth = 0; /* loop depth */
4930 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4931 unsigned i = 0, j;
4932
4933 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4934 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4935 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4936 if (first_writes[inst->dst[j].index] == -1)
4937 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4938 }
4939 }
4940
4941 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4942 if (depth++ == 0)
4943 loop_start = i;
4944 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4945 if (--depth == 0)
4946 loop_start = -1;
4947 }
4948 assert(depth >= 0);
4949 i++;
4950 }
4951 }
4952
4953 void
4954 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
4955 {
4956 int depth = 0; /* loop depth */
4957 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4958 unsigned i = 0, j;
4959
4960 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4961 for (j = 0; j < num_inst_src_regs(inst); j++) {
4962 if (inst->src[j].file == PROGRAM_TEMPORARY) {
4963 if (first_reads[inst->src[j].index] == -1)
4964 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
4965 }
4966 }
4967 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4968 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
4969 if (first_reads[inst->tex_offsets[j].index] == -1)
4970 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
4971 }
4972 }
4973 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4974 if (depth++ == 0)
4975 loop_start = i;
4976 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4977 if (--depth == 0)
4978 loop_start = -1;
4979 }
4980 assert(depth >= 0);
4981 i++;
4982 }
4983 }
4984
4985 void
4986 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
4987 {
4988 int depth = 0; /* loop depth */
4989 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4990 unsigned i = 0, j;
4991 int k;
4992 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4993 for (j = 0; j < num_inst_src_regs(inst); j++) {
4994 if (inst->src[j].file == PROGRAM_TEMPORARY)
4995 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
4996 }
4997 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4998 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4999 if (first_writes[inst->dst[j].index] == -1)
5000 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5001 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
5002 }
5003 }
5004 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5005 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
5006 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
5007 }
5008 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5009 if (depth++ == 0)
5010 loop_start = i;
5011 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5012 if (--depth == 0) {
5013 loop_start = -1;
5014 for (k = 0; k < this->next_temp; k++) {
5015 if (last_reads[k] == -2) {
5016 last_reads[k] = i;
5017 }
5018 }
5019 }
5020 }
5021 assert(depth >= 0);
5022 i++;
5023 }
5024 }
5025
5026 void
5027 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
5028 {
5029 int depth = 0; /* loop depth */
5030 int i = 0, k;
5031 unsigned j;
5032
5033 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5034 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5035 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5036 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5037 }
5038
5039 if (inst->op == TGSI_OPCODE_BGNLOOP)
5040 depth++;
5041 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5042 if (--depth == 0) {
5043 for (k = 0; k < this->next_temp; k++) {
5044 if (last_writes[k] == -2) {
5045 last_writes[k] = i;
5046 }
5047 }
5048 }
5049 assert(depth >= 0);
5050 i++;
5051 }
5052 }
5053
5054 /*
5055 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5056 * channels for copy propagation and updates following instructions to
5057 * use the original versions.
5058 *
5059 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5060 * will occur. As an example, a TXP production before this pass:
5061 *
5062 * 0: MOV TEMP[1], INPUT[4].xyyy;
5063 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5064 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5065 *
5066 * and after:
5067 *
5068 * 0: MOV TEMP[1], INPUT[4].xyyy;
5069 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5070 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5071 *
5072 * which allows for dead code elimination on TEMP[1]'s writes.
5073 */
5074 void
5075 glsl_to_tgsi_visitor::copy_propagate(void)
5076 {
5077 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5078 glsl_to_tgsi_instruction *,
5079 this->next_temp * 4);
5080 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5081 int level = 0;
5082
5083 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5084 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5085 || inst->dst[0].index < this->next_temp);
5086
5087 /* First, do any copy propagation possible into the src regs. */
5088 for (int r = 0; r < 3; r++) {
5089 glsl_to_tgsi_instruction *first = NULL;
5090 bool good = true;
5091 int acp_base = inst->src[r].index * 4;
5092
5093 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5094 inst->src[r].reladdr ||
5095 inst->src[r].reladdr2)
5096 continue;
5097
5098 /* See if we can find entries in the ACP consisting of MOVs
5099 * from the same src register for all the swizzled channels
5100 * of this src register reference.
5101 */
5102 for (int i = 0; i < 4; i++) {
5103 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5104 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5105
5106 if (!copy_chan) {
5107 good = false;
5108 break;
5109 }
5110
5111 assert(acp_level[acp_base + src_chan] <= level);
5112
5113 if (!first) {
5114 first = copy_chan;
5115 } else {
5116 if (first->src[0].file != copy_chan->src[0].file ||
5117 first->src[0].index != copy_chan->src[0].index ||
5118 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5119 first->src[0].index2D != copy_chan->src[0].index2D) {
5120 good = false;
5121 break;
5122 }
5123 }
5124 }
5125
5126 if (good) {
5127 /* We've now validated that we can copy-propagate to
5128 * replace this src register reference. Do it.
5129 */
5130 inst->src[r].file = first->src[0].file;
5131 inst->src[r].index = first->src[0].index;
5132 inst->src[r].index2D = first->src[0].index2D;
5133 inst->src[r].has_index2 = first->src[0].has_index2;
5134 inst->src[r].double_reg2 = first->src[0].double_reg2;
5135 inst->src[r].array_id = first->src[0].array_id;
5136
5137 int swizzle = 0;
5138 for (int i = 0; i < 4; i++) {
5139 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5140 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5141 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5142 }
5143 inst->src[r].swizzle = swizzle;
5144 }
5145 }
5146
5147 switch (inst->op) {
5148 case TGSI_OPCODE_BGNLOOP:
5149 case TGSI_OPCODE_ENDLOOP:
5150 /* End of a basic block, clear the ACP entirely. */
5151 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5152 break;
5153
5154 case TGSI_OPCODE_IF:
5155 case TGSI_OPCODE_UIF:
5156 ++level;
5157 break;
5158
5159 case TGSI_OPCODE_ENDIF:
5160 case TGSI_OPCODE_ELSE:
5161 /* Clear all channels written inside the block from the ACP, but
5162 * leaving those that were not touched.
5163 */
5164 for (int r = 0; r < this->next_temp; r++) {
5165 for (int c = 0; c < 4; c++) {
5166 if (!acp[4 * r + c])
5167 continue;
5168
5169 if (acp_level[4 * r + c] >= level)
5170 acp[4 * r + c] = NULL;
5171 }
5172 }
5173 if (inst->op == TGSI_OPCODE_ENDIF)
5174 --level;
5175 break;
5176
5177 default:
5178 /* Continuing the block, clear any written channels from
5179 * the ACP.
5180 */
5181 for (int d = 0; d < 2; d++) {
5182 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5183 /* Any temporary might be written, so no copy propagation
5184 * across this instruction.
5185 */
5186 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5187 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5188 inst->dst[d].reladdr) {
5189 /* Any output might be written, so no copy propagation
5190 * from outputs across this instruction.
5191 */
5192 for (int r = 0; r < this->next_temp; r++) {
5193 for (int c = 0; c < 4; c++) {
5194 if (!acp[4 * r + c])
5195 continue;
5196
5197 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5198 acp[4 * r + c] = NULL;
5199 }
5200 }
5201 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5202 inst->dst[d].file == PROGRAM_OUTPUT) {
5203 /* Clear where it's used as dst. */
5204 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5205 for (int c = 0; c < 4; c++) {
5206 if (inst->dst[d].writemask & (1 << c))
5207 acp[4 * inst->dst[d].index + c] = NULL;
5208 }
5209 }
5210
5211 /* Clear where it's used as src. */
5212 for (int r = 0; r < this->next_temp; r++) {
5213 for (int c = 0; c < 4; c++) {
5214 if (!acp[4 * r + c])
5215 continue;
5216
5217 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5218
5219 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5220 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5221 inst->dst[d].writemask & (1 << src_chan)) {
5222 acp[4 * r + c] = NULL;
5223 }
5224 }
5225 }
5226 }
5227 }
5228 break;
5229 }
5230
5231 /* If this is a copy, add it to the ACP. */
5232 if (inst->op == TGSI_OPCODE_MOV &&
5233 inst->dst[0].file == PROGRAM_TEMPORARY &&
5234 !(inst->dst[0].file == inst->src[0].file &&
5235 inst->dst[0].index == inst->src[0].index) &&
5236 !inst->dst[0].reladdr &&
5237 !inst->dst[0].reladdr2 &&
5238 !inst->saturate &&
5239 inst->src[0].file != PROGRAM_ARRAY &&
5240 (inst->src[0].file != PROGRAM_OUTPUT ||
5241 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5242 !inst->src[0].reladdr &&
5243 !inst->src[0].reladdr2 &&
5244 !inst->src[0].negate &&
5245 !inst->src[0].abs) {
5246 for (int i = 0; i < 4; i++) {
5247 if (inst->dst[0].writemask & (1 << i)) {
5248 acp[4 * inst->dst[0].index + i] = inst;
5249 acp_level[4 * inst->dst[0].index + i] = level;
5250 }
5251 }
5252 }
5253 }
5254
5255 ralloc_free(acp_level);
5256 ralloc_free(acp);
5257 }
5258
5259 static void
5260 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5261 {
5262 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5263 /* Clear where it's used as src. */
5264 int swz = GET_SWZ(reladdr->swizzle, 0);
5265 writes[4 * reladdr->index + swz] = NULL;
5266 }
5267 }
5268
5269 /*
5270 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5271 * code elimination.
5272 *
5273 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5274 * will occur. As an example, a TXP production after copy propagation but
5275 * before this pass:
5276 *
5277 * 0: MOV TEMP[1], INPUT[4].xyyy;
5278 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5279 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5280 *
5281 * and after this pass:
5282 *
5283 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5284 */
5285 int
5286 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5287 {
5288 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5289 glsl_to_tgsi_instruction *,
5290 this->next_temp * 4);
5291 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5292 int level = 0;
5293 int removed = 0;
5294
5295 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5296 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5297 || inst->dst[0].index < this->next_temp);
5298
5299 switch (inst->op) {
5300 case TGSI_OPCODE_BGNLOOP:
5301 case TGSI_OPCODE_ENDLOOP:
5302 case TGSI_OPCODE_CONT:
5303 case TGSI_OPCODE_BRK:
5304 /* End of a basic block, clear the write array entirely.
5305 *
5306 * This keeps us from killing dead code when the writes are
5307 * on either side of a loop, even when the register isn't touched
5308 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5309 * dead code of this type, so it shouldn't make a difference as long as
5310 * the dead code elimination pass in the GLSL compiler does its job.
5311 */
5312 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5313 break;
5314
5315 case TGSI_OPCODE_ENDIF:
5316 case TGSI_OPCODE_ELSE:
5317 /* Promote the recorded level of all channels written inside the
5318 * preceding if or else block to the level above the if/else block.
5319 */
5320 for (int r = 0; r < this->next_temp; r++) {
5321 for (int c = 0; c < 4; c++) {
5322 if (!writes[4 * r + c])
5323 continue;
5324
5325 if (write_level[4 * r + c] == level)
5326 write_level[4 * r + c] = level-1;
5327 }
5328 }
5329 if (inst->op == TGSI_OPCODE_ENDIF)
5330 --level;
5331 break;
5332
5333 case TGSI_OPCODE_IF:
5334 case TGSI_OPCODE_UIF:
5335 ++level;
5336 /* fallthrough to default case to mark the condition as read */
5337 default:
5338 /* Continuing the block, clear any channels from the write array that
5339 * are read by this instruction.
5340 */
5341 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5342 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5343 /* Any temporary might be read, so no dead code elimination
5344 * across this instruction.
5345 */
5346 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5347 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5348 /* Clear where it's used as src. */
5349 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5350 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5351 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5352 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5353
5354 for (int c = 0; c < 4; c++) {
5355 if (src_chans & (1 << c))
5356 writes[4 * inst->src[i].index + c] = NULL;
5357 }
5358 }
5359 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5360 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5361 }
5362 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5363 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5364 /* Any temporary might be read, so no dead code elimination
5365 * across this instruction.
5366 */
5367 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5368 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5369 /* Clear where it's used as src. */
5370 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5371 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5372 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5373 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5374
5375 for (int c = 0; c < 4; c++) {
5376 if (src_chans & (1 << c))
5377 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5378 }
5379 }
5380 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5381 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5382 }
5383
5384 if (inst->resource.file == PROGRAM_TEMPORARY) {
5385 int src_chans;
5386
5387 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5388 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5389 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5390 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5391
5392 for (int c = 0; c < 4; c++) {
5393 if (src_chans & (1 << c))
5394 writes[4 * inst->resource.index + c] = NULL;
5395 }
5396 }
5397 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5398 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5399
5400 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5401 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5402 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5403 }
5404 break;
5405 }
5406
5407 /* If this instruction writes to a temporary, add it to the write array.
5408 * If there is already an instruction in the write array for one or more
5409 * of the channels, flag that channel write as dead.
5410 */
5411 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5412 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5413 !inst->dst[i].reladdr) {
5414 for (int c = 0; c < 4; c++) {
5415 if (inst->dst[i].writemask & (1 << c)) {
5416 if (writes[4 * inst->dst[i].index + c]) {
5417 if (write_level[4 * inst->dst[i].index + c] < level)
5418 continue;
5419 else
5420 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5421 }
5422 writes[4 * inst->dst[i].index + c] = inst;
5423 write_level[4 * inst->dst[i].index + c] = level;
5424 }
5425 }
5426 }
5427 }
5428 }
5429
5430 /* Anything still in the write array at this point is dead code. */
5431 for (int r = 0; r < this->next_temp; r++) {
5432 for (int c = 0; c < 4; c++) {
5433 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5434 if (inst)
5435 inst->dead_mask |= (1 << c);
5436 }
5437 }
5438
5439 /* Now actually remove the instructions that are completely dead and update
5440 * the writemask of other instructions with dead channels.
5441 */
5442 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5443 if (!inst->dead_mask || !inst->dst[0].writemask)
5444 continue;
5445 /* No amount of dead masks should remove memory stores */
5446 if (inst->info->is_store)
5447 continue;
5448
5449 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5450 inst->remove();
5451 delete inst;
5452 removed++;
5453 } else {
5454 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5455 if (inst->dead_mask == WRITEMASK_XY ||
5456 inst->dead_mask == WRITEMASK_ZW)
5457 inst->dst[0].writemask &= ~(inst->dead_mask);
5458 } else
5459 inst->dst[0].writemask &= ~(inst->dead_mask);
5460 }
5461 }
5462
5463 ralloc_free(write_level);
5464 ralloc_free(writes);
5465
5466 return removed;
5467 }
5468
5469 /* merge DFRACEXP instructions into one. */
5470 void
5471 glsl_to_tgsi_visitor::merge_two_dsts(void)
5472 {
5473 /* We never delete inst, but we may delete its successor. */
5474 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5475 glsl_to_tgsi_instruction *inst2;
5476 unsigned defined;
5477
5478 if (num_inst_dst_regs(inst) != 2)
5479 continue;
5480
5481 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5482 inst->dst[1].file != PROGRAM_UNDEFINED)
5483 continue;
5484
5485 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5486 inst->dst[1].file != PROGRAM_UNDEFINED);
5487
5488 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5489 defined = 1;
5490 else
5491 defined = 0;
5492
5493 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5494 while (!inst2->is_tail_sentinel()) {
5495 if (inst->op == inst2->op &&
5496 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5497 inst->src[0].file == inst2->src[0].file &&
5498 inst->src[0].index == inst2->src[0].index &&
5499 inst->src[0].type == inst2->src[0].type &&
5500 inst->src[0].swizzle == inst2->src[0].swizzle)
5501 break;
5502 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5503 }
5504
5505 if (inst2->is_tail_sentinel()) {
5506 /* Undefined destinations are not allowed, substitute with an unused
5507 * temporary register.
5508 */
5509 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5510 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5511 inst->dst[defined ^ 1].writemask = 0;
5512 continue;
5513 }
5514
5515 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5516 inst2->remove();
5517 delete inst2;
5518 }
5519 }
5520
5521 template <typename st_reg>
5522 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5523 {
5524 if (reg.file == PROGRAM_ARRAY) {
5525 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5526 has_indirect_access[reg.array_id] = true;
5527 if (reg.reladdr)
5528 test_indirect_access(*reg.reladdr, has_indirect_access);
5529 if (reg.reladdr2)
5530 test_indirect_access(*reg.reladdr2, has_indirect_access);
5531 }
5532 }
5533 }
5534
5535 template <typename st_reg>
5536 void remap_array(st_reg& reg, const int *array_remap_info,
5537 const bool *has_indirect_access)
5538 {
5539 if (reg.file == PROGRAM_ARRAY) {
5540 if (!has_indirect_access[reg.array_id]) {
5541 reg.file = PROGRAM_TEMPORARY;
5542 reg.index = reg.index + array_remap_info[reg.array_id];
5543 reg.array_id = 0;
5544 } else {
5545 reg.array_id = array_remap_info[reg.array_id];
5546 }
5547
5548 if (reg.reladdr)
5549 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5550
5551 if (reg.reladdr2)
5552 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5553 }
5554 }
5555
5556 /* One-dimensional arrays whose elements are only accessed directly are
5557 * replaced by an according set of temporary registers that then can become
5558 * subject to further optimization steps like copy propagation and
5559 * register merging.
5560 */
5561 void
5562 glsl_to_tgsi_visitor::split_arrays(void)
5563 {
5564 if (!next_array)
5565 return;
5566
5567 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5568
5569 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5570 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5571 test_indirect_access(inst->src[j], has_indirect_access);
5572
5573 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5574 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5575
5576 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5577 test_indirect_access(inst->dst[j], has_indirect_access);
5578
5579 test_indirect_access(inst->resource, has_indirect_access);
5580 }
5581
5582 unsigned array_offset = 0;
5583 unsigned n_remaining_arrays = 0;
5584
5585 /* Double use: For arrays that get split this value will contain
5586 * the base index of the temporary registers this array is replaced
5587 * with. For arrays that remain it contains the new array ID.
5588 */
5589 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5590 next_array + 1);
5591
5592 for (unsigned i = 1; i <= next_array; ++i) {
5593 if (!has_indirect_access[i]) {
5594 array_remap_info[i] = this->next_temp + array_offset;
5595 array_offset += array_sizes[i - 1];
5596 } else {
5597 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5598 array_remap_info[i] = ++n_remaining_arrays;
5599 }
5600 }
5601
5602 if (next_array != n_remaining_arrays) {
5603 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5604 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5605 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5606
5607 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5608 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5609
5610 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5611 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5612 }
5613 remap_array(inst->resource, array_remap_info, has_indirect_access);
5614 }
5615 }
5616
5617 ralloc_free(has_indirect_access);
5618 this->next_temp += array_offset;
5619 next_array = n_remaining_arrays;
5620 }
5621
5622 /* Merges temporary registers together where possible to reduce the number of
5623 * registers needed to run a program.
5624 *
5625 * Produces optimal code only after copy propagation and dead code elimination
5626 * have been run. */
5627 void
5628 glsl_to_tgsi_visitor::merge_registers(void)
5629 {
5630 class array_live_range *arr_live_ranges = NULL;
5631
5632 struct register_live_range *reg_live_ranges =
5633 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5634
5635 if (this->next_array > 0) {
5636 arr_live_ranges = new array_live_range[this->next_array];
5637 for (unsigned i = 0; i < this->next_array; ++i)
5638 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5639 }
5640
5641
5642 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5643 this->next_temp, reg_live_ranges,
5644 this->next_array, arr_live_ranges)) {
5645 struct rename_reg_pair *renames =
5646 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5647 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5648 reg_live_ranges, renames);
5649 rename_temp_registers(renames);
5650
5651 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5652 &this->instructions, arr_live_ranges);
5653 }
5654
5655 if (arr_live_ranges)
5656 delete[] arr_live_ranges;
5657
5658 ralloc_free(reg_live_ranges);
5659 }
5660
5661 /* Reassign indices to temporary registers by reusing unused indices created
5662 * by optimization passes. */
5663 void
5664 glsl_to_tgsi_visitor::renumber_registers(void)
5665 {
5666 int i = 0;
5667 int new_index = 0;
5668 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5669 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5670
5671 for (i = 0; i < this->next_temp; i++) {
5672 first_writes[i] = -1;
5673 }
5674 get_first_temp_write(first_writes);
5675
5676 for (i = 0; i < this->next_temp; i++) {
5677 if (first_writes[i] < 0) continue;
5678 if (i != new_index) {
5679 renames[i].new_reg = new_index;
5680 renames[i].valid = true;
5681 }
5682 new_index++;
5683 }
5684
5685 rename_temp_registers(renames);
5686 this->next_temp = new_index;
5687 ralloc_free(renames);
5688 ralloc_free(first_writes);
5689 }
5690
5691 #ifndef NDEBUG
5692 void glsl_to_tgsi_visitor::print_stats()
5693 {
5694 int narray_registers = 0;
5695 for (unsigned i = 0; i < this->next_array; ++i)
5696 narray_registers += this->array_sizes[i];
5697
5698 int ninstructions = 0;
5699 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5700 ++ninstructions;
5701 }
5702
5703 simple_mtx_lock(&print_stats_mutex);
5704 stats_log << next_array << ", "
5705 << next_temp << ", "
5706 << narray_registers << ", "
5707 << next_temp + narray_registers << ", "
5708 << ninstructions << "\n";
5709 simple_mtx_unlock(&print_stats_mutex);
5710 }
5711 #endif
5712 /* ------------------------- TGSI conversion stuff -------------------------- */
5713
5714 /**
5715 * Intermediate state used during shader translation.
5716 */
5717 struct st_translate {
5718 struct ureg_program *ureg;
5719
5720 unsigned temps_size;
5721 struct ureg_dst *temps;
5722
5723 struct ureg_dst *arrays;
5724 unsigned num_temp_arrays;
5725 struct ureg_src *constants;
5726 int num_constants;
5727 struct ureg_src *immediates;
5728 int num_immediates;
5729 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5730 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5731 struct ureg_dst address[3];
5732 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5733 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5734 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5735 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5736 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5737 struct ureg_src shared_memory;
5738 unsigned *array_sizes;
5739 struct inout_decl *input_decls;
5740 unsigned num_input_decls;
5741 struct inout_decl *output_decls;
5742 unsigned num_output_decls;
5743
5744 const ubyte *inputMapping;
5745 const ubyte *outputMapping;
5746
5747 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5748 bool need_uarl;
5749 };
5750
5751 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5752 enum tgsi_semantic
5753 _mesa_sysval_to_semantic(unsigned sysval)
5754 {
5755 switch (sysval) {
5756 /* Vertex shader */
5757 case SYSTEM_VALUE_VERTEX_ID:
5758 return TGSI_SEMANTIC_VERTEXID;
5759 case SYSTEM_VALUE_INSTANCE_ID:
5760 return TGSI_SEMANTIC_INSTANCEID;
5761 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
5762 return TGSI_SEMANTIC_VERTEXID_NOBASE;
5763 case SYSTEM_VALUE_BASE_VERTEX:
5764 return TGSI_SEMANTIC_BASEVERTEX;
5765 case SYSTEM_VALUE_BASE_INSTANCE:
5766 return TGSI_SEMANTIC_BASEINSTANCE;
5767 case SYSTEM_VALUE_DRAW_ID:
5768 return TGSI_SEMANTIC_DRAWID;
5769
5770 /* Geometry shader */
5771 case SYSTEM_VALUE_INVOCATION_ID:
5772 return TGSI_SEMANTIC_INVOCATIONID;
5773
5774 /* Fragment shader */
5775 case SYSTEM_VALUE_FRAG_COORD:
5776 return TGSI_SEMANTIC_POSITION;
5777 case SYSTEM_VALUE_POINT_COORD:
5778 return TGSI_SEMANTIC_PCOORD;
5779 case SYSTEM_VALUE_FRONT_FACE:
5780 return TGSI_SEMANTIC_FACE;
5781 case SYSTEM_VALUE_SAMPLE_ID:
5782 return TGSI_SEMANTIC_SAMPLEID;
5783 case SYSTEM_VALUE_SAMPLE_POS:
5784 return TGSI_SEMANTIC_SAMPLEPOS;
5785 case SYSTEM_VALUE_SAMPLE_MASK_IN:
5786 return TGSI_SEMANTIC_SAMPLEMASK;
5787 case SYSTEM_VALUE_HELPER_INVOCATION:
5788 return TGSI_SEMANTIC_HELPER_INVOCATION;
5789
5790 /* Tessellation shader */
5791 case SYSTEM_VALUE_TESS_COORD:
5792 return TGSI_SEMANTIC_TESSCOORD;
5793 case SYSTEM_VALUE_VERTICES_IN:
5794 return TGSI_SEMANTIC_VERTICESIN;
5795 case SYSTEM_VALUE_PRIMITIVE_ID:
5796 return TGSI_SEMANTIC_PRIMID;
5797 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
5798 return TGSI_SEMANTIC_TESSOUTER;
5799 case SYSTEM_VALUE_TESS_LEVEL_INNER:
5800 return TGSI_SEMANTIC_TESSINNER;
5801
5802 /* Compute shader */
5803 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
5804 return TGSI_SEMANTIC_THREAD_ID;
5805 case SYSTEM_VALUE_WORK_GROUP_ID:
5806 return TGSI_SEMANTIC_BLOCK_ID;
5807 case SYSTEM_VALUE_NUM_WORK_GROUPS:
5808 return TGSI_SEMANTIC_GRID_SIZE;
5809 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
5810 return TGSI_SEMANTIC_BLOCK_SIZE;
5811
5812 /* ARB_shader_ballot */
5813 case SYSTEM_VALUE_SUBGROUP_SIZE:
5814 return TGSI_SEMANTIC_SUBGROUP_SIZE;
5815 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
5816 return TGSI_SEMANTIC_SUBGROUP_INVOCATION;
5817 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
5818 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
5819 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
5820 return TGSI_SEMANTIC_SUBGROUP_GE_MASK;
5821 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
5822 return TGSI_SEMANTIC_SUBGROUP_GT_MASK;
5823 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
5824 return TGSI_SEMANTIC_SUBGROUP_LE_MASK;
5825 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
5826 return TGSI_SEMANTIC_SUBGROUP_LT_MASK;
5827
5828 /* Unhandled */
5829 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
5830 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
5831 case SYSTEM_VALUE_VERTEX_CNT:
5832 case SYSTEM_VALUE_BARYCENTRIC_PIXEL:
5833 case SYSTEM_VALUE_BARYCENTRIC_SAMPLE:
5834 case SYSTEM_VALUE_BARYCENTRIC_CENTROID:
5835 case SYSTEM_VALUE_BARYCENTRIC_SIZE:
5836 default:
5837 assert(!"Unexpected SYSTEM_VALUE_ enum");
5838 return TGSI_SEMANTIC_COUNT;
5839 }
5840 }
5841
5842 /**
5843 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5844 */
5845 static struct ureg_src
5846 emit_immediate(struct st_translate *t,
5847 gl_constant_value values[4],
5848 GLenum type, int size)
5849 {
5850 struct ureg_program *ureg = t->ureg;
5851
5852 switch (type) {
5853 case GL_FLOAT:
5854 return ureg_DECL_immediate(ureg, &values[0].f, size);
5855 case GL_DOUBLE:
5856 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5857 case GL_INT64_ARB:
5858 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5859 case GL_UNSIGNED_INT64_ARB:
5860 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5861 case GL_INT:
5862 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5863 case GL_UNSIGNED_INT:
5864 case GL_BOOL:
5865 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5866 default:
5867 assert(!"should not get here - type must be float, int, uint, or bool");
5868 return ureg_src_undef();
5869 }
5870 }
5871
5872 /**
5873 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5874 */
5875 static struct ureg_dst
5876 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5877 unsigned array_id)
5878 {
5879 unsigned array;
5880
5881 switch (file) {
5882 case PROGRAM_UNDEFINED:
5883 return ureg_dst_undef();
5884
5885 case PROGRAM_TEMPORARY:
5886 /* Allocate space for temporaries on demand. */
5887 if (index >= t->temps_size) {
5888 const int inc = align(index - t->temps_size + 1, 4096);
5889
5890 t->temps = (struct ureg_dst*)
5891 realloc(t->temps,
5892 (t->temps_size + inc) * sizeof(struct ureg_dst));
5893 if (!t->temps)
5894 return ureg_dst_undef();
5895
5896 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5897 t->temps_size += inc;
5898 }
5899
5900 if (ureg_dst_is_undef(t->temps[index]))
5901 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5902
5903 return t->temps[index];
5904
5905 case PROGRAM_ARRAY:
5906 assert(array_id && array_id <= t->num_temp_arrays);
5907 array = array_id - 1;
5908
5909 if (ureg_dst_is_undef(t->arrays[array]))
5910 t->arrays[array] = ureg_DECL_array_temporary(
5911 t->ureg, t->array_sizes[array], TRUE);
5912
5913 return ureg_dst_array_offset(t->arrays[array], index);
5914
5915 case PROGRAM_OUTPUT:
5916 if (!array_id) {
5917 if (t->procType == PIPE_SHADER_FRAGMENT)
5918 assert(index < 2 * FRAG_RESULT_MAX);
5919 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5920 t->procType == PIPE_SHADER_TESS_EVAL)
5921 assert(index < VARYING_SLOT_TESS_MAX);
5922 else
5923 assert(index < VARYING_SLOT_MAX);
5924
5925 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5926 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5927 return t->outputs[t->outputMapping[index]];
5928 }
5929 else {
5930 struct inout_decl *decl =
5931 find_inout_array(t->output_decls,
5932 t->num_output_decls, array_id);
5933 unsigned mesa_index = decl->mesa_index;
5934 int slot = t->outputMapping[mesa_index];
5935
5936 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5937
5938 struct ureg_dst dst = t->outputs[slot];
5939 dst.ArrayID = array_id;
5940 return ureg_dst_array_offset(dst, index - mesa_index);
5941 }
5942
5943 case PROGRAM_ADDRESS:
5944 return t->address[index];
5945
5946 default:
5947 assert(!"unknown dst register file");
5948 return ureg_dst_undef();
5949 }
5950 }
5951
5952 static struct ureg_src
5953 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5954
5955 static struct ureg_src
5956 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5957 unsigned addr_index)
5958 {
5959 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5960 return ureg_src(t->address[addr_index]);
5961
5962 return translate_src(t, reladdr);
5963 }
5964
5965 /**
5966 * Create a TGSI ureg_dst register from an st_dst_reg.
5967 */
5968 static struct ureg_dst
5969 translate_dst(struct st_translate *t,
5970 const st_dst_reg *dst_reg,
5971 bool saturate)
5972 {
5973 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5974 dst_reg->array_id);
5975
5976 if (dst.File == TGSI_FILE_NULL)
5977 return dst;
5978
5979 dst = ureg_writemask(dst, dst_reg->writemask);
5980
5981 if (saturate)
5982 dst = ureg_saturate(dst);
5983
5984 if (dst_reg->reladdr != NULL) {
5985 assert(dst_reg->file != PROGRAM_TEMPORARY);
5986 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5987 }
5988
5989 if (dst_reg->has_index2) {
5990 if (dst_reg->reladdr2)
5991 dst = ureg_dst_dimension_indirect(dst,
5992 translate_addr(t, dst_reg->reladdr2, 1),
5993 dst_reg->index2D);
5994 else
5995 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5996 }
5997
5998 return dst;
5999 }
6000
6001 /**
6002 * Create a TGSI ureg_src register from an st_src_reg.
6003 */
6004 static struct ureg_src
6005 translate_src(struct st_translate *t, const st_src_reg *src_reg)
6006 {
6007 struct ureg_src src;
6008 int index = src_reg->index;
6009 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
6010
6011 switch (src_reg->file) {
6012 case PROGRAM_UNDEFINED:
6013 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
6014 break;
6015
6016 case PROGRAM_TEMPORARY:
6017 case PROGRAM_ARRAY:
6018 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
6019 src_reg->array_id));
6020 break;
6021
6022 case PROGRAM_OUTPUT: {
6023 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
6024 src_reg->array_id);
6025 assert(dst.WriteMask != 0);
6026 unsigned shift = ffs(dst.WriteMask) - 1;
6027 src = ureg_swizzle(ureg_src(dst),
6028 shift,
6029 MIN2(shift + 1, 3),
6030 MIN2(shift + 2, 3),
6031 MIN2(shift + 3, 3));
6032 break;
6033 }
6034
6035 case PROGRAM_UNIFORM:
6036 assert(src_reg->index >= 0);
6037 src = src_reg->index < t->num_constants ?
6038 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6039 break;
6040 case PROGRAM_STATE_VAR:
6041 case PROGRAM_CONSTANT: /* ie, immediate */
6042 if (src_reg->has_index2)
6043 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6044 else
6045 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6046 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6047 break;
6048
6049 case PROGRAM_IMMEDIATE:
6050 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6051 src = t->immediates[src_reg->index];
6052 break;
6053
6054 case PROGRAM_INPUT:
6055 /* GLSL inputs are 64-bit containers, so we have to
6056 * map back to the original index and add the offset after
6057 * mapping. */
6058 index -= double_reg2;
6059 if (!src_reg->array_id) {
6060 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6061 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6062 src = t->inputs[t->inputMapping[index] + double_reg2];
6063 }
6064 else {
6065 struct inout_decl *decl = find_inout_array(t->input_decls,
6066 t->num_input_decls,
6067 src_reg->array_id);
6068 unsigned mesa_index = decl->mesa_index;
6069 int slot = t->inputMapping[mesa_index];
6070
6071 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6072
6073 src = t->inputs[slot];
6074 src.ArrayID = src_reg->array_id;
6075 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6076 }
6077 break;
6078
6079 case PROGRAM_ADDRESS:
6080 src = ureg_src(t->address[src_reg->index]);
6081 break;
6082
6083 case PROGRAM_SYSTEM_VALUE:
6084 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6085 src = t->systemValues[src_reg->index];
6086 break;
6087
6088 case PROGRAM_HW_ATOMIC:
6089 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6090 src_reg->array_id);
6091 break;
6092
6093 default:
6094 assert(!"unknown src register file");
6095 return ureg_src_undef();
6096 }
6097
6098 if (src_reg->has_index2) {
6099 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6100 * and UBO constant buffers (buffer, position).
6101 */
6102 if (src_reg->reladdr2)
6103 src = ureg_src_dimension_indirect(src,
6104 translate_addr(t, src_reg->reladdr2, 1),
6105 src_reg->index2D);
6106 else
6107 src = ureg_src_dimension(src, src_reg->index2D);
6108 }
6109
6110 src = ureg_swizzle(src,
6111 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6112 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6113 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6114 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6115
6116 if (src_reg->abs)
6117 src = ureg_abs(src);
6118
6119 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6120 src = ureg_negate(src);
6121
6122 if (src_reg->reladdr != NULL) {
6123 assert(src_reg->file != PROGRAM_TEMPORARY);
6124 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6125 }
6126
6127 return src;
6128 }
6129
6130 static struct tgsi_texture_offset
6131 translate_tex_offset(struct st_translate *t,
6132 const st_src_reg *in_offset)
6133 {
6134 struct tgsi_texture_offset offset;
6135 struct ureg_src src = translate_src(t, in_offset);
6136
6137 offset.File = src.File;
6138 offset.Index = src.Index;
6139 offset.SwizzleX = src.SwizzleX;
6140 offset.SwizzleY = src.SwizzleY;
6141 offset.SwizzleZ = src.SwizzleZ;
6142 offset.Padding = 0;
6143
6144 assert(!src.Indirect);
6145 assert(!src.DimIndirect);
6146 assert(!src.Dimension);
6147 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6148 assert(!src.Negate);
6149
6150 return offset;
6151 }
6152
6153 static void
6154 compile_tgsi_instruction(struct st_translate *t,
6155 const glsl_to_tgsi_instruction *inst)
6156 {
6157 struct ureg_program *ureg = t->ureg;
6158 int i;
6159 struct ureg_dst dst[2];
6160 struct ureg_src src[4];
6161 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6162
6163 int num_dst;
6164 int num_src;
6165 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6166
6167 num_dst = num_inst_dst_regs(inst);
6168 num_src = num_inst_src_regs(inst);
6169
6170 for (i = 0; i < num_dst; i++)
6171 dst[i] = translate_dst(t,
6172 &inst->dst[i],
6173 inst->saturate);
6174
6175 for (i = 0; i < num_src; i++)
6176 src[i] = translate_src(t, &inst->src[i]);
6177
6178 switch (inst->op) {
6179 case TGSI_OPCODE_BGNLOOP:
6180 case TGSI_OPCODE_ELSE:
6181 case TGSI_OPCODE_ENDLOOP:
6182 case TGSI_OPCODE_IF:
6183 case TGSI_OPCODE_UIF:
6184 assert(num_dst == 0);
6185 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6186 return;
6187
6188 case TGSI_OPCODE_TEX:
6189 case TGSI_OPCODE_TEX_LZ:
6190 case TGSI_OPCODE_TXB:
6191 case TGSI_OPCODE_TXD:
6192 case TGSI_OPCODE_TXL:
6193 case TGSI_OPCODE_TXP:
6194 case TGSI_OPCODE_TXQ:
6195 case TGSI_OPCODE_TXQS:
6196 case TGSI_OPCODE_TXF:
6197 case TGSI_OPCODE_TXF_LZ:
6198 case TGSI_OPCODE_TEX2:
6199 case TGSI_OPCODE_TXB2:
6200 case TGSI_OPCODE_TXL2:
6201 case TGSI_OPCODE_TG4:
6202 case TGSI_OPCODE_LODQ:
6203 case TGSI_OPCODE_SAMP2HND:
6204 if (inst->resource.file == PROGRAM_SAMPLER) {
6205 src[num_src] = t->samplers[inst->resource.index];
6206 } else {
6207 /* Bindless samplers. */
6208 src[num_src] = translate_src(t, &inst->resource);
6209 }
6210 assert(src[num_src].File != TGSI_FILE_NULL);
6211 if (inst->resource.reladdr)
6212 src[num_src] =
6213 ureg_src_indirect(src[num_src],
6214 translate_addr(t, inst->resource.reladdr, 2));
6215 num_src++;
6216 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6217 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6218 }
6219 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6220
6221 ureg_tex_insn(ureg,
6222 inst->op,
6223 dst, num_dst,
6224 tex_target,
6225 st_translate_texture_type(inst->tex_type),
6226 texoffsets, inst->tex_offset_num_offset,
6227 src, num_src);
6228 return;
6229
6230 case TGSI_OPCODE_RESQ:
6231 case TGSI_OPCODE_LOAD:
6232 case TGSI_OPCODE_ATOMUADD:
6233 case TGSI_OPCODE_ATOMXCHG:
6234 case TGSI_OPCODE_ATOMCAS:
6235 case TGSI_OPCODE_ATOMAND:
6236 case TGSI_OPCODE_ATOMOR:
6237 case TGSI_OPCODE_ATOMXOR:
6238 case TGSI_OPCODE_ATOMUMIN:
6239 case TGSI_OPCODE_ATOMUMAX:
6240 case TGSI_OPCODE_ATOMIMIN:
6241 case TGSI_OPCODE_ATOMIMAX:
6242 case TGSI_OPCODE_ATOMFADD:
6243 case TGSI_OPCODE_IMG2HND:
6244 case TGSI_OPCODE_ATOMINC_WRAP:
6245 case TGSI_OPCODE_ATOMDEC_WRAP:
6246 for (i = num_src - 1; i >= 0; i--)
6247 src[i + 1] = src[i];
6248 num_src++;
6249 if (inst->resource.file == PROGRAM_MEMORY) {
6250 src[0] = t->shared_memory;
6251 } else if (inst->resource.file == PROGRAM_BUFFER) {
6252 src[0] = t->buffers[inst->resource.index];
6253 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6254 src[0] = translate_src(t, &inst->resource);
6255 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6256 assert(inst->resource.has_index2);
6257 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6258 } else {
6259 assert(inst->resource.file != PROGRAM_UNDEFINED);
6260 if (inst->resource.file == PROGRAM_IMAGE) {
6261 src[0] = t->images[inst->resource.index];
6262 } else {
6263 /* Bindless images. */
6264 src[0] = translate_src(t, &inst->resource);
6265 }
6266 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6267 }
6268 if (inst->resource.reladdr)
6269 src[0] = ureg_src_indirect(src[0],
6270 translate_addr(t, inst->resource.reladdr, 2));
6271 assert(src[0].File != TGSI_FILE_NULL);
6272 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6273 inst->buffer_access,
6274 tex_target, inst->image_format);
6275 break;
6276
6277 case TGSI_OPCODE_STORE:
6278 if (inst->resource.file == PROGRAM_MEMORY) {
6279 dst[0] = ureg_dst(t->shared_memory);
6280 } else if (inst->resource.file == PROGRAM_BUFFER) {
6281 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6282 } else {
6283 if (inst->resource.file == PROGRAM_IMAGE) {
6284 dst[0] = ureg_dst(t->images[inst->resource.index]);
6285 } else {
6286 /* Bindless images. */
6287 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6288 }
6289 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6290 }
6291 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6292 if (inst->resource.reladdr)
6293 dst[0] = ureg_dst_indirect(dst[0],
6294 translate_addr(t, inst->resource.reladdr, 2));
6295 assert(dst[0].File != TGSI_FILE_NULL);
6296 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6297 inst->buffer_access,
6298 tex_target, inst->image_format);
6299 break;
6300
6301 default:
6302 ureg_insn(ureg,
6303 inst->op,
6304 dst, num_dst,
6305 src, num_src, inst->precise);
6306 break;
6307 }
6308 }
6309
6310 /* Invert SamplePos.y when rendering to the default framebuffer. */
6311 static void
6312 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6313 {
6314 struct ureg_program *ureg = t->ureg;
6315
6316 assert(wpos_y_transform >= 0);
6317 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6318 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6319 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6320 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6321
6322 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6323 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6324
6325 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6326 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6327 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6328 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6329 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6330 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6331 samplepos_sysval);
6332
6333 /* Use the result in place of the system value. */
6334 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6335 }
6336
6337
6338 /**
6339 * Emit the TGSI instructions for inverting and adjusting WPOS.
6340 * This code is unavoidable because it also depends on whether
6341 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6342 */
6343 static void
6344 emit_wpos_adjustment(struct gl_context *ctx,
6345 struct st_translate *t,
6346 int wpos_transform_const,
6347 boolean invert,
6348 GLfloat adjX, GLfloat adjY[2])
6349 {
6350 struct ureg_program *ureg = t->ureg;
6351
6352 assert(wpos_transform_const >= 0);
6353
6354 /* Fragment program uses fragment position input.
6355 * Need to replace instances of INPUT[WPOS] with temp T
6356 * where T = INPUT[WPOS] is inverted by Y.
6357 */
6358 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6359 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6360 struct ureg_src *wpos =
6361 ctx->Const.GLSLFragCoordIsSysVal ?
6362 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6363 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6364 struct ureg_src wpos_input = *wpos;
6365
6366 /* First, apply the coordinate shift: */
6367 if (adjX || adjY[0] || adjY[1]) {
6368 if (adjY[0] != adjY[1]) {
6369 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6370 * depending on whether inversion is actually going to be applied
6371 * or not, which is determined by testing against the inversion
6372 * state variable used below, which will be either +1 or -1.
6373 */
6374 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6375
6376 ureg_CMP(ureg, adj_temp,
6377 ureg_scalar(wpostrans, invert ? 2 : 0),
6378 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6379 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6380 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6381 } else {
6382 ureg_ADD(ureg, wpos_temp, wpos_input,
6383 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6384 }
6385 wpos_input = ureg_src(wpos_temp);
6386 } else {
6387 /* MOV wpos_temp, input[wpos]
6388 */
6389 ureg_MOV(ureg, wpos_temp, wpos_input);
6390 }
6391
6392 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6393 * inversion/identity, or the other way around if we're drawing to an FBO.
6394 */
6395 if (invert) {
6396 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6397 */
6398 ureg_MAD(ureg,
6399 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6400 wpos_input,
6401 ureg_scalar(wpostrans, 0),
6402 ureg_scalar(wpostrans, 1));
6403 } else {
6404 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6405 */
6406 ureg_MAD(ureg,
6407 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6408 wpos_input,
6409 ureg_scalar(wpostrans, 2),
6410 ureg_scalar(wpostrans, 3));
6411 }
6412
6413 /* Use wpos_temp as position input from here on:
6414 */
6415 *wpos = ureg_src(wpos_temp);
6416 }
6417
6418
6419 /**
6420 * Emit fragment position/ooordinate code.
6421 */
6422 static void
6423 emit_wpos(struct st_context *st,
6424 struct st_translate *t,
6425 const struct gl_program *program,
6426 struct ureg_program *ureg,
6427 int wpos_transform_const)
6428 {
6429 struct pipe_screen *pscreen = st->pipe->screen;
6430 GLfloat adjX = 0.0f;
6431 GLfloat adjY[2] = { 0.0f, 0.0f };
6432 boolean invert = FALSE;
6433
6434 /* Query the pixel center conventions supported by the pipe driver and set
6435 * adjX, adjY to help out if it cannot handle the requested one internally.
6436 *
6437 * The bias of the y-coordinate depends on whether y-inversion takes place
6438 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6439 * drawing to an FBO (causes additional inversion), and whether the pipe
6440 * driver origin and the requested origin differ (the latter condition is
6441 * stored in the 'invert' variable).
6442 *
6443 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6444 *
6445 * center shift only:
6446 * i -> h: +0.5
6447 * h -> i: -0.5
6448 *
6449 * inversion only:
6450 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6451 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6452 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6453 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6454 *
6455 * inversion and center shift:
6456 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6457 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6458 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6459 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6460 */
6461 if (program->info.fs.origin_upper_left) {
6462 /* Fragment shader wants origin in upper-left */
6463 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6464 /* the driver supports upper-left origin */
6465 }
6466 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6467 /* the driver supports lower-left origin, need to invert Y */
6468 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6469 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6470 invert = TRUE;
6471 }
6472 else
6473 assert(0);
6474 }
6475 else {
6476 /* Fragment shader wants origin in lower-left */
6477 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6478 /* the driver supports lower-left origin */
6479 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6480 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6481 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6482 /* the driver supports upper-left origin, need to invert Y */
6483 invert = TRUE;
6484 else
6485 assert(0);
6486 }
6487
6488 if (program->info.fs.pixel_center_integer) {
6489 /* Fragment shader wants pixel center integer */
6490 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6491 /* the driver supports pixel center integer */
6492 adjY[1] = 1.0f;
6493 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6494 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6495 }
6496 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6497 /* the driver supports pixel center half integer, need to bias X,Y */
6498 adjX = -0.5f;
6499 adjY[0] = -0.5f;
6500 adjY[1] = 0.5f;
6501 }
6502 else
6503 assert(0);
6504 }
6505 else {
6506 /* Fragment shader wants pixel center half integer */
6507 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6508 /* the driver supports pixel center half integer */
6509 }
6510 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6511 /* the driver supports pixel center integer, need to bias X,Y */
6512 adjX = adjY[0] = adjY[1] = 0.5f;
6513 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6514 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6515 }
6516 else
6517 assert(0);
6518 }
6519
6520 /* we invert after adjustment so that we avoid the MOV to temporary,
6521 * and reuse the adjustment ADD instead */
6522 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6523 }
6524
6525 /**
6526 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6527 * TGSI uses +1 for front, -1 for back.
6528 * This function converts the TGSI value to the GL value. Simply clamping/
6529 * saturating the value to [0,1] does the job.
6530 */
6531 static void
6532 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6533 {
6534 struct ureg_program *ureg = t->ureg;
6535 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6536 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6537
6538 if (ctx->Const.NativeIntegers) {
6539 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6540 }
6541 else {
6542 /* MOV_SAT face_temp, input[face] */
6543 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6544 }
6545
6546 /* Use face_temp as face input from here on: */
6547 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6548 }
6549
6550 static void
6551 emit_compute_block_size(const struct gl_program *prog,
6552 struct ureg_program *ureg) {
6553 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6554 prog->info.cs.local_size[0]);
6555 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6556 prog->info.cs.local_size[1]);
6557 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6558 prog->info.cs.local_size[2]);
6559 }
6560
6561 struct sort_inout_decls {
6562 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6563 return mapping[a.mesa_index] < mapping[b.mesa_index];
6564 }
6565
6566 const ubyte *mapping;
6567 };
6568
6569 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6570 *
6571 * This is for the benefit of older drivers which are broken when the
6572 * declarations aren't sorted in this way.
6573 */
6574 static void
6575 sort_inout_decls_by_slot(struct inout_decl *decls,
6576 unsigned count,
6577 const ubyte mapping[])
6578 {
6579 sort_inout_decls sorter;
6580 sorter.mapping = mapping;
6581 std::sort(decls, decls + count, sorter);
6582 }
6583
6584 static enum tgsi_interpolate_mode
6585 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6586 {
6587 switch (glsl_qual) {
6588 case INTERP_MODE_NONE:
6589 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6590 return TGSI_INTERPOLATE_COLOR;
6591 return TGSI_INTERPOLATE_PERSPECTIVE;
6592 case INTERP_MODE_SMOOTH:
6593 return TGSI_INTERPOLATE_PERSPECTIVE;
6594 case INTERP_MODE_FLAT:
6595 return TGSI_INTERPOLATE_CONSTANT;
6596 case INTERP_MODE_NOPERSPECTIVE:
6597 return TGSI_INTERPOLATE_LINEAR;
6598 default:
6599 assert(0 && "unexpected interp mode in st_translate_interp()");
6600 return TGSI_INTERPOLATE_PERSPECTIVE;
6601 }
6602 }
6603
6604 /**
6605 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6606 * \param program the program to translate
6607 * \param numInputs number of input registers used
6608 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6609 * input indexes
6610 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6611 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6612 * each input
6613 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6614 * \param numOutputs number of output registers used
6615 * \param outputMapping maps Mesa fragment program outputs to TGSI
6616 * generic outputs
6617 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6618 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6619 * each output
6620 *
6621 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6622 */
6623 extern "C" enum pipe_error
6624 st_translate_program(
6625 struct gl_context *ctx,
6626 enum pipe_shader_type procType,
6627 struct ureg_program *ureg,
6628 glsl_to_tgsi_visitor *program,
6629 const struct gl_program *proginfo,
6630 GLuint numInputs,
6631 const ubyte inputMapping[],
6632 const ubyte inputSlotToAttr[],
6633 const ubyte inputSemanticName[],
6634 const ubyte inputSemanticIndex[],
6635 const ubyte interpMode[],
6636 GLuint numOutputs,
6637 const ubyte outputMapping[],
6638 const ubyte outputSemanticName[],
6639 const ubyte outputSemanticIndex[])
6640 {
6641 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6642 struct st_translate *t;
6643 unsigned i;
6644 struct gl_program_constants *frag_const =
6645 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6646 enum pipe_error ret = PIPE_OK;
6647
6648 assert(numInputs <= ARRAY_SIZE(t->inputs));
6649 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6650
6651 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6652 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6653 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6654 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6655 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6656 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6657 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6658 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6659 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6660 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6661
6662 t = CALLOC_STRUCT(st_translate);
6663 if (!t) {
6664 ret = PIPE_ERROR_OUT_OF_MEMORY;
6665 goto out;
6666 }
6667
6668 t->procType = procType;
6669 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6670 t->inputMapping = inputMapping;
6671 t->outputMapping = outputMapping;
6672 t->ureg = ureg;
6673 t->num_temp_arrays = program->next_array;
6674 if (t->num_temp_arrays)
6675 t->arrays = (struct ureg_dst*)
6676 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6677
6678 /*
6679 * Declare input attributes.
6680 */
6681 switch (procType) {
6682 case PIPE_SHADER_FRAGMENT:
6683 case PIPE_SHADER_GEOMETRY:
6684 case PIPE_SHADER_TESS_EVAL:
6685 case PIPE_SHADER_TESS_CTRL:
6686 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6687
6688 for (i = 0; i < program->num_inputs; ++i) {
6689 struct inout_decl *decl = &program->inputs[i];
6690 unsigned slot = inputMapping[decl->mesa_index];
6691 struct ureg_src src;
6692 ubyte tgsi_usage_mask = decl->usage_mask;
6693
6694 if (glsl_base_type_is_64bit(decl->base_type)) {
6695 if (tgsi_usage_mask == 1)
6696 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6697 else if (tgsi_usage_mask == 2)
6698 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6699 else
6700 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6701 }
6702
6703 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6704 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6705 if (procType == PIPE_SHADER_FRAGMENT) {
6706 assert(interpMode);
6707 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6708 (enum tgsi_interpolate_mode) interpMode[slot] :
6709 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6710
6711 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6712 }
6713
6714 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6715 (enum tgsi_semantic) inputSemanticName[slot],
6716 inputSemanticIndex[slot],
6717 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6718 decl->array_id, decl->size);
6719
6720 for (unsigned j = 0; j < decl->size; ++j) {
6721 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6722 /* The ArrayID is set up in dst_register */
6723 t->inputs[slot + j] = src;
6724 t->inputs[slot + j].ArrayID = 0;
6725 t->inputs[slot + j].Index += j;
6726 }
6727 }
6728 }
6729 break;
6730 case PIPE_SHADER_VERTEX:
6731 for (i = 0; i < numInputs; i++) {
6732 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6733 }
6734 break;
6735 case PIPE_SHADER_COMPUTE:
6736 break;
6737 default:
6738 assert(0);
6739 }
6740
6741 /*
6742 * Declare output attributes.
6743 */
6744 switch (procType) {
6745 case PIPE_SHADER_FRAGMENT:
6746 case PIPE_SHADER_COMPUTE:
6747 break;
6748 case PIPE_SHADER_GEOMETRY:
6749 case PIPE_SHADER_TESS_EVAL:
6750 case PIPE_SHADER_TESS_CTRL:
6751 case PIPE_SHADER_VERTEX:
6752 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6753
6754 for (i = 0; i < program->num_outputs; ++i) {
6755 struct inout_decl *decl = &program->outputs[i];
6756 unsigned slot = outputMapping[decl->mesa_index];
6757 struct ureg_dst dst;
6758 ubyte tgsi_usage_mask = decl->usage_mask;
6759
6760 if (glsl_base_type_is_64bit(decl->base_type)) {
6761 if (tgsi_usage_mask == 1)
6762 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6763 else if (tgsi_usage_mask == 2)
6764 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6765 else
6766 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6767 }
6768
6769 dst = ureg_DECL_output_layout(ureg,
6770 (enum tgsi_semantic) outputSemanticName[slot],
6771 outputSemanticIndex[slot],
6772 decl->gs_out_streams,
6773 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6774 dst.Invariant = decl->invariant;
6775 for (unsigned j = 0; j < decl->size; ++j) {
6776 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6777 /* The ArrayID is set up in dst_register */
6778 t->outputs[slot + j] = dst;
6779 t->outputs[slot + j].ArrayID = 0;
6780 t->outputs[slot + j].Index += j;
6781 t->outputs[slot + j].Invariant = decl->invariant;
6782 }
6783 }
6784 }
6785 break;
6786 default:
6787 assert(0);
6788 }
6789
6790 if (procType == PIPE_SHADER_FRAGMENT) {
6791 if (program->shader->Program->info.fs.early_fragment_tests ||
6792 program->shader->Program->info.fs.post_depth_coverage) {
6793 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6794
6795 if (program->shader->Program->info.fs.post_depth_coverage)
6796 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6797 }
6798
6799 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6800 /* Must do this after setting up t->inputs. */
6801 emit_wpos(st_context(ctx), t, proginfo, ureg,
6802 program->wpos_transform_const);
6803 }
6804
6805 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6806 emit_face_var(ctx, t);
6807
6808 for (i = 0; i < numOutputs; i++) {
6809 switch (outputSemanticName[i]) {
6810 case TGSI_SEMANTIC_POSITION:
6811 t->outputs[i] = ureg_DECL_output(ureg,
6812 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6813 outputSemanticIndex[i]);
6814 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6815 break;
6816 case TGSI_SEMANTIC_STENCIL:
6817 t->outputs[i] = ureg_DECL_output(ureg,
6818 TGSI_SEMANTIC_STENCIL, /* Stencil */
6819 outputSemanticIndex[i]);
6820 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6821 break;
6822 case TGSI_SEMANTIC_COLOR:
6823 t->outputs[i] = ureg_DECL_output(ureg,
6824 TGSI_SEMANTIC_COLOR,
6825 outputSemanticIndex[i]);
6826 break;
6827 case TGSI_SEMANTIC_SAMPLEMASK:
6828 t->outputs[i] = ureg_DECL_output(ureg,
6829 TGSI_SEMANTIC_SAMPLEMASK,
6830 outputSemanticIndex[i]);
6831 /* TODO: If we ever support more than 32 samples, this will have
6832 * to become an array.
6833 */
6834 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6835 break;
6836 default:
6837 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6838 ret = PIPE_ERROR_BAD_INPUT;
6839 goto out;
6840 }
6841 }
6842 }
6843 else if (procType == PIPE_SHADER_VERTEX) {
6844 for (i = 0; i < numOutputs; i++) {
6845 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6846 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6847 ureg_MOV(ureg,
6848 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6849 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6850 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6851 }
6852 }
6853 }
6854
6855 if (procType == PIPE_SHADER_COMPUTE) {
6856 emit_compute_block_size(proginfo, ureg);
6857 }
6858
6859 /* Declare address register.
6860 */
6861 if (program->num_address_regs > 0) {
6862 assert(program->num_address_regs <= 3);
6863 for (int i = 0; i < program->num_address_regs; i++)
6864 t->address[i] = ureg_DECL_address(ureg);
6865 }
6866
6867 /* Declare misc input registers
6868 */
6869 {
6870 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6871
6872 for (i = 0; sysInputs; i++) {
6873 if (sysInputs & (1ull << i)) {
6874 enum tgsi_semantic semName = _mesa_sysval_to_semantic(i);
6875
6876 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6877
6878 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6879 semName == TGSI_SEMANTIC_VERTEXID) {
6880 /* From Gallium perspective, these system values are always
6881 * integer, and require native integer support. However, if
6882 * native integer is supported on the vertex stage but not the
6883 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6884 * assumes these system values are floats. To resolve the
6885 * inconsistency, we insert a U2F.
6886 */
6887 struct st_context *st = st_context(ctx);
6888 struct pipe_screen *pscreen = st->pipe->screen;
6889 assert(procType == PIPE_SHADER_VERTEX);
6890 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6891 (void) pscreen;
6892 if (!ctx->Const.NativeIntegers) {
6893 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6894 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6895 t->systemValues[i]);
6896 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6897 }
6898 }
6899
6900 if (procType == PIPE_SHADER_FRAGMENT &&
6901 semName == TGSI_SEMANTIC_POSITION)
6902 emit_wpos(st_context(ctx), t, proginfo, ureg,
6903 program->wpos_transform_const);
6904
6905 if (procType == PIPE_SHADER_FRAGMENT &&
6906 semName == TGSI_SEMANTIC_SAMPLEPOS)
6907 emit_samplepos_adjustment(t, program->wpos_transform_const);
6908
6909 sysInputs &= ~(1ull << i);
6910 }
6911 }
6912 }
6913
6914 t->array_sizes = program->array_sizes;
6915 t->input_decls = program->inputs;
6916 t->num_input_decls = program->num_inputs;
6917 t->output_decls = program->outputs;
6918 t->num_output_decls = program->num_outputs;
6919
6920 /* Emit constants and uniforms. TGSI uses a single index space for these,
6921 * so we put all the translated regs in t->constants.
6922 */
6923 if (proginfo->Parameters) {
6924 t->constants = (struct ureg_src *)
6925 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6926 if (t->constants == NULL) {
6927 ret = PIPE_ERROR_OUT_OF_MEMORY;
6928 goto out;
6929 }
6930 t->num_constants = proginfo->Parameters->NumParameters;
6931
6932 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6933 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6934
6935 switch (proginfo->Parameters->Parameters[i].Type) {
6936 case PROGRAM_STATE_VAR:
6937 case PROGRAM_UNIFORM:
6938 t->constants[i] = ureg_DECL_constant(ureg, i);
6939 break;
6940
6941 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6942 * addressing of the const buffer.
6943 * FIXME: Be smarter and recognize param arrays:
6944 * indirect addressing is only valid within the referenced
6945 * array.
6946 */
6947 case PROGRAM_CONSTANT:
6948 if (program->indirect_addr_consts)
6949 t->constants[i] = ureg_DECL_constant(ureg, i);
6950 else
6951 t->constants[i] = emit_immediate(t,
6952 proginfo->Parameters->ParameterValues + pvo,
6953 proginfo->Parameters->Parameters[i].DataType,
6954 4);
6955 break;
6956 default:
6957 break;
6958 }
6959 }
6960 }
6961
6962 for (i = 0; i < proginfo->info.num_ubos; i++) {
6963 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6964 unsigned num_const_vecs = (size + 15) / 16;
6965 unsigned first, last;
6966 assert(num_const_vecs > 0);
6967 first = 0;
6968 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6969 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6970 }
6971
6972 /* Emit immediate values.
6973 */
6974 t->immediates = (struct ureg_src *)
6975 calloc(program->num_immediates, sizeof(struct ureg_src));
6976 if (t->immediates == NULL) {
6977 ret = PIPE_ERROR_OUT_OF_MEMORY;
6978 goto out;
6979 }
6980 t->num_immediates = program->num_immediates;
6981
6982 i = 0;
6983 foreach_in_list(immediate_storage, imm, &program->immediates) {
6984 assert(i < program->num_immediates);
6985 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6986 }
6987 assert(i == program->num_immediates);
6988
6989 /* texture samplers */
6990 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6991 if (program->samplers_used & (1u << i)) {
6992 enum tgsi_return_type type =
6993 st_translate_texture_type(program->sampler_types[i]);
6994
6995 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6996
6997 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6998 type, type, type, type);
6999 }
7000 }
7001
7002 /* Declare atomic and shader storage buffers. */
7003 {
7004 struct gl_program *prog = program->prog;
7005
7006 if (!st_context(ctx)->has_hw_atomics) {
7007 for (i = 0; i < prog->info.num_abos; i++) {
7008 unsigned index = prog->sh.AtomicBuffers[i]->Binding;
7009 assert(index < frag_const->MaxAtomicBuffers);
7010 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
7011 }
7012 } else {
7013 for (i = 0; i < program->num_atomics; i++) {
7014 struct hwatomic_decl *ainfo = &program->atomic_info[i];
7015 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
7016 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
7017 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
7018 ainfo->array_id);
7019 }
7020 }
7021
7022 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
7023 for (i = 0; i < prog->info.num_ssbos; i++) {
7024 unsigned index = i;
7025 if (!st_context(ctx)->has_hw_atomics)
7026 index += frag_const->MaxAtomicBuffers;
7027
7028 t->buffers[index] = ureg_DECL_buffer(ureg, index, false);
7029 }
7030 }
7031
7032 if (program->use_shared_memory)
7033 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
7034
7035 for (i = 0; i < program->shader->Program->info.num_images; i++) {
7036 if (program->images_used & (1 << i)) {
7037 t->images[i] = ureg_DECL_image(ureg, i,
7038 program->image_targets[i],
7039 program->image_formats[i],
7040 program->image_wr[i],
7041 false);
7042 }
7043 }
7044
7045 /* Emit each instruction in turn:
7046 */
7047 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
7048 compile_tgsi_instruction(t, inst);
7049
7050 /* Set the next shader stage hint for VS and TES. */
7051 switch (procType) {
7052 case PIPE_SHADER_VERTEX:
7053 case PIPE_SHADER_TESS_EVAL:
7054 if (program->shader_program->SeparateShader)
7055 break;
7056
7057 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
7058 if (program->shader_program->_LinkedShaders[i]) {
7059 ureg_set_next_shader_processor(
7060 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
7061 break;
7062 }
7063 }
7064 break;
7065 default:
7066 ; /* nothing - silence compiler warning */
7067 }
7068
7069 out:
7070 if (t) {
7071 free(t->arrays);
7072 free(t->temps);
7073 free(t->constants);
7074 t->num_constants = 0;
7075 free(t->immediates);
7076 t->num_immediates = 0;
7077 FREE(t);
7078 }
7079
7080 return ret;
7081 }
7082 /* ----------------------------- End TGSI code ------------------------------ */
7083
7084
7085 /**
7086 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7087 * generating Mesa IR.
7088 */
7089 static struct gl_program *
7090 get_mesa_program_tgsi(struct gl_context *ctx,
7091 struct gl_shader_program *shader_program,
7092 struct gl_linked_shader *shader)
7093 {
7094 glsl_to_tgsi_visitor* v;
7095 struct gl_program *prog;
7096 struct gl_shader_compiler_options *options =
7097 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7098 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7099 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7100 unsigned skip_merge_registers;
7101
7102 validate_ir_tree(shader->ir);
7103
7104 prog = shader->Program;
7105
7106 prog->Parameters = _mesa_new_parameter_list();
7107 v = new glsl_to_tgsi_visitor();
7108 v->ctx = ctx;
7109 v->prog = prog;
7110 v->shader_program = shader_program;
7111 v->shader = shader;
7112 v->options = options;
7113 v->native_integers = ctx->Const.NativeIntegers;
7114
7115 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7116 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7117 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7118 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7119 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7120 PIPE_CAP_TGSI_TEX_TXF_LZ);
7121 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7122
7123 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7124 _mesa_key_pointer_equal);
7125 skip_merge_registers =
7126 pscreen->get_shader_param(pscreen, ptarget,
7127 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7128
7129 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7130 prog->Parameters);
7131
7132 /* Remove reads from output registers. */
7133 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7134 lower_output_reads(shader->Stage, shader->ir);
7135
7136 /* Emit intermediate IR for main(). */
7137 visit_exec_list(shader->ir, v);
7138
7139 #if 0
7140 /* Print out some information (for debugging purposes) used by the
7141 * optimization passes. */
7142 {
7143 int i;
7144 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7145 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7146 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7147 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7148
7149 for (i = 0; i < v->next_temp; i++) {
7150 first_writes[i] = -1;
7151 first_reads[i] = -1;
7152 last_writes[i] = -1;
7153 last_reads[i] = -1;
7154 }
7155 v->get_first_temp_read(first_reads);
7156 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7157 v->get_last_temp_write(last_writes);
7158 for (i = 0; i < v->next_temp; i++)
7159 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7160 first_writes[i],
7161 last_reads[i],
7162 last_writes[i]);
7163 ralloc_free(first_writes);
7164 ralloc_free(first_reads);
7165 ralloc_free(last_writes);
7166 ralloc_free(last_reads);
7167 }
7168 #endif
7169
7170 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7171 v->simplify_cmp();
7172 v->copy_propagate();
7173
7174 while (v->eliminate_dead_code());
7175
7176 v->merge_two_dsts();
7177
7178 if (!skip_merge_registers) {
7179 v->split_arrays();
7180 v->copy_propagate();
7181 while (v->eliminate_dead_code());
7182
7183 v->merge_registers();
7184 v->copy_propagate();
7185 while (v->eliminate_dead_code());
7186 }
7187
7188 v->renumber_registers();
7189
7190 /* Write the END instruction. */
7191 v->emit_asm(NULL, TGSI_OPCODE_END);
7192
7193 if (ctx->_Shader->Flags & GLSL_DUMP) {
7194 _mesa_log("\n");
7195 _mesa_log("GLSL IR for linked %s program %d:\n",
7196 _mesa_shader_stage_to_string(shader->Stage),
7197 shader_program->Name);
7198 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7199 _mesa_log("\n\n");
7200 }
7201
7202 do_set_program_inouts(shader->ir, prog, shader->Stage);
7203
7204 _mesa_copy_linked_program_data(shader_program, shader);
7205
7206 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS)) {
7207 mark_array_io(v->inputs, v->num_inputs,
7208 &prog->info.inputs_read,
7209 prog->DualSlotInputs,
7210 &prog->info.patch_inputs_read);
7211
7212 mark_array_io(v->outputs, v->num_outputs,
7213 &prog->info.outputs_written, 0ULL,
7214 &prog->info.patch_outputs_written);
7215 } else {
7216 shrink_array_declarations(v->inputs, v->num_inputs,
7217 &prog->info.inputs_read,
7218 prog->DualSlotInputs,
7219 &prog->info.patch_inputs_read);
7220 shrink_array_declarations(v->outputs, v->num_outputs,
7221 &prog->info.outputs_written, 0ULL,
7222 &prog->info.patch_outputs_written);
7223 }
7224
7225 count_resources(v, prog);
7226
7227 /* The GLSL IR won't be needed anymore. */
7228 ralloc_free(shader->ir);
7229 shader->ir = NULL;
7230
7231 /* This must be done before the uniform storage is associated. */
7232 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7233 (prog->info.inputs_read & VARYING_BIT_POS ||
7234 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
7235 prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
7236 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7237 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7238 };
7239
7240 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7241 wposTransformState);
7242 }
7243
7244 /* Avoid reallocation of the program parameter list, because the uniform
7245 * storage is only associated with the original parameter list.
7246 * This should be enough for Bitmap and DrawPixels constants.
7247 */
7248 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7249
7250 /* This has to be done last. Any operation the can cause
7251 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7252 * program constant) has to happen before creating this linkage.
7253 */
7254 _mesa_associate_uniform_storage(ctx, shader_program, prog);
7255 if (!shader_program->data->LinkStatus) {
7256 free_glsl_to_tgsi_visitor(v);
7257 _mesa_reference_program(ctx, &shader->Program, NULL);
7258 return NULL;
7259 }
7260
7261 struct st_vertex_program *stvp;
7262 struct st_fragment_program *stfp;
7263 struct st_common_program *stp;
7264 struct st_compute_program *stcp;
7265
7266 switch (shader->Stage) {
7267 case MESA_SHADER_VERTEX:
7268 stvp = (struct st_vertex_program *)prog;
7269 stvp->glsl_to_tgsi = v;
7270 break;
7271 case MESA_SHADER_FRAGMENT:
7272 stfp = (struct st_fragment_program *)prog;
7273 stfp->glsl_to_tgsi = v;
7274 break;
7275 case MESA_SHADER_TESS_CTRL:
7276 case MESA_SHADER_TESS_EVAL:
7277 case MESA_SHADER_GEOMETRY:
7278 stp = st_common_program(prog);
7279 stp->glsl_to_tgsi = v;
7280 break;
7281 case MESA_SHADER_COMPUTE:
7282 stcp = (struct st_compute_program *)prog;
7283 stcp->glsl_to_tgsi = v;
7284 break;
7285 default:
7286 assert(!"should not be reached");
7287 return NULL;
7288 }
7289
7290 PRINT_STATS(v->print_stats());
7291
7292 return prog;
7293 }
7294
7295 /* See if there are unsupported control flow statements. */
7296 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7297 private:
7298 const struct gl_shader_compiler_options *options;
7299 public:
7300 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7301 : options(options),
7302 unsupported(false)
7303 {
7304 }
7305
7306 virtual ir_visitor_status visit_enter(ir_function *ir)
7307 {
7308 /* Other functions are skipped (same as glsl_to_tgsi). */
7309 if (strcmp(ir->name, "main") == 0)
7310 return visit_continue;
7311
7312 return visit_continue_with_parent;
7313 }
7314
7315 virtual ir_visitor_status visit_enter(ir_call *ir)
7316 {
7317 if (!ir->callee->is_intrinsic()) {
7318 unsupported = true; /* it's a function call */
7319 return visit_stop;
7320 }
7321 return visit_continue;
7322 }
7323
7324 virtual ir_visitor_status visit_enter(ir_return *ir)
7325 {
7326 if (options->EmitNoMainReturn) {
7327 unsupported = true;
7328 return visit_stop;
7329 }
7330 return visit_continue;
7331 }
7332
7333 bool unsupported;
7334 };
7335
7336 static bool
7337 has_unsupported_control_flow(exec_list *ir,
7338 const struct gl_shader_compiler_options *options)
7339 {
7340 ir_control_flow_info_visitor visitor(options);
7341 visit_list_elements(&visitor, ir);
7342 return visitor.unsupported;
7343 }
7344
7345 /**
7346 * Link a shader.
7347 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7348 * with code lowering and other optimizations.
7349 */
7350 GLboolean
7351 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7352 {
7353 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7354
7355 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7356 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7357 if (shader == NULL)
7358 continue;
7359
7360 exec_list *ir = shader->ir;
7361 gl_shader_stage stage = shader->Stage;
7362 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7363 const struct gl_shader_compiler_options *options =
7364 &ctx->Const.ShaderCompilerOptions[stage];
7365
7366 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7367 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7368 if (ctx->Const.GLSLOptimizeConservatively) {
7369 /* Do it once and repeat only if there's unsupported control flow. */
7370 do {
7371 do_common_optimization(ir, true, true, options,
7372 ctx->Const.NativeIntegers);
7373 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7374 options->MaxIfDepth, if_threshold);
7375 } while (has_unsupported_control_flow(ir, options));
7376 } else {
7377 /* Repeat it until it stops making changes. */
7378 bool progress;
7379 do {
7380 progress = do_common_optimization(ir, true, true, options,
7381 ctx->Const.NativeIntegers);
7382 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7383 options->MaxIfDepth, if_threshold);
7384 } while (progress);
7385 }
7386
7387 /* Do this again to lower ir_binop_vector_extract introduced
7388 * by optimization passes.
7389 */
7390 do_vec_index_to_cond_assign(ir);
7391
7392 validate_ir_tree(ir);
7393
7394 struct gl_program *linked_prog =
7395 get_mesa_program_tgsi(ctx, prog, shader);
7396 st_set_prog_affected_state_flags(linked_prog);
7397
7398 if (linked_prog) {
7399 if (!ctx->Driver.ProgramStringNotify(ctx,
7400 _mesa_shader_stage_to_program(i),
7401 linked_prog)) {
7402 _mesa_reference_program(ctx, &shader->Program, NULL);
7403 return GL_FALSE;
7404 }
7405 }
7406 }
7407
7408 return GL_TRUE;
7409 }
7410
7411 extern "C" {
7412
7413 void
7414 st_translate_stream_output_info(struct gl_transform_feedback_info *info,
7415 const ubyte outputMapping[],
7416 struct pipe_stream_output_info *so)
7417 {
7418 unsigned i;
7419
7420 if (!info) {
7421 so->num_outputs = 0;
7422 return;
7423 }
7424
7425 for (i = 0; i < info->NumOutputs; i++) {
7426 so->output[i].register_index =
7427 outputMapping[info->Outputs[i].OutputRegister];
7428 so->output[i].start_component = info->Outputs[i].ComponentOffset;
7429 so->output[i].num_components = info->Outputs[i].NumComponents;
7430 so->output[i].output_buffer = info->Outputs[i].OutputBuffer;
7431 so->output[i].dst_offset = info->Outputs[i].DstOffset;
7432 so->output[i].stream = info->Outputs[i].StreamId;
7433 }
7434
7435 for (i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
7436 so->stride[i] = info->Buffers[i].Stride;
7437 }
7438 so->num_outputs = info->NumOutputs;
7439 }
7440
7441 } /* extern "C" */