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glsl: Add ir_demote
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
56 #include "st_glsl_to_tgsi_temprename.h"
57
58 #include "util/hash_table.h"
59 #include <algorithm>
60
61 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
62 (1 << PROGRAM_CONSTANT) | \
63 (1 << PROGRAM_UNIFORM))
64
65 #define MAX_GLSL_TEXTURE_OFFSET 4
66
67 #ifndef NDEBUG
68 #include "util/u_atomic.h"
69 #include "util/simple_mtx.h"
70 #include <fstream>
71 #include <ios>
72
73 /* Prepare to make it possible to specify log file */
74 static std::ofstream stats_log;
75
76 /* Helper function to check whether we want to write some statistics
77 * of the shader conversion.
78 */
79
80 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
81
82 static inline bool print_stats_enabled ()
83 {
84 static int stats_enabled = 0;
85
86 if (!stats_enabled) {
87 simple_mtx_lock(&print_stats_mutex);
88 if (!stats_enabled) {
89 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
90 if (stats_filename) {
91 bool write_header = std::ifstream(stats_filename).fail();
92 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
93 stats_enabled = stats_log.good() ? 1 : -1;
94 if (write_header)
95 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
96 } else {
97 stats_enabled = -1;
98 }
99 }
100 simple_mtx_unlock(&print_stats_mutex);
101 }
102 return stats_enabled > 0;
103 }
104 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
105 #else
106 #define PRINT_STATS(X)
107 #endif
108
109
110 static unsigned is_precise(const ir_variable *ir)
111 {
112 if (!ir)
113 return 0;
114 return ir->data.precise || ir->data.invariant;
115 }
116
117 class variable_storage {
118 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
119
120 public:
121 variable_storage(ir_variable *var, gl_register_file file, int index,
122 unsigned array_id = 0)
123 : file(file), index(index), component(0), var(var), array_id(array_id)
124 {
125 assert(file != PROGRAM_ARRAY || array_id != 0);
126 }
127
128 gl_register_file file;
129 int index;
130
131 /* Explicit component location. This is given in terms of the GLSL-style
132 * swizzles where each double is a single component, i.e. for 64-bit types
133 * it can only be 0 or 1.
134 */
135 int component;
136 ir_variable *var; /* variable that maps to this, if any */
137 unsigned array_id;
138 };
139
140 class immediate_storage : public exec_node {
141 public:
142 immediate_storage(gl_constant_value *values, int size32, GLenum type)
143 {
144 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
145 this->size32 = size32;
146 this->type = type;
147 }
148
149 /* doubles are stored across 2 gl_constant_values */
150 gl_constant_value values[4];
151 int size32; /**< Number of 32-bit components (1-4) */
152 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
153 };
154
155 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
156 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
157
158 struct inout_decl {
159 unsigned mesa_index;
160 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
161 unsigned size;
162 unsigned interp_loc;
163 unsigned gs_out_streams;
164 enum glsl_interp_mode interp;
165 enum glsl_base_type base_type;
166 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
167 bool invariant;
168 };
169
170 static struct inout_decl *
171 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
172 {
173 assert(array_id != 0);
174
175 for (unsigned i = 0; i < count; i++) {
176 struct inout_decl *decl = &decls[i];
177
178 if (array_id == decl->array_id) {
179 return decl;
180 }
181 }
182
183 return NULL;
184 }
185
186 static enum glsl_base_type
187 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
188 {
189 if (!array_id)
190 return GLSL_TYPE_ERROR;
191 struct inout_decl *decl = find_inout_array(decls, count, array_id);
192 if (decl)
193 return decl->base_type;
194 return GLSL_TYPE_ERROR;
195 }
196
197 struct hwatomic_decl {
198 unsigned location;
199 unsigned binding;
200 unsigned size;
201 unsigned array_id;
202 };
203
204 struct glsl_to_tgsi_visitor : public ir_visitor {
205 public:
206 glsl_to_tgsi_visitor();
207 ~glsl_to_tgsi_visitor();
208
209 struct gl_context *ctx;
210 struct gl_program *prog;
211 struct gl_shader_program *shader_program;
212 struct gl_linked_shader *shader;
213 struct gl_shader_compiler_options *options;
214
215 int next_temp;
216
217 unsigned *array_sizes;
218 unsigned max_num_arrays;
219 unsigned next_array;
220
221 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
222 unsigned num_inputs;
223 unsigned num_input_arrays;
224 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
225 unsigned num_outputs;
226 unsigned num_output_arrays;
227
228 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
229 unsigned num_atomics;
230 unsigned num_atomic_arrays;
231 int num_address_regs;
232 uint32_t samplers_used;
233 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
234 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
235 int images_used;
236 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
237 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
238 bool image_wr[PIPE_MAX_SHADER_IMAGES];
239 bool indirect_addr_consts;
240 int wpos_transform_const;
241
242 bool native_integers;
243 bool have_sqrt;
244 bool have_fma;
245 bool use_shared_memory;
246 bool has_tex_txf_lz;
247 bool precise;
248 bool need_uarl;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_demote *);
288 virtual void visit(ir_texture *);
289 virtual void visit(ir_if *);
290 virtual void visit(ir_emit_vertex *);
291 virtual void visit(ir_end_primitive *);
292 virtual void visit(ir_barrier *);
293 /*@}*/
294
295 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
296
297 void visit_atomic_counter_intrinsic(ir_call *);
298 void visit_ssbo_intrinsic(ir_call *);
299 void visit_membar_intrinsic(ir_call *);
300 void visit_shared_intrinsic(ir_call *);
301 void visit_image_intrinsic(ir_call *);
302 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
303
304 st_src_reg result;
305
306 /** List of variable_storage */
307 struct hash_table *variables;
308
309 /** List of immediate_storage */
310 exec_list immediates;
311 unsigned num_immediates;
312
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions;
315
316 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
317 st_dst_reg dst = undef_dst,
318 st_src_reg src0 = undef_src,
319 st_src_reg src1 = undef_src,
320 st_src_reg src2 = undef_src,
321 st_src_reg src3 = undef_src);
322
323 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
324 st_dst_reg dst, st_dst_reg dst1,
325 st_src_reg src0 = undef_src,
326 st_src_reg src1 = undef_src,
327 st_src_reg src2 = undef_src,
328 st_src_reg src3 = undef_src);
329
330 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
331 st_dst_reg dst,
332 st_src_reg src0, st_src_reg src1);
333
334 /**
335 * Emit the correct dot-product instruction for the type of arguments
336 */
337 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
338 st_dst_reg dst,
339 st_src_reg src0,
340 st_src_reg src1,
341 unsigned elements);
342
343 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
344 st_dst_reg dst, st_src_reg src0);
345
346 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
347 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
348
349 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
350
351 void get_deref_offsets(ir_dereference *ir,
352 unsigned *array_size,
353 unsigned *base,
354 uint16_t *index,
355 st_src_reg *reladdr,
356 bool opaque);
357 void calc_deref_offsets(ir_dereference *tail,
358 unsigned *array_elements,
359 uint16_t *index,
360 st_src_reg *indirect,
361 unsigned *location);
362 st_src_reg canonicalize_gather_offset(st_src_reg offset);
363 bool handle_bound_deref(ir_dereference *ir);
364
365 bool try_emit_mad(ir_expression *ir,
366 int mul_operand);
367 bool try_emit_mad_for_and_not(ir_expression *ir,
368 int mul_operand);
369
370 void emit_swz(ir_expression *ir);
371
372 bool process_move_condition(ir_rvalue *ir);
373
374 void simplify_cmp(void);
375
376 void rename_temp_registers(struct rename_reg_pair *renames);
377 void get_first_temp_read(int *first_reads);
378 void get_first_temp_write(int *first_writes);
379 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
380 void get_last_temp_write(int *last_writes);
381
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
384
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
389
390 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
391 st_dst_reg *l, st_src_reg *r,
392 st_src_reg *cond, bool cond_swap);
393
394 void print_stats();
395
396 void *mem_ctx;
397 };
398
399 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
400 GLSL_TYPE_FLOAT, 0);
401 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
402 GLSL_TYPE_FLOAT, 1);
403 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
404 GLSL_TYPE_FLOAT, 2);
405
406 static void
407 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
408 PRINTFLIKE(2, 3);
409
410 static void
411 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
412 {
413 va_list args;
414 va_start(args, fmt);
415 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
416 va_end(args);
417
418 prog->data->LinkStatus = LINKING_FAILURE;
419 }
420
421 int
422 swizzle_for_size(int size)
423 {
424 static const int size_swizzles[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
428 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
429 };
430
431 assert((size >= 1) && (size <= 4));
432 return size_swizzles[size - 1];
433 }
434
435
436 glsl_to_tgsi_instruction *
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
438 st_dst_reg dst, st_dst_reg dst1,
439 st_src_reg src0, st_src_reg src1,
440 st_src_reg src2, st_src_reg src3)
441 {
442 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
443 int num_reladdr = 0, i, j;
444 bool dst_is_64bit[2];
445
446 op = get_opcode(op, dst, src0, src1);
447
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
451 */
452 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
453 assert(!dst1.reladdr); /* should be lowered in earlier passes */
454 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
455 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
456 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
457 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
458
459 reladdr_to_temp(ir, &src3, &num_reladdr);
460 reladdr_to_temp(ir, &src2, &num_reladdr);
461 reladdr_to_temp(ir, &src1, &num_reladdr);
462 reladdr_to_temp(ir, &src0, &num_reladdr);
463
464 if (dst.reladdr || dst.reladdr2) {
465 if (dst.reladdr)
466 emit_arl(ir, address_reg, *dst.reladdr);
467 if (dst.reladdr2)
468 emit_arl(ir, address_reg2, *dst.reladdr2);
469 num_reladdr--;
470 }
471
472 assert(num_reladdr == 0);
473
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
476
477 inst->op = op;
478 inst->precise = this->precise;
479 inst->info = tgsi_get_opcode_info(op);
480 inst->dst[0] = dst;
481 inst->dst[1] = dst1;
482 inst->src[0] = src0;
483 inst->src[1] = src1;
484 inst->src[2] = src2;
485 inst->src[3] = src3;
486 inst->is_64bit_expanded = false;
487 inst->ir = ir;
488 inst->dead_mask = 0;
489 inst->tex_offsets = NULL;
490 inst->tex_offset_num_offset = 0;
491 inst->saturate = 0;
492 inst->tex_shadow = 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
495 */
496 inst->tex_type = GLSL_TYPE_FLOAT;
497
498 /* Update indirect addressing status used by TGSI */
499 if (dst.reladdr || dst.reladdr2) {
500 switch (dst.file) {
501 case PROGRAM_STATE_VAR:
502 case PROGRAM_CONSTANT:
503 case PROGRAM_UNIFORM:
504 this->indirect_addr_consts = true;
505 break;
506 case PROGRAM_IMMEDIATE:
507 assert(!"immediates should not have indirect addressing");
508 break;
509 default:
510 break;
511 }
512 }
513 else {
514 for (i = 0; i < 4; i++) {
515 if (inst->src[i].reladdr) {
516 switch (inst->src[i].file) {
517 case PROGRAM_STATE_VAR:
518 case PROGRAM_CONSTANT:
519 case PROGRAM_UNIFORM:
520 this->indirect_addr_consts = true;
521 break;
522 case PROGRAM_IMMEDIATE:
523 assert(!"immediates should not have indirect addressing");
524 break;
525 default:
526 break;
527 }
528 }
529 }
530 }
531
532 /*
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
536 *
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
541 *
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
544 *
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
549 */
550 for (j = 0; j < 2; j++) {
551 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
552 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
553 inst->dst[j].type == GLSL_TYPE_ARRAY) {
554 enum glsl_base_type type = find_array_type(this->outputs,
555 this->num_outputs,
556 inst->dst[j].array_id);
557 if (glsl_base_type_is_64bit(type))
558 dst_is_64bit[j] = true;
559 }
560 }
561
562 if (dst_is_64bit[0] || dst_is_64bit[1] ||
563 glsl_base_type_is_64bit(inst->src[0].type)) {
564 glsl_to_tgsi_instruction *dinst = NULL;
565 int initial_src_swz[4], initial_src_idx[4];
566 int initial_dst_idx[2], initial_dst_writemask[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
569 ? inst->dst[0].writemask : inst->dst[1].writemask;
570
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j = 0; j < 2; j++) {
573 initial_dst_writemask[j] = inst->dst[j].writemask;
574 initial_dst_idx[j] = inst->dst[j].index;
575 }
576
577 for (j = 0; j < 4; j++) {
578 initial_src_swz[j] = inst->src[j].swizzle;
579 initial_src_idx[j] = inst->src[j].index;
580 }
581
582 /*
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
585 */
586 st_src_reg addr;
587 while (writemask) {
588
589 int i = u_bit_scan(&writemask);
590
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
594 inst->op == TGSI_OPCODE_STORE) &&
595 addr.file == PROGRAM_UNDEFINED) {
596 /* We have to advance the buffer address by 16 */
597 addr = get_temp(glsl_type::uint_type);
598 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
599 inst->src[0], st_src_reg_for_int(16));
600 }
601
602 /* first time use previous instruction */
603 if (dinst == NULL) {
604 dinst = inst;
605 } else {
606 /* create a new instructions for subsequent attempts */
607 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
608 *dinst = *inst;
609 dinst->next = NULL;
610 dinst->prev = NULL;
611 }
612 this->instructions.push_tail(dinst);
613 dinst->is_64bit_expanded = true;
614
615 /* modify the destination if we are splitting */
616 for (j = 0; j < 2; j++) {
617 if (dst_is_64bit[j]) {
618 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
619 dinst->dst[j].index = initial_dst_idx[j];
620 if (i > 1) {
621 if (dinst->op == TGSI_OPCODE_LOAD ||
622 dinst->op == TGSI_OPCODE_STORE)
623 dinst->src[0] = addr;
624 if (dinst->op != TGSI_OPCODE_STORE)
625 dinst->dst[j].index++;
626 }
627 } else {
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
630 */
631 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
632 }
633 }
634
635 /* modify the src registers */
636 for (j = 0; j < 4; j++) {
637 int swz = GET_SWZ(initial_src_swz[j], i);
638
639 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
640 dinst->src[j].index = initial_src_idx[j];
641 if (swz > 1) {
642 dinst->src[j].double_reg2 = true;
643 dinst->src[j].index++;
644 }
645
646 if (swz & 1)
647 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
648 SWIZZLE_Z, SWIZZLE_W);
649 else
650 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
651 SWIZZLE_X, SWIZZLE_Y);
652
653 } else {
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
656 * integer src1
657 */
658 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
659 op == TGSI_OPCODE_I2D ||
660 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
661 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
662 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
663 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
664 }
665 }
666 }
667 }
668 inst = dinst;
669 } else {
670 this->instructions.push_tail(inst);
671 }
672
673
674 return inst;
675 }
676
677 glsl_to_tgsi_instruction *
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
679 st_dst_reg dst,
680 st_src_reg src0, st_src_reg src1,
681 st_src_reg src2, st_src_reg src3)
682 {
683 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
684 }
685
686 /**
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
689 */
690 enum tgsi_opcode
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
692 st_dst_reg dst,
693 st_src_reg src0, st_src_reg src1)
694 {
695 enum glsl_base_type type = GLSL_TYPE_FLOAT;
696
697 if (op == TGSI_OPCODE_MOV)
698 return op;
699
700 assert(src0.type != GLSL_TYPE_ARRAY);
701 assert(src0.type != GLSL_TYPE_STRUCT);
702 assert(src1.type != GLSL_TYPE_ARRAY);
703 assert(src1.type != GLSL_TYPE_STRUCT);
704
705 if (is_resource_instruction(op))
706 type = src1.type;
707 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
708 type = GLSL_TYPE_INT64;
709 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
710 type = GLSL_TYPE_UINT64;
711 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
712 type = GLSL_TYPE_DOUBLE;
713 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
714 type = GLSL_TYPE_FLOAT;
715 else if (native_integers)
716 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
717
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
730 else \
731 op = TGSI_OPCODE_##f; \
732 break;
733
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
748 else \
749 op = TGSI_OPCODE_##c; \
750 break;
751
752 switch (op) {
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
755 *
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
757 */
758 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
759 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
760 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
761 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
762 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
763 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
764 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
765 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
766 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
767 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
768 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
769 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
770 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
771 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
772 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
773 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
774
775 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
776 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
777 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
778 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
779 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
780 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
781 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
782 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
783 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
784
785 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
786 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
787 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
788 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
789
790 default:
791 break;
792 }
793
794 assert(op != TGSI_OPCODE_LAST);
795 return op;
796 }
797
798 glsl_to_tgsi_instruction *
799 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
800 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
801 unsigned elements)
802 {
803 static const enum tgsi_opcode dot_opcodes[] = {
804 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
805 };
806
807 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
808 }
809
810 /**
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
812 *
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
817 */
818 void
819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
820 st_dst_reg dst,
821 st_src_reg orig_src0, st_src_reg orig_src1)
822 {
823 int i, j;
824 int done_mask = ~dst.writemask;
825
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
828 * dst channels.
829 */
830 for (i = 0; i < 4; i++) {
831 GLuint this_mask = (1 << i);
832 st_src_reg src0 = orig_src0;
833 st_src_reg src1 = orig_src1;
834
835 if (done_mask & this_mask)
836 continue;
837
838 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
839 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
840 for (j = i + 1; j < 4; j++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
843 * well.
844 */
845 if (!(done_mask & (1 << j)) &&
846 GET_SWZ(src0.swizzle, j) == src0_swiz &&
847 GET_SWZ(src1.swizzle, j) == src1_swiz) {
848 this_mask |= (1 << j);
849 }
850 }
851 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
852 src0_swiz, src0_swiz);
853 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
854 src1_swiz, src1_swiz);
855
856 dst.writemask = this_mask;
857 emit_asm(ir, op, dst, src0, src1);
858 done_mask |= this_mask;
859 }
860 }
861
862 void
863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
864 st_dst_reg dst, st_src_reg src0)
865 {
866 st_src_reg undef = undef_src;
867
868 undef.swizzle = SWIZZLE_XXXX;
869
870 emit_scalar(ir, op, dst, src0, undef);
871 }
872
873 void
874 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
875 st_dst_reg dst, st_src_reg src0)
876 {
877 enum tgsi_opcode op = TGSI_OPCODE_ARL;
878
879 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
880 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
881 return;
882
883 op = TGSI_OPCODE_UARL;
884 }
885
886 assert(dst.file == PROGRAM_ADDRESS);
887 if (dst.index >= this->num_address_regs)
888 this->num_address_regs = dst.index + 1;
889
890 emit_asm(NULL, op, dst, src0);
891 }
892
893 int
894 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
895 gl_constant_value values[8], int size,
896 GLenum datatype,
897 uint16_t *swizzle_out)
898 {
899 if (file == PROGRAM_CONSTANT) {
900 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
901 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
902 values, size, datatype,
903 &swizzle);
904 if (swizzle_out)
905 *swizzle_out = swizzle;
906 return result;
907 }
908
909 assert(file == PROGRAM_IMMEDIATE);
910
911 int index = 0;
912 immediate_storage *entry;
913 int size32 = size * ((datatype == GL_DOUBLE ||
914 datatype == GL_INT64_ARB ||
915 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
916 int i;
917
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
920 */
921 foreach_in_list(immediate_storage, entry, &this->immediates) {
922 immediate_storage *tmp = entry;
923
924 for (i = 0; i * 4 < size32; i++) {
925 int slot_size = MIN2(size32 - (i * 4), 4);
926 if (tmp->type != datatype || tmp->size32 != slot_size)
927 break;
928 if (memcmp(tmp->values, &values[i * 4],
929 slot_size * sizeof(gl_constant_value)))
930 break;
931
932 /* Everything matches, keep going until the full size is matched */
933 tmp = (immediate_storage *)tmp->next;
934 }
935
936 /* The full value matched */
937 if (i * 4 >= size32)
938 return index;
939
940 index++;
941 }
942
943 for (i = 0; i * 4 < size32; i++) {
944 int slot_size = MIN2(size32 - (i * 4), 4);
945 /* Add this immediate to the list. */
946 entry = new(mem_ctx) immediate_storage(&values[i * 4],
947 slot_size, datatype);
948 this->immediates.push_tail(entry);
949 this->num_immediates++;
950 }
951 return index;
952 }
953
954 st_src_reg
955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
956 {
957 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
958 union gl_constant_value uval;
959
960 uval.f = val;
961 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
962
963 return src;
964 }
965
966 st_src_reg
967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
968 {
969 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
970 union gl_constant_value uval[2];
971
972 memcpy(uval, &val, sizeof(uval));
973 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
974 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
975 return src;
976 }
977
978 st_src_reg
979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
980 {
981 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
982 union gl_constant_value uval;
983
984 assert(native_integers);
985
986 uval.i = val;
987 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
988
989 return src;
990 }
991
992 st_src_reg
993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
994 {
995 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
996 union gl_constant_value uval[2];
997
998 memcpy(uval, &val, sizeof(uval));
999 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
1000 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1001
1002 return src;
1003 }
1004
1005 st_src_reg
1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1007 {
1008 if (native_integers)
1009 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1010 st_src_reg_for_int(val);
1011 else
1012 return st_src_reg_for_float(val);
1013 }
1014
1015 static int
1016 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1017 {
1018 return type->count_attribute_slots(is_vs_input);
1019 }
1020
1021 static int
1022 type_size(const struct glsl_type *type)
1023 {
1024 return type->count_attribute_slots(false);
1025 }
1026
1027 static void
1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1029 exec_list *instructions, ir_constant *access)
1030 {
1031 /**
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1034 */
1035 enum tgsi_opcode op = inst->op;
1036 do {
1037 inst->resource = *buf;
1038 if (access)
1039 inst->buffer_access = access->value.u[0];
1040
1041 if (inst == instructions->get_head_raw())
1042 break;
1043 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1044
1045 if (inst->op == TGSI_OPCODE_UADD) {
1046 if (inst == instructions->get_head_raw())
1047 break;
1048 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1049 }
1050 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1051 }
1052
1053 /**
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1056 *
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1061 */
1062 static bool
1063 type_has_array_or_matrix(const glsl_type *type)
1064 {
1065 if (type->is_array() || type->is_matrix())
1066 return true;
1067
1068 if (type->is_struct()) {
1069 for (unsigned i = 0; i < type->length; i++) {
1070 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1071 return true;
1072 }
1073 }
1074 }
1075
1076 return false;
1077 }
1078
1079
1080 /**
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1083 * storage).
1084 */
1085 st_src_reg
1086 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1087 {
1088 st_src_reg src;
1089
1090 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1091 src.reladdr = NULL;
1092 src.negate = 0;
1093 src.abs = 0;
1094
1095 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1096 if (next_array >= max_num_arrays) {
1097 max_num_arrays += 32;
1098 array_sizes = (unsigned*)
1099 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1100 }
1101
1102 src.file = PROGRAM_ARRAY;
1103 src.index = 0;
1104 src.array_id = next_array + 1;
1105 array_sizes[next_array] = type_size(type);
1106 ++next_array;
1107
1108 } else {
1109 src.file = PROGRAM_TEMPORARY;
1110 src.index = next_temp;
1111 next_temp += type_size(type);
1112 }
1113
1114 if (type->is_array() || type->is_struct()) {
1115 src.swizzle = SWIZZLE_NOOP;
1116 } else {
1117 src.swizzle = swizzle_for_size(type->vector_elements);
1118 }
1119
1120 return src;
1121 }
1122
1123 variable_storage *
1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1125 {
1126 struct hash_entry *entry;
1127
1128 entry = _mesa_hash_table_search(this->variables, var);
1129 if (!entry)
1130 return NULL;
1131
1132 return (variable_storage *)entry->data;
1133 }
1134
1135 void
1136 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1137 {
1138 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1139 unsigned int i;
1140 const ir_state_slot *const slots = ir->get_state_slots();
1141 assert(slots != NULL);
1142
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1147 * out.
1148 */
1149 for (i = 0; i < ir->get_num_state_slots(); i++) {
1150 if (slots[i].swizzle != SWIZZLE_XYZW) {
1151 break;
1152 }
1153 }
1154
1155 variable_storage *storage;
1156 st_dst_reg dst;
1157 if (i == ir->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1160
1161 _mesa_hash_table_insert(this->variables, ir, storage);
1162
1163 dst = undef_dst;
1164 } else {
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1168 */
1169 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1170
1171 dst = st_dst_reg(get_temp(ir->type));
1172
1173 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1174 dst.array_id);
1175
1176 _mesa_hash_table_insert(this->variables, ir, storage);
1177 }
1178
1179
1180 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1181 int index = _mesa_add_state_reference(this->prog->Parameters,
1182 slots[i].tokens);
1183
1184 if (storage->file == PROGRAM_STATE_VAR) {
1185 if (storage->index == -1) {
1186 storage->index = index;
1187 } else {
1188 assert(index == storage->index + (int)i);
1189 }
1190 } else {
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1195 */
1196 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1197 src.swizzle = slots[i].swizzle;
1198 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1200 dst.index++;
1201 }
1202 }
1203
1204 if (storage->file == PROGRAM_TEMPORARY &&
1205 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1206 fail_link(this->shader_program,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir->name, dst.index - storage->index,
1209 type_size(ir->type));
1210 }
1211 }
1212 }
1213
1214 void
1215 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1216 {
1217 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1218
1219 visit_exec_list(&ir->body_instructions, this);
1220
1221 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1222 }
1223
1224 void
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1226 {
1227 switch (ir->mode) {
1228 case ir_loop_jump::jump_break:
1229 emit_asm(NULL, TGSI_OPCODE_BRK);
1230 break;
1231 case ir_loop_jump::jump_continue:
1232 emit_asm(NULL, TGSI_OPCODE_CONT);
1233 break;
1234 }
1235 }
1236
1237
1238 void
1239 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1240 {
1241 assert(0);
1242 (void)ir;
1243 }
1244
1245 void
1246 glsl_to_tgsi_visitor::visit(ir_function *ir)
1247 {
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1250 */
1251 if (strcmp(ir->name, "main") == 0) {
1252 const ir_function_signature *sig;
1253 exec_list empty;
1254
1255 sig = ir->matching_signature(NULL, &empty, false);
1256
1257 assert(sig);
1258
1259 foreach_in_list(ir_instruction, ir, &sig->body) {
1260 ir->accept(this);
1261 }
1262 }
1263 }
1264
1265 bool
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1267 {
1268 int nonmul_operand = 1 - mul_operand;
1269 st_src_reg a, b, c;
1270 st_dst_reg result_dst;
1271
1272 // there is no TGSI opcode for this
1273 if (ir->type->is_integer_64())
1274 return false;
1275
1276 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1277 if (!expr || expr->operation != ir_binop_mul)
1278 return false;
1279
1280 expr->operands[0]->accept(this);
1281 a = this->result;
1282 expr->operands[1]->accept(this);
1283 b = this->result;
1284 ir->operands[nonmul_operand]->accept(this);
1285 c = this->result;
1286
1287 this->result = get_temp(ir->type);
1288 result_dst = st_dst_reg(this->result);
1289 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1290 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1291
1292 return true;
1293 }
1294
1295 /**
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1297 *
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1302 *
1303 * - a * !b
1304 * - a * (1 - b)
1305 * - (a * 1) - (a * b)
1306 * - a + -(a * b)
1307 * - a + (a * -b)
1308 *
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1310 * instruction.
1311 */
1312 bool
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1314 int try_operand)
1315 {
1316 const int other_operand = 1 - try_operand;
1317 st_src_reg a, b;
1318
1319 ir_expression *expr = ir->operands[try_operand]->as_expression();
1320 if (!expr || expr->operation != ir_unop_logic_not)
1321 return false;
1322
1323 ir->operands[other_operand]->accept(this);
1324 a = this->result;
1325 expr->operands[0]->accept(this);
1326 b = this->result;
1327
1328 b.negate = ~b.negate;
1329
1330 this->result = get_temp(ir->type);
1331 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1332
1333 return true;
1334 }
1335
1336 void
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1338 st_src_reg *reg, int *num_reladdr)
1339 {
1340 if (!reg->reladdr && !reg->reladdr2)
1341 return;
1342
1343 if (reg->reladdr)
1344 emit_arl(ir, address_reg, *reg->reladdr);
1345 if (reg->reladdr2)
1346 emit_arl(ir, address_reg2, *reg->reladdr2);
1347
1348 if (*num_reladdr != 1) {
1349 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1350
1351 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1352 *reg = temp;
1353 }
1354
1355 (*num_reladdr)--;
1356 }
1357
1358 void
1359 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1360 {
1361 st_src_reg op[ARRAY_SIZE(ir->operands)];
1362
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1364 */
1365 if (!this->precise && ir->operation == ir_binop_add) {
1366 if (try_emit_mad(ir, 1))
1367 return;
1368 if (try_emit_mad(ir, 0))
1369 return;
1370 }
1371
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1373 */
1374 if (!native_integers && ir->operation == ir_binop_logic_and) {
1375 if (try_emit_mad_for_and_not(ir, 1))
1376 return;
1377 if (try_emit_mad_for_and_not(ir, 0))
1378 return;
1379 }
1380
1381 if (ir->operation == ir_quadop_vector)
1382 assert(!"ir_quadop_vector should have been lowered");
1383
1384 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1385 this->result.file = PROGRAM_UNDEFINED;
1386 ir->operands[operand]->accept(this);
1387 if (this->result.file == PROGRAM_UNDEFINED) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir->operands[operand]->print();
1390 printf("\n");
1391 exit(1);
1392 }
1393 op[operand] = this->result;
1394
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1397 */
1398 assert(!ir->operands[operand]->type->is_matrix());
1399 }
1400
1401 visit_expression(ir, op);
1402 }
1403
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1407 */
1408 void
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1410 {
1411 st_src_reg result_src;
1412 st_dst_reg result_dst;
1413
1414 int vector_elements = ir->operands[0]->type->vector_elements;
1415 if (ir->operands[1] &&
1416 ir->operation != ir_binop_interpolate_at_offset &&
1417 ir->operation != ir_binop_interpolate_at_sample) {
1418 st_src_reg *swz_op = NULL;
1419 if (vector_elements > ir->operands[1]->type->vector_elements) {
1420 assert(ir->operands[1]->type->vector_elements == 1);
1421 swz_op = &op[1];
1422 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1423 assert(ir->operands[0]->type->vector_elements == 1);
1424 swz_op = &op[0];
1425 }
1426 if (swz_op) {
1427 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1428 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1429 swizzle_x, swizzle_x);
1430 }
1431 vector_elements = MAX2(vector_elements,
1432 ir->operands[1]->type->vector_elements);
1433 }
1434 if (ir->operands[2] &&
1435 ir->operands[2]->type->vector_elements != vector_elements) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir->operands[2]->type->vector_elements == 1);
1438 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1439 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1440 swizzle_x, swizzle_x);
1441 }
1442
1443 this->result.file = PROGRAM_UNDEFINED;
1444
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1447 */
1448 result_src = get_temp(ir->type);
1449 /* convenience for the emit functions below. */
1450 result_dst = st_dst_reg(result_src);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1453 * sequences.
1454 */
1455 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1456
1457 switch (ir->operation) {
1458 case ir_unop_logic_not:
1459 if (result_dst.type != GLSL_TYPE_FLOAT)
1460 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1461 else {
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1466 */
1467 op[0].negate = ~op[0].negate;
1468 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1469 st_src_reg_for_float(1.0));
1470 }
1471 break;
1472 case ir_unop_neg:
1473 if (result_dst.type == GLSL_TYPE_INT64 ||
1474 result_dst.type == GLSL_TYPE_UINT64)
1475 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1476 else if (result_dst.type == GLSL_TYPE_INT ||
1477 result_dst.type == GLSL_TYPE_UINT)
1478 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1479 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1480 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1481 else {
1482 op[0].negate = ~op[0].negate;
1483 result_src = op[0];
1484 }
1485 break;
1486 case ir_unop_subroutine_to_int:
1487 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1488 break;
1489 case ir_unop_abs:
1490 if (result_dst.type == GLSL_TYPE_FLOAT)
1491 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1492 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1493 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1494 else if (result_dst.type == GLSL_TYPE_INT64 ||
1495 result_dst.type == GLSL_TYPE_UINT64)
1496 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1497 else
1498 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1499 break;
1500 case ir_unop_sign:
1501 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1502 break;
1503 case ir_unop_rcp:
1504 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1505 break;
1506
1507 case ir_unop_exp2:
1508 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1509 break;
1510 case ir_unop_exp:
1511 assert(!"not reached: should be handled by exp_to_exp2");
1512 break;
1513 case ir_unop_log:
1514 assert(!"not reached: should be handled by log_to_log2");
1515 break;
1516 case ir_unop_log2:
1517 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1518 break;
1519 case ir_unop_sin:
1520 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1521 break;
1522 case ir_unop_cos:
1523 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1524 break;
1525 case ir_unop_saturate: {
1526 glsl_to_tgsi_instruction *inst;
1527 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1528 inst->saturate = true;
1529 break;
1530 }
1531
1532 case ir_unop_dFdx:
1533 case ir_unop_dFdx_coarse:
1534 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1535 break;
1536 case ir_unop_dFdx_fine:
1537 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1538 break;
1539 case ir_unop_dFdy:
1540 case ir_unop_dFdy_coarse:
1541 case ir_unop_dFdy_fine:
1542 {
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1546 */
1547 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1548 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1549
1550 unsigned transform_y_index =
1551 _mesa_add_state_reference(this->prog->Parameters,
1552 transform_y_state);
1553
1554 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1555 transform_y_index,
1556 glsl_type::vec4_type);
1557 transform_y.swizzle = SWIZZLE_XXXX;
1558
1559 st_src_reg temp = get_temp(glsl_type::vec4_type);
1560
1561 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1562 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1563 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1564 break;
1565 }
1566
1567 case ir_unop_frexp_sig:
1568 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1569 break;
1570
1571 case ir_unop_frexp_exp:
1572 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1573 break;
1574
1575 case ir_unop_noise: {
1576 /* At some point, a motivated person could add a better
1577 * implementation of noise. Currently not even the nvidia
1578 * binary drivers do anything more than this. In any case, the
1579 * place to do this is in the GL state tracker, not the poor
1580 * driver.
1581 */
1582 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1583 break;
1584 }
1585
1586 case ir_binop_add:
1587 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1588 break;
1589 case ir_binop_sub:
1590 op[1].negate = ~op[1].negate;
1591 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1592 break;
1593
1594 case ir_binop_mul:
1595 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1596 break;
1597 case ir_binop_div:
1598 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1599 break;
1600 case ir_binop_mod:
1601 if (result_dst.type == GLSL_TYPE_FLOAT)
1602 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1603 else
1604 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1605 break;
1606
1607 case ir_binop_less:
1608 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1609 break;
1610 case ir_binop_gequal:
1611 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1612 break;
1613 case ir_binop_equal:
1614 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1615 break;
1616 case ir_binop_nequal:
1617 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1618 break;
1619 case ir_binop_all_equal:
1620 /* "==" operator producing a scalar boolean. */
1621 if (ir->operands[0]->type->is_vector() ||
1622 ir->operands[1]->type->is_vector()) {
1623 st_src_reg temp = get_temp(native_integers ?
1624 glsl_type::uvec4_type :
1625 glsl_type::vec4_type);
1626
1627 if (native_integers) {
1628 st_dst_reg temp_dst = st_dst_reg(temp);
1629 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1630
1631 if (ir->operands[0]->type->is_boolean() &&
1632 ir->operands[1]->as_constant() &&
1633 ir->operands[1]->as_constant()->is_one()) {
1634 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1635 } else {
1636 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1637 }
1638
1639 /* Emit 1-3 AND operations to combine the SEQ results. */
1640 switch (ir->operands[0]->type->vector_elements) {
1641 case 2:
1642 break;
1643 case 3:
1644 temp_dst.writemask = WRITEMASK_Y;
1645 temp1.swizzle = SWIZZLE_YYYY;
1646 temp2.swizzle = SWIZZLE_ZZZZ;
1647 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1648 break;
1649 case 4:
1650 temp_dst.writemask = WRITEMASK_X;
1651 temp1.swizzle = SWIZZLE_XXXX;
1652 temp2.swizzle = SWIZZLE_YYYY;
1653 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1654 temp_dst.writemask = WRITEMASK_Y;
1655 temp1.swizzle = SWIZZLE_ZZZZ;
1656 temp2.swizzle = SWIZZLE_WWWW;
1657 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1658 }
1659
1660 temp1.swizzle = SWIZZLE_XXXX;
1661 temp2.swizzle = SWIZZLE_YYYY;
1662 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1663 } else {
1664 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1665
1666 /* After the dot-product, the value will be an integer on the
1667 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1668 */
1669 emit_dp(ir, result_dst, temp, temp, vector_elements);
1670
1671 /* Negating the result of the dot-product gives values on the range
1672 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1673 * This is achieved using SGE.
1674 */
1675 st_src_reg sge_src = result_src;
1676 sge_src.negate = ~sge_src.negate;
1677 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1678 st_src_reg_for_float(0.0));
1679 }
1680 } else {
1681 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1682 }
1683 break;
1684 case ir_binop_any_nequal:
1685 /* "!=" operator producing a scalar boolean. */
1686 if (ir->operands[0]->type->is_vector() ||
1687 ir->operands[1]->type->is_vector()) {
1688 st_src_reg temp = get_temp(native_integers ?
1689 glsl_type::uvec4_type :
1690 glsl_type::vec4_type);
1691 if (ir->operands[0]->type->is_boolean() &&
1692 ir->operands[1]->as_constant() &&
1693 ir->operands[1]->as_constant()->is_zero()) {
1694 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1695 } else {
1696 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1697 }
1698
1699 if (native_integers) {
1700 st_dst_reg temp_dst = st_dst_reg(temp);
1701 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1702
1703 /* Emit 1-3 OR operations to combine the SNE results. */
1704 switch (ir->operands[0]->type->vector_elements) {
1705 case 2:
1706 break;
1707 case 3:
1708 temp_dst.writemask = WRITEMASK_Y;
1709 temp1.swizzle = SWIZZLE_YYYY;
1710 temp2.swizzle = SWIZZLE_ZZZZ;
1711 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1712 break;
1713 case 4:
1714 temp_dst.writemask = WRITEMASK_X;
1715 temp1.swizzle = SWIZZLE_XXXX;
1716 temp2.swizzle = SWIZZLE_YYYY;
1717 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1718 temp_dst.writemask = WRITEMASK_Y;
1719 temp1.swizzle = SWIZZLE_ZZZZ;
1720 temp2.swizzle = SWIZZLE_WWWW;
1721 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1722 }
1723
1724 temp1.swizzle = SWIZZLE_XXXX;
1725 temp2.swizzle = SWIZZLE_YYYY;
1726 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1727 } else {
1728 /* After the dot-product, the value will be an integer on the
1729 * range [0,4]. Zero stays zero, and positive values become 1.0.
1730 */
1731 glsl_to_tgsi_instruction *const dp =
1732 emit_dp(ir, result_dst, temp, temp, vector_elements);
1733 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1734 /* The clamping to [0,1] can be done for free in the fragment
1735 * shader with a saturate.
1736 */
1737 dp->saturate = true;
1738 } else {
1739 /* Negating the result of the dot-product gives values on the
1740 * range [-4, 0]. Zero stays zero, and negative values become
1741 * 1.0. This achieved using SLT.
1742 */
1743 st_src_reg slt_src = result_src;
1744 slt_src.negate = ~slt_src.negate;
1745 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1746 st_src_reg_for_float(0.0));
1747 }
1748 }
1749 } else {
1750 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1751 }
1752 break;
1753
1754 case ir_binop_logic_xor:
1755 if (native_integers)
1756 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1757 else
1758 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1759 break;
1760
1761 case ir_binop_logic_or: {
1762 if (native_integers) {
1763 /* If integers are used as booleans, we can use an actual "or"
1764 * instruction.
1765 */
1766 assert(native_integers);
1767 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1768 } else {
1769 /* After the addition, the value will be an integer on the
1770 * range [0,2]. Zero stays zero, and positive values become 1.0.
1771 */
1772 glsl_to_tgsi_instruction *add =
1773 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1774 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1775 /* The clamping to [0,1] can be done for free in the fragment
1776 * shader with a saturate if floats are being used as boolean
1777 * values.
1778 */
1779 add->saturate = true;
1780 } else {
1781 /* Negating the result of the addition gives values on the range
1782 * [-2, 0]. Zero stays zero, and negative values become 1.0
1783 * This is achieved using SLT.
1784 */
1785 st_src_reg slt_src = result_src;
1786 slt_src.negate = ~slt_src.negate;
1787 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1788 st_src_reg_for_float(0.0));
1789 }
1790 }
1791 break;
1792 }
1793
1794 case ir_binop_logic_and:
1795 /* If native integers are disabled, the bool args are stored as float 0.0
1796 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1797 * actual AND opcode.
1798 */
1799 if (native_integers)
1800 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1801 else
1802 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1803 break;
1804
1805 case ir_binop_dot:
1806 assert(ir->operands[0]->type->is_vector());
1807 assert(ir->operands[0]->type == ir->operands[1]->type);
1808 emit_dp(ir, result_dst, op[0], op[1],
1809 ir->operands[0]->type->vector_elements);
1810 break;
1811
1812 case ir_unop_sqrt:
1813 if (have_sqrt) {
1814 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1815 } else {
1816 /* This is the only instruction sequence that makes the game "Risen"
1817 * render correctly. ABS is not required for the game, but since GLSL
1818 * declares negative values as "undefined", allowing us to do whatever
1819 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1820 * behavior.
1821 */
1822 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1823 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1824 }
1825 break;
1826 case ir_unop_rsq:
1827 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1828 break;
1829 case ir_unop_i2f:
1830 if (native_integers) {
1831 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1832 break;
1833 }
1834 /* fallthrough to next case otherwise */
1835 case ir_unop_b2f:
1836 if (native_integers) {
1837 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1838 st_src_reg_for_float(1.0));
1839 break;
1840 }
1841 /* fallthrough to next case otherwise */
1842 case ir_unop_i2u:
1843 case ir_unop_u2i:
1844 case ir_unop_i642u64:
1845 case ir_unop_u642i64:
1846 /* Converting between signed and unsigned integers is a no-op. */
1847 result_src = op[0];
1848 result_src.type = result_dst.type;
1849 break;
1850 case ir_unop_b2i:
1851 if (native_integers) {
1852 /* Booleans are stored as integers using ~0 for true and 0 for false.
1853 * GLSL requires that int(bool) return 1 for true and 0 for false.
1854 * This conversion is done with AND, but it could be done with NEG.
1855 */
1856 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1857 st_src_reg_for_int(1));
1858 } else {
1859 /* Booleans and integers are both stored as floats when native
1860 * integers are disabled.
1861 */
1862 result_src = op[0];
1863 }
1864 break;
1865 case ir_unop_f2i:
1866 if (native_integers)
1867 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1868 else
1869 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1870 break;
1871 case ir_unop_f2u:
1872 if (native_integers)
1873 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1874 else
1875 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1876 break;
1877 case ir_unop_bitcast_f2i:
1878 case ir_unop_bitcast_f2u:
1879 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1880 if (op[0].negate || op[0].abs)
1881 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1882 else
1883 result_src = op[0];
1884 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1885 GLSL_TYPE_UINT;
1886 break;
1887 case ir_unop_bitcast_i2f:
1888 case ir_unop_bitcast_u2f:
1889 result_src = op[0];
1890 result_src.type = GLSL_TYPE_FLOAT;
1891 break;
1892 case ir_unop_f2b:
1893 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1894 st_src_reg_for_float(0.0));
1895 break;
1896 case ir_unop_d2b:
1897 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1898 st_src_reg_for_double(0.0));
1899 break;
1900 case ir_unop_i2b:
1901 if (native_integers)
1902 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1903 st_src_reg_for_int(0));
1904 else
1905 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1906 st_src_reg_for_float(0.0));
1907 break;
1908 case ir_unop_bitcast_u642d:
1909 case ir_unop_bitcast_i642d:
1910 result_src = op[0];
1911 result_src.type = GLSL_TYPE_DOUBLE;
1912 break;
1913 case ir_unop_bitcast_d2i64:
1914 result_src = op[0];
1915 result_src.type = GLSL_TYPE_INT64;
1916 break;
1917 case ir_unop_bitcast_d2u64:
1918 result_src = op[0];
1919 result_src.type = GLSL_TYPE_UINT64;
1920 break;
1921 case ir_unop_trunc:
1922 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1923 break;
1924 case ir_unop_ceil:
1925 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1926 break;
1927 case ir_unop_floor:
1928 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1929 break;
1930 case ir_unop_round_even:
1931 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1932 break;
1933 case ir_unop_fract:
1934 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1935 break;
1936
1937 case ir_binop_min:
1938 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1939 break;
1940 case ir_binop_max:
1941 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1942 break;
1943 case ir_binop_pow:
1944 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1945 break;
1946
1947 case ir_unop_bit_not:
1948 if (native_integers) {
1949 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1950 break;
1951 }
1952 case ir_unop_u2f:
1953 if (native_integers) {
1954 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1955 break;
1956 }
1957 case ir_binop_lshift:
1958 case ir_binop_rshift:
1959 if (native_integers) {
1960 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1961 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1962 st_src_reg count;
1963
1964 if (glsl_base_type_is_64bit(op[0].type)) {
1965 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1966 * 64 bits.
1967 */
1968 count = get_temp(glsl_type::u64vec(ir->operands[1]
1969 ->type->components()));
1970 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1971 } else {
1972 count = op[1];
1973 }
1974
1975 emit_asm(ir, opcode, result_dst, op[0], count);
1976 break;
1977 }
1978 case ir_binop_bit_and:
1979 if (native_integers) {
1980 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1981 break;
1982 }
1983 case ir_binop_bit_xor:
1984 if (native_integers) {
1985 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1986 break;
1987 }
1988 case ir_binop_bit_or:
1989 if (native_integers) {
1990 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1991 break;
1992 }
1993
1994 assert(!"GLSL 1.30 features unsupported");
1995 break;
1996
1997 case ir_binop_ubo_load: {
1998 if (ctx->Const.UseSTD430AsDefaultPacking) {
1999 ir_rvalue *block = ir->operands[0];
2000 ir_rvalue *offset = ir->operands[1];
2001 ir_constant *const_block = block->as_constant();
2002
2003 st_src_reg cbuf(PROGRAM_CONSTANT,
2004 (const_block ? const_block->value.u[0] + 1 : 1),
2005 ir->type->base_type);
2006
2007 cbuf.has_index2 = true;
2008
2009 if (!const_block) {
2010 block->accept(this);
2011 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2012 *cbuf.reladdr = this->result;
2013 emit_arl(ir, sampler_reladdr, this->result);
2014 }
2015
2016 /* Calculate the surface offset */
2017 offset->accept(this);
2018 st_src_reg off = this->result;
2019
2020 glsl_to_tgsi_instruction *inst =
2021 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2022
2023 if (result_dst.type == GLSL_TYPE_BOOL)
2024 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2025 st_src_reg_for_int(0));
2026
2027 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2028 NULL);
2029 } else {
2030 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2031 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2032 unsigned const_offset = const_offset_ir ?
2033 const_offset_ir->value.u[0] : 0;
2034 unsigned const_block = const_uniform_block ?
2035 const_uniform_block->value.u[0] + 1 : 1;
2036 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2037 st_src_reg cbuf;
2038
2039 cbuf.type = ir->type->base_type;
2040 cbuf.file = PROGRAM_CONSTANT;
2041 cbuf.index = 0;
2042 cbuf.reladdr = NULL;
2043 cbuf.negate = 0;
2044 cbuf.abs = 0;
2045 cbuf.index2D = const_block;
2046
2047 assert(ir->type->is_vector() || ir->type->is_scalar());
2048
2049 if (const_offset_ir) {
2050 /* Constant index into constant buffer */
2051 cbuf.reladdr = NULL;
2052 cbuf.index = const_offset / 16;
2053 } else {
2054 ir_expression *offset_expr = ir->operands[1]->as_expression();
2055 st_src_reg offset = op[1];
2056
2057 /* The OpenGL spec is written in such a way that accesses with
2058 * non-constant offset are almost always vec4-aligned. The only
2059 * exception to this are members of structs in arrays of structs:
2060 * each struct in an array of structs is at least vec4-aligned,
2061 * but single-element and [ui]vec2 members of the struct may be at
2062 * an offset that is not a multiple of 16 bytes.
2063 *
2064 * Here, we extract that offset, relying on previous passes to
2065 * always generate offset expressions of the form
2066 * (+ expr constant_offset).
2067 *
2068 * Note that the std430 layout, which allows more cases of
2069 * alignment less than vec4 in arrays, is not supported for
2070 * uniform blocks, so we do not have to deal with it here.
2071 */
2072 if (offset_expr && offset_expr->operation == ir_binop_add) {
2073 const_offset_ir = offset_expr->operands[1]->as_constant();
2074 if (const_offset_ir) {
2075 const_offset = const_offset_ir->value.u[0];
2076 cbuf.index = const_offset / 16;
2077 offset_expr->operands[0]->accept(this);
2078 offset = this->result;
2079 }
2080 }
2081
2082 /* Relative/variable index into constant buffer */
2083 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2084 st_src_reg_for_int(4));
2085 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2086 *cbuf.reladdr = index_reg;
2087 }
2088
2089 if (const_uniform_block) {
2090 /* Constant constant buffer */
2091 cbuf.reladdr2 = NULL;
2092 } else {
2093 /* Relative/variable constant buffer */
2094 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2095 *cbuf.reladdr2 = op[0];
2096 }
2097 cbuf.has_index2 = true;
2098
2099 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2100 if (glsl_base_type_is_64bit(cbuf.type))
2101 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2102 const_offset % 16 / 8,
2103 const_offset % 16 / 8,
2104 const_offset % 16 / 8);
2105 else
2106 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2107 const_offset % 16 / 4,
2108 const_offset % 16 / 4,
2109 const_offset % 16 / 4);
2110
2111 if (ir->type->is_boolean()) {
2112 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2113 st_src_reg_for_int(0));
2114 } else {
2115 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2116 }
2117 }
2118 break;
2119 }
2120 case ir_triop_lrp:
2121 /* note: we have to reorder the three args here */
2122 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2123 break;
2124 case ir_triop_csel:
2125 if (this->ctx->Const.NativeIntegers)
2126 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2127 else {
2128 op[0].negate = ~op[0].negate;
2129 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2130 }
2131 break;
2132 case ir_triop_bitfield_extract:
2133 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2134 break;
2135 case ir_quadop_bitfield_insert:
2136 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2137 break;
2138 case ir_unop_bitfield_reverse:
2139 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2140 break;
2141 case ir_unop_bit_count:
2142 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2143 break;
2144 case ir_unop_find_msb:
2145 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2146 break;
2147 case ir_unop_find_lsb:
2148 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2149 break;
2150 case ir_binop_imul_high:
2151 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2152 break;
2153 case ir_triop_fma:
2154 /* In theory, MAD is incorrect here. */
2155 if (have_fma)
2156 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2157 else
2158 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2159 break;
2160 case ir_unop_interpolate_at_centroid:
2161 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2162 break;
2163 case ir_binop_interpolate_at_offset: {
2164 /* The y coordinate needs to be flipped for the default fb */
2165 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2166 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2167
2168 unsigned transform_y_index =
2169 _mesa_add_state_reference(this->prog->Parameters,
2170 transform_y_state);
2171
2172 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2173 transform_y_index,
2174 glsl_type::vec4_type);
2175 transform_y.swizzle = SWIZZLE_XXXX;
2176
2177 st_src_reg temp = get_temp(glsl_type::vec2_type);
2178 st_dst_reg temp_dst = st_dst_reg(temp);
2179
2180 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2181 temp_dst.writemask = WRITEMASK_Y;
2182 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2183 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2184 break;
2185 }
2186 case ir_binop_interpolate_at_sample:
2187 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2188 break;
2189
2190 case ir_unop_d2f:
2191 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2192 break;
2193 case ir_unop_f2d:
2194 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2195 break;
2196 case ir_unop_d2i:
2197 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2198 break;
2199 case ir_unop_i2d:
2200 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2201 break;
2202 case ir_unop_d2u:
2203 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2204 break;
2205 case ir_unop_u2d:
2206 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2207 break;
2208 case ir_unop_unpack_double_2x32:
2209 case ir_unop_pack_double_2x32:
2210 case ir_unop_unpack_int_2x32:
2211 case ir_unop_pack_int_2x32:
2212 case ir_unop_unpack_uint_2x32:
2213 case ir_unop_pack_uint_2x32:
2214 case ir_unop_unpack_sampler_2x32:
2215 case ir_unop_pack_sampler_2x32:
2216 case ir_unop_unpack_image_2x32:
2217 case ir_unop_pack_image_2x32:
2218 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2219 break;
2220
2221 case ir_binop_ldexp:
2222 if (ir->operands[0]->type->is_double()) {
2223 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2224 } else if (ir->operands[0]->type->is_float()) {
2225 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2226 } else {
2227 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2228 }
2229 break;
2230
2231 case ir_unop_pack_half_2x16:
2232 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2233 break;
2234 case ir_unop_unpack_half_2x16:
2235 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2236 break;
2237
2238 case ir_unop_get_buffer_size: {
2239 ir_constant *const_offset = ir->operands[0]->as_constant();
2240 int buf_base = ctx->st->has_hw_atomics
2241 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
2242 st_src_reg buffer(
2243 PROGRAM_BUFFER,
2244 buf_base + (const_offset ? const_offset->value.u[0] : 0),
2245 GLSL_TYPE_UINT);
2246 if (!const_offset) {
2247 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2248 *buffer.reladdr = op[0];
2249 emit_arl(ir, sampler_reladdr, op[0]);
2250 }
2251 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2252 break;
2253 }
2254
2255 case ir_unop_u2i64:
2256 case ir_unop_u2u64:
2257 case ir_unop_b2i64: {
2258 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2259 st_dst_reg temp_dst = st_dst_reg(temp);
2260 unsigned orig_swz = op[0].swizzle;
2261 /*
2262 * To convert unsigned to 64-bit:
2263 * zero Y channel, copy X channel.
2264 */
2265 temp_dst.writemask = WRITEMASK_Y;
2266 if (vector_elements > 1)
2267 temp_dst.writemask |= WRITEMASK_W;
2268 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2269 temp_dst.writemask = WRITEMASK_X;
2270 if (vector_elements > 1)
2271 temp_dst.writemask |= WRITEMASK_Z;
2272 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2273 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2274 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2275 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2276 else
2277 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2278 result_src = temp;
2279 result_src.type = GLSL_TYPE_UINT64;
2280 if (vector_elements > 2) {
2281 /* Subtle: We rely on the fact that get_temp here returns the next
2282 * TGSI temporary register directly after the temp register used for
2283 * the first two components, so that the result gets picked up
2284 * automatically.
2285 */
2286 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2287 st_dst_reg temp_dst = st_dst_reg(temp);
2288 temp_dst.writemask = WRITEMASK_Y;
2289 if (vector_elements > 3)
2290 temp_dst.writemask |= WRITEMASK_W;
2291 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2292
2293 temp_dst.writemask = WRITEMASK_X;
2294 if (vector_elements > 3)
2295 temp_dst.writemask |= WRITEMASK_Z;
2296 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2297 GET_SWZ(orig_swz, 2),
2298 GET_SWZ(orig_swz, 3),
2299 GET_SWZ(orig_swz, 3));
2300 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2301 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2302 else
2303 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2304 st_src_reg_for_int(1));
2305 }
2306 break;
2307 }
2308 case ir_unop_i642i:
2309 case ir_unop_u642i:
2310 case ir_unop_u642u:
2311 case ir_unop_i642u: {
2312 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2313 st_dst_reg temp_dst = st_dst_reg(temp);
2314 unsigned orig_swz = op[0].swizzle;
2315 unsigned orig_idx = op[0].index;
2316 int el;
2317 temp_dst.writemask = WRITEMASK_X;
2318
2319 for (el = 0; el < vector_elements; el++) {
2320 unsigned swz = GET_SWZ(orig_swz, el);
2321 if (swz & 1)
2322 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2323 SWIZZLE_Z, SWIZZLE_Z);
2324 else
2325 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2326 SWIZZLE_X, SWIZZLE_X);
2327 if (swz > 2)
2328 op[0].index = orig_idx + 1;
2329 op[0].type = GLSL_TYPE_UINT;
2330 temp_dst.writemask = WRITEMASK_X << el;
2331 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2332 }
2333 result_src = temp;
2334 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2335 result_src.type = GLSL_TYPE_UINT;
2336 else
2337 result_src.type = GLSL_TYPE_INT;
2338 break;
2339 }
2340 case ir_unop_i642b:
2341 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2342 st_src_reg_for_int64(0));
2343 break;
2344 case ir_unop_i642f:
2345 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2346 break;
2347 case ir_unop_u642f:
2348 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2349 break;
2350 case ir_unop_i642d:
2351 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2352 break;
2353 case ir_unop_u642d:
2354 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2355 break;
2356 case ir_unop_i2i64:
2357 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2358 break;
2359 case ir_unop_f2i64:
2360 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2361 break;
2362 case ir_unop_d2i64:
2363 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2364 break;
2365 case ir_unop_i2u64:
2366 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2367 break;
2368 case ir_unop_f2u64:
2369 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2370 break;
2371 case ir_unop_d2u64:
2372 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2373 break;
2374 /* these might be needed */
2375 case ir_unop_pack_snorm_2x16:
2376 case ir_unop_pack_unorm_2x16:
2377 case ir_unop_pack_snorm_4x8:
2378 case ir_unop_pack_unorm_4x8:
2379
2380 case ir_unop_unpack_snorm_2x16:
2381 case ir_unop_unpack_unorm_2x16:
2382 case ir_unop_unpack_snorm_4x8:
2383 case ir_unop_unpack_unorm_4x8:
2384
2385 case ir_quadop_vector:
2386 case ir_binop_vector_extract:
2387 case ir_triop_vector_insert:
2388 case ir_binop_carry:
2389 case ir_binop_borrow:
2390 case ir_unop_ssbo_unsized_array_length:
2391 /* This operation is not supported, or should have already been handled.
2392 */
2393 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2394 break;
2395 }
2396
2397 this->result = result_src;
2398 }
2399
2400
2401 void
2402 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2403 {
2404 st_src_reg src;
2405 int i;
2406 int swizzle[4];
2407
2408 /* Note that this is only swizzles in expressions, not those on the left
2409 * hand side of an assignment, which do write masking. See ir_assignment
2410 * for that.
2411 */
2412
2413 ir->val->accept(this);
2414 src = this->result;
2415 assert(src.file != PROGRAM_UNDEFINED);
2416 assert(ir->type->vector_elements > 0);
2417
2418 for (i = 0; i < 4; i++) {
2419 if (i < ir->type->vector_elements) {
2420 switch (i) {
2421 case 0:
2422 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2423 break;
2424 case 1:
2425 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2426 break;
2427 case 2:
2428 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2429 break;
2430 case 3:
2431 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2432 break;
2433 }
2434 } else {
2435 /* If the type is smaller than a vec4, replicate the last
2436 * channel out.
2437 */
2438 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2439 }
2440 }
2441
2442 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2443
2444 this->result = src;
2445 }
2446
2447 /* Test if the variable is an array. Note that geometry and
2448 * tessellation shader inputs are outputs are always arrays (except
2449 * for patch inputs), so only the array element type is considered.
2450 */
2451 static bool
2452 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2453 {
2454 const glsl_type *type = var->type;
2455
2456 *remove_array = false;
2457
2458 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2459 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2460 return false;
2461
2462 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2463 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2464 stage == MESA_SHADER_TESS_CTRL) &&
2465 !var->data.patch) {
2466 if (!var->type->is_array())
2467 return false; /* a system value probably */
2468
2469 type = var->type->fields.array;
2470 *remove_array = true;
2471 }
2472
2473 return type->is_array() || type->is_matrix();
2474 }
2475
2476 static unsigned
2477 st_translate_interp_loc(ir_variable *var)
2478 {
2479 if (var->data.centroid)
2480 return TGSI_INTERPOLATE_LOC_CENTROID;
2481 else if (var->data.sample)
2482 return TGSI_INTERPOLATE_LOC_SAMPLE;
2483 else
2484 return TGSI_INTERPOLATE_LOC_CENTER;
2485 }
2486
2487 void
2488 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2489 {
2490 variable_storage *entry;
2491 ir_variable *var = ir->var;
2492 bool remove_array;
2493
2494 if (handle_bound_deref(ir->as_dereference()))
2495 return;
2496
2497 entry = find_variable_storage(ir->var);
2498
2499 if (!entry) {
2500 switch (var->data.mode) {
2501 case ir_var_uniform:
2502 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2503 var->data.param_index);
2504 _mesa_hash_table_insert(this->variables, var, entry);
2505 break;
2506 case ir_var_shader_in: {
2507 /* The linker assigns locations for varyings and attributes,
2508 * including deprecated builtins (like gl_Color), user-assign
2509 * generic attributes (glBindVertexLocation), and
2510 * user-defined varyings.
2511 */
2512 assert(var->data.location != -1);
2513
2514 const glsl_type *type_without_array = var->type->without_array();
2515 struct inout_decl *decl = &inputs[num_inputs];
2516 unsigned component = var->data.location_frac;
2517 unsigned num_components;
2518 num_inputs++;
2519
2520 if (type_without_array->is_64bit())
2521 component = component / 2;
2522 if (type_without_array->vector_elements)
2523 num_components = type_without_array->vector_elements;
2524 else
2525 num_components = 4;
2526
2527 decl->mesa_index = var->data.location;
2528 decl->interp = (glsl_interp_mode) var->data.interpolation;
2529 decl->interp_loc = st_translate_interp_loc(var);
2530 decl->base_type = type_without_array->base_type;
2531 decl->usage_mask = u_bit_consecutive(component, num_components);
2532
2533 if (is_inout_array(shader->Stage, var, &remove_array)) {
2534 decl->array_id = num_input_arrays + 1;
2535 num_input_arrays++;
2536 } else {
2537 decl->array_id = 0;
2538 }
2539
2540 if (remove_array)
2541 decl->size = type_size(var->type->fields.array);
2542 else
2543 decl->size = type_size(var->type);
2544
2545 entry = new(mem_ctx) variable_storage(var,
2546 PROGRAM_INPUT,
2547 decl->mesa_index,
2548 decl->array_id);
2549 entry->component = component;
2550
2551 _mesa_hash_table_insert(this->variables, var, entry);
2552
2553 break;
2554 }
2555 case ir_var_shader_out: {
2556 assert(var->data.location != -1);
2557
2558 const glsl_type *type_without_array = var->type->without_array();
2559 struct inout_decl *decl = &outputs[num_outputs];
2560 unsigned component = var->data.location_frac;
2561 unsigned num_components;
2562 num_outputs++;
2563
2564 decl->invariant = var->data.invariant;
2565
2566 if (type_without_array->is_64bit())
2567 component = component / 2;
2568 if (type_without_array->vector_elements)
2569 num_components = type_without_array->vector_elements;
2570 else
2571 num_components = 4;
2572
2573 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2574 decl->base_type = type_without_array->base_type;
2575 decl->usage_mask = u_bit_consecutive(component, num_components);
2576 if (var->data.stream & (1u << 31)) {
2577 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2578 } else {
2579 assert(var->data.stream < 4);
2580 decl->gs_out_streams = 0;
2581 for (unsigned i = 0; i < num_components; ++i)
2582 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2583 }
2584
2585 if (is_inout_array(shader->Stage, var, &remove_array)) {
2586 decl->array_id = num_output_arrays + 1;
2587 num_output_arrays++;
2588 } else {
2589 decl->array_id = 0;
2590 }
2591
2592 if (remove_array)
2593 decl->size = type_size(var->type->fields.array);
2594 else
2595 decl->size = type_size(var->type);
2596
2597 if (var->data.fb_fetch_output) {
2598 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2599 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2600 var->type, component, decl->array_id);
2601 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2602 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2603 dst.array_id);
2604 } else {
2605 entry = new(mem_ctx) variable_storage(var,
2606 PROGRAM_OUTPUT,
2607 decl->mesa_index,
2608 decl->array_id);
2609 }
2610 entry->component = component;
2611
2612 _mesa_hash_table_insert(this->variables, var, entry);
2613
2614 break;
2615 }
2616 case ir_var_system_value:
2617 entry = new(mem_ctx) variable_storage(var,
2618 PROGRAM_SYSTEM_VALUE,
2619 var->data.location);
2620 break;
2621 case ir_var_auto:
2622 case ir_var_temporary:
2623 st_src_reg src = get_temp(var->type);
2624
2625 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2626 src.array_id);
2627 _mesa_hash_table_insert(this->variables, var, entry);
2628
2629 break;
2630 }
2631
2632 if (!entry) {
2633 printf("Failed to make storage for %s\n", var->name);
2634 exit(1);
2635 }
2636 }
2637
2638 this->result = st_src_reg(entry->file, entry->index, var->type,
2639 entry->component, entry->array_id);
2640 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2641 var->data.mode == ir_var_shader_in &&
2642 var->type->without_array()->is_double())
2643 this->result.is_double_vertex_input = true;
2644 if (!native_integers)
2645 this->result.type = GLSL_TYPE_FLOAT;
2646 }
2647
2648 static void
2649 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2650 GLbitfield64* usage_mask,
2651 GLbitfield64 double_usage_mask,
2652 GLbitfield* patch_usage_mask)
2653 {
2654 unsigned i;
2655 int j;
2656
2657 /* Fix array declarations by removing unused array elements at both ends
2658 * of the arrays. For example, mat4[3] where only mat[1] is used.
2659 */
2660 for (i = 0; i < count; i++) {
2661 struct inout_decl *decl = &decls[i];
2662 if (!decl->array_id)
2663 continue;
2664
2665 /* Shrink the beginning. */
2666 for (j = 0; j < (int)decl->size; j++) {
2667 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2668 if (*patch_usage_mask &
2669 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2670 break;
2671 }
2672 else {
2673 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2674 break;
2675 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2676 break;
2677 }
2678
2679 decl->mesa_index++;
2680 decl->size--;
2681 j--;
2682 }
2683
2684 /* Shrink the end. */
2685 for (j = decl->size-1; j >= 0; j--) {
2686 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2687 if (*patch_usage_mask &
2688 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2689 break;
2690 }
2691 else {
2692 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2693 break;
2694 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2695 break;
2696 }
2697
2698 decl->size--;
2699 }
2700
2701 /* When not all entries of an array are accessed, we mark them as used
2702 * here anyway, to ensure that the input/output mapping logic doesn't get
2703 * confused.
2704 *
2705 * TODO This happens when an array isn't used via indirect access, which
2706 * some game ports do (at least eON-based). There is an optimization
2707 * opportunity here by replacing the array declaration with non-array
2708 * declarations of those slots that are actually used.
2709 */
2710 for (j = 1; j < (int)decl->size; ++j) {
2711 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2712 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2713 else
2714 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2715 }
2716 }
2717 }
2718
2719
2720 static void
2721 mark_array_io(struct inout_decl *decls, unsigned count,
2722 GLbitfield64* usage_mask,
2723 GLbitfield64 double_usage_mask,
2724 GLbitfield* patch_usage_mask)
2725 {
2726 unsigned i;
2727 int j;
2728
2729 /* Fix array declarations by removing unused array elements at both ends
2730 * of the arrays. For example, mat4[3] where only mat[1] is used.
2731 */
2732 for (i = 0; i < count; i++) {
2733 struct inout_decl *decl = &decls[i];
2734 if (!decl->array_id)
2735 continue;
2736
2737 /* When not all entries of an array are accessed, we mark them as used
2738 * here anyway, to ensure that the input/output mapping logic doesn't get
2739 * confused.
2740 *
2741 * TODO This happens when an array isn't used via indirect access, which
2742 * some game ports do (at least eON-based). There is an optimization
2743 * opportunity here by replacing the array declaration with non-array
2744 * declarations of those slots that are actually used.
2745 */
2746 for (j = 0; j < (int)decl->size; ++j) {
2747 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2748 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2749 else
2750 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2751 }
2752 }
2753 }
2754
2755 void
2756 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2757 {
2758 ir_constant *index;
2759 st_src_reg src;
2760 bool is_2D = false;
2761 ir_variable *var = ir->variable_referenced();
2762
2763 if (handle_bound_deref(ir->as_dereference()))
2764 return;
2765
2766 /* We only need the logic provided by st_glsl_storage_type_size()
2767 * for arrays of structs. Indirect sampler and image indexing is handled
2768 * elsewhere.
2769 */
2770 int element_size = ir->type->without_array()->is_struct() ?
2771 st_glsl_storage_type_size(ir->type, var->data.bindless) :
2772 type_size(ir->type);
2773
2774 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2775
2776 ir->array->accept(this);
2777 src = this->result;
2778
2779 if (!src.has_index2) {
2780 switch (this->prog->Target) {
2781 case GL_TESS_CONTROL_PROGRAM_NV:
2782 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2783 !ir->variable_referenced()->data.patch;
2784 break;
2785 case GL_TESS_EVALUATION_PROGRAM_NV:
2786 is_2D = src.file == PROGRAM_INPUT &&
2787 !ir->variable_referenced()->data.patch;
2788 break;
2789 case GL_GEOMETRY_PROGRAM_NV:
2790 is_2D = src.file == PROGRAM_INPUT;
2791 break;
2792 }
2793 }
2794
2795 if (is_2D)
2796 element_size = 1;
2797
2798 if (index) {
2799
2800 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2801 src.file == PROGRAM_INPUT)
2802 element_size = attrib_type_size(ir->type, true);
2803 if (is_2D) {
2804 src.index2D = index->value.i[0];
2805 src.has_index2 = true;
2806 } else
2807 src.index += index->value.i[0] * element_size;
2808 } else {
2809 /* Variable index array dereference. It eats the "vec4" of the
2810 * base of the array and an index that offsets the TGSI register
2811 * index.
2812 */
2813 ir->array_index->accept(this);
2814
2815 st_src_reg index_reg;
2816
2817 if (element_size == 1) {
2818 index_reg = this->result;
2819 } else {
2820 index_reg = get_temp(native_integers ?
2821 glsl_type::int_type : glsl_type::float_type);
2822
2823 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2824 this->result, st_src_reg_for_type(index_reg.type, element_size));
2825 }
2826
2827 /* If there was already a relative address register involved, add the
2828 * new and the old together to get the new offset.
2829 */
2830 if (!is_2D && src.reladdr != NULL) {
2831 st_src_reg accum_reg = get_temp(native_integers ?
2832 glsl_type::int_type : glsl_type::float_type);
2833
2834 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2835 index_reg, *src.reladdr);
2836
2837 index_reg = accum_reg;
2838 }
2839
2840 if (is_2D) {
2841 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2842 *src.reladdr2 = index_reg;
2843 src.index2D = 0;
2844 src.has_index2 = true;
2845 } else {
2846 src.reladdr = ralloc(mem_ctx, st_src_reg);
2847 *src.reladdr = index_reg;
2848 }
2849 }
2850
2851 /* Change the register type to the element type of the array. */
2852 src.type = ir->type->base_type;
2853
2854 this->result = src;
2855 }
2856
2857 void
2858 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2859 {
2860 unsigned int i;
2861 const glsl_type *struct_type = ir->record->type;
2862 ir_variable *var = ir->record->variable_referenced();
2863 int offset = 0;
2864
2865 if (handle_bound_deref(ir->as_dereference()))
2866 return;
2867
2868 ir->record->accept(this);
2869
2870 assert(ir->field_idx >= 0);
2871 assert(var);
2872 for (i = 0; i < struct_type->length; i++) {
2873 if (i == (unsigned) ir->field_idx)
2874 break;
2875 const glsl_type *member_type = struct_type->fields.structure[i].type;
2876 offset += st_glsl_storage_type_size(member_type, var->data.bindless);
2877 }
2878
2879 /* If the type is smaller than a vec4, replicate the last channel out. */
2880 if (ir->type->is_scalar() || ir->type->is_vector())
2881 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2882 else
2883 this->result.swizzle = SWIZZLE_NOOP;
2884
2885 this->result.index += offset;
2886 this->result.type = ir->type->base_type;
2887 }
2888
2889 /**
2890 * We want to be careful in assignment setup to hit the actual storage
2891 * instead of potentially using a temporary like we might with the
2892 * ir_dereference handler.
2893 */
2894 static st_dst_reg
2895 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2896 {
2897 /* The LHS must be a dereference. If the LHS is a variable indexed array
2898 * access of a vector, it must be separated into a series conditional moves
2899 * before reaching this point (see ir_vec_index_to_cond_assign).
2900 */
2901 assert(ir->as_dereference());
2902 ir_dereference_array *deref_array = ir->as_dereference_array();
2903 if (deref_array) {
2904 assert(!deref_array->array->type->is_vector());
2905 }
2906
2907 /* Use the rvalue deref handler for the most part. We write swizzles using
2908 * the writemask, but we do extract the base component for enhanced layouts
2909 * from the source swizzle.
2910 */
2911 ir->accept(v);
2912 *component = GET_SWZ(v->result.swizzle, 0);
2913 return st_dst_reg(v->result);
2914 }
2915
2916 /**
2917 * Process the condition of a conditional assignment
2918 *
2919 * Examines the condition of a conditional assignment to generate the optimal
2920 * first operand of a \c CMP instruction. If the condition is a relational
2921 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2922 * used as the source for the \c CMP instruction. Otherwise the comparison
2923 * is processed to a boolean result, and the boolean result is used as the
2924 * operand to the CMP instruction.
2925 */
2926 bool
2927 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2928 {
2929 ir_rvalue *src_ir = ir;
2930 bool negate = true;
2931 bool switch_order = false;
2932
2933 ir_expression *const expr = ir->as_expression();
2934
2935 if (native_integers) {
2936 if ((expr != NULL) && (expr->num_operands == 2)) {
2937 enum glsl_base_type type = expr->operands[0]->type->base_type;
2938 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2939 type == GLSL_TYPE_BOOL) {
2940 if (expr->operation == ir_binop_equal) {
2941 if (expr->operands[0]->is_zero()) {
2942 src_ir = expr->operands[1];
2943 switch_order = true;
2944 }
2945 else if (expr->operands[1]->is_zero()) {
2946 src_ir = expr->operands[0];
2947 switch_order = true;
2948 }
2949 }
2950 else if (expr->operation == ir_binop_nequal) {
2951 if (expr->operands[0]->is_zero()) {
2952 src_ir = expr->operands[1];
2953 }
2954 else if (expr->operands[1]->is_zero()) {
2955 src_ir = expr->operands[0];
2956 }
2957 }
2958 }
2959 }
2960
2961 src_ir->accept(this);
2962 return switch_order;
2963 }
2964
2965 if ((expr != NULL) && (expr->num_operands == 2)) {
2966 bool zero_on_left = false;
2967
2968 if (expr->operands[0]->is_zero()) {
2969 src_ir = expr->operands[1];
2970 zero_on_left = true;
2971 } else if (expr->operands[1]->is_zero()) {
2972 src_ir = expr->operands[0];
2973 zero_on_left = false;
2974 }
2975
2976 /* a is - 0 + - 0 +
2977 * (a < 0) T F F ( a < 0) T F F
2978 * (0 < a) F F T (-a < 0) F F T
2979 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2980 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2981 *
2982 * Note that exchanging the order of 0 and 'a' in the comparison simply
2983 * means that the value of 'a' should be negated.
2984 */
2985 if (src_ir != ir) {
2986 switch (expr->operation) {
2987 case ir_binop_less:
2988 switch_order = false;
2989 negate = zero_on_left;
2990 break;
2991
2992 case ir_binop_gequal:
2993 switch_order = true;
2994 negate = zero_on_left;
2995 break;
2996
2997 default:
2998 /* This isn't the right kind of comparison afterall, so make sure
2999 * the whole condition is visited.
3000 */
3001 src_ir = ir;
3002 break;
3003 }
3004 }
3005 }
3006
3007 src_ir->accept(this);
3008
3009 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3010 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3011 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3012 * computing the condition.
3013 */
3014 if (negate)
3015 this->result.negate = ~this->result.negate;
3016
3017 return switch_order;
3018 }
3019
3020 void
3021 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
3022 st_dst_reg *l, st_src_reg *r,
3023 st_src_reg *cond, bool cond_swap)
3024 {
3025 if (type->is_struct()) {
3026 for (unsigned int i = 0; i < type->length; i++) {
3027 emit_block_mov(ir, type->fields.structure[i].type, l, r,
3028 cond, cond_swap);
3029 }
3030 return;
3031 }
3032
3033 if (type->is_array()) {
3034 for (unsigned int i = 0; i < type->length; i++) {
3035 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
3036 }
3037 return;
3038 }
3039
3040 if (type->is_matrix()) {
3041 const struct glsl_type *vec_type;
3042
3043 vec_type = glsl_type::get_instance(type->is_double()
3044 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3045 type->vector_elements, 1);
3046
3047 for (int i = 0; i < type->matrix_columns; i++) {
3048 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3049 }
3050 return;
3051 }
3052
3053 assert(type->is_scalar() || type->is_vector());
3054
3055 l->type = type->base_type;
3056 r->type = type->base_type;
3057 if (cond) {
3058 st_src_reg l_src = st_src_reg(*l);
3059
3060 if (l_src.file == PROGRAM_OUTPUT &&
3061 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3062 (l_src.index == FRAG_RESULT_DEPTH ||
3063 l_src.index == FRAG_RESULT_STENCIL)) {
3064 /* This is a special case because the source swizzles will be shifted
3065 * later to account for the difference between GLSL (where they're
3066 * plain floats) and TGSI (where they're Z and Y components). */
3067 l_src.swizzle = SWIZZLE_XXXX;
3068 }
3069
3070 if (native_integers) {
3071 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3072 cond_swap ? l_src : *r,
3073 cond_swap ? *r : l_src);
3074 } else {
3075 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3076 cond_swap ? l_src : *r,
3077 cond_swap ? *r : l_src);
3078 }
3079 } else {
3080 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3081 }
3082 l->index++;
3083 r->index++;
3084 if (type->is_dual_slot()) {
3085 l->index++;
3086 if (r->is_double_vertex_input == false)
3087 r->index++;
3088 }
3089 }
3090
3091 void
3092 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3093 {
3094 int dst_component;
3095 st_dst_reg l;
3096 st_src_reg r;
3097
3098 /* all generated instructions need to be flaged as precise */
3099 this->precise = is_precise(ir->lhs->variable_referenced());
3100 ir->rhs->accept(this);
3101 r = this->result;
3102
3103 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3104
3105 {
3106 int swizzles[4];
3107 int first_enabled_chan = 0;
3108 int rhs_chan = 0;
3109 ir_variable *variable = ir->lhs->variable_referenced();
3110
3111 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3112 variable->data.mode == ir_var_shader_out &&
3113 (variable->data.location == FRAG_RESULT_DEPTH ||
3114 variable->data.location == FRAG_RESULT_STENCIL)) {
3115 assert(ir->lhs->type->is_scalar());
3116 assert(ir->write_mask == WRITEMASK_X);
3117
3118 if (variable->data.location == FRAG_RESULT_DEPTH)
3119 l.writemask = WRITEMASK_Z;
3120 else {
3121 assert(variable->data.location == FRAG_RESULT_STENCIL);
3122 l.writemask = WRITEMASK_Y;
3123 }
3124 } else if (ir->write_mask == 0) {
3125 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3126
3127 unsigned num_elements =
3128 ir->lhs->type->without_array()->vector_elements;
3129
3130 if (num_elements) {
3131 l.writemask = u_bit_consecutive(0, num_elements);
3132 } else {
3133 /* The type is a struct or an array of (array of) structs. */
3134 l.writemask = WRITEMASK_XYZW;
3135 }
3136 } else {
3137 l.writemask = ir->write_mask;
3138 }
3139
3140 for (int i = 0; i < 4; i++) {
3141 if (l.writemask & (1 << i)) {
3142 first_enabled_chan = GET_SWZ(r.swizzle, i);
3143 break;
3144 }
3145 }
3146
3147 l.writemask = l.writemask << dst_component;
3148
3149 /* Swizzle a small RHS vector into the channels being written.
3150 *
3151 * glsl ir treats write_mask as dictating how many channels are
3152 * present on the RHS while TGSI treats write_mask as just
3153 * showing which channels of the vec4 RHS get written.
3154 */
3155 for (int i = 0; i < 4; i++) {
3156 if (l.writemask & (1 << i))
3157 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3158 else
3159 swizzles[i] = first_enabled_chan;
3160 }
3161 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3162 swizzles[2], swizzles[3]);
3163 }
3164
3165 assert(l.file != PROGRAM_UNDEFINED);
3166 assert(r.file != PROGRAM_UNDEFINED);
3167
3168 if (ir->condition) {
3169 const bool switch_order = this->process_move_condition(ir->condition);
3170 st_src_reg condition = this->result;
3171
3172 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3173 } else if (ir->rhs->as_expression() &&
3174 this->instructions.get_tail() &&
3175 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3176 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3177 type_size(ir->lhs->type) == 1 &&
3178 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3179 /* To avoid emitting an extra MOV when assigning an expression to a
3180 * variable, emit the last instruction of the expression again, but
3181 * replace the destination register with the target of the assignment.
3182 * Dead code elimination will remove the original instruction.
3183 */
3184 glsl_to_tgsi_instruction *inst, *new_inst;
3185 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3186 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3187 new_inst->saturate = inst->saturate;
3188 new_inst->resource = inst->resource;
3189 inst->dead_mask = inst->dst[0].writemask;
3190 } else {
3191 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3192 }
3193 this->precise = 0;
3194 }
3195
3196
3197 void
3198 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3199 {
3200 st_src_reg src;
3201 GLdouble stack_vals[4] = { 0 };
3202 gl_constant_value *values = (gl_constant_value *) stack_vals;
3203 GLenum gl_type = GL_NONE;
3204 unsigned int i, elements;
3205 static int in_array = 0;
3206 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3207
3208 /* Unfortunately, 4 floats is all we can get into
3209 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3210 * aggregate constant and move each constant value into it. If we
3211 * get lucky, copy propagation will eliminate the extra moves.
3212 */
3213 if (ir->type->is_struct()) {
3214 st_src_reg temp_base = get_temp(ir->type);
3215 st_dst_reg temp = st_dst_reg(temp_base);
3216
3217 for (i = 0; i < ir->type->length; i++) {
3218 ir_constant *const field_value = ir->get_record_field(i);
3219 int size = type_size(field_value->type);
3220
3221 assert(size > 0);
3222
3223 field_value->accept(this);
3224 src = this->result;
3225
3226 for (unsigned j = 0; j < (unsigned int)size; j++) {
3227 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3228
3229 src.index++;
3230 temp.index++;
3231 }
3232 }
3233 this->result = temp_base;
3234 return;
3235 }
3236
3237 if (ir->type->is_array()) {
3238 st_src_reg temp_base = get_temp(ir->type);
3239 st_dst_reg temp = st_dst_reg(temp_base);
3240 int size = type_size(ir->type->fields.array);
3241
3242 assert(size > 0);
3243 in_array++;
3244
3245 for (i = 0; i < ir->type->length; i++) {
3246 ir->const_elements[i]->accept(this);
3247 src = this->result;
3248 for (int j = 0; j < size; j++) {
3249 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3250
3251 src.index++;
3252 temp.index++;
3253 }
3254 }
3255 this->result = temp_base;
3256 in_array--;
3257 return;
3258 }
3259
3260 if (ir->type->is_matrix()) {
3261 st_src_reg mat = get_temp(ir->type);
3262 st_dst_reg mat_column = st_dst_reg(mat);
3263
3264 for (i = 0; i < ir->type->matrix_columns; i++) {
3265 switch (ir->type->base_type) {
3266 case GLSL_TYPE_FLOAT:
3267 values = (gl_constant_value *)
3268 &ir->value.f[i * ir->type->vector_elements];
3269
3270 src = st_src_reg(file, -1, ir->type->base_type);
3271 src.index = add_constant(file,
3272 values,
3273 ir->type->vector_elements,
3274 GL_FLOAT,
3275 &src.swizzle);
3276 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3277 break;
3278 case GLSL_TYPE_DOUBLE:
3279 values = (gl_constant_value *)
3280 &ir->value.d[i * ir->type->vector_elements];
3281 src = st_src_reg(file, -1, ir->type->base_type);
3282 src.index = add_constant(file,
3283 values,
3284 ir->type->vector_elements,
3285 GL_DOUBLE,
3286 &src.swizzle);
3287 if (ir->type->vector_elements >= 2) {
3288 mat_column.writemask = WRITEMASK_XY;
3289 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3290 SWIZZLE_X, SWIZZLE_Y);
3291 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3292 } else {
3293 mat_column.writemask = WRITEMASK_X;
3294 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3295 SWIZZLE_X, SWIZZLE_X);
3296 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3297 }
3298 src.index++;
3299 if (ir->type->vector_elements > 2) {
3300 if (ir->type->vector_elements == 4) {
3301 mat_column.writemask = WRITEMASK_ZW;
3302 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3303 SWIZZLE_X, SWIZZLE_Y);
3304 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3305 } else {
3306 mat_column.writemask = WRITEMASK_Z;
3307 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3308 SWIZZLE_Y, SWIZZLE_Y);
3309 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3310 mat_column.writemask = WRITEMASK_XYZW;
3311 src.swizzle = SWIZZLE_XYZW;
3312 }
3313 mat_column.index++;
3314 }
3315 break;
3316 default:
3317 unreachable("Illegal matrix constant type.\n");
3318 break;
3319 }
3320 mat_column.index++;
3321 }
3322 this->result = mat;
3323 return;
3324 }
3325
3326 elements = ir->type->vector_elements;
3327 switch (ir->type->base_type) {
3328 case GLSL_TYPE_FLOAT:
3329 gl_type = GL_FLOAT;
3330 for (i = 0; i < ir->type->vector_elements; i++) {
3331 values[i].f = ir->value.f[i];
3332 }
3333 break;
3334 case GLSL_TYPE_DOUBLE:
3335 gl_type = GL_DOUBLE;
3336 for (i = 0; i < ir->type->vector_elements; i++) {
3337 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3338 }
3339 break;
3340 case GLSL_TYPE_INT64:
3341 gl_type = GL_INT64_ARB;
3342 for (i = 0; i < ir->type->vector_elements; i++) {
3343 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3344 }
3345 break;
3346 case GLSL_TYPE_UINT64:
3347 gl_type = GL_UNSIGNED_INT64_ARB;
3348 for (i = 0; i < ir->type->vector_elements; i++) {
3349 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3350 }
3351 break;
3352 case GLSL_TYPE_UINT:
3353 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3354 for (i = 0; i < ir->type->vector_elements; i++) {
3355 if (native_integers)
3356 values[i].u = ir->value.u[i];
3357 else
3358 values[i].f = ir->value.u[i];
3359 }
3360 break;
3361 case GLSL_TYPE_INT:
3362 gl_type = native_integers ? GL_INT : GL_FLOAT;
3363 for (i = 0; i < ir->type->vector_elements; i++) {
3364 if (native_integers)
3365 values[i].i = ir->value.i[i];
3366 else
3367 values[i].f = ir->value.i[i];
3368 }
3369 break;
3370 case GLSL_TYPE_BOOL:
3371 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3372 for (i = 0; i < ir->type->vector_elements; i++) {
3373 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3374 }
3375 break;
3376 case GLSL_TYPE_SAMPLER:
3377 case GLSL_TYPE_IMAGE:
3378 gl_type = GL_UNSIGNED_INT;
3379 elements = 2;
3380 values[0].u = ir->value.u64[0] & 0xffffffff;
3381 values[1].u = ir->value.u64[0] >> 32;
3382 break;
3383 default:
3384 assert(!"Non-float/uint/int/bool/sampler/image constant");
3385 }
3386
3387 this->result = st_src_reg(file, -1, ir->type);
3388 this->result.index = add_constant(file,
3389 values,
3390 elements,
3391 gl_type,
3392 &this->result.swizzle);
3393 }
3394
3395 void
3396 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3397 {
3398 exec_node *param = ir->actual_parameters.get_head();
3399 ir_dereference *deref = static_cast<ir_dereference *>(param);
3400 ir_variable *location = deref->variable_referenced();
3401 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3402 /* Calculate the surface offset */
3403 st_src_reg offset;
3404 unsigned array_size = 0, base = 0;
3405 uint16_t index = 0;
3406 st_src_reg resource;
3407
3408 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3409
3410 if (has_hw_atomics) {
3411 variable_storage *entry = find_variable_storage(location);
3412 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3413 location->data.binding);
3414
3415 if (!entry) {
3416 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3417 num_atomics);
3418 _mesa_hash_table_insert(this->variables, location, entry);
3419
3420 atomic_info[num_atomics].location = location->data.location;
3421 atomic_info[num_atomics].binding = location->data.binding;
3422 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3423 if (atomic_info[num_atomics].size == 0)
3424 atomic_info[num_atomics].size = 1;
3425 atomic_info[num_atomics].array_id = 0;
3426 num_atomics++;
3427 }
3428
3429 if (offset.file != PROGRAM_UNDEFINED) {
3430 if (atomic_info[entry->index].array_id == 0) {
3431 num_atomic_arrays++;
3432 atomic_info[entry->index].array_id = num_atomic_arrays;
3433 }
3434 buffer.array_id = atomic_info[entry->index].array_id;
3435 }
3436
3437 buffer.index = index;
3438 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3439 buffer.has_index2 = true;
3440
3441 if (offset.file != PROGRAM_UNDEFINED) {
3442 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3443 *buffer.reladdr = offset;
3444 emit_arl(ir, sampler_reladdr, offset);
3445 }
3446 offset = st_src_reg_for_int(0);
3447
3448 resource = buffer;
3449 } else {
3450 st_src_reg buffer(PROGRAM_BUFFER, location->data.binding,
3451 GLSL_TYPE_ATOMIC_UINT);
3452
3453 if (offset.file != PROGRAM_UNDEFINED) {
3454 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3455 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3456 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3457 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3458 } else {
3459 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3460 }
3461 resource = buffer;
3462 }
3463
3464 ir->return_deref->accept(this);
3465 st_dst_reg dst(this->result);
3466 dst.writemask = WRITEMASK_X;
3467
3468 glsl_to_tgsi_instruction *inst;
3469
3470 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3471 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3472 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3473 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3474 st_src_reg_for_int(1));
3475 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3476 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3477 st_src_reg_for_int(-1));
3478 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3479 } else {
3480 param = param->get_next();
3481 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3482 val->accept(this);
3483
3484 st_src_reg data = this->result, data2 = undef_src;
3485 enum tgsi_opcode opcode;
3486 switch (ir->callee->intrinsic_id) {
3487 case ir_intrinsic_atomic_counter_add:
3488 opcode = TGSI_OPCODE_ATOMUADD;
3489 break;
3490 case ir_intrinsic_atomic_counter_min:
3491 opcode = TGSI_OPCODE_ATOMIMIN;
3492 break;
3493 case ir_intrinsic_atomic_counter_max:
3494 opcode = TGSI_OPCODE_ATOMIMAX;
3495 break;
3496 case ir_intrinsic_atomic_counter_and:
3497 opcode = TGSI_OPCODE_ATOMAND;
3498 break;
3499 case ir_intrinsic_atomic_counter_or:
3500 opcode = TGSI_OPCODE_ATOMOR;
3501 break;
3502 case ir_intrinsic_atomic_counter_xor:
3503 opcode = TGSI_OPCODE_ATOMXOR;
3504 break;
3505 case ir_intrinsic_atomic_counter_exchange:
3506 opcode = TGSI_OPCODE_ATOMXCHG;
3507 break;
3508 case ir_intrinsic_atomic_counter_comp_swap: {
3509 opcode = TGSI_OPCODE_ATOMCAS;
3510 param = param->get_next();
3511 val = ((ir_instruction *)param)->as_rvalue();
3512 val->accept(this);
3513 data2 = this->result;
3514 break;
3515 }
3516 default:
3517 assert(!"Unexpected intrinsic");
3518 return;
3519 }
3520
3521 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3522 }
3523
3524 inst->resource = resource;
3525 }
3526
3527 void
3528 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3529 {
3530 exec_node *param = ir->actual_parameters.get_head();
3531
3532 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3533
3534 param = param->get_next();
3535 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3536
3537 ir_constant *const_block = block->as_constant();
3538 int buf_base = st_context(ctx)->has_hw_atomics
3539 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
3540 st_src_reg buffer(
3541 PROGRAM_BUFFER,
3542 buf_base + (const_block ? const_block->value.u[0] : 0),
3543 GLSL_TYPE_UINT);
3544
3545 if (!const_block) {
3546 block->accept(this);
3547 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3548 *buffer.reladdr = this->result;
3549 emit_arl(ir, sampler_reladdr, this->result);
3550 }
3551
3552 /* Calculate the surface offset */
3553 offset->accept(this);
3554 st_src_reg off = this->result;
3555
3556 st_dst_reg dst = undef_dst;
3557 if (ir->return_deref) {
3558 ir->return_deref->accept(this);
3559 dst = st_dst_reg(this->result);
3560 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3561 }
3562
3563 glsl_to_tgsi_instruction *inst;
3564
3565 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3566 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3567 if (dst.type == GLSL_TYPE_BOOL)
3568 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3569 st_src_reg_for_int(0));
3570 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3571 param = param->get_next();
3572 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3573 val->accept(this);
3574
3575 param = param->get_next();
3576 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3577 assert(write_mask);
3578 dst.writemask = write_mask->value.u[0];
3579
3580 dst.type = this->result.type;
3581 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3582 } else {
3583 param = param->get_next();
3584 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3585 val->accept(this);
3586
3587 st_src_reg data = this->result, data2 = undef_src;
3588 enum tgsi_opcode opcode;
3589 switch (ir->callee->intrinsic_id) {
3590 case ir_intrinsic_ssbo_atomic_add:
3591 opcode = TGSI_OPCODE_ATOMUADD;
3592 break;
3593 case ir_intrinsic_ssbo_atomic_min:
3594 opcode = TGSI_OPCODE_ATOMIMIN;
3595 break;
3596 case ir_intrinsic_ssbo_atomic_max:
3597 opcode = TGSI_OPCODE_ATOMIMAX;
3598 break;
3599 case ir_intrinsic_ssbo_atomic_and:
3600 opcode = TGSI_OPCODE_ATOMAND;
3601 break;
3602 case ir_intrinsic_ssbo_atomic_or:
3603 opcode = TGSI_OPCODE_ATOMOR;
3604 break;
3605 case ir_intrinsic_ssbo_atomic_xor:
3606 opcode = TGSI_OPCODE_ATOMXOR;
3607 break;
3608 case ir_intrinsic_ssbo_atomic_exchange:
3609 opcode = TGSI_OPCODE_ATOMXCHG;
3610 break;
3611 case ir_intrinsic_ssbo_atomic_comp_swap:
3612 opcode = TGSI_OPCODE_ATOMCAS;
3613 param = param->get_next();
3614 val = ((ir_instruction *)param)->as_rvalue();
3615 val->accept(this);
3616 data2 = this->result;
3617 break;
3618 default:
3619 assert(!"Unexpected intrinsic");
3620 return;
3621 }
3622
3623 inst = emit_asm(ir, opcode, dst, off, data, data2);
3624 }
3625
3626 param = param->get_next();
3627 ir_constant *access = NULL;
3628 if (!param->is_tail_sentinel()) {
3629 access = ((ir_instruction *)param)->as_constant();
3630 assert(access);
3631 }
3632
3633 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3634 }
3635
3636 void
3637 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3638 {
3639 switch (ir->callee->intrinsic_id) {
3640 case ir_intrinsic_memory_barrier:
3641 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3642 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3643 TGSI_MEMBAR_ATOMIC_BUFFER |
3644 TGSI_MEMBAR_SHADER_IMAGE |
3645 TGSI_MEMBAR_SHARED));
3646 break;
3647 case ir_intrinsic_memory_barrier_atomic_counter:
3648 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3649 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3650 break;
3651 case ir_intrinsic_memory_barrier_buffer:
3652 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3653 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3654 break;
3655 case ir_intrinsic_memory_barrier_image:
3656 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3657 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3658 break;
3659 case ir_intrinsic_memory_barrier_shared:
3660 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3661 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3662 break;
3663 case ir_intrinsic_group_memory_barrier:
3664 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3665 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3666 TGSI_MEMBAR_ATOMIC_BUFFER |
3667 TGSI_MEMBAR_SHADER_IMAGE |
3668 TGSI_MEMBAR_SHARED |
3669 TGSI_MEMBAR_THREAD_GROUP));
3670 break;
3671 default:
3672 assert(!"Unexpected memory barrier intrinsic");
3673 }
3674 }
3675
3676 void
3677 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3678 {
3679 exec_node *param = ir->actual_parameters.get_head();
3680
3681 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3682
3683 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3684
3685 /* Calculate the surface offset */
3686 offset->accept(this);
3687 st_src_reg off = this->result;
3688
3689 st_dst_reg dst = undef_dst;
3690 if (ir->return_deref) {
3691 ir->return_deref->accept(this);
3692 dst = st_dst_reg(this->result);
3693 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3694 }
3695
3696 glsl_to_tgsi_instruction *inst;
3697
3698 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3699 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3700 inst->resource = buffer;
3701 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3702 param = param->get_next();
3703 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3704 val->accept(this);
3705
3706 param = param->get_next();
3707 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3708 assert(write_mask);
3709 dst.writemask = write_mask->value.u[0];
3710
3711 dst.type = this->result.type;
3712 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3713 inst->resource = buffer;
3714 } else {
3715 param = param->get_next();
3716 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3717 val->accept(this);
3718
3719 st_src_reg data = this->result, data2 = undef_src;
3720 enum tgsi_opcode opcode;
3721 switch (ir->callee->intrinsic_id) {
3722 case ir_intrinsic_shared_atomic_add:
3723 opcode = TGSI_OPCODE_ATOMUADD;
3724 break;
3725 case ir_intrinsic_shared_atomic_min:
3726 opcode = TGSI_OPCODE_ATOMIMIN;
3727 break;
3728 case ir_intrinsic_shared_atomic_max:
3729 opcode = TGSI_OPCODE_ATOMIMAX;
3730 break;
3731 case ir_intrinsic_shared_atomic_and:
3732 opcode = TGSI_OPCODE_ATOMAND;
3733 break;
3734 case ir_intrinsic_shared_atomic_or:
3735 opcode = TGSI_OPCODE_ATOMOR;
3736 break;
3737 case ir_intrinsic_shared_atomic_xor:
3738 opcode = TGSI_OPCODE_ATOMXOR;
3739 break;
3740 case ir_intrinsic_shared_atomic_exchange:
3741 opcode = TGSI_OPCODE_ATOMXCHG;
3742 break;
3743 case ir_intrinsic_shared_atomic_comp_swap:
3744 opcode = TGSI_OPCODE_ATOMCAS;
3745 param = param->get_next();
3746 val = ((ir_instruction *)param)->as_rvalue();
3747 val->accept(this);
3748 data2 = this->result;
3749 break;
3750 default:
3751 assert(!"Unexpected intrinsic");
3752 return;
3753 }
3754
3755 inst = emit_asm(ir, opcode, dst, off, data, data2);
3756 inst->resource = buffer;
3757 }
3758 }
3759
3760 static void
3761 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3762 bool *memory_coherent, bool *memory_volatile,
3763 bool *memory_restrict, bool *memory_read_only,
3764 unsigned *image_format)
3765 {
3766
3767 switch (ir->ir_type) {
3768 case ir_type_dereference_record: {
3769 ir_dereference_record *deref_record = ir->as_dereference_record();
3770 const glsl_type *struct_type = deref_record->record->type;
3771 int fild_idx = deref_record->field_idx;
3772
3773 *type = struct_type->fields.structure[fild_idx].type->without_array();
3774 *memory_coherent =
3775 struct_type->fields.structure[fild_idx].memory_coherent;
3776 *memory_volatile =
3777 struct_type->fields.structure[fild_idx].memory_volatile;
3778 *memory_restrict =
3779 struct_type->fields.structure[fild_idx].memory_restrict;
3780 *memory_read_only =
3781 struct_type->fields.structure[fild_idx].memory_read_only;
3782 *image_format =
3783 struct_type->fields.structure[fild_idx].image_format;
3784 break;
3785 }
3786
3787 case ir_type_dereference_array: {
3788 ir_dereference_array *deref_arr = ir->as_dereference_array();
3789 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3790 memory_coherent, memory_volatile, memory_restrict,
3791 memory_read_only, image_format);
3792 break;
3793 }
3794
3795 case ir_type_dereference_variable: {
3796 ir_variable *var = ir->variable_referenced();
3797
3798 *type = var->type->without_array();
3799 *memory_coherent = var->data.memory_coherent;
3800 *memory_volatile = var->data.memory_volatile;
3801 *memory_restrict = var->data.memory_restrict;
3802 *memory_read_only = var->data.memory_read_only;
3803 *image_format = var->data.image_format;
3804 break;
3805 }
3806
3807 default:
3808 break;
3809 }
3810 }
3811
3812 void
3813 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3814 {
3815 exec_node *param = ir->actual_parameters.get_head();
3816
3817 ir_dereference *img = (ir_dereference *)param;
3818 const ir_variable *imgvar = img->variable_referenced();
3819 unsigned sampler_array_size = 1, sampler_base = 0;
3820 bool memory_coherent = false, memory_volatile = false,
3821 memory_restrict = false, memory_read_only = false;
3822 unsigned image_format = 0;
3823 const glsl_type *type = NULL;
3824
3825 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3826 &memory_restrict, &memory_read_only, &image_format);
3827
3828 st_src_reg reladdr;
3829 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3830 uint16_t index = 0;
3831 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3832 &index, &reladdr, !imgvar->contains_bindless());
3833
3834 image.index = index;
3835 if (reladdr.file != PROGRAM_UNDEFINED) {
3836 image.reladdr = ralloc(mem_ctx, st_src_reg);
3837 *image.reladdr = reladdr;
3838 emit_arl(ir, sampler_reladdr, reladdr);
3839 }
3840
3841 st_dst_reg dst = undef_dst;
3842 if (ir->return_deref) {
3843 ir->return_deref->accept(this);
3844 dst = st_dst_reg(this->result);
3845 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3846 }
3847
3848 glsl_to_tgsi_instruction *inst;
3849
3850 st_src_reg bindless;
3851 if (imgvar->contains_bindless()) {
3852 img->accept(this);
3853 bindless = this->result;
3854 }
3855
3856 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3857 dst.writemask = WRITEMASK_XYZ;
3858 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3859 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3860 st_src_reg res = get_temp(glsl_type::ivec4_type);
3861 st_dst_reg dstres = st_dst_reg(res);
3862 dstres.writemask = WRITEMASK_W;
3863 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3864 res.swizzle = SWIZZLE_WWWW;
3865 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3866 } else {
3867 st_src_reg arg1 = undef_src, arg2 = undef_src;
3868 st_src_reg coord;
3869 st_dst_reg coord_dst;
3870 coord = get_temp(glsl_type::ivec4_type);
3871 coord_dst = st_dst_reg(coord);
3872 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3873 param = param->get_next();
3874 ((ir_dereference *)param)->accept(this);
3875 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3876 coord.swizzle = SWIZZLE_XXXX;
3877 switch (type->coordinate_components()) {
3878 case 4: assert(!"unexpected coord count");
3879 /* fallthrough */
3880 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3881 /* fallthrough */
3882 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3883 }
3884
3885 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3886 param = param->get_next();
3887 ((ir_dereference *)param)->accept(this);
3888 st_src_reg sample = this->result;
3889 sample.swizzle = SWIZZLE_XXXX;
3890 coord_dst.writemask = WRITEMASK_W;
3891 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3892 coord.swizzle |= SWIZZLE_W << 9;
3893 }
3894
3895 param = param->get_next();
3896 if (!param->is_tail_sentinel()) {
3897 ((ir_dereference *)param)->accept(this);
3898 arg1 = this->result;
3899 param = param->get_next();
3900 }
3901
3902 if (!param->is_tail_sentinel()) {
3903 ((ir_dereference *)param)->accept(this);
3904 arg2 = this->result;
3905 param = param->get_next();
3906 }
3907
3908 assert(param->is_tail_sentinel());
3909
3910 enum tgsi_opcode opcode;
3911 switch (ir->callee->intrinsic_id) {
3912 case ir_intrinsic_image_load:
3913 opcode = TGSI_OPCODE_LOAD;
3914 break;
3915 case ir_intrinsic_image_store:
3916 opcode = TGSI_OPCODE_STORE;
3917 break;
3918 case ir_intrinsic_image_atomic_add:
3919 opcode = TGSI_OPCODE_ATOMUADD;
3920 break;
3921 case ir_intrinsic_image_atomic_min:
3922 opcode = TGSI_OPCODE_ATOMIMIN;
3923 break;
3924 case ir_intrinsic_image_atomic_max:
3925 opcode = TGSI_OPCODE_ATOMIMAX;
3926 break;
3927 case ir_intrinsic_image_atomic_and:
3928 opcode = TGSI_OPCODE_ATOMAND;
3929 break;
3930 case ir_intrinsic_image_atomic_or:
3931 opcode = TGSI_OPCODE_ATOMOR;
3932 break;
3933 case ir_intrinsic_image_atomic_xor:
3934 opcode = TGSI_OPCODE_ATOMXOR;
3935 break;
3936 case ir_intrinsic_image_atomic_exchange:
3937 opcode = TGSI_OPCODE_ATOMXCHG;
3938 break;
3939 case ir_intrinsic_image_atomic_comp_swap:
3940 opcode = TGSI_OPCODE_ATOMCAS;
3941 break;
3942 case ir_intrinsic_image_atomic_inc_wrap: {
3943 /* There's a bit of disagreement between GLSL and the hardware. The
3944 * hardware wants to wrap after the given wrap value, while GLSL
3945 * wants to wrap at the value. Subtract 1 to make up the difference.
3946 */
3947 st_src_reg wrap = get_temp(glsl_type::uint_type);
3948 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(wrap),
3949 arg1, st_src_reg_for_int(-1));
3950 arg1 = wrap;
3951 opcode = TGSI_OPCODE_ATOMINC_WRAP;
3952 break;
3953 }
3954 case ir_intrinsic_image_atomic_dec_wrap:
3955 opcode = TGSI_OPCODE_ATOMDEC_WRAP;
3956 break;
3957 default:
3958 assert(!"Unexpected intrinsic");
3959 return;
3960 }
3961
3962 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3963 if (opcode == TGSI_OPCODE_STORE)
3964 inst->dst[0].writemask = WRITEMASK_XYZW;
3965 }
3966
3967 if (imgvar->contains_bindless()) {
3968 inst->resource = bindless;
3969 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3970 SWIZZLE_X, SWIZZLE_Y);
3971 } else {
3972 inst->resource = image;
3973 inst->sampler_array_size = sampler_array_size;
3974 inst->sampler_base = sampler_base;
3975 }
3976
3977 inst->tex_target = type->sampler_index();
3978 inst->image_format = st_mesa_format_to_pipe_format(st_context(ctx),
3979 _mesa_get_shader_image_format(image_format));
3980 inst->read_only = memory_read_only;
3981
3982 if (memory_coherent)
3983 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3984 if (memory_restrict)
3985 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3986 if (memory_volatile)
3987 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3988 }
3989
3990 void
3991 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
3992 {
3993 ir->return_deref->accept(this);
3994 st_dst_reg dst = st_dst_reg(this->result);
3995
3996 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
3997
3998 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
3999 unsigned num_src = 0;
4000 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
4001 assert(num_src < ARRAY_SIZE(src));
4002
4003 this->result.file = PROGRAM_UNDEFINED;
4004 param->accept(this);
4005 assert(this->result.file != PROGRAM_UNDEFINED);
4006
4007 src[num_src] = this->result;
4008 num_src++;
4009 }
4010
4011 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
4012 }
4013
4014 void
4015 glsl_to_tgsi_visitor::visit(ir_call *ir)
4016 {
4017 ir_function_signature *sig = ir->callee;
4018
4019 /* Filter out intrinsics */
4020 switch (sig->intrinsic_id) {
4021 case ir_intrinsic_atomic_counter_read:
4022 case ir_intrinsic_atomic_counter_increment:
4023 case ir_intrinsic_atomic_counter_predecrement:
4024 case ir_intrinsic_atomic_counter_add:
4025 case ir_intrinsic_atomic_counter_min:
4026 case ir_intrinsic_atomic_counter_max:
4027 case ir_intrinsic_atomic_counter_and:
4028 case ir_intrinsic_atomic_counter_or:
4029 case ir_intrinsic_atomic_counter_xor:
4030 case ir_intrinsic_atomic_counter_exchange:
4031 case ir_intrinsic_atomic_counter_comp_swap:
4032 visit_atomic_counter_intrinsic(ir);
4033 return;
4034
4035 case ir_intrinsic_ssbo_load:
4036 case ir_intrinsic_ssbo_store:
4037 case ir_intrinsic_ssbo_atomic_add:
4038 case ir_intrinsic_ssbo_atomic_min:
4039 case ir_intrinsic_ssbo_atomic_max:
4040 case ir_intrinsic_ssbo_atomic_and:
4041 case ir_intrinsic_ssbo_atomic_or:
4042 case ir_intrinsic_ssbo_atomic_xor:
4043 case ir_intrinsic_ssbo_atomic_exchange:
4044 case ir_intrinsic_ssbo_atomic_comp_swap:
4045 visit_ssbo_intrinsic(ir);
4046 return;
4047
4048 case ir_intrinsic_memory_barrier:
4049 case ir_intrinsic_memory_barrier_atomic_counter:
4050 case ir_intrinsic_memory_barrier_buffer:
4051 case ir_intrinsic_memory_barrier_image:
4052 case ir_intrinsic_memory_barrier_shared:
4053 case ir_intrinsic_group_memory_barrier:
4054 visit_membar_intrinsic(ir);
4055 return;
4056
4057 case ir_intrinsic_shared_load:
4058 case ir_intrinsic_shared_store:
4059 case ir_intrinsic_shared_atomic_add:
4060 case ir_intrinsic_shared_atomic_min:
4061 case ir_intrinsic_shared_atomic_max:
4062 case ir_intrinsic_shared_atomic_and:
4063 case ir_intrinsic_shared_atomic_or:
4064 case ir_intrinsic_shared_atomic_xor:
4065 case ir_intrinsic_shared_atomic_exchange:
4066 case ir_intrinsic_shared_atomic_comp_swap:
4067 visit_shared_intrinsic(ir);
4068 return;
4069
4070 case ir_intrinsic_image_load:
4071 case ir_intrinsic_image_store:
4072 case ir_intrinsic_image_atomic_add:
4073 case ir_intrinsic_image_atomic_min:
4074 case ir_intrinsic_image_atomic_max:
4075 case ir_intrinsic_image_atomic_and:
4076 case ir_intrinsic_image_atomic_or:
4077 case ir_intrinsic_image_atomic_xor:
4078 case ir_intrinsic_image_atomic_exchange:
4079 case ir_intrinsic_image_atomic_comp_swap:
4080 case ir_intrinsic_image_size:
4081 case ir_intrinsic_image_samples:
4082 case ir_intrinsic_image_atomic_inc_wrap:
4083 case ir_intrinsic_image_atomic_dec_wrap:
4084 visit_image_intrinsic(ir);
4085 return;
4086
4087 case ir_intrinsic_shader_clock:
4088 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4089 return;
4090
4091 case ir_intrinsic_vote_all:
4092 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4093 return;
4094 case ir_intrinsic_vote_any:
4095 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4096 return;
4097 case ir_intrinsic_vote_eq:
4098 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4099 return;
4100 case ir_intrinsic_ballot:
4101 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4102 return;
4103 case ir_intrinsic_read_first_invocation:
4104 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4105 return;
4106 case ir_intrinsic_read_invocation:
4107 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4108 return;
4109
4110 case ir_intrinsic_invalid:
4111 case ir_intrinsic_generic_load:
4112 case ir_intrinsic_generic_store:
4113 case ir_intrinsic_generic_atomic_add:
4114 case ir_intrinsic_generic_atomic_and:
4115 case ir_intrinsic_generic_atomic_or:
4116 case ir_intrinsic_generic_atomic_xor:
4117 case ir_intrinsic_generic_atomic_min:
4118 case ir_intrinsic_generic_atomic_max:
4119 case ir_intrinsic_generic_atomic_exchange:
4120 case ir_intrinsic_generic_atomic_comp_swap:
4121 case ir_intrinsic_begin_invocation_interlock:
4122 case ir_intrinsic_end_invocation_interlock:
4123 unreachable("Invalid intrinsic");
4124 }
4125 }
4126
4127 void
4128 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4129 unsigned *array_elements,
4130 uint16_t *index,
4131 st_src_reg *indirect,
4132 unsigned *location)
4133 {
4134 switch (tail->ir_type) {
4135 case ir_type_dereference_record: {
4136 ir_dereference_record *deref_record = tail->as_dereference_record();
4137 const glsl_type *struct_type = deref_record->record->type;
4138 int field_index = deref_record->field_idx;
4139
4140 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4141
4142 assert(field_index >= 0);
4143 *location += struct_type->struct_location_offset(field_index);
4144 break;
4145 }
4146
4147 case ir_type_dereference_array: {
4148 ir_dereference_array *deref_arr = tail->as_dereference_array();
4149
4150 void *mem_ctx = ralloc_parent(deref_arr);
4151 ir_constant *array_index =
4152 deref_arr->array_index->constant_expression_value(mem_ctx);
4153
4154 if (!array_index) {
4155 st_src_reg temp_reg;
4156 st_dst_reg temp_dst;
4157
4158 temp_reg = get_temp(glsl_type::uint_type);
4159 temp_dst = st_dst_reg(temp_reg);
4160 temp_dst.writemask = 1;
4161
4162 deref_arr->array_index->accept(this);
4163 if (*array_elements != 1)
4164 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4165 else
4166 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4167
4168 if (indirect->file == PROGRAM_UNDEFINED)
4169 *indirect = temp_reg;
4170 else {
4171 temp_dst = st_dst_reg(*indirect);
4172 temp_dst.writemask = 1;
4173 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4174 }
4175 } else
4176 *index += array_index->value.u[0] * *array_elements;
4177
4178 *array_elements *= deref_arr->array->type->length;
4179
4180 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4181 break;
4182 }
4183 default:
4184 break;
4185 }
4186 }
4187
4188 void
4189 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4190 unsigned *array_size,
4191 unsigned *base,
4192 uint16_t *index,
4193 st_src_reg *reladdr,
4194 bool opaque)
4195 {
4196 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4197 unsigned location = 0;
4198 ir_variable *var = ir->variable_referenced();
4199
4200 reladdr->reset();
4201
4202 *base = 0;
4203 *array_size = 1;
4204
4205 assert(var);
4206 location = var->data.location;
4207 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4208
4209 /*
4210 * If we end up with no indirect then adjust the base to the index,
4211 * and set the array size to 1.
4212 */
4213 if (reladdr->file == PROGRAM_UNDEFINED) {
4214 *base = *index;
4215 *array_size = 1;
4216 }
4217
4218 if (opaque) {
4219 assert(location != 0xffffffff);
4220 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4221 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4222 }
4223 }
4224
4225 st_src_reg
4226 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4227 {
4228 if (offset.reladdr || offset.reladdr2 ||
4229 offset.has_index2 ||
4230 offset.file == PROGRAM_UNIFORM ||
4231 offset.file == PROGRAM_CONSTANT ||
4232 offset.file == PROGRAM_STATE_VAR) {
4233 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4234 st_dst_reg tmp_dst = st_dst_reg(tmp);
4235 tmp_dst.writemask = WRITEMASK_XY;
4236 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4237 return tmp;
4238 }
4239
4240 return offset;
4241 }
4242
4243 bool
4244 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4245 {
4246 ir_variable *var = ir->variable_referenced();
4247
4248 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4249 !(ir->type->is_image() || ir->type->is_sampler()))
4250 return false;
4251
4252 /* Convert from bound sampler/image to bindless handle. */
4253 bool is_image = ir->type->is_image();
4254 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4255 uint16_t index = 0;
4256 unsigned array_size = 1, base = 0;
4257 st_src_reg reladdr;
4258 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4259
4260 resource.index = index;
4261 if (reladdr.file != PROGRAM_UNDEFINED) {
4262 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4263 *resource.reladdr = reladdr;
4264 emit_arl(ir, sampler_reladdr, reladdr);
4265 }
4266
4267 this->result = get_temp(glsl_type::uvec2_type);
4268 st_dst_reg dst(this->result);
4269 dst.writemask = WRITEMASK_XY;
4270
4271 glsl_to_tgsi_instruction *inst = emit_asm(
4272 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4273
4274 inst->tex_target = ir->type->sampler_index();
4275 inst->resource = resource;
4276 inst->sampler_array_size = array_size;
4277 inst->sampler_base = base;
4278
4279 return true;
4280 }
4281
4282 void
4283 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4284 {
4285 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4286 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4287 st_src_reg levels_src, reladdr;
4288 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4289 glsl_to_tgsi_instruction *inst = NULL;
4290 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4291 const glsl_type *sampler_type = ir->sampler->type;
4292 unsigned sampler_array_size = 1, sampler_base = 0;
4293 bool is_cube_array = false, is_cube_shadow = false;
4294 ir_variable *var = ir->sampler->variable_referenced();
4295 unsigned i;
4296
4297 /* if we are a cube array sampler or a cube shadow */
4298 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4299 is_cube_array = sampler_type->sampler_array;
4300 is_cube_shadow = sampler_type->sampler_shadow;
4301 }
4302
4303 if (ir->coordinate) {
4304 ir->coordinate->accept(this);
4305
4306 /* Put our coords in a temp. We'll need to modify them for shadow,
4307 * projection, or LOD, so the only case we'd use it as-is is if
4308 * we're doing plain old texturing. The optimization passes on
4309 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4310 */
4311 coord = get_temp(glsl_type::vec4_type);
4312 coord_dst = st_dst_reg(coord);
4313 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4314 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4315 }
4316
4317 if (ir->projector) {
4318 ir->projector->accept(this);
4319 projector = this->result;
4320 }
4321
4322 /* Storage for our result. Ideally for an assignment we'd be using
4323 * the actual storage for the result here, instead.
4324 */
4325 result_src = get_temp(ir->type);
4326 result_dst = st_dst_reg(result_src);
4327 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4328
4329 switch (ir->op) {
4330 case ir_tex:
4331 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4332 if (ir->offset) {
4333 ir->offset->accept(this);
4334 offset[0] = this->result;
4335 }
4336 break;
4337 case ir_txb:
4338 if (is_cube_array || is_cube_shadow) {
4339 opcode = TGSI_OPCODE_TXB2;
4340 }
4341 else {
4342 opcode = TGSI_OPCODE_TXB;
4343 }
4344 ir->lod_info.bias->accept(this);
4345 lod_info = this->result;
4346 if (ir->offset) {
4347 ir->offset->accept(this);
4348 offset[0] = this->result;
4349 }
4350 break;
4351 case ir_txl:
4352 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4353 opcode = TGSI_OPCODE_TEX_LZ;
4354 } else {
4355 opcode = is_cube_array ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4356 ir->lod_info.lod->accept(this);
4357 lod_info = this->result;
4358 }
4359 if (ir->offset) {
4360 ir->offset->accept(this);
4361 offset[0] = this->result;
4362 }
4363 break;
4364 case ir_txd:
4365 opcode = TGSI_OPCODE_TXD;
4366 ir->lod_info.grad.dPdx->accept(this);
4367 dx = this->result;
4368 ir->lod_info.grad.dPdy->accept(this);
4369 dy = this->result;
4370 if (ir->offset) {
4371 ir->offset->accept(this);
4372 offset[0] = this->result;
4373 }
4374 break;
4375 case ir_txs:
4376 opcode = TGSI_OPCODE_TXQ;
4377 ir->lod_info.lod->accept(this);
4378 lod_info = this->result;
4379 break;
4380 case ir_query_levels:
4381 opcode = TGSI_OPCODE_TXQ;
4382 lod_info = undef_src;
4383 levels_src = get_temp(ir->type);
4384 break;
4385 case ir_txf:
4386 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4387 opcode = TGSI_OPCODE_TXF_LZ;
4388 } else {
4389 opcode = TGSI_OPCODE_TXF;
4390 ir->lod_info.lod->accept(this);
4391 lod_info = this->result;
4392 }
4393 if (ir->offset) {
4394 ir->offset->accept(this);
4395 offset[0] = this->result;
4396 }
4397 break;
4398 case ir_txf_ms:
4399 opcode = TGSI_OPCODE_TXF;
4400 ir->lod_info.sample_index->accept(this);
4401 sample_index = this->result;
4402 break;
4403 case ir_tg4:
4404 opcode = TGSI_OPCODE_TG4;
4405 ir->lod_info.component->accept(this);
4406 component = this->result;
4407 if (ir->offset) {
4408 ir->offset->accept(this);
4409 if (ir->offset->type->is_array()) {
4410 const glsl_type *elt_type = ir->offset->type->fields.array;
4411 for (i = 0; i < ir->offset->type->length; i++) {
4412 offset[i] = this->result;
4413 offset[i].index += i * type_size(elt_type);
4414 offset[i].type = elt_type->base_type;
4415 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4416 offset[i] = canonicalize_gather_offset(offset[i]);
4417 }
4418 } else {
4419 offset[0] = canonicalize_gather_offset(this->result);
4420 }
4421 }
4422 break;
4423 case ir_lod:
4424 opcode = TGSI_OPCODE_LODQ;
4425 break;
4426 case ir_texture_samples:
4427 opcode = TGSI_OPCODE_TXQS;
4428 break;
4429 case ir_samples_identical:
4430 unreachable("Unexpected ir_samples_identical opcode");
4431 }
4432
4433 if (ir->projector) {
4434 if (opcode == TGSI_OPCODE_TEX) {
4435 /* Slot the projector in as the last component of the coord. */
4436 coord_dst.writemask = WRITEMASK_W;
4437 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4438 coord_dst.writemask = WRITEMASK_XYZW;
4439 opcode = TGSI_OPCODE_TXP;
4440 } else {
4441 st_src_reg coord_w = coord;
4442 coord_w.swizzle = SWIZZLE_WWWW;
4443
4444 /* For the other TEX opcodes there's no projective version
4445 * since the last slot is taken up by LOD info. Do the
4446 * projective divide now.
4447 */
4448 coord_dst.writemask = WRITEMASK_W;
4449 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4450
4451 /* In the case where we have to project the coordinates "by hand,"
4452 * the shadow comparator value must also be projected.
4453 */
4454 st_src_reg tmp_src = coord;
4455 if (ir->shadow_comparator) {
4456 /* Slot the shadow value in as the second to last component of the
4457 * coord.
4458 */
4459 ir->shadow_comparator->accept(this);
4460
4461 tmp_src = get_temp(glsl_type::vec4_type);
4462 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4463
4464 /* Projective division not allowed for array samplers. */
4465 assert(!sampler_type->sampler_array);
4466
4467 tmp_dst.writemask = WRITEMASK_Z;
4468 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4469
4470 tmp_dst.writemask = WRITEMASK_XY;
4471 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4472 }
4473
4474 coord_dst.writemask = WRITEMASK_XYZ;
4475 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4476
4477 coord_dst.writemask = WRITEMASK_XYZW;
4478 coord.swizzle = SWIZZLE_XYZW;
4479 }
4480 }
4481
4482 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4483 * shadow comparator was put in the correct place (and projected) by the
4484 * code, above, that handles by-hand projection.
4485 */
4486 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4487 /* Slot the shadow value in as the second to last component of the
4488 * coord.
4489 */
4490 ir->shadow_comparator->accept(this);
4491
4492 if (is_cube_array) {
4493 cube_sc = get_temp(glsl_type::float_type);
4494 cube_sc_dst = st_dst_reg(cube_sc);
4495 cube_sc_dst.writemask = WRITEMASK_X;
4496 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4497 cube_sc_dst.writemask = WRITEMASK_X;
4498 }
4499 else {
4500 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4501 sampler_type->sampler_array) ||
4502 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4503 coord_dst.writemask = WRITEMASK_W;
4504 } else {
4505 coord_dst.writemask = WRITEMASK_Z;
4506 }
4507 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4508 coord_dst.writemask = WRITEMASK_XYZW;
4509 }
4510 }
4511
4512 if (ir->op == ir_txf_ms) {
4513 coord_dst.writemask = WRITEMASK_W;
4514 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4515 coord_dst.writemask = WRITEMASK_XYZW;
4516 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4517 opcode == TGSI_OPCODE_TXF) {
4518 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4519 coord_dst.writemask = WRITEMASK_W;
4520 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4521 coord_dst.writemask = WRITEMASK_XYZW;
4522 }
4523
4524 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4525
4526 uint16_t index = 0;
4527 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4528 &index, &reladdr, !var->contains_bindless());
4529
4530 sampler.index = index;
4531 if (reladdr.file != PROGRAM_UNDEFINED) {
4532 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4533 *sampler.reladdr = reladdr;
4534 emit_arl(ir, sampler_reladdr, reladdr);
4535 }
4536
4537 st_src_reg bindless;
4538 if (var->contains_bindless()) {
4539 ir->sampler->accept(this);
4540 bindless = this->result;
4541 }
4542
4543 if (opcode == TGSI_OPCODE_TXD)
4544 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4545 else if (opcode == TGSI_OPCODE_TXQ) {
4546 if (ir->op == ir_query_levels) {
4547 /* the level is stored in W */
4548 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4549 result_dst.writemask = WRITEMASK_X;
4550 levels_src.swizzle = SWIZZLE_WWWW;
4551 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4552 } else
4553 inst = emit_asm(ir, opcode, result_dst, lod_info);
4554 } else if (opcode == TGSI_OPCODE_TXQS) {
4555 inst = emit_asm(ir, opcode, result_dst);
4556 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4557 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4558 } else if (opcode == TGSI_OPCODE_TEX2) {
4559 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4560 } else if (opcode == TGSI_OPCODE_TG4) {
4561 if (is_cube_array && ir->shadow_comparator) {
4562 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4563 } else {
4564 inst = emit_asm(ir, opcode, result_dst, coord, component);
4565 }
4566 } else
4567 inst = emit_asm(ir, opcode, result_dst, coord);
4568
4569 if (ir->shadow_comparator)
4570 inst->tex_shadow = GL_TRUE;
4571
4572 if (var->contains_bindless()) {
4573 inst->resource = bindless;
4574 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4575 SWIZZLE_X, SWIZZLE_Y);
4576 } else {
4577 inst->resource = sampler;
4578 inst->sampler_array_size = sampler_array_size;
4579 inst->sampler_base = sampler_base;
4580 }
4581
4582 if (ir->offset) {
4583 if (!inst->tex_offsets)
4584 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4585 MAX_GLSL_TEXTURE_OFFSET);
4586
4587 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4588 offset[i].file != PROGRAM_UNDEFINED; i++)
4589 inst->tex_offsets[i] = offset[i];
4590 inst->tex_offset_num_offset = i;
4591 }
4592
4593 inst->tex_target = sampler_type->sampler_index();
4594 inst->tex_type = ir->type->base_type;
4595
4596 this->result = result_src;
4597 }
4598
4599 void
4600 glsl_to_tgsi_visitor::visit(ir_return *ir)
4601 {
4602 assert(!ir->get_value());
4603
4604 emit_asm(ir, TGSI_OPCODE_RET);
4605 }
4606
4607 void
4608 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4609 {
4610 if (ir->condition) {
4611 ir->condition->accept(this);
4612 st_src_reg condition = this->result;
4613
4614 /* Convert the bool condition to a float so we can negate. */
4615 if (native_integers) {
4616 st_src_reg temp = get_temp(ir->condition->type);
4617 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4618 condition, st_src_reg_for_float(1.0));
4619 condition = temp;
4620 }
4621
4622 condition.negate = ~condition.negate;
4623 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4624 } else {
4625 /* unconditional kil */
4626 emit_asm(ir, TGSI_OPCODE_KILL);
4627 }
4628 }
4629
4630 void
4631 glsl_to_tgsi_visitor::visit(ir_demote *ir)
4632 {
4633 assert(!"demote statement unsupported");
4634 }
4635
4636 void
4637 glsl_to_tgsi_visitor::visit(ir_if *ir)
4638 {
4639 enum tgsi_opcode if_opcode;
4640 glsl_to_tgsi_instruction *if_inst;
4641
4642 ir->condition->accept(this);
4643 assert(this->result.file != PROGRAM_UNDEFINED);
4644
4645 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4646
4647 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4648
4649 this->instructions.push_tail(if_inst);
4650
4651 visit_exec_list(&ir->then_instructions, this);
4652
4653 if (!ir->else_instructions.is_empty()) {
4654 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4655 visit_exec_list(&ir->else_instructions, this);
4656 }
4657
4658 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4659 }
4660
4661
4662 void
4663 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4664 {
4665 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4666
4667 ir->stream->accept(this);
4668 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4669 }
4670
4671 void
4672 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4673 {
4674 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4675
4676 ir->stream->accept(this);
4677 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4678 }
4679
4680 void
4681 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4682 {
4683 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4684 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4685
4686 emit_asm(ir, TGSI_OPCODE_BARRIER);
4687 }
4688
4689 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4690 {
4691 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4692
4693 result.file = PROGRAM_UNDEFINED;
4694 next_temp = 1;
4695 array_sizes = NULL;
4696 max_num_arrays = 0;
4697 next_array = 0;
4698 num_inputs = 0;
4699 num_outputs = 0;
4700 num_input_arrays = 0;
4701 num_output_arrays = 0;
4702 num_atomics = 0;
4703 num_atomic_arrays = 0;
4704 num_immediates = 0;
4705 num_address_regs = 0;
4706 samplers_used = 0;
4707 images_used = 0;
4708 indirect_addr_consts = false;
4709 wpos_transform_const = -1;
4710 native_integers = false;
4711 mem_ctx = ralloc_context(NULL);
4712 ctx = NULL;
4713 prog = NULL;
4714 precise = 0;
4715 need_uarl = false;
4716 shader_program = NULL;
4717 shader = NULL;
4718 options = NULL;
4719 have_sqrt = false;
4720 have_fma = false;
4721 use_shared_memory = false;
4722 has_tex_txf_lz = false;
4723 variables = NULL;
4724 }
4725
4726 static void var_destroy(struct hash_entry *entry)
4727 {
4728 variable_storage *storage = (variable_storage *)entry->data;
4729
4730 delete storage;
4731 }
4732
4733 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4734 {
4735 _mesa_hash_table_destroy(variables, var_destroy);
4736 free(array_sizes);
4737 ralloc_free(mem_ctx);
4738 }
4739
4740 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4741 {
4742 delete v;
4743 }
4744
4745
4746 /**
4747 * Count resources used by the given gpu program (number of texture
4748 * samplers, etc).
4749 */
4750 static void
4751 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4752 {
4753 v->samplers_used = 0;
4754 v->images_used = 0;
4755 prog->info.textures_used_by_txf = 0;
4756
4757 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4758 if (inst->info->is_tex) {
4759 for (int i = 0; i < inst->sampler_array_size; i++) {
4760 unsigned idx = inst->sampler_base + i;
4761 v->samplers_used |= 1u << idx;
4762
4763 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4764 v->sampler_types[idx] = inst->tex_type;
4765 v->sampler_targets[idx] =
4766 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4767
4768 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4769 prog->info.textures_used_by_txf |= 1u << idx;
4770 }
4771 }
4772 }
4773
4774 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4775 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4776
4777 if (inst->resource.file != PROGRAM_UNDEFINED && (
4778 is_resource_instruction(inst->op) ||
4779 inst->op == TGSI_OPCODE_STORE)) {
4780 if (inst->resource.file == PROGRAM_MEMORY) {
4781 v->use_shared_memory = true;
4782 } else if (inst->resource.file == PROGRAM_IMAGE) {
4783 for (int i = 0; i < inst->sampler_array_size; i++) {
4784 unsigned idx = inst->sampler_base + i;
4785 v->images_used |= 1 << idx;
4786 v->image_targets[idx] =
4787 st_translate_texture_target(inst->tex_target, false);
4788 v->image_formats[idx] = inst->image_format;
4789 v->image_wr[idx] = !inst->read_only;
4790 }
4791 }
4792 }
4793 }
4794 prog->SamplersUsed = v->samplers_used;
4795
4796 if (v->shader_program != NULL)
4797 _mesa_update_shader_textures_used(v->shader_program, prog);
4798 }
4799
4800 /**
4801 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4802 * are read from the given src in this instruction
4803 */
4804 static int
4805 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4806 {
4807 int read_mask = 0, comp;
4808
4809 /* Now, given the src swizzle and the written channels, find which
4810 * components are actually read
4811 */
4812 for (comp = 0; comp < 4; ++comp) {
4813 const unsigned coord = GET_SWZ(src.swizzle, comp);
4814 assert(coord < 4);
4815 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4816 read_mask |= 1 << coord;
4817 }
4818
4819 return read_mask;
4820 }
4821
4822 /**
4823 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4824 * instruction is the first instruction to write to register T0. There are
4825 * several lowering passes done in GLSL IR (e.g. branches and
4826 * relative addressing) that create a large number of conditional assignments
4827 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4828 *
4829 * Here is why this conversion is safe:
4830 * CMP T0, T1 T2 T0 can be expanded to:
4831 * if (T1 < 0.0)
4832 * MOV T0, T2;
4833 * else
4834 * MOV T0, T0;
4835 *
4836 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4837 * as the original program. If (T1 < 0.0) evaluates to false, executing
4838 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4839 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4840 * because any instruction that was going to read from T0 after this was going
4841 * to read a garbage value anyway.
4842 */
4843 void
4844 glsl_to_tgsi_visitor::simplify_cmp(void)
4845 {
4846 int tempWritesSize = 0;
4847 unsigned *tempWrites = NULL;
4848 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4849
4850 memset(outputWrites, 0, sizeof(outputWrites));
4851
4852 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4853 unsigned prevWriteMask = 0;
4854
4855 /* Give up if we encounter relative addressing or flow control. */
4856 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4857 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4858 inst->info->is_branch ||
4859 inst->op == TGSI_OPCODE_CONT ||
4860 inst->op == TGSI_OPCODE_END ||
4861 inst->op == TGSI_OPCODE_RET) {
4862 break;
4863 }
4864
4865 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4866 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4867 prevWriteMask = outputWrites[inst->dst[0].index];
4868 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4869 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4870 if (inst->dst[0].index >= tempWritesSize) {
4871 const int inc = 4096;
4872
4873 tempWrites = (unsigned*)
4874 realloc(tempWrites,
4875 (tempWritesSize + inc) * sizeof(unsigned));
4876 if (!tempWrites)
4877 return;
4878
4879 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4880 tempWritesSize += inc;
4881 }
4882
4883 prevWriteMask = tempWrites[inst->dst[0].index];
4884 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4885 } else
4886 continue;
4887
4888 /* For a CMP to be considered a conditional write, the destination
4889 * register and source register two must be the same. */
4890 if (inst->op == TGSI_OPCODE_CMP
4891 && !(inst->dst[0].writemask & prevWriteMask)
4892 && inst->src[2].file == inst->dst[0].file
4893 && inst->src[2].index == inst->dst[0].index
4894 && inst->dst[0].writemask ==
4895 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4896
4897 inst->op = TGSI_OPCODE_MOV;
4898 inst->info = tgsi_get_opcode_info(inst->op);
4899 inst->src[0] = inst->src[1];
4900 }
4901 }
4902
4903 free(tempWrites);
4904 }
4905
4906 static void
4907 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4908 {
4909 if (src && src->file == PROGRAM_TEMPORARY) {
4910 int old_idx = src->index;
4911 if (renames[old_idx].valid)
4912 src->index = renames[old_idx].new_reg;
4913 }
4914 }
4915
4916 /* Replaces all references to a temporary register index with another index. */
4917 void
4918 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4919 {
4920 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4921 unsigned j;
4922 for (j = 0; j < num_inst_src_regs(inst); j++) {
4923 rename_temp_handle_src(renames, &inst->src[j]);
4924 rename_temp_handle_src(renames, inst->src[j].reladdr);
4925 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4926 }
4927
4928 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4929 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4930 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4931 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4932 }
4933
4934 rename_temp_handle_src(renames, &inst->resource);
4935 rename_temp_handle_src(renames, inst->resource.reladdr);
4936 rename_temp_handle_src(renames, inst->resource.reladdr2);
4937
4938 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4939 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4940 int old_idx = inst->dst[j].index;
4941 if (renames[old_idx].valid)
4942 inst->dst[j].index = renames[old_idx].new_reg;
4943 }
4944 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4945 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4946 }
4947 }
4948 }
4949
4950 void
4951 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4952 {
4953 int depth = 0; /* loop depth */
4954 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4955 unsigned i = 0, j;
4956
4957 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4958 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4959 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4960 if (first_writes[inst->dst[j].index] == -1)
4961 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4962 }
4963 }
4964
4965 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4966 if (depth++ == 0)
4967 loop_start = i;
4968 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4969 if (--depth == 0)
4970 loop_start = -1;
4971 }
4972 assert(depth >= 0);
4973 i++;
4974 }
4975 }
4976
4977 void
4978 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
4979 {
4980 int depth = 0; /* loop depth */
4981 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4982 unsigned i = 0, j;
4983
4984 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4985 for (j = 0; j < num_inst_src_regs(inst); j++) {
4986 if (inst->src[j].file == PROGRAM_TEMPORARY) {
4987 if (first_reads[inst->src[j].index] == -1)
4988 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
4989 }
4990 }
4991 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4992 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
4993 if (first_reads[inst->tex_offsets[j].index] == -1)
4994 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
4995 }
4996 }
4997 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4998 if (depth++ == 0)
4999 loop_start = i;
5000 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5001 if (--depth == 0)
5002 loop_start = -1;
5003 }
5004 assert(depth >= 0);
5005 i++;
5006 }
5007 }
5008
5009 void
5010 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
5011 {
5012 int depth = 0; /* loop depth */
5013 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5014 unsigned i = 0, j;
5015 int k;
5016 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5017 for (j = 0; j < num_inst_src_regs(inst); j++) {
5018 if (inst->src[j].file == PROGRAM_TEMPORARY)
5019 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
5020 }
5021 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5022 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
5023 if (first_writes[inst->dst[j].index] == -1)
5024 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5025 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
5026 }
5027 }
5028 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5029 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
5030 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
5031 }
5032 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5033 if (depth++ == 0)
5034 loop_start = i;
5035 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5036 if (--depth == 0) {
5037 loop_start = -1;
5038 for (k = 0; k < this->next_temp; k++) {
5039 if (last_reads[k] == -2) {
5040 last_reads[k] = i;
5041 }
5042 }
5043 }
5044 }
5045 assert(depth >= 0);
5046 i++;
5047 }
5048 }
5049
5050 void
5051 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
5052 {
5053 int depth = 0; /* loop depth */
5054 int i = 0, k;
5055 unsigned j;
5056
5057 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5058 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5059 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5060 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5061 }
5062
5063 if (inst->op == TGSI_OPCODE_BGNLOOP)
5064 depth++;
5065 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5066 if (--depth == 0) {
5067 for (k = 0; k < this->next_temp; k++) {
5068 if (last_writes[k] == -2) {
5069 last_writes[k] = i;
5070 }
5071 }
5072 }
5073 assert(depth >= 0);
5074 i++;
5075 }
5076 }
5077
5078 /*
5079 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5080 * channels for copy propagation and updates following instructions to
5081 * use the original versions.
5082 *
5083 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5084 * will occur. As an example, a TXP production before this pass:
5085 *
5086 * 0: MOV TEMP[1], INPUT[4].xyyy;
5087 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5088 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5089 *
5090 * and after:
5091 *
5092 * 0: MOV TEMP[1], INPUT[4].xyyy;
5093 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5094 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5095 *
5096 * which allows for dead code elimination on TEMP[1]'s writes.
5097 */
5098 void
5099 glsl_to_tgsi_visitor::copy_propagate(void)
5100 {
5101 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5102 glsl_to_tgsi_instruction *,
5103 this->next_temp * 4);
5104 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5105 int level = 0;
5106
5107 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5108 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5109 || inst->dst[0].index < this->next_temp);
5110
5111 /* First, do any copy propagation possible into the src regs. */
5112 for (int r = 0; r < 3; r++) {
5113 glsl_to_tgsi_instruction *first = NULL;
5114 bool good = true;
5115 int acp_base = inst->src[r].index * 4;
5116
5117 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5118 inst->src[r].reladdr ||
5119 inst->src[r].reladdr2)
5120 continue;
5121
5122 /* See if we can find entries in the ACP consisting of MOVs
5123 * from the same src register for all the swizzled channels
5124 * of this src register reference.
5125 */
5126 for (int i = 0; i < 4; i++) {
5127 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5128 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5129
5130 if (!copy_chan) {
5131 good = false;
5132 break;
5133 }
5134
5135 assert(acp_level[acp_base + src_chan] <= level);
5136
5137 if (!first) {
5138 first = copy_chan;
5139 } else {
5140 if (first->src[0].file != copy_chan->src[0].file ||
5141 first->src[0].index != copy_chan->src[0].index ||
5142 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5143 first->src[0].index2D != copy_chan->src[0].index2D) {
5144 good = false;
5145 break;
5146 }
5147 }
5148 }
5149
5150 if (good) {
5151 /* We've now validated that we can copy-propagate to
5152 * replace this src register reference. Do it.
5153 */
5154 inst->src[r].file = first->src[0].file;
5155 inst->src[r].index = first->src[0].index;
5156 inst->src[r].index2D = first->src[0].index2D;
5157 inst->src[r].has_index2 = first->src[0].has_index2;
5158 inst->src[r].double_reg2 = first->src[0].double_reg2;
5159 inst->src[r].array_id = first->src[0].array_id;
5160
5161 int swizzle = 0;
5162 for (int i = 0; i < 4; i++) {
5163 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5164 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5165 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5166 }
5167 inst->src[r].swizzle = swizzle;
5168 }
5169 }
5170
5171 switch (inst->op) {
5172 case TGSI_OPCODE_BGNLOOP:
5173 case TGSI_OPCODE_ENDLOOP:
5174 /* End of a basic block, clear the ACP entirely. */
5175 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5176 break;
5177
5178 case TGSI_OPCODE_IF:
5179 case TGSI_OPCODE_UIF:
5180 ++level;
5181 break;
5182
5183 case TGSI_OPCODE_ENDIF:
5184 case TGSI_OPCODE_ELSE:
5185 /* Clear all channels written inside the block from the ACP, but
5186 * leaving those that were not touched.
5187 */
5188 for (int r = 0; r < this->next_temp; r++) {
5189 for (int c = 0; c < 4; c++) {
5190 if (!acp[4 * r + c])
5191 continue;
5192
5193 if (acp_level[4 * r + c] >= level)
5194 acp[4 * r + c] = NULL;
5195 }
5196 }
5197 if (inst->op == TGSI_OPCODE_ENDIF)
5198 --level;
5199 break;
5200
5201 default:
5202 /* Continuing the block, clear any written channels from
5203 * the ACP.
5204 */
5205 for (int d = 0; d < 2; d++) {
5206 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5207 /* Any temporary might be written, so no copy propagation
5208 * across this instruction.
5209 */
5210 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5211 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5212 inst->dst[d].reladdr) {
5213 /* Any output might be written, so no copy propagation
5214 * from outputs across this instruction.
5215 */
5216 for (int r = 0; r < this->next_temp; r++) {
5217 for (int c = 0; c < 4; c++) {
5218 if (!acp[4 * r + c])
5219 continue;
5220
5221 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5222 acp[4 * r + c] = NULL;
5223 }
5224 }
5225 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5226 inst->dst[d].file == PROGRAM_OUTPUT) {
5227 /* Clear where it's used as dst. */
5228 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5229 for (int c = 0; c < 4; c++) {
5230 if (inst->dst[d].writemask & (1 << c))
5231 acp[4 * inst->dst[d].index + c] = NULL;
5232 }
5233 }
5234
5235 /* Clear where it's used as src. */
5236 for (int r = 0; r < this->next_temp; r++) {
5237 for (int c = 0; c < 4; c++) {
5238 if (!acp[4 * r + c])
5239 continue;
5240
5241 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5242
5243 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5244 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5245 inst->dst[d].writemask & (1 << src_chan)) {
5246 acp[4 * r + c] = NULL;
5247 }
5248 }
5249 }
5250 }
5251 }
5252 break;
5253 }
5254
5255 /* If this is a copy, add it to the ACP. */
5256 if (inst->op == TGSI_OPCODE_MOV &&
5257 inst->dst[0].file == PROGRAM_TEMPORARY &&
5258 !(inst->dst[0].file == inst->src[0].file &&
5259 inst->dst[0].index == inst->src[0].index) &&
5260 !inst->dst[0].reladdr &&
5261 !inst->dst[0].reladdr2 &&
5262 !inst->saturate &&
5263 inst->src[0].file != PROGRAM_ARRAY &&
5264 (inst->src[0].file != PROGRAM_OUTPUT ||
5265 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5266 !inst->src[0].reladdr &&
5267 !inst->src[0].reladdr2 &&
5268 !inst->src[0].negate &&
5269 !inst->src[0].abs) {
5270 for (int i = 0; i < 4; i++) {
5271 if (inst->dst[0].writemask & (1 << i)) {
5272 acp[4 * inst->dst[0].index + i] = inst;
5273 acp_level[4 * inst->dst[0].index + i] = level;
5274 }
5275 }
5276 }
5277 }
5278
5279 ralloc_free(acp_level);
5280 ralloc_free(acp);
5281 }
5282
5283 static void
5284 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5285 {
5286 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5287 /* Clear where it's used as src. */
5288 int swz = GET_SWZ(reladdr->swizzle, 0);
5289 writes[4 * reladdr->index + swz] = NULL;
5290 }
5291 }
5292
5293 /*
5294 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5295 * code elimination.
5296 *
5297 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5298 * will occur. As an example, a TXP production after copy propagation but
5299 * before this pass:
5300 *
5301 * 0: MOV TEMP[1], INPUT[4].xyyy;
5302 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5303 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5304 *
5305 * and after this pass:
5306 *
5307 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5308 */
5309 int
5310 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5311 {
5312 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5313 glsl_to_tgsi_instruction *,
5314 this->next_temp * 4);
5315 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5316 int level = 0;
5317 int removed = 0;
5318
5319 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5320 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5321 || inst->dst[0].index < this->next_temp);
5322
5323 switch (inst->op) {
5324 case TGSI_OPCODE_BGNLOOP:
5325 case TGSI_OPCODE_ENDLOOP:
5326 case TGSI_OPCODE_CONT:
5327 case TGSI_OPCODE_BRK:
5328 /* End of a basic block, clear the write array entirely.
5329 *
5330 * This keeps us from killing dead code when the writes are
5331 * on either side of a loop, even when the register isn't touched
5332 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5333 * dead code of this type, so it shouldn't make a difference as long as
5334 * the dead code elimination pass in the GLSL compiler does its job.
5335 */
5336 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5337 break;
5338
5339 case TGSI_OPCODE_ENDIF:
5340 case TGSI_OPCODE_ELSE:
5341 /* Promote the recorded level of all channels written inside the
5342 * preceding if or else block to the level above the if/else block.
5343 */
5344 for (int r = 0; r < this->next_temp; r++) {
5345 for (int c = 0; c < 4; c++) {
5346 if (!writes[4 * r + c])
5347 continue;
5348
5349 if (write_level[4 * r + c] == level)
5350 write_level[4 * r + c] = level-1;
5351 }
5352 }
5353 if (inst->op == TGSI_OPCODE_ENDIF)
5354 --level;
5355 break;
5356
5357 case TGSI_OPCODE_IF:
5358 case TGSI_OPCODE_UIF:
5359 ++level;
5360 /* fallthrough to default case to mark the condition as read */
5361 default:
5362 /* Continuing the block, clear any channels from the write array that
5363 * are read by this instruction.
5364 */
5365 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5366 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5367 /* Any temporary might be read, so no dead code elimination
5368 * across this instruction.
5369 */
5370 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5371 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5372 /* Clear where it's used as src. */
5373 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5374 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5375 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5376 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5377
5378 for (int c = 0; c < 4; c++) {
5379 if (src_chans & (1 << c))
5380 writes[4 * inst->src[i].index + c] = NULL;
5381 }
5382 }
5383 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5384 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5385 }
5386 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5387 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5388 /* Any temporary might be read, so no dead code elimination
5389 * across this instruction.
5390 */
5391 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5392 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5393 /* Clear where it's used as src. */
5394 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5395 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5396 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5397 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5398
5399 for (int c = 0; c < 4; c++) {
5400 if (src_chans & (1 << c))
5401 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5402 }
5403 }
5404 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5405 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5406 }
5407
5408 if (inst->resource.file == PROGRAM_TEMPORARY) {
5409 int src_chans;
5410
5411 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5412 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5413 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5414 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5415
5416 for (int c = 0; c < 4; c++) {
5417 if (src_chans & (1 << c))
5418 writes[4 * inst->resource.index + c] = NULL;
5419 }
5420 }
5421 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5422 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5423
5424 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5425 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5426 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5427 }
5428 break;
5429 }
5430
5431 /* If this instruction writes to a temporary, add it to the write array.
5432 * If there is already an instruction in the write array for one or more
5433 * of the channels, flag that channel write as dead.
5434 */
5435 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5436 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5437 !inst->dst[i].reladdr) {
5438 for (int c = 0; c < 4; c++) {
5439 if (inst->dst[i].writemask & (1 << c)) {
5440 if (writes[4 * inst->dst[i].index + c]) {
5441 if (write_level[4 * inst->dst[i].index + c] < level)
5442 continue;
5443 else
5444 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5445 }
5446 writes[4 * inst->dst[i].index + c] = inst;
5447 write_level[4 * inst->dst[i].index + c] = level;
5448 }
5449 }
5450 }
5451 }
5452 }
5453
5454 /* Anything still in the write array at this point is dead code. */
5455 for (int r = 0; r < this->next_temp; r++) {
5456 for (int c = 0; c < 4; c++) {
5457 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5458 if (inst)
5459 inst->dead_mask |= (1 << c);
5460 }
5461 }
5462
5463 /* Now actually remove the instructions that are completely dead and update
5464 * the writemask of other instructions with dead channels.
5465 */
5466 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5467 if (!inst->dead_mask || !inst->dst[0].writemask)
5468 continue;
5469 /* No amount of dead masks should remove memory stores */
5470 if (inst->info->is_store)
5471 continue;
5472
5473 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5474 inst->remove();
5475 delete inst;
5476 removed++;
5477 } else {
5478 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5479 if (inst->dead_mask == WRITEMASK_XY ||
5480 inst->dead_mask == WRITEMASK_ZW)
5481 inst->dst[0].writemask &= ~(inst->dead_mask);
5482 } else
5483 inst->dst[0].writemask &= ~(inst->dead_mask);
5484 }
5485 }
5486
5487 ralloc_free(write_level);
5488 ralloc_free(writes);
5489
5490 return removed;
5491 }
5492
5493 /* merge DFRACEXP instructions into one. */
5494 void
5495 glsl_to_tgsi_visitor::merge_two_dsts(void)
5496 {
5497 /* We never delete inst, but we may delete its successor. */
5498 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5499 glsl_to_tgsi_instruction *inst2;
5500 unsigned defined;
5501
5502 if (num_inst_dst_regs(inst) != 2)
5503 continue;
5504
5505 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5506 inst->dst[1].file != PROGRAM_UNDEFINED)
5507 continue;
5508
5509 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5510 inst->dst[1].file != PROGRAM_UNDEFINED);
5511
5512 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5513 defined = 1;
5514 else
5515 defined = 0;
5516
5517 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5518 while (!inst2->is_tail_sentinel()) {
5519 if (inst->op == inst2->op &&
5520 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5521 inst->src[0].file == inst2->src[0].file &&
5522 inst->src[0].index == inst2->src[0].index &&
5523 inst->src[0].type == inst2->src[0].type &&
5524 inst->src[0].swizzle == inst2->src[0].swizzle)
5525 break;
5526 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5527 }
5528
5529 if (inst2->is_tail_sentinel()) {
5530 /* Undefined destinations are not allowed, substitute with an unused
5531 * temporary register.
5532 */
5533 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5534 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5535 inst->dst[defined ^ 1].writemask = 0;
5536 continue;
5537 }
5538
5539 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5540 inst2->remove();
5541 delete inst2;
5542 }
5543 }
5544
5545 template <typename st_reg>
5546 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5547 {
5548 if (reg.file == PROGRAM_ARRAY) {
5549 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5550 has_indirect_access[reg.array_id] = true;
5551 if (reg.reladdr)
5552 test_indirect_access(*reg.reladdr, has_indirect_access);
5553 if (reg.reladdr2)
5554 test_indirect_access(*reg.reladdr2, has_indirect_access);
5555 }
5556 }
5557 }
5558
5559 template <typename st_reg>
5560 void remap_array(st_reg& reg, const int *array_remap_info,
5561 const bool *has_indirect_access)
5562 {
5563 if (reg.file == PROGRAM_ARRAY) {
5564 if (!has_indirect_access[reg.array_id]) {
5565 reg.file = PROGRAM_TEMPORARY;
5566 reg.index = reg.index + array_remap_info[reg.array_id];
5567 reg.array_id = 0;
5568 } else {
5569 reg.array_id = array_remap_info[reg.array_id];
5570 }
5571
5572 if (reg.reladdr)
5573 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5574
5575 if (reg.reladdr2)
5576 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5577 }
5578 }
5579
5580 /* One-dimensional arrays whose elements are only accessed directly are
5581 * replaced by an according set of temporary registers that then can become
5582 * subject to further optimization steps like copy propagation and
5583 * register merging.
5584 */
5585 void
5586 glsl_to_tgsi_visitor::split_arrays(void)
5587 {
5588 if (!next_array)
5589 return;
5590
5591 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5592
5593 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5594 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5595 test_indirect_access(inst->src[j], has_indirect_access);
5596
5597 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5598 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5599
5600 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5601 test_indirect_access(inst->dst[j], has_indirect_access);
5602
5603 test_indirect_access(inst->resource, has_indirect_access);
5604 }
5605
5606 unsigned array_offset = 0;
5607 unsigned n_remaining_arrays = 0;
5608
5609 /* Double use: For arrays that get split this value will contain
5610 * the base index of the temporary registers this array is replaced
5611 * with. For arrays that remain it contains the new array ID.
5612 */
5613 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5614 next_array + 1);
5615
5616 for (unsigned i = 1; i <= next_array; ++i) {
5617 if (!has_indirect_access[i]) {
5618 array_remap_info[i] = this->next_temp + array_offset;
5619 array_offset += array_sizes[i - 1];
5620 } else {
5621 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5622 array_remap_info[i] = ++n_remaining_arrays;
5623 }
5624 }
5625
5626 if (next_array != n_remaining_arrays) {
5627 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5628 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5629 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5630
5631 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5632 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5633
5634 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5635 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5636 }
5637 remap_array(inst->resource, array_remap_info, has_indirect_access);
5638 }
5639 }
5640
5641 ralloc_free(has_indirect_access);
5642 this->next_temp += array_offset;
5643 next_array = n_remaining_arrays;
5644 }
5645
5646 /* Merges temporary registers together where possible to reduce the number of
5647 * registers needed to run a program.
5648 *
5649 * Produces optimal code only after copy propagation and dead code elimination
5650 * have been run. */
5651 void
5652 glsl_to_tgsi_visitor::merge_registers(void)
5653 {
5654 class array_live_range *arr_live_ranges = NULL;
5655
5656 struct register_live_range *reg_live_ranges =
5657 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5658
5659 if (this->next_array > 0) {
5660 arr_live_ranges = new array_live_range[this->next_array];
5661 for (unsigned i = 0; i < this->next_array; ++i)
5662 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5663 }
5664
5665
5666 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5667 this->next_temp, reg_live_ranges,
5668 this->next_array, arr_live_ranges)) {
5669 struct rename_reg_pair *renames =
5670 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5671 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5672 reg_live_ranges, renames);
5673 rename_temp_registers(renames);
5674
5675 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5676 &this->instructions, arr_live_ranges);
5677 }
5678
5679 if (arr_live_ranges)
5680 delete[] arr_live_ranges;
5681
5682 ralloc_free(reg_live_ranges);
5683 }
5684
5685 /* Reassign indices to temporary registers by reusing unused indices created
5686 * by optimization passes. */
5687 void
5688 glsl_to_tgsi_visitor::renumber_registers(void)
5689 {
5690 int i = 0;
5691 int new_index = 0;
5692 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5693 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5694
5695 for (i = 0; i < this->next_temp; i++) {
5696 first_writes[i] = -1;
5697 }
5698 get_first_temp_write(first_writes);
5699
5700 for (i = 0; i < this->next_temp; i++) {
5701 if (first_writes[i] < 0) continue;
5702 if (i != new_index) {
5703 renames[i].new_reg = new_index;
5704 renames[i].valid = true;
5705 }
5706 new_index++;
5707 }
5708
5709 rename_temp_registers(renames);
5710 this->next_temp = new_index;
5711 ralloc_free(renames);
5712 ralloc_free(first_writes);
5713 }
5714
5715 #ifndef NDEBUG
5716 void glsl_to_tgsi_visitor::print_stats()
5717 {
5718 int narray_registers = 0;
5719 for (unsigned i = 0; i < this->next_array; ++i)
5720 narray_registers += this->array_sizes[i];
5721
5722 int ninstructions = 0;
5723 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5724 ++ninstructions;
5725 }
5726
5727 simple_mtx_lock(&print_stats_mutex);
5728 stats_log << next_array << ", "
5729 << next_temp << ", "
5730 << narray_registers << ", "
5731 << next_temp + narray_registers << ", "
5732 << ninstructions << "\n";
5733 simple_mtx_unlock(&print_stats_mutex);
5734 }
5735 #endif
5736 /* ------------------------- TGSI conversion stuff -------------------------- */
5737
5738 /**
5739 * Intermediate state used during shader translation.
5740 */
5741 struct st_translate {
5742 struct ureg_program *ureg;
5743
5744 unsigned temps_size;
5745 struct ureg_dst *temps;
5746
5747 struct ureg_dst *arrays;
5748 unsigned num_temp_arrays;
5749 struct ureg_src *constants;
5750 int num_constants;
5751 struct ureg_src *immediates;
5752 int num_immediates;
5753 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5754 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5755 struct ureg_dst address[3];
5756 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5757 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5758 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5759 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5760 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5761 struct ureg_src shared_memory;
5762 unsigned *array_sizes;
5763 struct inout_decl *input_decls;
5764 unsigned num_input_decls;
5765 struct inout_decl *output_decls;
5766 unsigned num_output_decls;
5767
5768 const ubyte *inputMapping;
5769 const ubyte *outputMapping;
5770
5771 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5772 bool need_uarl;
5773 };
5774
5775 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5776 enum tgsi_semantic
5777 _mesa_sysval_to_semantic(unsigned sysval)
5778 {
5779 switch (sysval) {
5780 /* Vertex shader */
5781 case SYSTEM_VALUE_VERTEX_ID:
5782 return TGSI_SEMANTIC_VERTEXID;
5783 case SYSTEM_VALUE_INSTANCE_ID:
5784 return TGSI_SEMANTIC_INSTANCEID;
5785 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
5786 return TGSI_SEMANTIC_VERTEXID_NOBASE;
5787 case SYSTEM_VALUE_BASE_VERTEX:
5788 return TGSI_SEMANTIC_BASEVERTEX;
5789 case SYSTEM_VALUE_BASE_INSTANCE:
5790 return TGSI_SEMANTIC_BASEINSTANCE;
5791 case SYSTEM_VALUE_DRAW_ID:
5792 return TGSI_SEMANTIC_DRAWID;
5793
5794 /* Geometry shader */
5795 case SYSTEM_VALUE_INVOCATION_ID:
5796 return TGSI_SEMANTIC_INVOCATIONID;
5797
5798 /* Fragment shader */
5799 case SYSTEM_VALUE_FRAG_COORD:
5800 return TGSI_SEMANTIC_POSITION;
5801 case SYSTEM_VALUE_POINT_COORD:
5802 return TGSI_SEMANTIC_PCOORD;
5803 case SYSTEM_VALUE_FRONT_FACE:
5804 return TGSI_SEMANTIC_FACE;
5805 case SYSTEM_VALUE_SAMPLE_ID:
5806 return TGSI_SEMANTIC_SAMPLEID;
5807 case SYSTEM_VALUE_SAMPLE_POS:
5808 return TGSI_SEMANTIC_SAMPLEPOS;
5809 case SYSTEM_VALUE_SAMPLE_MASK_IN:
5810 return TGSI_SEMANTIC_SAMPLEMASK;
5811 case SYSTEM_VALUE_HELPER_INVOCATION:
5812 return TGSI_SEMANTIC_HELPER_INVOCATION;
5813
5814 /* Tessellation shader */
5815 case SYSTEM_VALUE_TESS_COORD:
5816 return TGSI_SEMANTIC_TESSCOORD;
5817 case SYSTEM_VALUE_VERTICES_IN:
5818 return TGSI_SEMANTIC_VERTICESIN;
5819 case SYSTEM_VALUE_PRIMITIVE_ID:
5820 return TGSI_SEMANTIC_PRIMID;
5821 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
5822 return TGSI_SEMANTIC_TESSOUTER;
5823 case SYSTEM_VALUE_TESS_LEVEL_INNER:
5824 return TGSI_SEMANTIC_TESSINNER;
5825
5826 /* Compute shader */
5827 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
5828 return TGSI_SEMANTIC_THREAD_ID;
5829 case SYSTEM_VALUE_WORK_GROUP_ID:
5830 return TGSI_SEMANTIC_BLOCK_ID;
5831 case SYSTEM_VALUE_NUM_WORK_GROUPS:
5832 return TGSI_SEMANTIC_GRID_SIZE;
5833 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
5834 return TGSI_SEMANTIC_BLOCK_SIZE;
5835
5836 /* ARB_shader_ballot */
5837 case SYSTEM_VALUE_SUBGROUP_SIZE:
5838 return TGSI_SEMANTIC_SUBGROUP_SIZE;
5839 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
5840 return TGSI_SEMANTIC_SUBGROUP_INVOCATION;
5841 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
5842 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
5843 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
5844 return TGSI_SEMANTIC_SUBGROUP_GE_MASK;
5845 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
5846 return TGSI_SEMANTIC_SUBGROUP_GT_MASK;
5847 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
5848 return TGSI_SEMANTIC_SUBGROUP_LE_MASK;
5849 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
5850 return TGSI_SEMANTIC_SUBGROUP_LT_MASK;
5851
5852 /* Unhandled */
5853 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
5854 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
5855 case SYSTEM_VALUE_VERTEX_CNT:
5856 case SYSTEM_VALUE_BARYCENTRIC_PIXEL:
5857 case SYSTEM_VALUE_BARYCENTRIC_SAMPLE:
5858 case SYSTEM_VALUE_BARYCENTRIC_CENTROID:
5859 case SYSTEM_VALUE_BARYCENTRIC_SIZE:
5860 default:
5861 assert(!"Unexpected SYSTEM_VALUE_ enum");
5862 return TGSI_SEMANTIC_COUNT;
5863 }
5864 }
5865
5866 /**
5867 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5868 */
5869 static struct ureg_src
5870 emit_immediate(struct st_translate *t,
5871 gl_constant_value values[4],
5872 GLenum type, int size)
5873 {
5874 struct ureg_program *ureg = t->ureg;
5875
5876 switch (type) {
5877 case GL_FLOAT:
5878 return ureg_DECL_immediate(ureg, &values[0].f, size);
5879 case GL_DOUBLE:
5880 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5881 case GL_INT64_ARB:
5882 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5883 case GL_UNSIGNED_INT64_ARB:
5884 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5885 case GL_INT:
5886 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5887 case GL_UNSIGNED_INT:
5888 case GL_BOOL:
5889 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5890 default:
5891 assert(!"should not get here - type must be float, int, uint, or bool");
5892 return ureg_src_undef();
5893 }
5894 }
5895
5896 /**
5897 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5898 */
5899 static struct ureg_dst
5900 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5901 unsigned array_id)
5902 {
5903 unsigned array;
5904
5905 switch (file) {
5906 case PROGRAM_UNDEFINED:
5907 return ureg_dst_undef();
5908
5909 case PROGRAM_TEMPORARY:
5910 /* Allocate space for temporaries on demand. */
5911 if (index >= t->temps_size) {
5912 const int inc = align(index - t->temps_size + 1, 4096);
5913
5914 t->temps = (struct ureg_dst*)
5915 realloc(t->temps,
5916 (t->temps_size + inc) * sizeof(struct ureg_dst));
5917 if (!t->temps)
5918 return ureg_dst_undef();
5919
5920 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5921 t->temps_size += inc;
5922 }
5923
5924 if (ureg_dst_is_undef(t->temps[index]))
5925 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5926
5927 return t->temps[index];
5928
5929 case PROGRAM_ARRAY:
5930 assert(array_id && array_id <= t->num_temp_arrays);
5931 array = array_id - 1;
5932
5933 if (ureg_dst_is_undef(t->arrays[array]))
5934 t->arrays[array] = ureg_DECL_array_temporary(
5935 t->ureg, t->array_sizes[array], TRUE);
5936
5937 return ureg_dst_array_offset(t->arrays[array], index);
5938
5939 case PROGRAM_OUTPUT:
5940 if (!array_id) {
5941 if (t->procType == PIPE_SHADER_FRAGMENT)
5942 assert(index < 2 * FRAG_RESULT_MAX);
5943 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5944 t->procType == PIPE_SHADER_TESS_EVAL)
5945 assert(index < VARYING_SLOT_TESS_MAX);
5946 else
5947 assert(index < VARYING_SLOT_MAX);
5948
5949 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5950 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5951 return t->outputs[t->outputMapping[index]];
5952 }
5953 else {
5954 struct inout_decl *decl =
5955 find_inout_array(t->output_decls,
5956 t->num_output_decls, array_id);
5957 unsigned mesa_index = decl->mesa_index;
5958 int slot = t->outputMapping[mesa_index];
5959
5960 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5961
5962 struct ureg_dst dst = t->outputs[slot];
5963 dst.ArrayID = array_id;
5964 return ureg_dst_array_offset(dst, index - mesa_index);
5965 }
5966
5967 case PROGRAM_ADDRESS:
5968 return t->address[index];
5969
5970 default:
5971 assert(!"unknown dst register file");
5972 return ureg_dst_undef();
5973 }
5974 }
5975
5976 static struct ureg_src
5977 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5978
5979 static struct ureg_src
5980 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5981 unsigned addr_index)
5982 {
5983 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5984 return ureg_src(t->address[addr_index]);
5985
5986 return translate_src(t, reladdr);
5987 }
5988
5989 /**
5990 * Create a TGSI ureg_dst register from an st_dst_reg.
5991 */
5992 static struct ureg_dst
5993 translate_dst(struct st_translate *t,
5994 const st_dst_reg *dst_reg,
5995 bool saturate)
5996 {
5997 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5998 dst_reg->array_id);
5999
6000 if (dst.File == TGSI_FILE_NULL)
6001 return dst;
6002
6003 dst = ureg_writemask(dst, dst_reg->writemask);
6004
6005 if (saturate)
6006 dst = ureg_saturate(dst);
6007
6008 if (dst_reg->reladdr != NULL) {
6009 assert(dst_reg->file != PROGRAM_TEMPORARY);
6010 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
6011 }
6012
6013 if (dst_reg->has_index2) {
6014 if (dst_reg->reladdr2)
6015 dst = ureg_dst_dimension_indirect(dst,
6016 translate_addr(t, dst_reg->reladdr2, 1),
6017 dst_reg->index2D);
6018 else
6019 dst = ureg_dst_dimension(dst, dst_reg->index2D);
6020 }
6021
6022 return dst;
6023 }
6024
6025 /**
6026 * Create a TGSI ureg_src register from an st_src_reg.
6027 */
6028 static struct ureg_src
6029 translate_src(struct st_translate *t, const st_src_reg *src_reg)
6030 {
6031 struct ureg_src src;
6032 int index = src_reg->index;
6033 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
6034
6035 switch (src_reg->file) {
6036 case PROGRAM_UNDEFINED:
6037 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
6038 break;
6039
6040 case PROGRAM_TEMPORARY:
6041 case PROGRAM_ARRAY:
6042 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
6043 src_reg->array_id));
6044 break;
6045
6046 case PROGRAM_OUTPUT: {
6047 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
6048 src_reg->array_id);
6049 assert(dst.WriteMask != 0);
6050 unsigned shift = ffs(dst.WriteMask) - 1;
6051 src = ureg_swizzle(ureg_src(dst),
6052 shift,
6053 MIN2(shift + 1, 3),
6054 MIN2(shift + 2, 3),
6055 MIN2(shift + 3, 3));
6056 break;
6057 }
6058
6059 case PROGRAM_UNIFORM:
6060 assert(src_reg->index >= 0);
6061 src = src_reg->index < t->num_constants ?
6062 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6063 break;
6064 case PROGRAM_STATE_VAR:
6065 case PROGRAM_CONSTANT: /* ie, immediate */
6066 if (src_reg->has_index2)
6067 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6068 else
6069 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6070 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6071 break;
6072
6073 case PROGRAM_IMMEDIATE:
6074 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6075 src = t->immediates[src_reg->index];
6076 break;
6077
6078 case PROGRAM_INPUT:
6079 /* GLSL inputs are 64-bit containers, so we have to
6080 * map back to the original index and add the offset after
6081 * mapping. */
6082 index -= double_reg2;
6083 if (!src_reg->array_id) {
6084 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6085 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6086 src = t->inputs[t->inputMapping[index] + double_reg2];
6087 }
6088 else {
6089 struct inout_decl *decl = find_inout_array(t->input_decls,
6090 t->num_input_decls,
6091 src_reg->array_id);
6092 unsigned mesa_index = decl->mesa_index;
6093 int slot = t->inputMapping[mesa_index];
6094
6095 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6096
6097 src = t->inputs[slot];
6098 src.ArrayID = src_reg->array_id;
6099 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6100 }
6101 break;
6102
6103 case PROGRAM_ADDRESS:
6104 src = ureg_src(t->address[src_reg->index]);
6105 break;
6106
6107 case PROGRAM_SYSTEM_VALUE:
6108 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6109 src = t->systemValues[src_reg->index];
6110 break;
6111
6112 case PROGRAM_HW_ATOMIC:
6113 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6114 src_reg->array_id);
6115 break;
6116
6117 default:
6118 assert(!"unknown src register file");
6119 return ureg_src_undef();
6120 }
6121
6122 if (src_reg->has_index2) {
6123 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6124 * and UBO constant buffers (buffer, position).
6125 */
6126 if (src_reg->reladdr2)
6127 src = ureg_src_dimension_indirect(src,
6128 translate_addr(t, src_reg->reladdr2, 1),
6129 src_reg->index2D);
6130 else
6131 src = ureg_src_dimension(src, src_reg->index2D);
6132 }
6133
6134 src = ureg_swizzle(src,
6135 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6136 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6137 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6138 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6139
6140 if (src_reg->abs)
6141 src = ureg_abs(src);
6142
6143 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6144 src = ureg_negate(src);
6145
6146 if (src_reg->reladdr != NULL) {
6147 assert(src_reg->file != PROGRAM_TEMPORARY);
6148 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6149 }
6150
6151 return src;
6152 }
6153
6154 static struct tgsi_texture_offset
6155 translate_tex_offset(struct st_translate *t,
6156 const st_src_reg *in_offset)
6157 {
6158 struct tgsi_texture_offset offset;
6159 struct ureg_src src = translate_src(t, in_offset);
6160
6161 offset.File = src.File;
6162 offset.Index = src.Index;
6163 offset.SwizzleX = src.SwizzleX;
6164 offset.SwizzleY = src.SwizzleY;
6165 offset.SwizzleZ = src.SwizzleZ;
6166 offset.Padding = 0;
6167
6168 assert(!src.Indirect);
6169 assert(!src.DimIndirect);
6170 assert(!src.Dimension);
6171 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6172 assert(!src.Negate);
6173
6174 return offset;
6175 }
6176
6177 static void
6178 compile_tgsi_instruction(struct st_translate *t,
6179 const glsl_to_tgsi_instruction *inst)
6180 {
6181 struct ureg_program *ureg = t->ureg;
6182 int i;
6183 struct ureg_dst dst[2];
6184 struct ureg_src src[4];
6185 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6186
6187 int num_dst;
6188 int num_src;
6189 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6190
6191 num_dst = num_inst_dst_regs(inst);
6192 num_src = num_inst_src_regs(inst);
6193
6194 for (i = 0; i < num_dst; i++)
6195 dst[i] = translate_dst(t,
6196 &inst->dst[i],
6197 inst->saturate);
6198
6199 for (i = 0; i < num_src; i++)
6200 src[i] = translate_src(t, &inst->src[i]);
6201
6202 switch (inst->op) {
6203 case TGSI_OPCODE_BGNLOOP:
6204 case TGSI_OPCODE_ELSE:
6205 case TGSI_OPCODE_ENDLOOP:
6206 case TGSI_OPCODE_IF:
6207 case TGSI_OPCODE_UIF:
6208 assert(num_dst == 0);
6209 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6210 return;
6211
6212 case TGSI_OPCODE_TEX:
6213 case TGSI_OPCODE_TEX_LZ:
6214 case TGSI_OPCODE_TXB:
6215 case TGSI_OPCODE_TXD:
6216 case TGSI_OPCODE_TXL:
6217 case TGSI_OPCODE_TXP:
6218 case TGSI_OPCODE_TXQ:
6219 case TGSI_OPCODE_TXQS:
6220 case TGSI_OPCODE_TXF:
6221 case TGSI_OPCODE_TXF_LZ:
6222 case TGSI_OPCODE_TEX2:
6223 case TGSI_OPCODE_TXB2:
6224 case TGSI_OPCODE_TXL2:
6225 case TGSI_OPCODE_TG4:
6226 case TGSI_OPCODE_LODQ:
6227 case TGSI_OPCODE_SAMP2HND:
6228 if (inst->resource.file == PROGRAM_SAMPLER) {
6229 src[num_src] = t->samplers[inst->resource.index];
6230 } else {
6231 /* Bindless samplers. */
6232 src[num_src] = translate_src(t, &inst->resource);
6233 }
6234 assert(src[num_src].File != TGSI_FILE_NULL);
6235 if (inst->resource.reladdr)
6236 src[num_src] =
6237 ureg_src_indirect(src[num_src],
6238 translate_addr(t, inst->resource.reladdr, 2));
6239 num_src++;
6240 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6241 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6242 }
6243 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6244
6245 ureg_tex_insn(ureg,
6246 inst->op,
6247 dst, num_dst,
6248 tex_target,
6249 st_translate_texture_type(inst->tex_type),
6250 texoffsets, inst->tex_offset_num_offset,
6251 src, num_src);
6252 return;
6253
6254 case TGSI_OPCODE_RESQ:
6255 case TGSI_OPCODE_LOAD:
6256 case TGSI_OPCODE_ATOMUADD:
6257 case TGSI_OPCODE_ATOMXCHG:
6258 case TGSI_OPCODE_ATOMCAS:
6259 case TGSI_OPCODE_ATOMAND:
6260 case TGSI_OPCODE_ATOMOR:
6261 case TGSI_OPCODE_ATOMXOR:
6262 case TGSI_OPCODE_ATOMUMIN:
6263 case TGSI_OPCODE_ATOMUMAX:
6264 case TGSI_OPCODE_ATOMIMIN:
6265 case TGSI_OPCODE_ATOMIMAX:
6266 case TGSI_OPCODE_ATOMFADD:
6267 case TGSI_OPCODE_IMG2HND:
6268 case TGSI_OPCODE_ATOMINC_WRAP:
6269 case TGSI_OPCODE_ATOMDEC_WRAP:
6270 for (i = num_src - 1; i >= 0; i--)
6271 src[i + 1] = src[i];
6272 num_src++;
6273 if (inst->resource.file == PROGRAM_MEMORY) {
6274 src[0] = t->shared_memory;
6275 } else if (inst->resource.file == PROGRAM_BUFFER) {
6276 src[0] = t->buffers[inst->resource.index];
6277 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6278 src[0] = translate_src(t, &inst->resource);
6279 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6280 assert(inst->resource.has_index2);
6281 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6282 } else {
6283 assert(inst->resource.file != PROGRAM_UNDEFINED);
6284 if (inst->resource.file == PROGRAM_IMAGE) {
6285 src[0] = t->images[inst->resource.index];
6286 } else {
6287 /* Bindless images. */
6288 src[0] = translate_src(t, &inst->resource);
6289 }
6290 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6291 }
6292 if (inst->resource.reladdr)
6293 src[0] = ureg_src_indirect(src[0],
6294 translate_addr(t, inst->resource.reladdr, 2));
6295 assert(src[0].File != TGSI_FILE_NULL);
6296 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6297 inst->buffer_access,
6298 tex_target, inst->image_format);
6299 break;
6300
6301 case TGSI_OPCODE_STORE:
6302 if (inst->resource.file == PROGRAM_MEMORY) {
6303 dst[0] = ureg_dst(t->shared_memory);
6304 } else if (inst->resource.file == PROGRAM_BUFFER) {
6305 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6306 } else {
6307 if (inst->resource.file == PROGRAM_IMAGE) {
6308 dst[0] = ureg_dst(t->images[inst->resource.index]);
6309 } else {
6310 /* Bindless images. */
6311 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6312 }
6313 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6314 }
6315 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6316 if (inst->resource.reladdr)
6317 dst[0] = ureg_dst_indirect(dst[0],
6318 translate_addr(t, inst->resource.reladdr, 2));
6319 assert(dst[0].File != TGSI_FILE_NULL);
6320 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6321 inst->buffer_access,
6322 tex_target, inst->image_format);
6323 break;
6324
6325 default:
6326 ureg_insn(ureg,
6327 inst->op,
6328 dst, num_dst,
6329 src, num_src, inst->precise);
6330 break;
6331 }
6332 }
6333
6334 /* Invert SamplePos.y when rendering to the default framebuffer. */
6335 static void
6336 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6337 {
6338 struct ureg_program *ureg = t->ureg;
6339
6340 assert(wpos_y_transform >= 0);
6341 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6342 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6343 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6344 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6345
6346 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6347 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6348
6349 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6350 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6351 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6352 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6353 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6354 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6355 samplepos_sysval);
6356
6357 /* Use the result in place of the system value. */
6358 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6359 }
6360
6361
6362 /**
6363 * Emit the TGSI instructions for inverting and adjusting WPOS.
6364 * This code is unavoidable because it also depends on whether
6365 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6366 */
6367 static void
6368 emit_wpos_adjustment(struct gl_context *ctx,
6369 struct st_translate *t,
6370 int wpos_transform_const,
6371 boolean invert,
6372 GLfloat adjX, GLfloat adjY[2])
6373 {
6374 struct ureg_program *ureg = t->ureg;
6375
6376 assert(wpos_transform_const >= 0);
6377
6378 /* Fragment program uses fragment position input.
6379 * Need to replace instances of INPUT[WPOS] with temp T
6380 * where T = INPUT[WPOS] is inverted by Y.
6381 */
6382 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6383 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6384 struct ureg_src *wpos =
6385 ctx->Const.GLSLFragCoordIsSysVal ?
6386 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6387 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6388 struct ureg_src wpos_input = *wpos;
6389
6390 /* First, apply the coordinate shift: */
6391 if (adjX || adjY[0] || adjY[1]) {
6392 if (adjY[0] != adjY[1]) {
6393 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6394 * depending on whether inversion is actually going to be applied
6395 * or not, which is determined by testing against the inversion
6396 * state variable used below, which will be either +1 or -1.
6397 */
6398 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6399
6400 ureg_CMP(ureg, adj_temp,
6401 ureg_scalar(wpostrans, invert ? 2 : 0),
6402 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6403 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6404 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6405 } else {
6406 ureg_ADD(ureg, wpos_temp, wpos_input,
6407 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6408 }
6409 wpos_input = ureg_src(wpos_temp);
6410 } else {
6411 /* MOV wpos_temp, input[wpos]
6412 */
6413 ureg_MOV(ureg, wpos_temp, wpos_input);
6414 }
6415
6416 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6417 * inversion/identity, or the other way around if we're drawing to an FBO.
6418 */
6419 if (invert) {
6420 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6421 */
6422 ureg_MAD(ureg,
6423 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6424 wpos_input,
6425 ureg_scalar(wpostrans, 0),
6426 ureg_scalar(wpostrans, 1));
6427 } else {
6428 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6429 */
6430 ureg_MAD(ureg,
6431 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6432 wpos_input,
6433 ureg_scalar(wpostrans, 2),
6434 ureg_scalar(wpostrans, 3));
6435 }
6436
6437 /* Use wpos_temp as position input from here on:
6438 */
6439 *wpos = ureg_src(wpos_temp);
6440 }
6441
6442
6443 /**
6444 * Emit fragment position/ooordinate code.
6445 */
6446 static void
6447 emit_wpos(struct st_context *st,
6448 struct st_translate *t,
6449 const struct gl_program *program,
6450 struct ureg_program *ureg,
6451 int wpos_transform_const)
6452 {
6453 struct pipe_screen *pscreen = st->pipe->screen;
6454 GLfloat adjX = 0.0f;
6455 GLfloat adjY[2] = { 0.0f, 0.0f };
6456 boolean invert = FALSE;
6457
6458 /* Query the pixel center conventions supported by the pipe driver and set
6459 * adjX, adjY to help out if it cannot handle the requested one internally.
6460 *
6461 * The bias of the y-coordinate depends on whether y-inversion takes place
6462 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6463 * drawing to an FBO (causes additional inversion), and whether the pipe
6464 * driver origin and the requested origin differ (the latter condition is
6465 * stored in the 'invert' variable).
6466 *
6467 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6468 *
6469 * center shift only:
6470 * i -> h: +0.5
6471 * h -> i: -0.5
6472 *
6473 * inversion only:
6474 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6475 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6476 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6477 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6478 *
6479 * inversion and center shift:
6480 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6481 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6482 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6483 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6484 */
6485 if (program->info.fs.origin_upper_left) {
6486 /* Fragment shader wants origin in upper-left */
6487 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6488 /* the driver supports upper-left origin */
6489 }
6490 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6491 /* the driver supports lower-left origin, need to invert Y */
6492 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6493 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6494 invert = TRUE;
6495 }
6496 else
6497 assert(0);
6498 }
6499 else {
6500 /* Fragment shader wants origin in lower-left */
6501 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6502 /* the driver supports lower-left origin */
6503 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6504 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6505 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6506 /* the driver supports upper-left origin, need to invert Y */
6507 invert = TRUE;
6508 else
6509 assert(0);
6510 }
6511
6512 if (program->info.fs.pixel_center_integer) {
6513 /* Fragment shader wants pixel center integer */
6514 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6515 /* the driver supports pixel center integer */
6516 adjY[1] = 1.0f;
6517 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6518 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6519 }
6520 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6521 /* the driver supports pixel center half integer, need to bias X,Y */
6522 adjX = -0.5f;
6523 adjY[0] = -0.5f;
6524 adjY[1] = 0.5f;
6525 }
6526 else
6527 assert(0);
6528 }
6529 else {
6530 /* Fragment shader wants pixel center half integer */
6531 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6532 /* the driver supports pixel center half integer */
6533 }
6534 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6535 /* the driver supports pixel center integer, need to bias X,Y */
6536 adjX = adjY[0] = adjY[1] = 0.5f;
6537 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6538 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6539 }
6540 else
6541 assert(0);
6542 }
6543
6544 /* we invert after adjustment so that we avoid the MOV to temporary,
6545 * and reuse the adjustment ADD instead */
6546 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6547 }
6548
6549 /**
6550 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6551 * TGSI uses +1 for front, -1 for back.
6552 * This function converts the TGSI value to the GL value. Simply clamping/
6553 * saturating the value to [0,1] does the job.
6554 */
6555 static void
6556 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6557 {
6558 struct ureg_program *ureg = t->ureg;
6559 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6560 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6561
6562 if (ctx->Const.NativeIntegers) {
6563 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6564 }
6565 else {
6566 /* MOV_SAT face_temp, input[face] */
6567 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6568 }
6569
6570 /* Use face_temp as face input from here on: */
6571 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6572 }
6573
6574 static void
6575 emit_compute_block_size(const struct gl_program *prog,
6576 struct ureg_program *ureg) {
6577 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6578 prog->info.cs.local_size[0]);
6579 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6580 prog->info.cs.local_size[1]);
6581 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6582 prog->info.cs.local_size[2]);
6583 }
6584
6585 struct sort_inout_decls {
6586 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6587 return mapping[a.mesa_index] < mapping[b.mesa_index];
6588 }
6589
6590 const ubyte *mapping;
6591 };
6592
6593 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6594 *
6595 * This is for the benefit of older drivers which are broken when the
6596 * declarations aren't sorted in this way.
6597 */
6598 static void
6599 sort_inout_decls_by_slot(struct inout_decl *decls,
6600 unsigned count,
6601 const ubyte mapping[])
6602 {
6603 sort_inout_decls sorter;
6604 sorter.mapping = mapping;
6605 std::sort(decls, decls + count, sorter);
6606 }
6607
6608 static enum tgsi_interpolate_mode
6609 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6610 {
6611 switch (glsl_qual) {
6612 case INTERP_MODE_NONE:
6613 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6614 return TGSI_INTERPOLATE_COLOR;
6615 return TGSI_INTERPOLATE_PERSPECTIVE;
6616 case INTERP_MODE_SMOOTH:
6617 return TGSI_INTERPOLATE_PERSPECTIVE;
6618 case INTERP_MODE_FLAT:
6619 return TGSI_INTERPOLATE_CONSTANT;
6620 case INTERP_MODE_NOPERSPECTIVE:
6621 return TGSI_INTERPOLATE_LINEAR;
6622 default:
6623 assert(0 && "unexpected interp mode in st_translate_interp()");
6624 return TGSI_INTERPOLATE_PERSPECTIVE;
6625 }
6626 }
6627
6628 /**
6629 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6630 * \param program the program to translate
6631 * \param numInputs number of input registers used
6632 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6633 * input indexes
6634 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6635 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6636 * each input
6637 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6638 * \param numOutputs number of output registers used
6639 * \param outputMapping maps Mesa fragment program outputs to TGSI
6640 * generic outputs
6641 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6642 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6643 * each output
6644 *
6645 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6646 */
6647 extern "C" enum pipe_error
6648 st_translate_program(
6649 struct gl_context *ctx,
6650 enum pipe_shader_type procType,
6651 struct ureg_program *ureg,
6652 glsl_to_tgsi_visitor *program,
6653 const struct gl_program *proginfo,
6654 GLuint numInputs,
6655 const ubyte inputMapping[],
6656 const ubyte inputSlotToAttr[],
6657 const ubyte inputSemanticName[],
6658 const ubyte inputSemanticIndex[],
6659 const ubyte interpMode[],
6660 GLuint numOutputs,
6661 const ubyte outputMapping[],
6662 const ubyte outputSemanticName[],
6663 const ubyte outputSemanticIndex[])
6664 {
6665 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6666 struct st_translate *t;
6667 unsigned i;
6668 struct gl_program_constants *frag_const =
6669 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6670 enum pipe_error ret = PIPE_OK;
6671
6672 assert(numInputs <= ARRAY_SIZE(t->inputs));
6673 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6674
6675 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6676 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6677 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6678 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6679 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6680 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6681 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6682 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6683 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6684 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6685
6686 t = CALLOC_STRUCT(st_translate);
6687 if (!t) {
6688 ret = PIPE_ERROR_OUT_OF_MEMORY;
6689 goto out;
6690 }
6691
6692 t->procType = procType;
6693 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6694 t->inputMapping = inputMapping;
6695 t->outputMapping = outputMapping;
6696 t->ureg = ureg;
6697 t->num_temp_arrays = program->next_array;
6698 if (t->num_temp_arrays)
6699 t->arrays = (struct ureg_dst*)
6700 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6701
6702 /*
6703 * Declare input attributes.
6704 */
6705 switch (procType) {
6706 case PIPE_SHADER_FRAGMENT:
6707 case PIPE_SHADER_GEOMETRY:
6708 case PIPE_SHADER_TESS_EVAL:
6709 case PIPE_SHADER_TESS_CTRL:
6710 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6711
6712 for (i = 0; i < program->num_inputs; ++i) {
6713 struct inout_decl *decl = &program->inputs[i];
6714 unsigned slot = inputMapping[decl->mesa_index];
6715 struct ureg_src src;
6716 ubyte tgsi_usage_mask = decl->usage_mask;
6717
6718 if (glsl_base_type_is_64bit(decl->base_type)) {
6719 if (tgsi_usage_mask == 1)
6720 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6721 else if (tgsi_usage_mask == 2)
6722 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6723 else
6724 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6725 }
6726
6727 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6728 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6729 if (procType == PIPE_SHADER_FRAGMENT) {
6730 assert(interpMode);
6731 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6732 (enum tgsi_interpolate_mode) interpMode[slot] :
6733 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6734
6735 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6736 }
6737
6738 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6739 (enum tgsi_semantic) inputSemanticName[slot],
6740 inputSemanticIndex[slot],
6741 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6742 decl->array_id, decl->size);
6743
6744 for (unsigned j = 0; j < decl->size; ++j) {
6745 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6746 /* The ArrayID is set up in dst_register */
6747 t->inputs[slot + j] = src;
6748 t->inputs[slot + j].ArrayID = 0;
6749 t->inputs[slot + j].Index += j;
6750 }
6751 }
6752 }
6753 break;
6754 case PIPE_SHADER_VERTEX:
6755 for (i = 0; i < numInputs; i++) {
6756 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6757 }
6758 break;
6759 case PIPE_SHADER_COMPUTE:
6760 break;
6761 default:
6762 assert(0);
6763 }
6764
6765 /*
6766 * Declare output attributes.
6767 */
6768 switch (procType) {
6769 case PIPE_SHADER_FRAGMENT:
6770 case PIPE_SHADER_COMPUTE:
6771 break;
6772 case PIPE_SHADER_GEOMETRY:
6773 case PIPE_SHADER_TESS_EVAL:
6774 case PIPE_SHADER_TESS_CTRL:
6775 case PIPE_SHADER_VERTEX:
6776 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6777
6778 for (i = 0; i < program->num_outputs; ++i) {
6779 struct inout_decl *decl = &program->outputs[i];
6780 unsigned slot = outputMapping[decl->mesa_index];
6781 struct ureg_dst dst;
6782 ubyte tgsi_usage_mask = decl->usage_mask;
6783
6784 if (glsl_base_type_is_64bit(decl->base_type)) {
6785 if (tgsi_usage_mask == 1)
6786 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6787 else if (tgsi_usage_mask == 2)
6788 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6789 else
6790 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6791 }
6792
6793 dst = ureg_DECL_output_layout(ureg,
6794 (enum tgsi_semantic) outputSemanticName[slot],
6795 outputSemanticIndex[slot],
6796 decl->gs_out_streams,
6797 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6798 dst.Invariant = decl->invariant;
6799 for (unsigned j = 0; j < decl->size; ++j) {
6800 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6801 /* The ArrayID is set up in dst_register */
6802 t->outputs[slot + j] = dst;
6803 t->outputs[slot + j].ArrayID = 0;
6804 t->outputs[slot + j].Index += j;
6805 t->outputs[slot + j].Invariant = decl->invariant;
6806 }
6807 }
6808 }
6809 break;
6810 default:
6811 assert(0);
6812 }
6813
6814 if (procType == PIPE_SHADER_FRAGMENT) {
6815 if (program->shader->Program->info.fs.early_fragment_tests ||
6816 program->shader->Program->info.fs.post_depth_coverage) {
6817 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6818
6819 if (program->shader->Program->info.fs.post_depth_coverage)
6820 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6821 }
6822
6823 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6824 /* Must do this after setting up t->inputs. */
6825 emit_wpos(st_context(ctx), t, proginfo, ureg,
6826 program->wpos_transform_const);
6827 }
6828
6829 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6830 emit_face_var(ctx, t);
6831
6832 for (i = 0; i < numOutputs; i++) {
6833 switch (outputSemanticName[i]) {
6834 case TGSI_SEMANTIC_POSITION:
6835 t->outputs[i] = ureg_DECL_output(ureg,
6836 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6837 outputSemanticIndex[i]);
6838 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6839 break;
6840 case TGSI_SEMANTIC_STENCIL:
6841 t->outputs[i] = ureg_DECL_output(ureg,
6842 TGSI_SEMANTIC_STENCIL, /* Stencil */
6843 outputSemanticIndex[i]);
6844 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6845 break;
6846 case TGSI_SEMANTIC_COLOR:
6847 t->outputs[i] = ureg_DECL_output(ureg,
6848 TGSI_SEMANTIC_COLOR,
6849 outputSemanticIndex[i]);
6850 break;
6851 case TGSI_SEMANTIC_SAMPLEMASK:
6852 t->outputs[i] = ureg_DECL_output(ureg,
6853 TGSI_SEMANTIC_SAMPLEMASK,
6854 outputSemanticIndex[i]);
6855 /* TODO: If we ever support more than 32 samples, this will have
6856 * to become an array.
6857 */
6858 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6859 break;
6860 default:
6861 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6862 ret = PIPE_ERROR_BAD_INPUT;
6863 goto out;
6864 }
6865 }
6866 }
6867 else if (procType == PIPE_SHADER_VERTEX) {
6868 for (i = 0; i < numOutputs; i++) {
6869 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6870 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6871 ureg_MOV(ureg,
6872 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6873 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6874 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6875 }
6876 }
6877 }
6878
6879 if (procType == PIPE_SHADER_COMPUTE) {
6880 emit_compute_block_size(proginfo, ureg);
6881 }
6882
6883 /* Declare address register.
6884 */
6885 if (program->num_address_regs > 0) {
6886 assert(program->num_address_regs <= 3);
6887 for (int i = 0; i < program->num_address_regs; i++)
6888 t->address[i] = ureg_DECL_address(ureg);
6889 }
6890
6891 /* Declare misc input registers
6892 */
6893 {
6894 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6895
6896 for (i = 0; sysInputs; i++) {
6897 if (sysInputs & (1ull << i)) {
6898 enum tgsi_semantic semName = _mesa_sysval_to_semantic(i);
6899
6900 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6901
6902 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6903 semName == TGSI_SEMANTIC_VERTEXID) {
6904 /* From Gallium perspective, these system values are always
6905 * integer, and require native integer support. However, if
6906 * native integer is supported on the vertex stage but not the
6907 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6908 * assumes these system values are floats. To resolve the
6909 * inconsistency, we insert a U2F.
6910 */
6911 struct st_context *st = st_context(ctx);
6912 struct pipe_screen *pscreen = st->pipe->screen;
6913 assert(procType == PIPE_SHADER_VERTEX);
6914 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6915 (void) pscreen;
6916 if (!ctx->Const.NativeIntegers) {
6917 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6918 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6919 t->systemValues[i]);
6920 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6921 }
6922 }
6923
6924 if (procType == PIPE_SHADER_FRAGMENT &&
6925 semName == TGSI_SEMANTIC_POSITION)
6926 emit_wpos(st_context(ctx), t, proginfo, ureg,
6927 program->wpos_transform_const);
6928
6929 if (procType == PIPE_SHADER_FRAGMENT &&
6930 semName == TGSI_SEMANTIC_SAMPLEPOS)
6931 emit_samplepos_adjustment(t, program->wpos_transform_const);
6932
6933 sysInputs &= ~(1ull << i);
6934 }
6935 }
6936 }
6937
6938 t->array_sizes = program->array_sizes;
6939 t->input_decls = program->inputs;
6940 t->num_input_decls = program->num_inputs;
6941 t->output_decls = program->outputs;
6942 t->num_output_decls = program->num_outputs;
6943
6944 /* Emit constants and uniforms. TGSI uses a single index space for these,
6945 * so we put all the translated regs in t->constants.
6946 */
6947 if (proginfo->Parameters) {
6948 t->constants = (struct ureg_src *)
6949 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6950 if (t->constants == NULL) {
6951 ret = PIPE_ERROR_OUT_OF_MEMORY;
6952 goto out;
6953 }
6954 t->num_constants = proginfo->Parameters->NumParameters;
6955
6956 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6957 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6958
6959 switch (proginfo->Parameters->Parameters[i].Type) {
6960 case PROGRAM_STATE_VAR:
6961 case PROGRAM_UNIFORM:
6962 t->constants[i] = ureg_DECL_constant(ureg, i);
6963 break;
6964
6965 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6966 * addressing of the const buffer.
6967 * FIXME: Be smarter and recognize param arrays:
6968 * indirect addressing is only valid within the referenced
6969 * array.
6970 */
6971 case PROGRAM_CONSTANT:
6972 if (program->indirect_addr_consts)
6973 t->constants[i] = ureg_DECL_constant(ureg, i);
6974 else
6975 t->constants[i] = emit_immediate(t,
6976 proginfo->Parameters->ParameterValues + pvo,
6977 proginfo->Parameters->Parameters[i].DataType,
6978 4);
6979 break;
6980 default:
6981 break;
6982 }
6983 }
6984 }
6985
6986 for (i = 0; i < proginfo->info.num_ubos; i++) {
6987 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6988 unsigned num_const_vecs = (size + 15) / 16;
6989 unsigned first, last;
6990 assert(num_const_vecs > 0);
6991 first = 0;
6992 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6993 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6994 }
6995
6996 /* Emit immediate values.
6997 */
6998 t->immediates = (struct ureg_src *)
6999 calloc(program->num_immediates, sizeof(struct ureg_src));
7000 if (t->immediates == NULL) {
7001 ret = PIPE_ERROR_OUT_OF_MEMORY;
7002 goto out;
7003 }
7004 t->num_immediates = program->num_immediates;
7005
7006 i = 0;
7007 foreach_in_list(immediate_storage, imm, &program->immediates) {
7008 assert(i < program->num_immediates);
7009 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
7010 }
7011 assert(i == program->num_immediates);
7012
7013 /* texture samplers */
7014 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
7015 if (program->samplers_used & (1u << i)) {
7016 enum tgsi_return_type type =
7017 st_translate_texture_type(program->sampler_types[i]);
7018
7019 t->samplers[i] = ureg_DECL_sampler(ureg, i);
7020
7021 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
7022 type, type, type, type);
7023 }
7024 }
7025
7026 /* Declare atomic and shader storage buffers. */
7027 {
7028 struct gl_program *prog = program->prog;
7029
7030 if (!st_context(ctx)->has_hw_atomics) {
7031 for (i = 0; i < prog->info.num_abos; i++) {
7032 unsigned index = prog->sh.AtomicBuffers[i]->Binding;
7033 assert(index < frag_const->MaxAtomicBuffers);
7034 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
7035 }
7036 } else {
7037 for (i = 0; i < program->num_atomics; i++) {
7038 struct hwatomic_decl *ainfo = &program->atomic_info[i];
7039 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
7040 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
7041 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
7042 ainfo->array_id);
7043 }
7044 }
7045
7046 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
7047 for (i = 0; i < prog->info.num_ssbos; i++) {
7048 unsigned index = i;
7049 if (!st_context(ctx)->has_hw_atomics)
7050 index += frag_const->MaxAtomicBuffers;
7051
7052 t->buffers[index] = ureg_DECL_buffer(ureg, index, false);
7053 }
7054 }
7055
7056 if (program->use_shared_memory)
7057 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
7058
7059 for (i = 0; i < program->shader->Program->info.num_images; i++) {
7060 if (program->images_used & (1 << i)) {
7061 t->images[i] = ureg_DECL_image(ureg, i,
7062 program->image_targets[i],
7063 program->image_formats[i],
7064 program->image_wr[i],
7065 false);
7066 }
7067 }
7068
7069 /* Emit each instruction in turn:
7070 */
7071 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
7072 compile_tgsi_instruction(t, inst);
7073
7074 /* Set the next shader stage hint for VS and TES. */
7075 switch (procType) {
7076 case PIPE_SHADER_VERTEX:
7077 case PIPE_SHADER_TESS_EVAL:
7078 if (program->shader_program->SeparateShader)
7079 break;
7080
7081 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
7082 if (program->shader_program->_LinkedShaders[i]) {
7083 ureg_set_next_shader_processor(
7084 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
7085 break;
7086 }
7087 }
7088 break;
7089 default:
7090 ; /* nothing - silence compiler warning */
7091 }
7092
7093 out:
7094 if (t) {
7095 free(t->arrays);
7096 free(t->temps);
7097 free(t->constants);
7098 t->num_constants = 0;
7099 free(t->immediates);
7100 t->num_immediates = 0;
7101 FREE(t);
7102 }
7103
7104 return ret;
7105 }
7106 /* ----------------------------- End TGSI code ------------------------------ */
7107
7108
7109 /**
7110 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7111 * generating Mesa IR.
7112 */
7113 static struct gl_program *
7114 get_mesa_program_tgsi(struct gl_context *ctx,
7115 struct gl_shader_program *shader_program,
7116 struct gl_linked_shader *shader)
7117 {
7118 glsl_to_tgsi_visitor* v;
7119 struct gl_program *prog;
7120 struct gl_shader_compiler_options *options =
7121 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7122 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7123 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7124 unsigned skip_merge_registers;
7125
7126 validate_ir_tree(shader->ir);
7127
7128 prog = shader->Program;
7129
7130 prog->Parameters = _mesa_new_parameter_list();
7131 v = new glsl_to_tgsi_visitor();
7132 v->ctx = ctx;
7133 v->prog = prog;
7134 v->shader_program = shader_program;
7135 v->shader = shader;
7136 v->options = options;
7137 v->native_integers = ctx->Const.NativeIntegers;
7138
7139 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7140 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7141 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7142 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7143 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7144 PIPE_CAP_TGSI_TEX_TXF_LZ);
7145 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7146
7147 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7148 _mesa_key_pointer_equal);
7149 skip_merge_registers =
7150 pscreen->get_shader_param(pscreen, ptarget,
7151 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7152
7153 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7154 prog->Parameters);
7155
7156 /* Remove reads from output registers. */
7157 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7158 lower_output_reads(shader->Stage, shader->ir);
7159
7160 /* Emit intermediate IR for main(). */
7161 visit_exec_list(shader->ir, v);
7162
7163 #if 0
7164 /* Print out some information (for debugging purposes) used by the
7165 * optimization passes. */
7166 {
7167 int i;
7168 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7169 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7170 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7171 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7172
7173 for (i = 0; i < v->next_temp; i++) {
7174 first_writes[i] = -1;
7175 first_reads[i] = -1;
7176 last_writes[i] = -1;
7177 last_reads[i] = -1;
7178 }
7179 v->get_first_temp_read(first_reads);
7180 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7181 v->get_last_temp_write(last_writes);
7182 for (i = 0; i < v->next_temp; i++)
7183 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7184 first_writes[i],
7185 last_reads[i],
7186 last_writes[i]);
7187 ralloc_free(first_writes);
7188 ralloc_free(first_reads);
7189 ralloc_free(last_writes);
7190 ralloc_free(last_reads);
7191 }
7192 #endif
7193
7194 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7195 v->simplify_cmp();
7196 v->copy_propagate();
7197
7198 while (v->eliminate_dead_code());
7199
7200 v->merge_two_dsts();
7201
7202 if (!skip_merge_registers) {
7203 v->split_arrays();
7204 v->copy_propagate();
7205 while (v->eliminate_dead_code());
7206
7207 v->merge_registers();
7208 v->copy_propagate();
7209 while (v->eliminate_dead_code());
7210 }
7211
7212 v->renumber_registers();
7213
7214 /* Write the END instruction. */
7215 v->emit_asm(NULL, TGSI_OPCODE_END);
7216
7217 if (ctx->_Shader->Flags & GLSL_DUMP) {
7218 _mesa_log("\n");
7219 _mesa_log("GLSL IR for linked %s program %d:\n",
7220 _mesa_shader_stage_to_string(shader->Stage),
7221 shader_program->Name);
7222 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7223 _mesa_log("\n\n");
7224 }
7225
7226 do_set_program_inouts(shader->ir, prog, shader->Stage);
7227
7228 _mesa_copy_linked_program_data(shader_program, shader);
7229
7230 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS)) {
7231 mark_array_io(v->inputs, v->num_inputs,
7232 &prog->info.inputs_read,
7233 prog->DualSlotInputs,
7234 &prog->info.patch_inputs_read);
7235
7236 mark_array_io(v->outputs, v->num_outputs,
7237 &prog->info.outputs_written, 0ULL,
7238 &prog->info.patch_outputs_written);
7239 } else {
7240 shrink_array_declarations(v->inputs, v->num_inputs,
7241 &prog->info.inputs_read,
7242 prog->DualSlotInputs,
7243 &prog->info.patch_inputs_read);
7244 shrink_array_declarations(v->outputs, v->num_outputs,
7245 &prog->info.outputs_written, 0ULL,
7246 &prog->info.patch_outputs_written);
7247 }
7248
7249 count_resources(v, prog);
7250
7251 /* The GLSL IR won't be needed anymore. */
7252 ralloc_free(shader->ir);
7253 shader->ir = NULL;
7254
7255 /* This must be done before the uniform storage is associated. */
7256 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7257 (prog->info.inputs_read & VARYING_BIT_POS ||
7258 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
7259 prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
7260 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7261 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7262 };
7263
7264 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7265 wposTransformState);
7266 }
7267
7268 /* Avoid reallocation of the program parameter list, because the uniform
7269 * storage is only associated with the original parameter list.
7270 * This should be enough for Bitmap and DrawPixels constants.
7271 */
7272 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7273
7274 /* This has to be done last. Any operation the can cause
7275 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7276 * program constant) has to happen before creating this linkage.
7277 */
7278 _mesa_associate_uniform_storage(ctx, shader_program, prog);
7279 if (!shader_program->data->LinkStatus) {
7280 free_glsl_to_tgsi_visitor(v);
7281 _mesa_reference_program(ctx, &shader->Program, NULL);
7282 return NULL;
7283 }
7284
7285 struct st_vertex_program *stvp;
7286 struct st_fragment_program *stfp;
7287 struct st_common_program *stp;
7288 struct st_compute_program *stcp;
7289
7290 switch (shader->Stage) {
7291 case MESA_SHADER_VERTEX:
7292 stvp = (struct st_vertex_program *)prog;
7293 stvp->glsl_to_tgsi = v;
7294 break;
7295 case MESA_SHADER_FRAGMENT:
7296 stfp = (struct st_fragment_program *)prog;
7297 stfp->glsl_to_tgsi = v;
7298 break;
7299 case MESA_SHADER_TESS_CTRL:
7300 case MESA_SHADER_TESS_EVAL:
7301 case MESA_SHADER_GEOMETRY:
7302 stp = st_common_program(prog);
7303 stp->glsl_to_tgsi = v;
7304 break;
7305 case MESA_SHADER_COMPUTE:
7306 stcp = (struct st_compute_program *)prog;
7307 stcp->glsl_to_tgsi = v;
7308 break;
7309 default:
7310 assert(!"should not be reached");
7311 return NULL;
7312 }
7313
7314 PRINT_STATS(v->print_stats());
7315
7316 return prog;
7317 }
7318
7319 /* See if there are unsupported control flow statements. */
7320 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7321 private:
7322 const struct gl_shader_compiler_options *options;
7323 public:
7324 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7325 : options(options),
7326 unsupported(false)
7327 {
7328 }
7329
7330 virtual ir_visitor_status visit_enter(ir_function *ir)
7331 {
7332 /* Other functions are skipped (same as glsl_to_tgsi). */
7333 if (strcmp(ir->name, "main") == 0)
7334 return visit_continue;
7335
7336 return visit_continue_with_parent;
7337 }
7338
7339 virtual ir_visitor_status visit_enter(ir_call *ir)
7340 {
7341 if (!ir->callee->is_intrinsic()) {
7342 unsupported = true; /* it's a function call */
7343 return visit_stop;
7344 }
7345 return visit_continue;
7346 }
7347
7348 virtual ir_visitor_status visit_enter(ir_return *ir)
7349 {
7350 if (options->EmitNoMainReturn) {
7351 unsupported = true;
7352 return visit_stop;
7353 }
7354 return visit_continue;
7355 }
7356
7357 bool unsupported;
7358 };
7359
7360 static bool
7361 has_unsupported_control_flow(exec_list *ir,
7362 const struct gl_shader_compiler_options *options)
7363 {
7364 ir_control_flow_info_visitor visitor(options);
7365 visit_list_elements(&visitor, ir);
7366 return visitor.unsupported;
7367 }
7368
7369 /**
7370 * Link a shader.
7371 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7372 * with code lowering and other optimizations.
7373 */
7374 GLboolean
7375 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7376 {
7377 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7378
7379 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7380 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7381 if (shader == NULL)
7382 continue;
7383
7384 exec_list *ir = shader->ir;
7385 gl_shader_stage stage = shader->Stage;
7386 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7387 const struct gl_shader_compiler_options *options =
7388 &ctx->Const.ShaderCompilerOptions[stage];
7389
7390 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7391 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7392 if (ctx->Const.GLSLOptimizeConservatively) {
7393 /* Do it once and repeat only if there's unsupported control flow. */
7394 do {
7395 do_common_optimization(ir, true, true, options,
7396 ctx->Const.NativeIntegers);
7397 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7398 options->MaxIfDepth, if_threshold);
7399 } while (has_unsupported_control_flow(ir, options));
7400 } else {
7401 /* Repeat it until it stops making changes. */
7402 bool progress;
7403 do {
7404 progress = do_common_optimization(ir, true, true, options,
7405 ctx->Const.NativeIntegers);
7406 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7407 options->MaxIfDepth, if_threshold);
7408 } while (progress);
7409 }
7410
7411 /* Do this again to lower ir_binop_vector_extract introduced
7412 * by optimization passes.
7413 */
7414 do_vec_index_to_cond_assign(ir);
7415
7416 validate_ir_tree(ir);
7417
7418 struct gl_program *linked_prog =
7419 get_mesa_program_tgsi(ctx, prog, shader);
7420 st_set_prog_affected_state_flags(linked_prog);
7421
7422 if (linked_prog) {
7423 if (!ctx->Driver.ProgramStringNotify(ctx,
7424 _mesa_shader_stage_to_program(i),
7425 linked_prog)) {
7426 _mesa_reference_program(ctx, &shader->Program, NULL);
7427 return GL_FALSE;
7428 }
7429 }
7430 }
7431
7432 return GL_TRUE;
7433 }
7434
7435 extern "C" {
7436
7437 void
7438 st_translate_stream_output_info(struct gl_transform_feedback_info *info,
7439 const ubyte outputMapping[],
7440 struct pipe_stream_output_info *so)
7441 {
7442 unsigned i;
7443
7444 if (!info) {
7445 so->num_outputs = 0;
7446 return;
7447 }
7448
7449 for (i = 0; i < info->NumOutputs; i++) {
7450 so->output[i].register_index =
7451 outputMapping[info->Outputs[i].OutputRegister];
7452 so->output[i].start_component = info->Outputs[i].ComponentOffset;
7453 so->output[i].num_components = info->Outputs[i].NumComponents;
7454 so->output[i].output_buffer = info->Outputs[i].OutputBuffer;
7455 so->output[i].dst_offset = info->Outputs[i].DstOffset;
7456 so->output[i].stream = info->Outputs[i].StreamId;
7457 }
7458
7459 for (i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
7460 so->stride[i] = info->Buffers[i].Stride;
7461 }
7462 so->num_outputs = info->NumOutputs;
7463 }
7464
7465 } /* extern "C" */