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st: add nir shader disk cache support
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
56 #include "st_nir.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
59
60 #include "util/hash_table.h"
61 #include <algorithm>
62
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
66
67 #define MAX_GLSL_TEXTURE_OFFSET 4
68
69 static unsigned is_precise(const ir_variable *ir)
70 {
71 if (!ir)
72 return 0;
73 return ir->data.precise || ir->data.invariant;
74 }
75
76 class variable_storage {
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
78
79 public:
80 variable_storage(ir_variable *var, gl_register_file file, int index,
81 unsigned array_id = 0)
82 : file(file), index(index), component(0), var(var), array_id(array_id)
83 {
84 assert(file != PROGRAM_ARRAY || array_id != 0);
85 }
86
87 gl_register_file file;
88 int index;
89
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
93 */
94 int component;
95 ir_variable *var; /* variable that maps to this, if any */
96 unsigned array_id;
97 };
98
99 class immediate_storage : public exec_node {
100 public:
101 immediate_storage(gl_constant_value *values, int size32, GLenum type)
102 {
103 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
104 this->size32 = size32;
105 this->type = type;
106 }
107
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values[4];
110 int size32; /**< Number of 32-bit components (1-4) */
111 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
112 };
113
114 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
115 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
116
117 struct inout_decl {
118 unsigned mesa_index;
119 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
120 unsigned size;
121 unsigned interp_loc;
122 unsigned gs_out_streams;
123 enum glsl_interp_mode interp;
124 enum glsl_base_type base_type;
125 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
126 };
127
128 static struct inout_decl *
129 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
130 {
131 assert(array_id != 0);
132
133 for (unsigned i = 0; i < count; i++) {
134 struct inout_decl *decl = &decls[i];
135
136 if (array_id == decl->array_id) {
137 return decl;
138 }
139 }
140
141 return NULL;
142 }
143
144 static enum glsl_base_type
145 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
146 {
147 if (!array_id)
148 return GLSL_TYPE_ERROR;
149 struct inout_decl *decl = find_inout_array(decls, count, array_id);
150 if (decl)
151 return decl->base_type;
152 return GLSL_TYPE_ERROR;
153 }
154
155 struct hwatomic_decl {
156 unsigned location;
157 unsigned binding;
158 unsigned size;
159 unsigned array_id;
160 };
161
162 struct glsl_to_tgsi_visitor : public ir_visitor {
163 public:
164 glsl_to_tgsi_visitor();
165 ~glsl_to_tgsi_visitor();
166
167 struct gl_context *ctx;
168 struct gl_program *prog;
169 struct gl_shader_program *shader_program;
170 struct gl_linked_shader *shader;
171 struct gl_shader_compiler_options *options;
172
173 int next_temp;
174
175 unsigned *array_sizes;
176 unsigned max_num_arrays;
177 unsigned next_array;
178
179 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
180 unsigned num_inputs;
181 unsigned num_input_arrays;
182 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
183 unsigned num_outputs;
184 unsigned num_output_arrays;
185
186 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
187 unsigned num_atomics;
188 unsigned num_atomic_arrays;
189 int num_address_regs;
190 uint32_t samplers_used;
191 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
192 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
193 int images_used;
194 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
195 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
196 bool indirect_addr_consts;
197 int wpos_transform_const;
198
199 bool native_integers;
200 bool have_sqrt;
201 bool have_fma;
202 bool use_shared_memory;
203 bool has_tex_txf_lz;
204 bool precise;
205 bool need_uarl;
206
207 variable_storage *find_variable_storage(ir_variable *var);
208
209 int add_constant(gl_register_file file, gl_constant_value values[8],
210 int size, GLenum datatype, uint16_t *swizzle_out);
211
212 st_src_reg get_temp(const glsl_type *type);
213 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
214
215 st_src_reg st_src_reg_for_double(double val);
216 st_src_reg st_src_reg_for_float(float val);
217 st_src_reg st_src_reg_for_int(int val);
218 st_src_reg st_src_reg_for_int64(int64_t val);
219 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
220
221 /**
222 * \name Visit methods
223 *
224 * As typical for the visitor pattern, there must be one \c visit method for
225 * each concrete subclass of \c ir_instruction. Virtual base classes within
226 * the hierarchy should not have \c visit methods.
227 */
228 /*@{*/
229 virtual void visit(ir_variable *);
230 virtual void visit(ir_loop *);
231 virtual void visit(ir_loop_jump *);
232 virtual void visit(ir_function_signature *);
233 virtual void visit(ir_function *);
234 virtual void visit(ir_expression *);
235 virtual void visit(ir_swizzle *);
236 virtual void visit(ir_dereference_variable *);
237 virtual void visit(ir_dereference_array *);
238 virtual void visit(ir_dereference_record *);
239 virtual void visit(ir_assignment *);
240 virtual void visit(ir_constant *);
241 virtual void visit(ir_call *);
242 virtual void visit(ir_return *);
243 virtual void visit(ir_discard *);
244 virtual void visit(ir_texture *);
245 virtual void visit(ir_if *);
246 virtual void visit(ir_emit_vertex *);
247 virtual void visit(ir_end_primitive *);
248 virtual void visit(ir_barrier *);
249 /*@}*/
250
251 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
252
253 void visit_atomic_counter_intrinsic(ir_call *);
254 void visit_ssbo_intrinsic(ir_call *);
255 void visit_membar_intrinsic(ir_call *);
256 void visit_shared_intrinsic(ir_call *);
257 void visit_image_intrinsic(ir_call *);
258 void visit_generic_intrinsic(ir_call *, unsigned op);
259
260 st_src_reg result;
261
262 /** List of variable_storage */
263 struct hash_table *variables;
264
265 /** List of immediate_storage */
266 exec_list immediates;
267 unsigned num_immediates;
268
269 /** List of glsl_to_tgsi_instruction */
270 exec_list instructions;
271
272 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
273 st_dst_reg dst = undef_dst,
274 st_src_reg src0 = undef_src,
275 st_src_reg src1 = undef_src,
276 st_src_reg src2 = undef_src,
277 st_src_reg src3 = undef_src);
278
279 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
280 st_dst_reg dst, st_dst_reg dst1,
281 st_src_reg src0 = undef_src,
282 st_src_reg src1 = undef_src,
283 st_src_reg src2 = undef_src,
284 st_src_reg src3 = undef_src);
285
286 unsigned get_opcode(unsigned op,
287 st_dst_reg dst,
288 st_src_reg src0, st_src_reg src1);
289
290 /**
291 * Emit the correct dot-product instruction for the type of arguments
292 */
293 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
294 st_dst_reg dst,
295 st_src_reg src0,
296 st_src_reg src1,
297 unsigned elements);
298
299 void emit_scalar(ir_instruction *ir, unsigned op,
300 st_dst_reg dst, st_src_reg src0);
301
302 void emit_scalar(ir_instruction *ir, unsigned op,
303 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
304
305 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
306
307 void get_deref_offsets(ir_dereference *ir,
308 unsigned *array_size,
309 unsigned *base,
310 uint16_t *index,
311 st_src_reg *reladdr,
312 bool opaque);
313 void calc_deref_offsets(ir_dereference *tail,
314 unsigned *array_elements,
315 uint16_t *index,
316 st_src_reg *indirect,
317 unsigned *location);
318 st_src_reg canonicalize_gather_offset(st_src_reg offset);
319
320 bool try_emit_mad(ir_expression *ir,
321 int mul_operand);
322 bool try_emit_mad_for_and_not(ir_expression *ir,
323 int mul_operand);
324
325 void emit_swz(ir_expression *ir);
326
327 bool process_move_condition(ir_rvalue *ir);
328
329 void simplify_cmp(void);
330
331 void rename_temp_registers(struct rename_reg_pair *renames);
332 void get_first_temp_read(int *first_reads);
333 void get_first_temp_write(int *first_writes);
334 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
335 void get_last_temp_write(int *last_writes);
336
337 void copy_propagate(void);
338 int eliminate_dead_code(void);
339
340 void merge_two_dsts(void);
341 void merge_registers(void);
342 void renumber_registers(void);
343
344 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
345 st_dst_reg *l, st_src_reg *r,
346 st_src_reg *cond, bool cond_swap);
347
348 void *mem_ctx;
349 };
350
351 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
352 GLSL_TYPE_FLOAT, 0);
353 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
354 GLSL_TYPE_FLOAT, 1);
355 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
356 GLSL_TYPE_FLOAT, 2);
357
358 static void
359 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
360 PRINTFLIKE(2, 3);
361
362 static void
363 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
364 {
365 va_list args;
366 va_start(args, fmt);
367 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
368 va_end(args);
369
370 prog->data->LinkStatus = LINKING_FAILURE;
371 }
372
373 int
374 swizzle_for_size(int size)
375 {
376 static const int size_swizzles[4] = {
377 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
378 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
379 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
380 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
381 };
382
383 assert((size >= 1) && (size <= 4));
384 return size_swizzles[size - 1];
385 }
386
387
388 glsl_to_tgsi_instruction *
389 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
390 st_dst_reg dst, st_dst_reg dst1,
391 st_src_reg src0, st_src_reg src1,
392 st_src_reg src2, st_src_reg src3)
393 {
394 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
395 int num_reladdr = 0, i, j;
396 bool dst_is_64bit[2];
397
398 op = get_opcode(op, dst, src0, src1);
399
400 /* If we have to do relative addressing, we want to load the ARL
401 * reg directly for one of the regs, and preload the other reladdr
402 * sources into temps.
403 */
404 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
405 assert(!dst1.reladdr); /* should be lowered in earlier passes */
406 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
407 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
408 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
409 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
410
411 reladdr_to_temp(ir, &src3, &num_reladdr);
412 reladdr_to_temp(ir, &src2, &num_reladdr);
413 reladdr_to_temp(ir, &src1, &num_reladdr);
414 reladdr_to_temp(ir, &src0, &num_reladdr);
415
416 if (dst.reladdr || dst.reladdr2) {
417 if (dst.reladdr)
418 emit_arl(ir, address_reg, *dst.reladdr);
419 if (dst.reladdr2)
420 emit_arl(ir, address_reg2, *dst.reladdr2);
421 num_reladdr--;
422 }
423
424 assert(num_reladdr == 0);
425
426 /* inst->op has only 8 bits. */
427 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
428
429 inst->op = op;
430 inst->precise = this->precise;
431 inst->info = tgsi_get_opcode_info(op);
432 inst->dst[0] = dst;
433 inst->dst[1] = dst1;
434 inst->src[0] = src0;
435 inst->src[1] = src1;
436 inst->src[2] = src2;
437 inst->src[3] = src3;
438 inst->is_64bit_expanded = false;
439 inst->ir = ir;
440 inst->dead_mask = 0;
441 inst->tex_offsets = NULL;
442 inst->tex_offset_num_offset = 0;
443 inst->saturate = 0;
444 inst->tex_shadow = 0;
445 /* default to float, for paths where this is not initialized
446 * (since 0==UINT which is likely wrong):
447 */
448 inst->tex_type = GLSL_TYPE_FLOAT;
449
450 /* Update indirect addressing status used by TGSI */
451 if (dst.reladdr || dst.reladdr2) {
452 switch (dst.file) {
453 case PROGRAM_STATE_VAR:
454 case PROGRAM_CONSTANT:
455 case PROGRAM_UNIFORM:
456 this->indirect_addr_consts = true;
457 break;
458 case PROGRAM_IMMEDIATE:
459 assert(!"immediates should not have indirect addressing");
460 break;
461 default:
462 break;
463 }
464 }
465 else {
466 for (i = 0; i < 4; i++) {
467 if (inst->src[i].reladdr) {
468 switch (inst->src[i].file) {
469 case PROGRAM_STATE_VAR:
470 case PROGRAM_CONSTANT:
471 case PROGRAM_UNIFORM:
472 this->indirect_addr_consts = true;
473 break;
474 case PROGRAM_IMMEDIATE:
475 assert(!"immediates should not have indirect addressing");
476 break;
477 default:
478 break;
479 }
480 }
481 }
482 }
483
484 /*
485 * This section contains the double processing.
486 * GLSL just represents doubles as single channel values,
487 * however most HW and TGSI represent doubles as pairs of register channels.
488 *
489 * so we have to fixup destination writemask/index and src swizzle/indexes.
490 * dest writemasks need to translate from single channel write mask
491 * to a dual-channel writemask, but also need to modify the index,
492 * if we are touching the Z,W fields in the pre-translated writemask.
493 *
494 * src channels have similiar index modifications along with swizzle
495 * changes to we pick the XY, ZW pairs from the correct index.
496 *
497 * GLSL [0].x -> TGSI [0].xy
498 * GLSL [0].y -> TGSI [0].zw
499 * GLSL [0].z -> TGSI [1].xy
500 * GLSL [0].w -> TGSI [1].zw
501 */
502 for (j = 0; j < 2; j++) {
503 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
504 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
505 inst->dst[j].type == GLSL_TYPE_ARRAY) {
506 enum glsl_base_type type = find_array_type(this->outputs,
507 this->num_outputs,
508 inst->dst[j].array_id);
509 if (glsl_base_type_is_64bit(type))
510 dst_is_64bit[j] = true;
511 }
512 }
513
514 if (dst_is_64bit[0] || dst_is_64bit[1] ||
515 glsl_base_type_is_64bit(inst->src[0].type)) {
516 glsl_to_tgsi_instruction *dinst = NULL;
517 int initial_src_swz[4], initial_src_idx[4];
518 int initial_dst_idx[2], initial_dst_writemask[2];
519 /* select the writemask for dst0 or dst1 */
520 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
521 ? inst->dst[0].writemask : inst->dst[1].writemask;
522
523 /* copy out the writemask, index and swizzles for all src/dsts. */
524 for (j = 0; j < 2; j++) {
525 initial_dst_writemask[j] = inst->dst[j].writemask;
526 initial_dst_idx[j] = inst->dst[j].index;
527 }
528
529 for (j = 0; j < 4; j++) {
530 initial_src_swz[j] = inst->src[j].swizzle;
531 initial_src_idx[j] = inst->src[j].index;
532 }
533
534 /*
535 * scan all the components in the dst writemask
536 * generate an instruction for each of them if required.
537 */
538 st_src_reg addr;
539 while (writemask) {
540
541 int i = u_bit_scan(&writemask);
542
543 /* before emitting the instruction, see if we have to adjust
544 * load / store address */
545 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
546 inst->op == TGSI_OPCODE_STORE) &&
547 addr.file == PROGRAM_UNDEFINED) {
548 /* We have to advance the buffer address by 16 */
549 addr = get_temp(glsl_type::uint_type);
550 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
551 inst->src[0], st_src_reg_for_int(16));
552 }
553
554 /* first time use previous instruction */
555 if (dinst == NULL) {
556 dinst = inst;
557 } else {
558 /* create a new instructions for subsequent attempts */
559 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
560 *dinst = *inst;
561 dinst->next = NULL;
562 dinst->prev = NULL;
563 }
564 this->instructions.push_tail(dinst);
565 dinst->is_64bit_expanded = true;
566
567 /* modify the destination if we are splitting */
568 for (j = 0; j < 2; j++) {
569 if (dst_is_64bit[j]) {
570 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
571 dinst->dst[j].index = initial_dst_idx[j];
572 if (i > 1) {
573 if (dinst->op == TGSI_OPCODE_LOAD ||
574 dinst->op == TGSI_OPCODE_STORE)
575 dinst->src[0] = addr;
576 if (dinst->op != TGSI_OPCODE_STORE)
577 dinst->dst[j].index++;
578 }
579 } else {
580 /* if we aren't writing to a double, just get the bit of the
581 * initial writemask for this channel
582 */
583 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
584 }
585 }
586
587 /* modify the src registers */
588 for (j = 0; j < 4; j++) {
589 int swz = GET_SWZ(initial_src_swz[j], i);
590
591 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
592 dinst->src[j].index = initial_src_idx[j];
593 if (swz > 1) {
594 dinst->src[j].double_reg2 = true;
595 dinst->src[j].index++;
596 }
597
598 if (swz & 1)
599 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
600 SWIZZLE_Z, SWIZZLE_W);
601 else
602 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
603 SWIZZLE_X, SWIZZLE_Y);
604
605 } else {
606 /* some opcodes are special case in what they use as sources
607 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
608 * integer src1
609 */
610 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
611 op == TGSI_OPCODE_I2D ||
612 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
613 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
614 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
615 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
616 }
617 }
618 }
619 }
620 inst = dinst;
621 } else {
622 this->instructions.push_tail(inst);
623 }
624
625
626 return inst;
627 }
628
629 glsl_to_tgsi_instruction *
630 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
631 st_dst_reg dst,
632 st_src_reg src0, st_src_reg src1,
633 st_src_reg src2, st_src_reg src3)
634 {
635 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
636 }
637
638 /**
639 * Determines whether to use an integer, unsigned integer, or float opcode
640 * based on the operands and input opcode, then emits the result.
641 */
642 unsigned
643 glsl_to_tgsi_visitor::get_opcode(unsigned op,
644 st_dst_reg dst,
645 st_src_reg src0, st_src_reg src1)
646 {
647 enum glsl_base_type type = GLSL_TYPE_FLOAT;
648
649 if (op == TGSI_OPCODE_MOV)
650 return op;
651
652 assert(src0.type != GLSL_TYPE_ARRAY);
653 assert(src0.type != GLSL_TYPE_STRUCT);
654 assert(src1.type != GLSL_TYPE_ARRAY);
655 assert(src1.type != GLSL_TYPE_STRUCT);
656
657 if (is_resource_instruction(op))
658 type = src1.type;
659 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
660 type = GLSL_TYPE_INT64;
661 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
662 type = GLSL_TYPE_UINT64;
663 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
664 type = GLSL_TYPE_DOUBLE;
665 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
666 type = GLSL_TYPE_FLOAT;
667 else if (native_integers)
668 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
669
670 #define case7(c, f, i, u, d, i64, ui64) \
671 case TGSI_OPCODE_##c: \
672 if (type == GLSL_TYPE_UINT64) \
673 op = TGSI_OPCODE_##ui64; \
674 else if (type == GLSL_TYPE_INT64) \
675 op = TGSI_OPCODE_##i64; \
676 else if (type == GLSL_TYPE_DOUBLE) \
677 op = TGSI_OPCODE_##d; \
678 else if (type == GLSL_TYPE_INT) \
679 op = TGSI_OPCODE_##i; \
680 else if (type == GLSL_TYPE_UINT) \
681 op = TGSI_OPCODE_##u; \
682 else \
683 op = TGSI_OPCODE_##f; \
684 break;
685
686 #define casecomp(c, f, i, u, d, i64, ui64) \
687 case TGSI_OPCODE_##c: \
688 if (type == GLSL_TYPE_INT64) \
689 op = TGSI_OPCODE_##i64; \
690 else if (type == GLSL_TYPE_UINT64) \
691 op = TGSI_OPCODE_##ui64; \
692 else if (type == GLSL_TYPE_DOUBLE) \
693 op = TGSI_OPCODE_##d; \
694 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
695 op = TGSI_OPCODE_##i; \
696 else if (type == GLSL_TYPE_UINT) \
697 op = TGSI_OPCODE_##u; \
698 else if (native_integers) \
699 op = TGSI_OPCODE_##f; \
700 else \
701 op = TGSI_OPCODE_##c; \
702 break;
703
704 switch (op) {
705 /* Some instructions are initially selected without considering the type.
706 * This fixes the type:
707 *
708 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
709 */
710 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
711 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
712 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
713 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
714 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
715 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
716 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
717 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
718 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
719 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
720 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
721 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
722 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
723 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
724 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
725 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
726
727 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
728 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
729 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
730 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
731 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
732 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
733 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
734 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
735
736 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
737 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
738 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
739 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
740
741 default:
742 break;
743 }
744
745 assert(op != TGSI_OPCODE_LAST);
746 return op;
747 }
748
749 glsl_to_tgsi_instruction *
750 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
751 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
752 unsigned elements)
753 {
754 static const unsigned dot_opcodes[] = {
755 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
756 };
757
758 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
759 }
760
761 /**
762 * Emits TGSI scalar opcodes to produce unique answers across channels.
763 *
764 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
765 * channel determines the result across all channels. So to do a vec4
766 * of this operation, we want to emit a scalar per source channel used
767 * to produce dest channels.
768 */
769 void
770 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, unsigned op,
771 st_dst_reg dst,
772 st_src_reg orig_src0, st_src_reg orig_src1)
773 {
774 int i, j;
775 int done_mask = ~dst.writemask;
776
777 /* TGSI RCP is a scalar operation splatting results to all channels,
778 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
779 * dst channels.
780 */
781 for (i = 0; i < 4; i++) {
782 GLuint this_mask = (1 << i);
783 st_src_reg src0 = orig_src0;
784 st_src_reg src1 = orig_src1;
785
786 if (done_mask & this_mask)
787 continue;
788
789 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
790 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
791 for (j = i + 1; j < 4; j++) {
792 /* If there is another enabled component in the destination that is
793 * derived from the same inputs, generate its value on this pass as
794 * well.
795 */
796 if (!(done_mask & (1 << j)) &&
797 GET_SWZ(src0.swizzle, j) == src0_swiz &&
798 GET_SWZ(src1.swizzle, j) == src1_swiz) {
799 this_mask |= (1 << j);
800 }
801 }
802 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
803 src0_swiz, src0_swiz);
804 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
805 src1_swiz, src1_swiz);
806
807 dst.writemask = this_mask;
808 emit_asm(ir, op, dst, src0, src1);
809 done_mask |= this_mask;
810 }
811 }
812
813 void
814 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, unsigned op,
815 st_dst_reg dst, st_src_reg src0)
816 {
817 st_src_reg undef = undef_src;
818
819 undef.swizzle = SWIZZLE_XXXX;
820
821 emit_scalar(ir, op, dst, src0, undef);
822 }
823
824 void
825 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
826 st_dst_reg dst, st_src_reg src0)
827 {
828 int op = TGSI_OPCODE_ARL;
829
830 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
831 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
832 return;
833
834 op = TGSI_OPCODE_UARL;
835 }
836
837 assert(dst.file == PROGRAM_ADDRESS);
838 if (dst.index >= this->num_address_regs)
839 this->num_address_regs = dst.index + 1;
840
841 emit_asm(NULL, op, dst, src0);
842 }
843
844 int
845 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
846 gl_constant_value values[8], int size,
847 GLenum datatype,
848 uint16_t *swizzle_out)
849 {
850 if (file == PROGRAM_CONSTANT) {
851 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
852 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
853 values, size, datatype,
854 &swizzle);
855 if (swizzle_out)
856 *swizzle_out = swizzle;
857 return result;
858 }
859
860 assert(file == PROGRAM_IMMEDIATE);
861
862 int index = 0;
863 immediate_storage *entry;
864 int size32 = size * ((datatype == GL_DOUBLE ||
865 datatype == GL_INT64_ARB ||
866 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
867 int i;
868
869 /* Search immediate storage to see if we already have an identical
870 * immediate that we can use instead of adding a duplicate entry.
871 */
872 foreach_in_list(immediate_storage, entry, &this->immediates) {
873 immediate_storage *tmp = entry;
874
875 for (i = 0; i * 4 < size32; i++) {
876 int slot_size = MIN2(size32 - (i * 4), 4);
877 if (tmp->type != datatype || tmp->size32 != slot_size)
878 break;
879 if (memcmp(tmp->values, &values[i * 4],
880 slot_size * sizeof(gl_constant_value)))
881 break;
882
883 /* Everything matches, keep going until the full size is matched */
884 tmp = (immediate_storage *)tmp->next;
885 }
886
887 /* The full value matched */
888 if (i * 4 >= size32)
889 return index;
890
891 index++;
892 }
893
894 for (i = 0; i * 4 < size32; i++) {
895 int slot_size = MIN2(size32 - (i * 4), 4);
896 /* Add this immediate to the list. */
897 entry = new(mem_ctx) immediate_storage(&values[i * 4],
898 slot_size, datatype);
899 this->immediates.push_tail(entry);
900 this->num_immediates++;
901 }
902 return index;
903 }
904
905 st_src_reg
906 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
907 {
908 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
909 union gl_constant_value uval;
910
911 uval.f = val;
912 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
913
914 return src;
915 }
916
917 st_src_reg
918 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
919 {
920 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
921 union gl_constant_value uval[2];
922
923 memcpy(uval, &val, sizeof(uval));
924 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
925 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
926 return src;
927 }
928
929 st_src_reg
930 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
931 {
932 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
933 union gl_constant_value uval;
934
935 assert(native_integers);
936
937 uval.i = val;
938 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
939
940 return src;
941 }
942
943 st_src_reg
944 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
945 {
946 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
947 union gl_constant_value uval[2];
948
949 memcpy(uval, &val, sizeof(uval));
950 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
951 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
952
953 return src;
954 }
955
956 st_src_reg
957 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
958 {
959 if (native_integers)
960 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
961 st_src_reg_for_int(val);
962 else
963 return st_src_reg_for_float(val);
964 }
965
966 static int
967 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
968 {
969 return type->count_attribute_slots(is_vs_input);
970 }
971
972 static int
973 type_size(const struct glsl_type *type)
974 {
975 return type->count_attribute_slots(false);
976 }
977
978 static void
979 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
980 exec_list *instructions, ir_constant *access)
981 {
982 /**
983 * emit_asm() might have actually split the op into pieces, e.g. for
984 * double stores. We have to go back and fix up all the generated ops.
985 */
986 unsigned op = inst->op;
987 do {
988 inst->resource = *buf;
989 if (access)
990 inst->buffer_access = access->value.u[0];
991
992 if (inst == instructions->get_head_raw())
993 break;
994 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
995
996 if (inst->op == TGSI_OPCODE_UADD) {
997 if (inst == instructions->get_head_raw())
998 break;
999 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1000 }
1001 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1002 }
1003
1004 /**
1005 * If the given GLSL type is an array or matrix or a structure containing
1006 * an array/matrix member, return true. Else return false.
1007 *
1008 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1009 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1010 * we have an array that might be indexed with a variable, we need to use
1011 * the later storage type.
1012 */
1013 static bool
1014 type_has_array_or_matrix(const glsl_type *type)
1015 {
1016 if (type->is_array() || type->is_matrix())
1017 return true;
1018
1019 if (type->is_record()) {
1020 for (unsigned i = 0; i < type->length; i++) {
1021 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1022 return true;
1023 }
1024 }
1025 }
1026
1027 return false;
1028 }
1029
1030
1031 /**
1032 * In the initial pass of codegen, we assign temporary numbers to
1033 * intermediate results. (not SSA -- variable assignments will reuse
1034 * storage).
1035 */
1036 st_src_reg
1037 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1038 {
1039 st_src_reg src;
1040
1041 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1042 src.reladdr = NULL;
1043 src.negate = 0;
1044 src.abs = 0;
1045
1046 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1047 if (next_array >= max_num_arrays) {
1048 max_num_arrays += 32;
1049 array_sizes = (unsigned*)
1050 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1051 }
1052
1053 src.file = PROGRAM_ARRAY;
1054 src.index = 0;
1055 src.array_id = next_array + 1;
1056 array_sizes[next_array] = type_size(type);
1057 ++next_array;
1058
1059 } else {
1060 src.file = PROGRAM_TEMPORARY;
1061 src.index = next_temp;
1062 next_temp += type_size(type);
1063 }
1064
1065 if (type->is_array() || type->is_record()) {
1066 src.swizzle = SWIZZLE_NOOP;
1067 } else {
1068 src.swizzle = swizzle_for_size(type->vector_elements);
1069 }
1070
1071 return src;
1072 }
1073
1074 variable_storage *
1075 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1076 {
1077 struct hash_entry *entry;
1078
1079 entry = _mesa_hash_table_search(this->variables, var);
1080 if (!entry)
1081 return NULL;
1082
1083 return (variable_storage *)entry->data;
1084 }
1085
1086 void
1087 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1088 {
1089 if (strcmp(ir->name, "gl_FragCoord") == 0) {
1090 this->prog->OriginUpperLeft = ir->data.origin_upper_left;
1091 this->prog->PixelCenterInteger = ir->data.pixel_center_integer;
1092 }
1093
1094 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1095 unsigned int i;
1096 const ir_state_slot *const slots = ir->get_state_slots();
1097 assert(slots != NULL);
1098
1099 /* Check if this statevar's setup in the STATE file exactly
1100 * matches how we'll want to reference it as a
1101 * struct/array/whatever. If not, then we need to move it into
1102 * temporary storage and hope that it'll get copy-propagated
1103 * out.
1104 */
1105 for (i = 0; i < ir->get_num_state_slots(); i++) {
1106 if (slots[i].swizzle != SWIZZLE_XYZW) {
1107 break;
1108 }
1109 }
1110
1111 variable_storage *storage;
1112 st_dst_reg dst;
1113 if (i == ir->get_num_state_slots()) {
1114 /* We'll set the index later. */
1115 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1116
1117 _mesa_hash_table_insert(this->variables, ir, storage);
1118
1119 dst = undef_dst;
1120 } else {
1121 /* The variable_storage constructor allocates slots based on the size
1122 * of the type. However, this had better match the number of state
1123 * elements that we're going to copy into the new temporary.
1124 */
1125 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1126
1127 dst = st_dst_reg(get_temp(ir->type));
1128
1129 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1130 dst.array_id);
1131
1132 _mesa_hash_table_insert(this->variables, ir, storage);
1133 }
1134
1135
1136 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1137 int index = _mesa_add_state_reference(this->prog->Parameters,
1138 (gl_state_index *)
1139 slots[i].tokens);
1140
1141 if (storage->file == PROGRAM_STATE_VAR) {
1142 if (storage->index == -1) {
1143 storage->index = index;
1144 } else {
1145 assert(index == storage->index + (int)i);
1146 }
1147 } else {
1148 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1149 * the data being moved since MOV does not care about the type of
1150 * data it is moving, and we don't want to declare registers with
1151 * array or struct types.
1152 */
1153 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1154 src.swizzle = slots[i].swizzle;
1155 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1156 /* even a float takes up a whole vec4 reg in a struct/array. */
1157 dst.index++;
1158 }
1159 }
1160
1161 if (storage->file == PROGRAM_TEMPORARY &&
1162 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1163 fail_link(this->shader_program,
1164 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1165 ir->name, dst.index - storage->index,
1166 type_size(ir->type));
1167 }
1168 }
1169 }
1170
1171 void
1172 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1173 {
1174 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1175
1176 visit_exec_list(&ir->body_instructions, this);
1177
1178 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1179 }
1180
1181 void
1182 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1183 {
1184 switch (ir->mode) {
1185 case ir_loop_jump::jump_break:
1186 emit_asm(NULL, TGSI_OPCODE_BRK);
1187 break;
1188 case ir_loop_jump::jump_continue:
1189 emit_asm(NULL, TGSI_OPCODE_CONT);
1190 break;
1191 }
1192 }
1193
1194
1195 void
1196 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1197 {
1198 assert(0);
1199 (void)ir;
1200 }
1201
1202 void
1203 glsl_to_tgsi_visitor::visit(ir_function *ir)
1204 {
1205 /* Ignore function bodies other than main() -- we shouldn't see calls to
1206 * them since they should all be inlined before we get to glsl_to_tgsi.
1207 */
1208 if (strcmp(ir->name, "main") == 0) {
1209 const ir_function_signature *sig;
1210 exec_list empty;
1211
1212 sig = ir->matching_signature(NULL, &empty, false);
1213
1214 assert(sig);
1215
1216 foreach_in_list(ir_instruction, ir, &sig->body) {
1217 ir->accept(this);
1218 }
1219 }
1220 }
1221
1222 bool
1223 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1224 {
1225 int nonmul_operand = 1 - mul_operand;
1226 st_src_reg a, b, c;
1227 st_dst_reg result_dst;
1228
1229 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1230 if (!expr || expr->operation != ir_binop_mul)
1231 return false;
1232
1233 expr->operands[0]->accept(this);
1234 a = this->result;
1235 expr->operands[1]->accept(this);
1236 b = this->result;
1237 ir->operands[nonmul_operand]->accept(this);
1238 c = this->result;
1239
1240 this->result = get_temp(ir->type);
1241 result_dst = st_dst_reg(this->result);
1242 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1243 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1244
1245 return true;
1246 }
1247
1248 /**
1249 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1250 *
1251 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1252 * implemented using multiplication, and logical-or is implemented using
1253 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1254 * As result, the logical expression (a & !b) can be rewritten as:
1255 *
1256 * - a * !b
1257 * - a * (1 - b)
1258 * - (a * 1) - (a * b)
1259 * - a + -(a * b)
1260 * - a + (a * -b)
1261 *
1262 * This final expression can be implemented as a single MAD(a, -b, a)
1263 * instruction.
1264 */
1265 bool
1266 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1267 int try_operand)
1268 {
1269 const int other_operand = 1 - try_operand;
1270 st_src_reg a, b;
1271
1272 ir_expression *expr = ir->operands[try_operand]->as_expression();
1273 if (!expr || expr->operation != ir_unop_logic_not)
1274 return false;
1275
1276 ir->operands[other_operand]->accept(this);
1277 a = this->result;
1278 expr->operands[0]->accept(this);
1279 b = this->result;
1280
1281 b.negate = ~b.negate;
1282
1283 this->result = get_temp(ir->type);
1284 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1285
1286 return true;
1287 }
1288
1289 void
1290 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1291 st_src_reg *reg, int *num_reladdr)
1292 {
1293 if (!reg->reladdr && !reg->reladdr2)
1294 return;
1295
1296 if (reg->reladdr)
1297 emit_arl(ir, address_reg, *reg->reladdr);
1298 if (reg->reladdr2)
1299 emit_arl(ir, address_reg2, *reg->reladdr2);
1300
1301 if (*num_reladdr != 1) {
1302 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1303
1304 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1305 *reg = temp;
1306 }
1307
1308 (*num_reladdr)--;
1309 }
1310
1311 void
1312 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1313 {
1314 st_src_reg op[ARRAY_SIZE(ir->operands)];
1315
1316 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1317 */
1318 if (!this->precise && ir->operation == ir_binop_add) {
1319 if (try_emit_mad(ir, 1))
1320 return;
1321 if (try_emit_mad(ir, 0))
1322 return;
1323 }
1324
1325 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1326 */
1327 if (!native_integers && ir->operation == ir_binop_logic_and) {
1328 if (try_emit_mad_for_and_not(ir, 1))
1329 return;
1330 if (try_emit_mad_for_and_not(ir, 0))
1331 return;
1332 }
1333
1334 if (ir->operation == ir_quadop_vector)
1335 assert(!"ir_quadop_vector should have been lowered");
1336
1337 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1338 this->result.file = PROGRAM_UNDEFINED;
1339 ir->operands[operand]->accept(this);
1340 if (this->result.file == PROGRAM_UNDEFINED) {
1341 printf("Failed to get tree for expression operand:\n");
1342 ir->operands[operand]->print();
1343 printf("\n");
1344 exit(1);
1345 }
1346 op[operand] = this->result;
1347
1348 /* Matrix expression operands should have been broken down to vector
1349 * operations already.
1350 */
1351 assert(!ir->operands[operand]->type->is_matrix());
1352 }
1353
1354 visit_expression(ir, op);
1355 }
1356
1357 /* The non-recursive part of the expression visitor lives in a separate
1358 * function and should be prevented from being inlined, to avoid a stack
1359 * explosion when deeply nested expressions are visited.
1360 */
1361 void
1362 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1363 {
1364 st_src_reg result_src;
1365 st_dst_reg result_dst;
1366
1367 int vector_elements = ir->operands[0]->type->vector_elements;
1368 if (ir->operands[1] &&
1369 ir->operation != ir_binop_interpolate_at_offset &&
1370 ir->operation != ir_binop_interpolate_at_sample) {
1371 st_src_reg *swz_op = NULL;
1372 if (vector_elements > ir->operands[1]->type->vector_elements) {
1373 assert(ir->operands[1]->type->vector_elements == 1);
1374 swz_op = &op[1];
1375 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1376 assert(ir->operands[0]->type->vector_elements == 1);
1377 swz_op = &op[0];
1378 }
1379 if (swz_op) {
1380 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1381 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1382 swizzle_x, swizzle_x);
1383 }
1384 vector_elements = MAX2(vector_elements,
1385 ir->operands[1]->type->vector_elements);
1386 }
1387 if (ir->operands[2] &&
1388 ir->operands[2]->type->vector_elements != vector_elements) {
1389 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1390 assert(ir->operands[2]->type->vector_elements == 1);
1391 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1392 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1393 swizzle_x, swizzle_x);
1394 }
1395
1396 this->result.file = PROGRAM_UNDEFINED;
1397
1398 /* Storage for our result. Ideally for an assignment we'd be using
1399 * the actual storage for the result here, instead.
1400 */
1401 result_src = get_temp(ir->type);
1402 /* convenience for the emit functions below. */
1403 result_dst = st_dst_reg(result_src);
1404 /* Limit writes to the channels that will be used by result_src later.
1405 * This does limit this temp's use as a temporary for multi-instruction
1406 * sequences.
1407 */
1408 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1409
1410 switch (ir->operation) {
1411 case ir_unop_logic_not:
1412 if (result_dst.type != GLSL_TYPE_FLOAT)
1413 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1414 else {
1415 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1416 * older GPUs implement SEQ using multiple instructions (i915 uses two
1417 * SGE instructions and a MUL instruction). Since our logic values are
1418 * 0.0 and 1.0, 1-x also implements !x.
1419 */
1420 op[0].negate = ~op[0].negate;
1421 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1422 st_src_reg_for_float(1.0));
1423 }
1424 break;
1425 case ir_unop_neg:
1426 if (result_dst.type == GLSL_TYPE_INT64 ||
1427 result_dst.type == GLSL_TYPE_UINT64)
1428 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1429 else if (result_dst.type == GLSL_TYPE_INT ||
1430 result_dst.type == GLSL_TYPE_UINT)
1431 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1432 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1433 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1434 else {
1435 op[0].negate = ~op[0].negate;
1436 result_src = op[0];
1437 }
1438 break;
1439 case ir_unop_subroutine_to_int:
1440 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1441 break;
1442 case ir_unop_abs:
1443 if (result_dst.type == GLSL_TYPE_FLOAT)
1444 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1445 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1446 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1447 else if (result_dst.type == GLSL_TYPE_INT64 ||
1448 result_dst.type == GLSL_TYPE_UINT64)
1449 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1450 else
1451 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1452 break;
1453 case ir_unop_sign:
1454 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1455 break;
1456 case ir_unop_rcp:
1457 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1458 break;
1459
1460 case ir_unop_exp2:
1461 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1462 break;
1463 case ir_unop_exp:
1464 assert(!"not reached: should be handled by exp_to_exp2");
1465 break;
1466 case ir_unop_log:
1467 assert(!"not reached: should be handled by log_to_log2");
1468 break;
1469 case ir_unop_log2:
1470 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1471 break;
1472 case ir_unop_sin:
1473 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1474 break;
1475 case ir_unop_cos:
1476 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1477 break;
1478 case ir_unop_saturate: {
1479 glsl_to_tgsi_instruction *inst;
1480 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1481 inst->saturate = true;
1482 break;
1483 }
1484
1485 case ir_unop_dFdx:
1486 case ir_unop_dFdx_coarse:
1487 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1488 break;
1489 case ir_unop_dFdx_fine:
1490 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1491 break;
1492 case ir_unop_dFdy:
1493 case ir_unop_dFdy_coarse:
1494 case ir_unop_dFdy_fine:
1495 {
1496 /* The X component contains 1 or -1 depending on whether the framebuffer
1497 * is a FBO or the window system buffer, respectively.
1498 * It is then multiplied with the source operand of DDY.
1499 */
1500 static const gl_state_index transform_y_state[STATE_LENGTH]
1501 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1502
1503 unsigned transform_y_index =
1504 _mesa_add_state_reference(this->prog->Parameters,
1505 transform_y_state);
1506
1507 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1508 transform_y_index,
1509 glsl_type::vec4_type);
1510 transform_y.swizzle = SWIZZLE_XXXX;
1511
1512 st_src_reg temp = get_temp(glsl_type::vec4_type);
1513
1514 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1515 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1516 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1517 break;
1518 }
1519
1520 case ir_unop_frexp_sig:
1521 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1522 break;
1523
1524 case ir_unop_frexp_exp:
1525 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1526 break;
1527
1528 case ir_unop_noise: {
1529 /* At some point, a motivated person could add a better
1530 * implementation of noise. Currently not even the nvidia
1531 * binary drivers do anything more than this. In any case, the
1532 * place to do this is in the GL state tracker, not the poor
1533 * driver.
1534 */
1535 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1536 break;
1537 }
1538
1539 case ir_binop_add:
1540 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1541 break;
1542 case ir_binop_sub:
1543 op[1].negate = ~op[1].negate;
1544 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1545 break;
1546
1547 case ir_binop_mul:
1548 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1549 break;
1550 case ir_binop_div:
1551 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1552 break;
1553 case ir_binop_mod:
1554 if (result_dst.type == GLSL_TYPE_FLOAT)
1555 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1556 else
1557 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1558 break;
1559
1560 case ir_binop_less:
1561 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1562 break;
1563 case ir_binop_gequal:
1564 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1565 break;
1566 case ir_binop_equal:
1567 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1568 break;
1569 case ir_binop_nequal:
1570 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1571 break;
1572 case ir_binop_all_equal:
1573 /* "==" operator producing a scalar boolean. */
1574 if (ir->operands[0]->type->is_vector() ||
1575 ir->operands[1]->type->is_vector()) {
1576 st_src_reg temp = get_temp(native_integers ?
1577 glsl_type::uvec4_type :
1578 glsl_type::vec4_type);
1579
1580 if (native_integers) {
1581 st_dst_reg temp_dst = st_dst_reg(temp);
1582 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1583
1584 if (ir->operands[0]->type->is_boolean() &&
1585 ir->operands[1]->as_constant() &&
1586 ir->operands[1]->as_constant()->is_one()) {
1587 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1588 } else {
1589 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1590 }
1591
1592 /* Emit 1-3 AND operations to combine the SEQ results. */
1593 switch (ir->operands[0]->type->vector_elements) {
1594 case 2:
1595 break;
1596 case 3:
1597 temp_dst.writemask = WRITEMASK_Y;
1598 temp1.swizzle = SWIZZLE_YYYY;
1599 temp2.swizzle = SWIZZLE_ZZZZ;
1600 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1601 break;
1602 case 4:
1603 temp_dst.writemask = WRITEMASK_X;
1604 temp1.swizzle = SWIZZLE_XXXX;
1605 temp2.swizzle = SWIZZLE_YYYY;
1606 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1607 temp_dst.writemask = WRITEMASK_Y;
1608 temp1.swizzle = SWIZZLE_ZZZZ;
1609 temp2.swizzle = SWIZZLE_WWWW;
1610 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1611 }
1612
1613 temp1.swizzle = SWIZZLE_XXXX;
1614 temp2.swizzle = SWIZZLE_YYYY;
1615 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1616 } else {
1617 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1618
1619 /* After the dot-product, the value will be an integer on the
1620 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1621 */
1622 emit_dp(ir, result_dst, temp, temp, vector_elements);
1623
1624 /* Negating the result of the dot-product gives values on the range
1625 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1626 * This is achieved using SGE.
1627 */
1628 st_src_reg sge_src = result_src;
1629 sge_src.negate = ~sge_src.negate;
1630 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1631 st_src_reg_for_float(0.0));
1632 }
1633 } else {
1634 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1635 }
1636 break;
1637 case ir_binop_any_nequal:
1638 /* "!=" operator producing a scalar boolean. */
1639 if (ir->operands[0]->type->is_vector() ||
1640 ir->operands[1]->type->is_vector()) {
1641 st_src_reg temp = get_temp(native_integers ?
1642 glsl_type::uvec4_type :
1643 glsl_type::vec4_type);
1644 if (ir->operands[0]->type->is_boolean() &&
1645 ir->operands[1]->as_constant() &&
1646 ir->operands[1]->as_constant()->is_zero()) {
1647 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1648 } else {
1649 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1650 }
1651
1652 if (native_integers) {
1653 st_dst_reg temp_dst = st_dst_reg(temp);
1654 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1655
1656 /* Emit 1-3 OR operations to combine the SNE results. */
1657 switch (ir->operands[0]->type->vector_elements) {
1658 case 2:
1659 break;
1660 case 3:
1661 temp_dst.writemask = WRITEMASK_Y;
1662 temp1.swizzle = SWIZZLE_YYYY;
1663 temp2.swizzle = SWIZZLE_ZZZZ;
1664 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1665 break;
1666 case 4:
1667 temp_dst.writemask = WRITEMASK_X;
1668 temp1.swizzle = SWIZZLE_XXXX;
1669 temp2.swizzle = SWIZZLE_YYYY;
1670 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1671 temp_dst.writemask = WRITEMASK_Y;
1672 temp1.swizzle = SWIZZLE_ZZZZ;
1673 temp2.swizzle = SWIZZLE_WWWW;
1674 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1675 }
1676
1677 temp1.swizzle = SWIZZLE_XXXX;
1678 temp2.swizzle = SWIZZLE_YYYY;
1679 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1680 } else {
1681 /* After the dot-product, the value will be an integer on the
1682 * range [0,4]. Zero stays zero, and positive values become 1.0.
1683 */
1684 glsl_to_tgsi_instruction *const dp =
1685 emit_dp(ir, result_dst, temp, temp, vector_elements);
1686 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1687 /* The clamping to [0,1] can be done for free in the fragment
1688 * shader with a saturate.
1689 */
1690 dp->saturate = true;
1691 } else {
1692 /* Negating the result of the dot-product gives values on the
1693 * range [-4, 0]. Zero stays zero, and negative values become
1694 * 1.0. This achieved using SLT.
1695 */
1696 st_src_reg slt_src = result_src;
1697 slt_src.negate = ~slt_src.negate;
1698 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1699 st_src_reg_for_float(0.0));
1700 }
1701 }
1702 } else {
1703 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1704 }
1705 break;
1706
1707 case ir_binop_logic_xor:
1708 if (native_integers)
1709 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1710 else
1711 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1712 break;
1713
1714 case ir_binop_logic_or: {
1715 if (native_integers) {
1716 /* If integers are used as booleans, we can use an actual "or"
1717 * instruction.
1718 */
1719 assert(native_integers);
1720 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1721 } else {
1722 /* After the addition, the value will be an integer on the
1723 * range [0,2]. Zero stays zero, and positive values become 1.0.
1724 */
1725 glsl_to_tgsi_instruction *add =
1726 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1727 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1728 /* The clamping to [0,1] can be done for free in the fragment
1729 * shader with a saturate if floats are being used as boolean
1730 * values.
1731 */
1732 add->saturate = true;
1733 } else {
1734 /* Negating the result of the addition gives values on the range
1735 * [-2, 0]. Zero stays zero, and negative values become 1.0
1736 * This is achieved using SLT.
1737 */
1738 st_src_reg slt_src = result_src;
1739 slt_src.negate = ~slt_src.negate;
1740 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1741 st_src_reg_for_float(0.0));
1742 }
1743 }
1744 break;
1745 }
1746
1747 case ir_binop_logic_and:
1748 /* If native integers are disabled, the bool args are stored as float 0.0
1749 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1750 * actual AND opcode.
1751 */
1752 if (native_integers)
1753 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1754 else
1755 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1756 break;
1757
1758 case ir_binop_dot:
1759 assert(ir->operands[0]->type->is_vector());
1760 assert(ir->operands[0]->type == ir->operands[1]->type);
1761 emit_dp(ir, result_dst, op[0], op[1],
1762 ir->operands[0]->type->vector_elements);
1763 break;
1764
1765 case ir_unop_sqrt:
1766 if (have_sqrt) {
1767 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1768 } else {
1769 /* This is the only instruction sequence that makes the game "Risen"
1770 * render correctly. ABS is not required for the game, but since GLSL
1771 * declares negative values as "undefined", allowing us to do whatever
1772 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1773 * behavior.
1774 */
1775 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1776 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1777 }
1778 break;
1779 case ir_unop_rsq:
1780 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1781 break;
1782 case ir_unop_i2f:
1783 if (native_integers) {
1784 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1785 break;
1786 }
1787 /* fallthrough to next case otherwise */
1788 case ir_unop_b2f:
1789 if (native_integers) {
1790 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1791 st_src_reg_for_float(1.0));
1792 break;
1793 }
1794 /* fallthrough to next case otherwise */
1795 case ir_unop_i2u:
1796 case ir_unop_u2i:
1797 case ir_unop_i642u64:
1798 case ir_unop_u642i64:
1799 /* Converting between signed and unsigned integers is a no-op. */
1800 result_src = op[0];
1801 result_src.type = result_dst.type;
1802 break;
1803 case ir_unop_b2i:
1804 if (native_integers) {
1805 /* Booleans are stored as integers using ~0 for true and 0 for false.
1806 * GLSL requires that int(bool) return 1 for true and 0 for false.
1807 * This conversion is done with AND, but it could be done with NEG.
1808 */
1809 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1810 st_src_reg_for_int(1));
1811 } else {
1812 /* Booleans and integers are both stored as floats when native
1813 * integers are disabled.
1814 */
1815 result_src = op[0];
1816 }
1817 break;
1818 case ir_unop_f2i:
1819 if (native_integers)
1820 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1821 else
1822 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1823 break;
1824 case ir_unop_f2u:
1825 if (native_integers)
1826 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1827 else
1828 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1829 break;
1830 case ir_unop_bitcast_f2i:
1831 case ir_unop_bitcast_f2u:
1832 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1833 if (op[0].negate || op[0].abs)
1834 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1835 else
1836 result_src = op[0];
1837 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1838 GLSL_TYPE_UINT;
1839 break;
1840 case ir_unop_bitcast_i2f:
1841 case ir_unop_bitcast_u2f:
1842 result_src = op[0];
1843 result_src.type = GLSL_TYPE_FLOAT;
1844 break;
1845 case ir_unop_f2b:
1846 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1847 st_src_reg_for_float(0.0));
1848 break;
1849 case ir_unop_d2b:
1850 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1851 st_src_reg_for_double(0.0));
1852 break;
1853 case ir_unop_i2b:
1854 if (native_integers)
1855 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1856 st_src_reg_for_int(0));
1857 else
1858 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1859 st_src_reg_for_float(0.0));
1860 break;
1861 case ir_unop_bitcast_u642d:
1862 case ir_unop_bitcast_i642d:
1863 result_src = op[0];
1864 result_src.type = GLSL_TYPE_DOUBLE;
1865 break;
1866 case ir_unop_bitcast_d2i64:
1867 result_src = op[0];
1868 result_src.type = GLSL_TYPE_INT64;
1869 break;
1870 case ir_unop_bitcast_d2u64:
1871 result_src = op[0];
1872 result_src.type = GLSL_TYPE_UINT64;
1873 break;
1874 case ir_unop_trunc:
1875 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1876 break;
1877 case ir_unop_ceil:
1878 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1879 break;
1880 case ir_unop_floor:
1881 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1882 break;
1883 case ir_unop_round_even:
1884 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1885 break;
1886 case ir_unop_fract:
1887 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1888 break;
1889
1890 case ir_binop_min:
1891 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1892 break;
1893 case ir_binop_max:
1894 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1895 break;
1896 case ir_binop_pow:
1897 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1898 break;
1899
1900 case ir_unop_bit_not:
1901 if (native_integers) {
1902 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1903 break;
1904 }
1905 case ir_unop_u2f:
1906 if (native_integers) {
1907 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1908 break;
1909 }
1910 case ir_binop_lshift:
1911 case ir_binop_rshift:
1912 if (native_integers) {
1913 unsigned opcode = ir->operation == ir_binop_lshift ? TGSI_OPCODE_SHL
1914 : TGSI_OPCODE_ISHR;
1915 st_src_reg count;
1916
1917 if (glsl_base_type_is_64bit(op[0].type)) {
1918 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1919 * 64 bits.
1920 */
1921 count = get_temp(glsl_type::u64vec(ir->operands[1]
1922 ->type->components()));
1923 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1924 } else {
1925 count = op[1];
1926 }
1927
1928 emit_asm(ir, opcode, result_dst, op[0], count);
1929 break;
1930 }
1931 case ir_binop_bit_and:
1932 if (native_integers) {
1933 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1934 break;
1935 }
1936 case ir_binop_bit_xor:
1937 if (native_integers) {
1938 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1939 break;
1940 }
1941 case ir_binop_bit_or:
1942 if (native_integers) {
1943 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1944 break;
1945 }
1946
1947 assert(!"GLSL 1.30 features unsupported");
1948 break;
1949
1950 case ir_binop_ubo_load: {
1951 if (ctx->Const.UseSTD430AsDefaultPacking) {
1952 ir_rvalue *block = ir->operands[0];
1953 ir_rvalue *offset = ir->operands[1];
1954 ir_constant *const_block = block->as_constant();
1955
1956 st_src_reg cbuf(PROGRAM_CONSTANT,
1957 (const_block ? const_block->value.u[0] + 1 : 1),
1958 ir->type->base_type);
1959
1960 cbuf.has_index2 = true;
1961
1962 if (!const_block) {
1963 block->accept(this);
1964 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
1965 *cbuf.reladdr = this->result;
1966 emit_arl(ir, sampler_reladdr, this->result);
1967 }
1968
1969 /* Calculate the surface offset */
1970 offset->accept(this);
1971 st_src_reg off = this->result;
1972
1973 glsl_to_tgsi_instruction *inst =
1974 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
1975
1976 if (result_dst.type == GLSL_TYPE_BOOL)
1977 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
1978 st_src_reg_for_int(0));
1979
1980 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
1981 NULL);
1982 } else {
1983 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
1984 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
1985 unsigned const_offset = const_offset_ir ?
1986 const_offset_ir->value.u[0] : 0;
1987 unsigned const_block = const_uniform_block ?
1988 const_uniform_block->value.u[0] + 1 : 1;
1989 st_src_reg index_reg = get_temp(glsl_type::uint_type);
1990 st_src_reg cbuf;
1991
1992 cbuf.type = ir->type->base_type;
1993 cbuf.file = PROGRAM_CONSTANT;
1994 cbuf.index = 0;
1995 cbuf.reladdr = NULL;
1996 cbuf.negate = 0;
1997 cbuf.abs = 0;
1998 cbuf.index2D = const_block;
1999
2000 assert(ir->type->is_vector() || ir->type->is_scalar());
2001
2002 if (const_offset_ir) {
2003 /* Constant index into constant buffer */
2004 cbuf.reladdr = NULL;
2005 cbuf.index = const_offset / 16;
2006 } else {
2007 ir_expression *offset_expr = ir->operands[1]->as_expression();
2008 st_src_reg offset = op[1];
2009
2010 /* The OpenGL spec is written in such a way that accesses with
2011 * non-constant offset are almost always vec4-aligned. The only
2012 * exception to this are members of structs in arrays of structs:
2013 * each struct in an array of structs is at least vec4-aligned,
2014 * but single-element and [ui]vec2 members of the struct may be at
2015 * an offset that is not a multiple of 16 bytes.
2016 *
2017 * Here, we extract that offset, relying on previous passes to
2018 * always generate offset expressions of the form
2019 * (+ expr constant_offset).
2020 *
2021 * Note that the std430 layout, which allows more cases of
2022 * alignment less than vec4 in arrays, is not supported for
2023 * uniform blocks, so we do not have to deal with it here.
2024 */
2025 if (offset_expr && offset_expr->operation == ir_binop_add) {
2026 const_offset_ir = offset_expr->operands[1]->as_constant();
2027 if (const_offset_ir) {
2028 const_offset = const_offset_ir->value.u[0];
2029 cbuf.index = const_offset / 16;
2030 offset_expr->operands[0]->accept(this);
2031 offset = this->result;
2032 }
2033 }
2034
2035 /* Relative/variable index into constant buffer */
2036 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2037 st_src_reg_for_int(4));
2038 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2039 memcpy(cbuf.reladdr, &index_reg, sizeof(index_reg));
2040 }
2041
2042 if (const_uniform_block) {
2043 /* Constant constant buffer */
2044 cbuf.reladdr2 = NULL;
2045 } else {
2046 /* Relative/variable constant buffer */
2047 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2048 memcpy(cbuf.reladdr2, &op[0], sizeof(st_src_reg));
2049 }
2050 cbuf.has_index2 = true;
2051
2052 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2053 if (glsl_base_type_is_64bit(cbuf.type))
2054 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2055 const_offset % 16 / 8,
2056 const_offset % 16 / 8,
2057 const_offset % 16 / 8);
2058 else
2059 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2060 const_offset % 16 / 4,
2061 const_offset % 16 / 4,
2062 const_offset % 16 / 4);
2063
2064 if (ir->type->is_boolean()) {
2065 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2066 st_src_reg_for_int(0));
2067 } else {
2068 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2069 }
2070 }
2071 break;
2072 }
2073 case ir_triop_lrp:
2074 /* note: we have to reorder the three args here */
2075 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2076 break;
2077 case ir_triop_csel:
2078 if (this->ctx->Const.NativeIntegers)
2079 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2080 else {
2081 op[0].negate = ~op[0].negate;
2082 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2083 }
2084 break;
2085 case ir_triop_bitfield_extract:
2086 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2087 break;
2088 case ir_quadop_bitfield_insert:
2089 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2090 break;
2091 case ir_unop_bitfield_reverse:
2092 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2093 break;
2094 case ir_unop_bit_count:
2095 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2096 break;
2097 case ir_unop_find_msb:
2098 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2099 break;
2100 case ir_unop_find_lsb:
2101 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2102 break;
2103 case ir_binop_imul_high:
2104 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2105 break;
2106 case ir_triop_fma:
2107 /* In theory, MAD is incorrect here. */
2108 if (have_fma)
2109 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2110 else
2111 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2112 break;
2113 case ir_unop_interpolate_at_centroid:
2114 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2115 break;
2116 case ir_binop_interpolate_at_offset: {
2117 /* The y coordinate needs to be flipped for the default fb */
2118 static const gl_state_index transform_y_state[STATE_LENGTH]
2119 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2120
2121 unsigned transform_y_index =
2122 _mesa_add_state_reference(this->prog->Parameters,
2123 transform_y_state);
2124
2125 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2126 transform_y_index,
2127 glsl_type::vec4_type);
2128 transform_y.swizzle = SWIZZLE_XXXX;
2129
2130 st_src_reg temp = get_temp(glsl_type::vec2_type);
2131 st_dst_reg temp_dst = st_dst_reg(temp);
2132
2133 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2134 temp_dst.writemask = WRITEMASK_Y;
2135 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2136 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2137 break;
2138 }
2139 case ir_binop_interpolate_at_sample:
2140 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2141 break;
2142
2143 case ir_unop_d2f:
2144 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2145 break;
2146 case ir_unop_f2d:
2147 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2148 break;
2149 case ir_unop_d2i:
2150 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2151 break;
2152 case ir_unop_i2d:
2153 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2154 break;
2155 case ir_unop_d2u:
2156 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2157 break;
2158 case ir_unop_u2d:
2159 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2160 break;
2161 case ir_unop_unpack_double_2x32:
2162 case ir_unop_pack_double_2x32:
2163 case ir_unop_unpack_int_2x32:
2164 case ir_unop_pack_int_2x32:
2165 case ir_unop_unpack_uint_2x32:
2166 case ir_unop_pack_uint_2x32:
2167 case ir_unop_unpack_sampler_2x32:
2168 case ir_unop_pack_sampler_2x32:
2169 case ir_unop_unpack_image_2x32:
2170 case ir_unop_pack_image_2x32:
2171 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2172 break;
2173
2174 case ir_binop_ldexp:
2175 if (ir->operands[0]->type->is_double()) {
2176 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2177 } else if (ir->operands[0]->type->is_float()) {
2178 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2179 } else {
2180 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2181 }
2182 break;
2183
2184 case ir_unop_pack_half_2x16:
2185 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2186 break;
2187 case ir_unop_unpack_half_2x16:
2188 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2189 break;
2190
2191 case ir_unop_get_buffer_size: {
2192 ir_constant *const_offset = ir->operands[0]->as_constant();
2193 int buf_base = ctx->st->has_hw_atomics
2194 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
2195 st_src_reg buffer(
2196 PROGRAM_BUFFER,
2197 buf_base + (const_offset ? const_offset->value.u[0] : 0),
2198 GLSL_TYPE_UINT);
2199 if (!const_offset) {
2200 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2201 *buffer.reladdr = op[0];
2202 emit_arl(ir, sampler_reladdr, op[0]);
2203 }
2204 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2205 break;
2206 }
2207
2208 case ir_unop_u2i64:
2209 case ir_unop_u2u64:
2210 case ir_unop_b2i64: {
2211 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2212 st_dst_reg temp_dst = st_dst_reg(temp);
2213 unsigned orig_swz = op[0].swizzle;
2214 /*
2215 * To convert unsigned to 64-bit:
2216 * zero Y channel, copy X channel.
2217 */
2218 temp_dst.writemask = WRITEMASK_Y;
2219 if (vector_elements > 1)
2220 temp_dst.writemask |= WRITEMASK_W;
2221 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2222 temp_dst.writemask = WRITEMASK_X;
2223 if (vector_elements > 1)
2224 temp_dst.writemask |= WRITEMASK_Z;
2225 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2226 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2227 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2228 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2229 else
2230 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2231 result_src = temp;
2232 result_src.type = GLSL_TYPE_UINT64;
2233 if (vector_elements > 2) {
2234 /* Subtle: We rely on the fact that get_temp here returns the next
2235 * TGSI temporary register directly after the temp register used for
2236 * the first two components, so that the result gets picked up
2237 * automatically.
2238 */
2239 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2240 st_dst_reg temp_dst = st_dst_reg(temp);
2241 temp_dst.writemask = WRITEMASK_Y;
2242 if (vector_elements > 3)
2243 temp_dst.writemask |= WRITEMASK_W;
2244 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2245
2246 temp_dst.writemask = WRITEMASK_X;
2247 if (vector_elements > 3)
2248 temp_dst.writemask |= WRITEMASK_Z;
2249 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2250 GET_SWZ(orig_swz, 2),
2251 GET_SWZ(orig_swz, 3),
2252 GET_SWZ(orig_swz, 3));
2253 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2254 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2255 else
2256 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2257 st_src_reg_for_int(1));
2258 }
2259 break;
2260 }
2261 case ir_unop_i642i:
2262 case ir_unop_u642i:
2263 case ir_unop_u642u:
2264 case ir_unop_i642u: {
2265 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2266 st_dst_reg temp_dst = st_dst_reg(temp);
2267 unsigned orig_swz = op[0].swizzle;
2268 unsigned orig_idx = op[0].index;
2269 int el;
2270 temp_dst.writemask = WRITEMASK_X;
2271
2272 for (el = 0; el < vector_elements; el++) {
2273 unsigned swz = GET_SWZ(orig_swz, el);
2274 if (swz & 1)
2275 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2276 SWIZZLE_Z, SWIZZLE_Z);
2277 else
2278 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2279 SWIZZLE_X, SWIZZLE_X);
2280 if (swz > 2)
2281 op[0].index = orig_idx + 1;
2282 op[0].type = GLSL_TYPE_UINT;
2283 temp_dst.writemask = WRITEMASK_X << el;
2284 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2285 }
2286 result_src = temp;
2287 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2288 result_src.type = GLSL_TYPE_UINT;
2289 else
2290 result_src.type = GLSL_TYPE_INT;
2291 break;
2292 }
2293 case ir_unop_i642b:
2294 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2295 st_src_reg_for_int64(0));
2296 break;
2297 case ir_unop_i642f:
2298 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2299 break;
2300 case ir_unop_u642f:
2301 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2302 break;
2303 case ir_unop_i642d:
2304 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2305 break;
2306 case ir_unop_u642d:
2307 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2308 break;
2309 case ir_unop_i2i64:
2310 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2311 break;
2312 case ir_unop_f2i64:
2313 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2314 break;
2315 case ir_unop_d2i64:
2316 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2317 break;
2318 case ir_unop_i2u64:
2319 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2320 break;
2321 case ir_unop_f2u64:
2322 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2323 break;
2324 case ir_unop_d2u64:
2325 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2326 break;
2327 /* these might be needed */
2328 case ir_unop_pack_snorm_2x16:
2329 case ir_unop_pack_unorm_2x16:
2330 case ir_unop_pack_snorm_4x8:
2331 case ir_unop_pack_unorm_4x8:
2332
2333 case ir_unop_unpack_snorm_2x16:
2334 case ir_unop_unpack_unorm_2x16:
2335 case ir_unop_unpack_snorm_4x8:
2336 case ir_unop_unpack_unorm_4x8:
2337
2338 case ir_quadop_vector:
2339 case ir_binop_vector_extract:
2340 case ir_triop_vector_insert:
2341 case ir_binop_carry:
2342 case ir_binop_borrow:
2343 case ir_unop_ssbo_unsized_array_length:
2344 /* This operation is not supported, or should have already been handled.
2345 */
2346 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2347 break;
2348 }
2349
2350 this->result = result_src;
2351 }
2352
2353
2354 void
2355 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2356 {
2357 st_src_reg src;
2358 int i;
2359 int swizzle[4];
2360
2361 /* Note that this is only swizzles in expressions, not those on the left
2362 * hand side of an assignment, which do write masking. See ir_assignment
2363 * for that.
2364 */
2365
2366 ir->val->accept(this);
2367 src = this->result;
2368 assert(src.file != PROGRAM_UNDEFINED);
2369 assert(ir->type->vector_elements > 0);
2370
2371 for (i = 0; i < 4; i++) {
2372 if (i < ir->type->vector_elements) {
2373 switch (i) {
2374 case 0:
2375 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2376 break;
2377 case 1:
2378 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2379 break;
2380 case 2:
2381 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2382 break;
2383 case 3:
2384 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2385 break;
2386 }
2387 } else {
2388 /* If the type is smaller than a vec4, replicate the last
2389 * channel out.
2390 */
2391 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2392 }
2393 }
2394
2395 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2396
2397 this->result = src;
2398 }
2399
2400 /* Test if the variable is an array. Note that geometry and
2401 * tessellation shader inputs are outputs are always arrays (except
2402 * for patch inputs), so only the array element type is considered.
2403 */
2404 static bool
2405 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2406 {
2407 const glsl_type *type = var->type;
2408
2409 *remove_array = false;
2410
2411 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2412 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2413 return false;
2414
2415 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2416 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2417 stage == MESA_SHADER_TESS_CTRL) &&
2418 !var->data.patch) {
2419 if (!var->type->is_array())
2420 return false; /* a system value probably */
2421
2422 type = var->type->fields.array;
2423 *remove_array = true;
2424 }
2425
2426 return type->is_array() || type->is_matrix();
2427 }
2428
2429 static unsigned
2430 st_translate_interp_loc(ir_variable *var)
2431 {
2432 if (var->data.centroid)
2433 return TGSI_INTERPOLATE_LOC_CENTROID;
2434 else if (var->data.sample)
2435 return TGSI_INTERPOLATE_LOC_SAMPLE;
2436 else
2437 return TGSI_INTERPOLATE_LOC_CENTER;
2438 }
2439
2440 void
2441 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2442 {
2443 variable_storage *entry = find_variable_storage(ir->var);
2444 ir_variable *var = ir->var;
2445 bool remove_array;
2446
2447 if (!entry) {
2448 switch (var->data.mode) {
2449 case ir_var_uniform:
2450 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2451 var->data.param_index);
2452 _mesa_hash_table_insert(this->variables, var, entry);
2453 break;
2454 case ir_var_shader_in: {
2455 /* The linker assigns locations for varyings and attributes,
2456 * including deprecated builtins (like gl_Color), user-assign
2457 * generic attributes (glBindVertexLocation), and
2458 * user-defined varyings.
2459 */
2460 assert(var->data.location != -1);
2461
2462 const glsl_type *type_without_array = var->type->without_array();
2463 struct inout_decl *decl = &inputs[num_inputs];
2464 unsigned component = var->data.location_frac;
2465 unsigned num_components;
2466 num_inputs++;
2467
2468 if (type_without_array->is_64bit())
2469 component = component / 2;
2470 if (type_without_array->vector_elements)
2471 num_components = type_without_array->vector_elements;
2472 else
2473 num_components = 4;
2474
2475 decl->mesa_index = var->data.location;
2476 decl->interp = (glsl_interp_mode) var->data.interpolation;
2477 decl->interp_loc = st_translate_interp_loc(var);
2478 decl->base_type = type_without_array->base_type;
2479 decl->usage_mask = u_bit_consecutive(component, num_components);
2480
2481 if (is_inout_array(shader->Stage, var, &remove_array)) {
2482 decl->array_id = num_input_arrays + 1;
2483 num_input_arrays++;
2484 } else {
2485 decl->array_id = 0;
2486 }
2487
2488 if (remove_array)
2489 decl->size = type_size(var->type->fields.array);
2490 else
2491 decl->size = type_size(var->type);
2492
2493 entry = new(mem_ctx) variable_storage(var,
2494 PROGRAM_INPUT,
2495 decl->mesa_index,
2496 decl->array_id);
2497 entry->component = component;
2498
2499 _mesa_hash_table_insert(this->variables, var, entry);
2500
2501 break;
2502 }
2503 case ir_var_shader_out: {
2504 assert(var->data.location != -1);
2505
2506 const glsl_type *type_without_array = var->type->without_array();
2507 struct inout_decl *decl = &outputs[num_outputs];
2508 unsigned component = var->data.location_frac;
2509 unsigned num_components;
2510 num_outputs++;
2511
2512 if (type_without_array->is_64bit())
2513 component = component / 2;
2514 if (type_without_array->vector_elements)
2515 num_components = type_without_array->vector_elements;
2516 else
2517 num_components = 4;
2518
2519 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2520 decl->base_type = type_without_array->base_type;
2521 decl->usage_mask = u_bit_consecutive(component, num_components);
2522 if (var->data.stream & (1u << 31)) {
2523 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2524 } else {
2525 assert(var->data.stream < 4);
2526 decl->gs_out_streams = 0;
2527 for (unsigned i = 0; i < num_components; ++i)
2528 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2529 }
2530
2531 if (is_inout_array(shader->Stage, var, &remove_array)) {
2532 decl->array_id = num_output_arrays + 1;
2533 num_output_arrays++;
2534 } else {
2535 decl->array_id = 0;
2536 }
2537
2538 if (remove_array)
2539 decl->size = type_size(var->type->fields.array);
2540 else
2541 decl->size = type_size(var->type);
2542
2543 if (var->data.fb_fetch_output) {
2544 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2545 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2546 var->type, component, decl->array_id);
2547 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2548 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2549 dst.array_id);
2550 } else {
2551 entry = new(mem_ctx) variable_storage(var,
2552 PROGRAM_OUTPUT,
2553 decl->mesa_index,
2554 decl->array_id);
2555 }
2556 entry->component = component;
2557
2558 _mesa_hash_table_insert(this->variables, var, entry);
2559
2560 break;
2561 }
2562 case ir_var_system_value:
2563 entry = new(mem_ctx) variable_storage(var,
2564 PROGRAM_SYSTEM_VALUE,
2565 var->data.location);
2566 break;
2567 case ir_var_auto:
2568 case ir_var_temporary:
2569 st_src_reg src = get_temp(var->type);
2570
2571 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2572 src.array_id);
2573 _mesa_hash_table_insert(this->variables, var, entry);
2574
2575 break;
2576 }
2577
2578 if (!entry) {
2579 printf("Failed to make storage for %s\n", var->name);
2580 exit(1);
2581 }
2582 }
2583
2584 this->result = st_src_reg(entry->file, entry->index, var->type,
2585 entry->component, entry->array_id);
2586 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2587 var->data.mode == ir_var_shader_in &&
2588 var->type->without_array()->is_double())
2589 this->result.is_double_vertex_input = true;
2590 if (!native_integers)
2591 this->result.type = GLSL_TYPE_FLOAT;
2592 }
2593
2594 static void
2595 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2596 GLbitfield64* usage_mask,
2597 GLbitfield64 double_usage_mask,
2598 GLbitfield* patch_usage_mask)
2599 {
2600 unsigned i;
2601 int j;
2602
2603 /* Fix array declarations by removing unused array elements at both ends
2604 * of the arrays. For example, mat4[3] where only mat[1] is used.
2605 */
2606 for (i = 0; i < count; i++) {
2607 struct inout_decl *decl = &decls[i];
2608 if (!decl->array_id)
2609 continue;
2610
2611 /* Shrink the beginning. */
2612 for (j = 0; j < (int)decl->size; j++) {
2613 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2614 if (*patch_usage_mask &
2615 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2616 break;
2617 }
2618 else {
2619 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2620 break;
2621 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2622 break;
2623 }
2624
2625 decl->mesa_index++;
2626 decl->size--;
2627 j--;
2628 }
2629
2630 /* Shrink the end. */
2631 for (j = decl->size-1; j >= 0; j--) {
2632 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2633 if (*patch_usage_mask &
2634 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2635 break;
2636 }
2637 else {
2638 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2639 break;
2640 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2641 break;
2642 }
2643
2644 decl->size--;
2645 }
2646
2647 /* When not all entries of an array are accessed, we mark them as used
2648 * here anyway, to ensure that the input/output mapping logic doesn't get
2649 * confused.
2650 *
2651 * TODO This happens when an array isn't used via indirect access, which
2652 * some game ports do (at least eON-based). There is an optimization
2653 * opportunity here by replacing the array declaration with non-array
2654 * declarations of those slots that are actually used.
2655 */
2656 for (j = 1; j < (int)decl->size; ++j) {
2657 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2658 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2659 else
2660 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2661 }
2662 }
2663 }
2664
2665 void
2666 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2667 {
2668 ir_constant *index;
2669 st_src_reg src;
2670 bool is_2D = false;
2671 ir_variable *var = ir->variable_referenced();
2672
2673 /* We only need the logic provided by st_glsl_storage_type_size()
2674 * for arrays of structs. Indirect sampler and image indexing is handled
2675 * elsewhere.
2676 */
2677 int element_size = ir->type->without_array()->is_record() ?
2678 st_glsl_storage_type_size(ir->type, var->data.bindless) :
2679 type_size(ir->type);
2680
2681 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2682
2683 ir->array->accept(this);
2684 src = this->result;
2685
2686 if (!src.has_index2) {
2687 switch (this->prog->Target) {
2688 case GL_TESS_CONTROL_PROGRAM_NV:
2689 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2690 !ir->variable_referenced()->data.patch;
2691 break;
2692 case GL_TESS_EVALUATION_PROGRAM_NV:
2693 is_2D = src.file == PROGRAM_INPUT &&
2694 !ir->variable_referenced()->data.patch;
2695 break;
2696 case GL_GEOMETRY_PROGRAM_NV:
2697 is_2D = src.file == PROGRAM_INPUT;
2698 break;
2699 }
2700 }
2701
2702 if (is_2D)
2703 element_size = 1;
2704
2705 if (index) {
2706
2707 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2708 src.file == PROGRAM_INPUT)
2709 element_size = attrib_type_size(ir->type, true);
2710 if (is_2D) {
2711 src.index2D = index->value.i[0];
2712 src.has_index2 = true;
2713 } else
2714 src.index += index->value.i[0] * element_size;
2715 } else {
2716 /* Variable index array dereference. It eats the "vec4" of the
2717 * base of the array and an index that offsets the TGSI register
2718 * index.
2719 */
2720 ir->array_index->accept(this);
2721
2722 st_src_reg index_reg;
2723
2724 if (element_size == 1) {
2725 index_reg = this->result;
2726 } else {
2727 index_reg = get_temp(native_integers ?
2728 glsl_type::int_type : glsl_type::float_type);
2729
2730 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2731 this->result, st_src_reg_for_type(index_reg.type, element_size));
2732 }
2733
2734 /* If there was already a relative address register involved, add the
2735 * new and the old together to get the new offset.
2736 */
2737 if (!is_2D && src.reladdr != NULL) {
2738 st_src_reg accum_reg = get_temp(native_integers ?
2739 glsl_type::int_type : glsl_type::float_type);
2740
2741 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2742 index_reg, *src.reladdr);
2743
2744 index_reg = accum_reg;
2745 }
2746
2747 if (is_2D) {
2748 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2749 memcpy(src.reladdr2, &index_reg, sizeof(index_reg));
2750 src.index2D = 0;
2751 src.has_index2 = true;
2752 } else {
2753 src.reladdr = ralloc(mem_ctx, st_src_reg);
2754 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
2755 }
2756 }
2757
2758 /* Change the register type to the element type of the array. */
2759 src.type = ir->type->base_type;
2760
2761 this->result = src;
2762 }
2763
2764 void
2765 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2766 {
2767 unsigned int i;
2768 const glsl_type *struct_type = ir->record->type;
2769 ir_variable *var = ir->record->variable_referenced();
2770 int offset = 0;
2771
2772 ir->record->accept(this);
2773
2774 assert(ir->field_idx >= 0);
2775 assert(var);
2776 for (i = 0; i < struct_type->length; i++) {
2777 if (i == (unsigned) ir->field_idx)
2778 break;
2779 const glsl_type *member_type = struct_type->fields.structure[i].type;
2780 offset += st_glsl_storage_type_size(member_type, var->data.bindless);
2781 }
2782
2783 /* If the type is smaller than a vec4, replicate the last channel out. */
2784 if (ir->type->is_scalar() || ir->type->is_vector())
2785 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2786 else
2787 this->result.swizzle = SWIZZLE_NOOP;
2788
2789 this->result.index += offset;
2790 this->result.type = ir->type->base_type;
2791 }
2792
2793 /**
2794 * We want to be careful in assignment setup to hit the actual storage
2795 * instead of potentially using a temporary like we might with the
2796 * ir_dereference handler.
2797 */
2798 static st_dst_reg
2799 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2800 {
2801 /* The LHS must be a dereference. If the LHS is a variable indexed array
2802 * access of a vector, it must be separated into a series conditional moves
2803 * before reaching this point (see ir_vec_index_to_cond_assign).
2804 */
2805 assert(ir->as_dereference());
2806 ir_dereference_array *deref_array = ir->as_dereference_array();
2807 if (deref_array) {
2808 assert(!deref_array->array->type->is_vector());
2809 }
2810
2811 /* Use the rvalue deref handler for the most part. We write swizzles using
2812 * the writemask, but we do extract the base component for enhanced layouts
2813 * from the source swizzle.
2814 */
2815 ir->accept(v);
2816 *component = GET_SWZ(v->result.swizzle, 0);
2817 return st_dst_reg(v->result);
2818 }
2819
2820 /**
2821 * Process the condition of a conditional assignment
2822 *
2823 * Examines the condition of a conditional assignment to generate the optimal
2824 * first operand of a \c CMP instruction. If the condition is a relational
2825 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2826 * used as the source for the \c CMP instruction. Otherwise the comparison
2827 * is processed to a boolean result, and the boolean result is used as the
2828 * operand to the CMP instruction.
2829 */
2830 bool
2831 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2832 {
2833 ir_rvalue *src_ir = ir;
2834 bool negate = true;
2835 bool switch_order = false;
2836
2837 ir_expression *const expr = ir->as_expression();
2838
2839 if (native_integers) {
2840 if ((expr != NULL) && (expr->num_operands == 2)) {
2841 enum glsl_base_type type = expr->operands[0]->type->base_type;
2842 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2843 type == GLSL_TYPE_BOOL) {
2844 if (expr->operation == ir_binop_equal) {
2845 if (expr->operands[0]->is_zero()) {
2846 src_ir = expr->operands[1];
2847 switch_order = true;
2848 }
2849 else if (expr->operands[1]->is_zero()) {
2850 src_ir = expr->operands[0];
2851 switch_order = true;
2852 }
2853 }
2854 else if (expr->operation == ir_binop_nequal) {
2855 if (expr->operands[0]->is_zero()) {
2856 src_ir = expr->operands[1];
2857 }
2858 else if (expr->operands[1]->is_zero()) {
2859 src_ir = expr->operands[0];
2860 }
2861 }
2862 }
2863 }
2864
2865 src_ir->accept(this);
2866 return switch_order;
2867 }
2868
2869 if ((expr != NULL) && (expr->num_operands == 2)) {
2870 bool zero_on_left = false;
2871
2872 if (expr->operands[0]->is_zero()) {
2873 src_ir = expr->operands[1];
2874 zero_on_left = true;
2875 } else if (expr->operands[1]->is_zero()) {
2876 src_ir = expr->operands[0];
2877 zero_on_left = false;
2878 }
2879
2880 /* a is - 0 + - 0 +
2881 * (a < 0) T F F ( a < 0) T F F
2882 * (0 < a) F F T (-a < 0) F F T
2883 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2884 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2885 *
2886 * Note that exchanging the order of 0 and 'a' in the comparison simply
2887 * means that the value of 'a' should be negated.
2888 */
2889 if (src_ir != ir) {
2890 switch (expr->operation) {
2891 case ir_binop_less:
2892 switch_order = false;
2893 negate = zero_on_left;
2894 break;
2895
2896 case ir_binop_gequal:
2897 switch_order = true;
2898 negate = zero_on_left;
2899 break;
2900
2901 default:
2902 /* This isn't the right kind of comparison afterall, so make sure
2903 * the whole condition is visited.
2904 */
2905 src_ir = ir;
2906 break;
2907 }
2908 }
2909 }
2910
2911 src_ir->accept(this);
2912
2913 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2914 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2915 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2916 * computing the condition.
2917 */
2918 if (negate)
2919 this->result.negate = ~this->result.negate;
2920
2921 return switch_order;
2922 }
2923
2924 void
2925 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
2926 st_dst_reg *l, st_src_reg *r,
2927 st_src_reg *cond, bool cond_swap)
2928 {
2929 if (type->is_record()) {
2930 for (unsigned int i = 0; i < type->length; i++) {
2931 emit_block_mov(ir, type->fields.structure[i].type, l, r,
2932 cond, cond_swap);
2933 }
2934 return;
2935 }
2936
2937 if (type->is_array()) {
2938 for (unsigned int i = 0; i < type->length; i++) {
2939 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
2940 }
2941 return;
2942 }
2943
2944 if (type->is_matrix()) {
2945 const struct glsl_type *vec_type;
2946
2947 vec_type = glsl_type::get_instance(type->is_double()
2948 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
2949 type->vector_elements, 1);
2950
2951 for (int i = 0; i < type->matrix_columns; i++) {
2952 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
2953 }
2954 return;
2955 }
2956
2957 assert(type->is_scalar() || type->is_vector());
2958
2959 l->type = type->base_type;
2960 r->type = type->base_type;
2961 if (cond) {
2962 st_src_reg l_src = st_src_reg(*l);
2963
2964 if (l_src.file == PROGRAM_OUTPUT &&
2965 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
2966 (l_src.index == FRAG_RESULT_DEPTH ||
2967 l_src.index == FRAG_RESULT_STENCIL)) {
2968 /* This is a special case because the source swizzles will be shifted
2969 * later to account for the difference between GLSL (where they're
2970 * plain floats) and TGSI (where they're Z and Y components). */
2971 l_src.swizzle = SWIZZLE_XXXX;
2972 }
2973
2974 if (native_integers) {
2975 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
2976 cond_swap ? l_src : *r,
2977 cond_swap ? *r : l_src);
2978 } else {
2979 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
2980 cond_swap ? l_src : *r,
2981 cond_swap ? *r : l_src);
2982 }
2983 } else {
2984 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
2985 }
2986 l->index++;
2987 r->index++;
2988 if (type->is_dual_slot()) {
2989 l->index++;
2990 if (r->is_double_vertex_input == false)
2991 r->index++;
2992 }
2993 }
2994
2995 void
2996 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
2997 {
2998 int dst_component;
2999 st_dst_reg l;
3000 st_src_reg r;
3001
3002 /* all generated instructions need to be flaged as precise */
3003 this->precise = is_precise(ir->lhs->variable_referenced());
3004 ir->rhs->accept(this);
3005 r = this->result;
3006
3007 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3008
3009 {
3010 int swizzles[4];
3011 int first_enabled_chan = 0;
3012 int rhs_chan = 0;
3013 ir_variable *variable = ir->lhs->variable_referenced();
3014
3015 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3016 variable->data.mode == ir_var_shader_out &&
3017 (variable->data.location == FRAG_RESULT_DEPTH ||
3018 variable->data.location == FRAG_RESULT_STENCIL)) {
3019 assert(ir->lhs->type->is_scalar());
3020 assert(ir->write_mask == WRITEMASK_X);
3021
3022 if (variable->data.location == FRAG_RESULT_DEPTH)
3023 l.writemask = WRITEMASK_Z;
3024 else {
3025 assert(variable->data.location == FRAG_RESULT_STENCIL);
3026 l.writemask = WRITEMASK_Y;
3027 }
3028 } else if (ir->write_mask == 0) {
3029 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3030
3031 unsigned num_elements =
3032 ir->lhs->type->without_array()->vector_elements;
3033
3034 if (num_elements) {
3035 l.writemask = u_bit_consecutive(0, num_elements);
3036 } else {
3037 /* The type is a struct or an array of (array of) structs. */
3038 l.writemask = WRITEMASK_XYZW;
3039 }
3040 } else {
3041 l.writemask = ir->write_mask;
3042 }
3043
3044 for (int i = 0; i < 4; i++) {
3045 if (l.writemask & (1 << i)) {
3046 first_enabled_chan = GET_SWZ(r.swizzle, i);
3047 break;
3048 }
3049 }
3050
3051 l.writemask = l.writemask << dst_component;
3052
3053 /* Swizzle a small RHS vector into the channels being written.
3054 *
3055 * glsl ir treats write_mask as dictating how many channels are
3056 * present on the RHS while TGSI treats write_mask as just
3057 * showing which channels of the vec4 RHS get written.
3058 */
3059 for (int i = 0; i < 4; i++) {
3060 if (l.writemask & (1 << i))
3061 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3062 else
3063 swizzles[i] = first_enabled_chan;
3064 }
3065 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3066 swizzles[2], swizzles[3]);
3067 }
3068
3069 assert(l.file != PROGRAM_UNDEFINED);
3070 assert(r.file != PROGRAM_UNDEFINED);
3071
3072 if (ir->condition) {
3073 const bool switch_order = this->process_move_condition(ir->condition);
3074 st_src_reg condition = this->result;
3075
3076 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3077 } else if (ir->rhs->as_expression() &&
3078 this->instructions.get_tail() &&
3079 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3080 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3081 type_size(ir->lhs->type) == 1 &&
3082 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3083 /* To avoid emitting an extra MOV when assigning an expression to a
3084 * variable, emit the last instruction of the expression again, but
3085 * replace the destination register with the target of the assignment.
3086 * Dead code elimination will remove the original instruction.
3087 */
3088 glsl_to_tgsi_instruction *inst, *new_inst;
3089 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3090 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3091 new_inst->saturate = inst->saturate;
3092 new_inst->resource = inst->resource;
3093 inst->dead_mask = inst->dst[0].writemask;
3094 } else {
3095 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3096 }
3097 this->precise = 0;
3098 }
3099
3100
3101 void
3102 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3103 {
3104 st_src_reg src;
3105 GLdouble stack_vals[4] = { 0 };
3106 gl_constant_value *values = (gl_constant_value *) stack_vals;
3107 GLenum gl_type = GL_NONE;
3108 unsigned int i;
3109 static int in_array = 0;
3110 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3111
3112 /* Unfortunately, 4 floats is all we can get into
3113 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3114 * aggregate constant and move each constant value into it. If we
3115 * get lucky, copy propagation will eliminate the extra moves.
3116 */
3117 if (ir->type->is_record()) {
3118 st_src_reg temp_base = get_temp(ir->type);
3119 st_dst_reg temp = st_dst_reg(temp_base);
3120
3121 for (i = 0; i < ir->type->length; i++) {
3122 ir_constant *const field_value = ir->get_record_field(i);
3123 int size = type_size(field_value->type);
3124
3125 assert(size > 0);
3126
3127 field_value->accept(this);
3128 src = this->result;
3129
3130 for (unsigned j = 0; j < (unsigned int)size; j++) {
3131 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3132
3133 src.index++;
3134 temp.index++;
3135 }
3136 }
3137 this->result = temp_base;
3138 return;
3139 }
3140
3141 if (ir->type->is_array()) {
3142 st_src_reg temp_base = get_temp(ir->type);
3143 st_dst_reg temp = st_dst_reg(temp_base);
3144 int size = type_size(ir->type->fields.array);
3145
3146 assert(size > 0);
3147 in_array++;
3148
3149 for (i = 0; i < ir->type->length; i++) {
3150 ir->const_elements[i]->accept(this);
3151 src = this->result;
3152 for (int j = 0; j < size; j++) {
3153 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3154
3155 src.index++;
3156 temp.index++;
3157 }
3158 }
3159 this->result = temp_base;
3160 in_array--;
3161 return;
3162 }
3163
3164 if (ir->type->is_matrix()) {
3165 st_src_reg mat = get_temp(ir->type);
3166 st_dst_reg mat_column = st_dst_reg(mat);
3167
3168 for (i = 0; i < ir->type->matrix_columns; i++) {
3169 switch (ir->type->base_type) {
3170 case GLSL_TYPE_FLOAT:
3171 values = (gl_constant_value *)
3172 &ir->value.f[i * ir->type->vector_elements];
3173
3174 src = st_src_reg(file, -1, ir->type->base_type);
3175 src.index = add_constant(file,
3176 values,
3177 ir->type->vector_elements,
3178 GL_FLOAT,
3179 &src.swizzle);
3180 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3181 break;
3182 case GLSL_TYPE_DOUBLE:
3183 values = (gl_constant_value *)
3184 &ir->value.d[i * ir->type->vector_elements];
3185 src = st_src_reg(file, -1, ir->type->base_type);
3186 src.index = add_constant(file,
3187 values,
3188 ir->type->vector_elements,
3189 GL_DOUBLE,
3190 &src.swizzle);
3191 if (ir->type->vector_elements >= 2) {
3192 mat_column.writemask = WRITEMASK_XY;
3193 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3194 SWIZZLE_X, SWIZZLE_Y);
3195 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3196 } else {
3197 mat_column.writemask = WRITEMASK_X;
3198 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3199 SWIZZLE_X, SWIZZLE_X);
3200 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3201 }
3202 src.index++;
3203 if (ir->type->vector_elements > 2) {
3204 if (ir->type->vector_elements == 4) {
3205 mat_column.writemask = WRITEMASK_ZW;
3206 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3207 SWIZZLE_X, SWIZZLE_Y);
3208 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3209 } else {
3210 mat_column.writemask = WRITEMASK_Z;
3211 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3212 SWIZZLE_Y, SWIZZLE_Y);
3213 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3214 mat_column.writemask = WRITEMASK_XYZW;
3215 src.swizzle = SWIZZLE_XYZW;
3216 }
3217 mat_column.index++;
3218 }
3219 break;
3220 default:
3221 unreachable("Illegal matrix constant type.\n");
3222 break;
3223 }
3224 mat_column.index++;
3225 }
3226 this->result = mat;
3227 return;
3228 }
3229
3230 switch (ir->type->base_type) {
3231 case GLSL_TYPE_FLOAT:
3232 gl_type = GL_FLOAT;
3233 for (i = 0; i < ir->type->vector_elements; i++) {
3234 values[i].f = ir->value.f[i];
3235 }
3236 break;
3237 case GLSL_TYPE_DOUBLE:
3238 gl_type = GL_DOUBLE;
3239 for (i = 0; i < ir->type->vector_elements; i++) {
3240 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3241 }
3242 break;
3243 case GLSL_TYPE_INT64:
3244 gl_type = GL_INT64_ARB;
3245 for (i = 0; i < ir->type->vector_elements; i++) {
3246 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3247 }
3248 break;
3249 case GLSL_TYPE_UINT64:
3250 gl_type = GL_UNSIGNED_INT64_ARB;
3251 for (i = 0; i < ir->type->vector_elements; i++) {
3252 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3253 }
3254 break;
3255 case GLSL_TYPE_UINT:
3256 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3257 for (i = 0; i < ir->type->vector_elements; i++) {
3258 if (native_integers)
3259 values[i].u = ir->value.u[i];
3260 else
3261 values[i].f = ir->value.u[i];
3262 }
3263 break;
3264 case GLSL_TYPE_INT:
3265 gl_type = native_integers ? GL_INT : GL_FLOAT;
3266 for (i = 0; i < ir->type->vector_elements; i++) {
3267 if (native_integers)
3268 values[i].i = ir->value.i[i];
3269 else
3270 values[i].f = ir->value.i[i];
3271 }
3272 break;
3273 case GLSL_TYPE_BOOL:
3274 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3275 for (i = 0; i < ir->type->vector_elements; i++) {
3276 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3277 }
3278 break;
3279 default:
3280 assert(!"Non-float/uint/int/bool constant");
3281 }
3282
3283 this->result = st_src_reg(file, -1, ir->type);
3284 this->result.index = add_constant(file,
3285 values,
3286 ir->type->vector_elements,
3287 gl_type,
3288 &this->result.swizzle);
3289 }
3290
3291 void
3292 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3293 {
3294 exec_node *param = ir->actual_parameters.get_head();
3295 ir_dereference *deref = static_cast<ir_dereference *>(param);
3296 ir_variable *location = deref->variable_referenced();
3297 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3298 /* Calculate the surface offset */
3299 st_src_reg offset;
3300 unsigned array_size = 0, base = 0;
3301 uint16_t index = 0;
3302 st_src_reg resource;
3303
3304 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3305
3306 if (has_hw_atomics) {
3307 variable_storage *entry = find_variable_storage(location);
3308 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3309 location->data.binding);
3310
3311 if (!entry) {
3312 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3313 num_atomics);
3314 _mesa_hash_table_insert(this->variables, location, entry);
3315
3316 atomic_info[num_atomics].location = location->data.location;
3317 atomic_info[num_atomics].binding = location->data.binding;
3318 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3319 if (atomic_info[num_atomics].size == 0)
3320 atomic_info[num_atomics].size = 1;
3321 atomic_info[num_atomics].array_id = 0;
3322 num_atomics++;
3323 }
3324
3325 if (offset.file != PROGRAM_UNDEFINED) {
3326 if (atomic_info[entry->index].array_id == 0) {
3327 num_atomic_arrays++;
3328 atomic_info[entry->index].array_id = num_atomic_arrays;
3329 }
3330 buffer.array_id = atomic_info[entry->index].array_id;
3331 }
3332
3333 buffer.index = index;
3334 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3335 buffer.has_index2 = true;
3336
3337 if (offset.file != PROGRAM_UNDEFINED) {
3338 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3339 *buffer.reladdr = offset;
3340 emit_arl(ir, sampler_reladdr, offset);
3341 }
3342 offset = st_src_reg_for_int(0);
3343
3344 resource = buffer;
3345 } else {
3346 st_src_reg buffer(PROGRAM_BUFFER, location->data.binding,
3347 GLSL_TYPE_ATOMIC_UINT);
3348
3349 if (offset.file != PROGRAM_UNDEFINED) {
3350 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3351 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3352 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3353 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3354 } else {
3355 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3356 }
3357 resource = buffer;
3358 }
3359
3360 ir->return_deref->accept(this);
3361 st_dst_reg dst(this->result);
3362 dst.writemask = WRITEMASK_X;
3363
3364 glsl_to_tgsi_instruction *inst;
3365
3366 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3367 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3368 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3369 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3370 st_src_reg_for_int(1));
3371 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3372 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3373 st_src_reg_for_int(-1));
3374 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3375 } else {
3376 param = param->get_next();
3377 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3378 val->accept(this);
3379
3380 st_src_reg data = this->result, data2 = undef_src;
3381 unsigned opcode;
3382 switch (ir->callee->intrinsic_id) {
3383 case ir_intrinsic_atomic_counter_add:
3384 opcode = TGSI_OPCODE_ATOMUADD;
3385 break;
3386 case ir_intrinsic_atomic_counter_min:
3387 opcode = TGSI_OPCODE_ATOMIMIN;
3388 break;
3389 case ir_intrinsic_atomic_counter_max:
3390 opcode = TGSI_OPCODE_ATOMIMAX;
3391 break;
3392 case ir_intrinsic_atomic_counter_and:
3393 opcode = TGSI_OPCODE_ATOMAND;
3394 break;
3395 case ir_intrinsic_atomic_counter_or:
3396 opcode = TGSI_OPCODE_ATOMOR;
3397 break;
3398 case ir_intrinsic_atomic_counter_xor:
3399 opcode = TGSI_OPCODE_ATOMXOR;
3400 break;
3401 case ir_intrinsic_atomic_counter_exchange:
3402 opcode = TGSI_OPCODE_ATOMXCHG;
3403 break;
3404 case ir_intrinsic_atomic_counter_comp_swap: {
3405 opcode = TGSI_OPCODE_ATOMCAS;
3406 param = param->get_next();
3407 val = ((ir_instruction *)param)->as_rvalue();
3408 val->accept(this);
3409 data2 = this->result;
3410 break;
3411 }
3412 default:
3413 assert(!"Unexpected intrinsic");
3414 return;
3415 }
3416
3417 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3418 }
3419
3420 inst->resource = resource;
3421 }
3422
3423 void
3424 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3425 {
3426 exec_node *param = ir->actual_parameters.get_head();
3427
3428 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3429
3430 param = param->get_next();
3431 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3432
3433 ir_constant *const_block = block->as_constant();
3434 int buf_base = st_context(ctx)->has_hw_atomics
3435 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
3436 st_src_reg buffer(
3437 PROGRAM_BUFFER,
3438 buf_base + (const_block ? const_block->value.u[0] : 0),
3439 GLSL_TYPE_UINT);
3440
3441 if (!const_block) {
3442 block->accept(this);
3443 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3444 *buffer.reladdr = this->result;
3445 emit_arl(ir, sampler_reladdr, this->result);
3446 }
3447
3448 /* Calculate the surface offset */
3449 offset->accept(this);
3450 st_src_reg off = this->result;
3451
3452 st_dst_reg dst = undef_dst;
3453 if (ir->return_deref) {
3454 ir->return_deref->accept(this);
3455 dst = st_dst_reg(this->result);
3456 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3457 }
3458
3459 glsl_to_tgsi_instruction *inst;
3460
3461 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3462 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3463 if (dst.type == GLSL_TYPE_BOOL)
3464 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3465 st_src_reg_for_int(0));
3466 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3467 param = param->get_next();
3468 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3469 val->accept(this);
3470
3471 param = param->get_next();
3472 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3473 assert(write_mask);
3474 dst.writemask = write_mask->value.u[0];
3475
3476 dst.type = this->result.type;
3477 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3478 } else {
3479 param = param->get_next();
3480 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3481 val->accept(this);
3482
3483 st_src_reg data = this->result, data2 = undef_src;
3484 unsigned opcode;
3485 switch (ir->callee->intrinsic_id) {
3486 case ir_intrinsic_ssbo_atomic_add:
3487 opcode = TGSI_OPCODE_ATOMUADD;
3488 break;
3489 case ir_intrinsic_ssbo_atomic_min:
3490 opcode = TGSI_OPCODE_ATOMIMIN;
3491 break;
3492 case ir_intrinsic_ssbo_atomic_max:
3493 opcode = TGSI_OPCODE_ATOMIMAX;
3494 break;
3495 case ir_intrinsic_ssbo_atomic_and:
3496 opcode = TGSI_OPCODE_ATOMAND;
3497 break;
3498 case ir_intrinsic_ssbo_atomic_or:
3499 opcode = TGSI_OPCODE_ATOMOR;
3500 break;
3501 case ir_intrinsic_ssbo_atomic_xor:
3502 opcode = TGSI_OPCODE_ATOMXOR;
3503 break;
3504 case ir_intrinsic_ssbo_atomic_exchange:
3505 opcode = TGSI_OPCODE_ATOMXCHG;
3506 break;
3507 case ir_intrinsic_ssbo_atomic_comp_swap:
3508 opcode = TGSI_OPCODE_ATOMCAS;
3509 param = param->get_next();
3510 val = ((ir_instruction *)param)->as_rvalue();
3511 val->accept(this);
3512 data2 = this->result;
3513 break;
3514 default:
3515 assert(!"Unexpected intrinsic");
3516 return;
3517 }
3518
3519 inst = emit_asm(ir, opcode, dst, off, data, data2);
3520 }
3521
3522 param = param->get_next();
3523 ir_constant *access = NULL;
3524 if (!param->is_tail_sentinel()) {
3525 access = ((ir_instruction *)param)->as_constant();
3526 assert(access);
3527 }
3528
3529 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3530 }
3531
3532 void
3533 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3534 {
3535 switch (ir->callee->intrinsic_id) {
3536 case ir_intrinsic_memory_barrier:
3537 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3538 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3539 TGSI_MEMBAR_ATOMIC_BUFFER |
3540 TGSI_MEMBAR_SHADER_IMAGE |
3541 TGSI_MEMBAR_SHARED));
3542 break;
3543 case ir_intrinsic_memory_barrier_atomic_counter:
3544 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3545 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3546 break;
3547 case ir_intrinsic_memory_barrier_buffer:
3548 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3549 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3550 break;
3551 case ir_intrinsic_memory_barrier_image:
3552 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3553 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3554 break;
3555 case ir_intrinsic_memory_barrier_shared:
3556 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3557 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3558 break;
3559 case ir_intrinsic_group_memory_barrier:
3560 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3561 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3562 TGSI_MEMBAR_ATOMIC_BUFFER |
3563 TGSI_MEMBAR_SHADER_IMAGE |
3564 TGSI_MEMBAR_SHARED |
3565 TGSI_MEMBAR_THREAD_GROUP));
3566 break;
3567 default:
3568 assert(!"Unexpected memory barrier intrinsic");
3569 }
3570 }
3571
3572 void
3573 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3574 {
3575 exec_node *param = ir->actual_parameters.get_head();
3576
3577 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3578
3579 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3580
3581 /* Calculate the surface offset */
3582 offset->accept(this);
3583 st_src_reg off = this->result;
3584
3585 st_dst_reg dst = undef_dst;
3586 if (ir->return_deref) {
3587 ir->return_deref->accept(this);
3588 dst = st_dst_reg(this->result);
3589 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3590 }
3591
3592 glsl_to_tgsi_instruction *inst;
3593
3594 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3595 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3596 inst->resource = buffer;
3597 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3598 param = param->get_next();
3599 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3600 val->accept(this);
3601
3602 param = param->get_next();
3603 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3604 assert(write_mask);
3605 dst.writemask = write_mask->value.u[0];
3606
3607 dst.type = this->result.type;
3608 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3609 inst->resource = buffer;
3610 } else {
3611 param = param->get_next();
3612 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3613 val->accept(this);
3614
3615 st_src_reg data = this->result, data2 = undef_src;
3616 unsigned opcode;
3617 switch (ir->callee->intrinsic_id) {
3618 case ir_intrinsic_shared_atomic_add:
3619 opcode = TGSI_OPCODE_ATOMUADD;
3620 break;
3621 case ir_intrinsic_shared_atomic_min:
3622 opcode = TGSI_OPCODE_ATOMIMIN;
3623 break;
3624 case ir_intrinsic_shared_atomic_max:
3625 opcode = TGSI_OPCODE_ATOMIMAX;
3626 break;
3627 case ir_intrinsic_shared_atomic_and:
3628 opcode = TGSI_OPCODE_ATOMAND;
3629 break;
3630 case ir_intrinsic_shared_atomic_or:
3631 opcode = TGSI_OPCODE_ATOMOR;
3632 break;
3633 case ir_intrinsic_shared_atomic_xor:
3634 opcode = TGSI_OPCODE_ATOMXOR;
3635 break;
3636 case ir_intrinsic_shared_atomic_exchange:
3637 opcode = TGSI_OPCODE_ATOMXCHG;
3638 break;
3639 case ir_intrinsic_shared_atomic_comp_swap:
3640 opcode = TGSI_OPCODE_ATOMCAS;
3641 param = param->get_next();
3642 val = ((ir_instruction *)param)->as_rvalue();
3643 val->accept(this);
3644 data2 = this->result;
3645 break;
3646 default:
3647 assert(!"Unexpected intrinsic");
3648 return;
3649 }
3650
3651 inst = emit_asm(ir, opcode, dst, off, data, data2);
3652 inst->resource = buffer;
3653 }
3654 }
3655
3656 static void
3657 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3658 bool *memory_coherent, bool *memory_volatile,
3659 bool *memory_restrict, unsigned *image_format)
3660 {
3661
3662 switch (ir->ir_type) {
3663 case ir_type_dereference_record: {
3664 ir_dereference_record *deref_record = ir->as_dereference_record();
3665 const glsl_type *struct_type = deref_record->record->type;
3666 int fild_idx = deref_record->field_idx;
3667
3668 *type = struct_type->fields.structure[fild_idx].type->without_array();
3669 *memory_coherent =
3670 struct_type->fields.structure[fild_idx].memory_coherent;
3671 *memory_volatile =
3672 struct_type->fields.structure[fild_idx].memory_volatile;
3673 *memory_restrict =
3674 struct_type->fields.structure[fild_idx].memory_restrict;
3675 *image_format =
3676 struct_type->fields.structure[fild_idx].image_format;
3677 break;
3678 }
3679
3680 case ir_type_dereference_array: {
3681 ir_dereference_array *deref_arr = ir->as_dereference_array();
3682 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3683 memory_coherent, memory_volatile, memory_restrict,
3684 image_format);
3685 break;
3686 }
3687
3688 case ir_type_dereference_variable: {
3689 ir_variable *var = ir->variable_referenced();
3690
3691 *type = var->type->without_array();
3692 *memory_coherent = var->data.memory_coherent;
3693 *memory_volatile = var->data.memory_volatile;
3694 *memory_restrict = var->data.memory_restrict;
3695 *image_format = var->data.image_format;
3696 break;
3697 }
3698
3699 default:
3700 break;
3701 }
3702 }
3703
3704 void
3705 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3706 {
3707 exec_node *param = ir->actual_parameters.get_head();
3708
3709 ir_dereference *img = (ir_dereference *)param;
3710 const ir_variable *imgvar = img->variable_referenced();
3711 unsigned sampler_array_size = 1, sampler_base = 0;
3712 bool memory_coherent = false, memory_volatile = false, memory_restrict = false;
3713 unsigned image_format = 0;
3714 const glsl_type *type = NULL;
3715
3716 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3717 &memory_restrict, &image_format);
3718
3719 st_src_reg reladdr;
3720 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3721 uint16_t index = 0;
3722 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3723 &index, &reladdr, !imgvar->contains_bindless());
3724
3725 image.index = index;
3726 if (reladdr.file != PROGRAM_UNDEFINED) {
3727 image.reladdr = ralloc(mem_ctx, st_src_reg);
3728 *image.reladdr = reladdr;
3729 emit_arl(ir, sampler_reladdr, reladdr);
3730 }
3731
3732 st_dst_reg dst = undef_dst;
3733 if (ir->return_deref) {
3734 ir->return_deref->accept(this);
3735 dst = st_dst_reg(this->result);
3736 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3737 }
3738
3739 glsl_to_tgsi_instruction *inst;
3740
3741 st_src_reg bindless;
3742 if (imgvar->contains_bindless()) {
3743 img->accept(this);
3744 bindless = this->result;
3745 }
3746
3747 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3748 dst.writemask = WRITEMASK_XYZ;
3749 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3750 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3751 st_src_reg res = get_temp(glsl_type::ivec4_type);
3752 st_dst_reg dstres = st_dst_reg(res);
3753 dstres.writemask = WRITEMASK_W;
3754 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3755 res.swizzle = SWIZZLE_WWWW;
3756 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3757 } else {
3758 st_src_reg arg1 = undef_src, arg2 = undef_src;
3759 st_src_reg coord;
3760 st_dst_reg coord_dst;
3761 coord = get_temp(glsl_type::ivec4_type);
3762 coord_dst = st_dst_reg(coord);
3763 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3764 param = param->get_next();
3765 ((ir_dereference *)param)->accept(this);
3766 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3767 coord.swizzle = SWIZZLE_XXXX;
3768 switch (type->coordinate_components()) {
3769 case 4: assert(!"unexpected coord count");
3770 /* fallthrough */
3771 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3772 /* fallthrough */
3773 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3774 }
3775
3776 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3777 param = param->get_next();
3778 ((ir_dereference *)param)->accept(this);
3779 st_src_reg sample = this->result;
3780 sample.swizzle = SWIZZLE_XXXX;
3781 coord_dst.writemask = WRITEMASK_W;
3782 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3783 coord.swizzle |= SWIZZLE_W << 9;
3784 }
3785
3786 param = param->get_next();
3787 if (!param->is_tail_sentinel()) {
3788 ((ir_dereference *)param)->accept(this);
3789 arg1 = this->result;
3790 param = param->get_next();
3791 }
3792
3793 if (!param->is_tail_sentinel()) {
3794 ((ir_dereference *)param)->accept(this);
3795 arg2 = this->result;
3796 param = param->get_next();
3797 }
3798
3799 assert(param->is_tail_sentinel());
3800
3801 unsigned opcode;
3802 switch (ir->callee->intrinsic_id) {
3803 case ir_intrinsic_image_load:
3804 opcode = TGSI_OPCODE_LOAD;
3805 break;
3806 case ir_intrinsic_image_store:
3807 opcode = TGSI_OPCODE_STORE;
3808 break;
3809 case ir_intrinsic_image_atomic_add:
3810 opcode = TGSI_OPCODE_ATOMUADD;
3811 break;
3812 case ir_intrinsic_image_atomic_min:
3813 opcode = TGSI_OPCODE_ATOMIMIN;
3814 break;
3815 case ir_intrinsic_image_atomic_max:
3816 opcode = TGSI_OPCODE_ATOMIMAX;
3817 break;
3818 case ir_intrinsic_image_atomic_and:
3819 opcode = TGSI_OPCODE_ATOMAND;
3820 break;
3821 case ir_intrinsic_image_atomic_or:
3822 opcode = TGSI_OPCODE_ATOMOR;
3823 break;
3824 case ir_intrinsic_image_atomic_xor:
3825 opcode = TGSI_OPCODE_ATOMXOR;
3826 break;
3827 case ir_intrinsic_image_atomic_exchange:
3828 opcode = TGSI_OPCODE_ATOMXCHG;
3829 break;
3830 case ir_intrinsic_image_atomic_comp_swap:
3831 opcode = TGSI_OPCODE_ATOMCAS;
3832 break;
3833 default:
3834 assert(!"Unexpected intrinsic");
3835 return;
3836 }
3837
3838 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3839 if (opcode == TGSI_OPCODE_STORE)
3840 inst->dst[0].writemask = WRITEMASK_XYZW;
3841 }
3842
3843 if (imgvar->contains_bindless()) {
3844 inst->resource = bindless;
3845 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3846 SWIZZLE_X, SWIZZLE_Y);
3847 } else {
3848 inst->resource = image;
3849 inst->sampler_array_size = sampler_array_size;
3850 inst->sampler_base = sampler_base;
3851 }
3852
3853 inst->tex_target = type->sampler_index();
3854 inst->image_format = st_mesa_format_to_pipe_format(st_context(ctx),
3855 _mesa_get_shader_image_format(image_format));
3856
3857 if (memory_coherent)
3858 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3859 if (memory_restrict)
3860 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3861 if (memory_volatile)
3862 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3863 }
3864
3865 void
3866 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, unsigned op)
3867 {
3868 ir->return_deref->accept(this);
3869 st_dst_reg dst = st_dst_reg(this->result);
3870
3871 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
3872
3873 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
3874 unsigned num_src = 0;
3875 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
3876 assert(num_src < ARRAY_SIZE(src));
3877
3878 this->result.file = PROGRAM_UNDEFINED;
3879 param->accept(this);
3880 assert(this->result.file != PROGRAM_UNDEFINED);
3881
3882 src[num_src] = this->result;
3883 num_src++;
3884 }
3885
3886 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
3887 }
3888
3889 void
3890 glsl_to_tgsi_visitor::visit(ir_call *ir)
3891 {
3892 ir_function_signature *sig = ir->callee;
3893
3894 /* Filter out intrinsics */
3895 switch (sig->intrinsic_id) {
3896 case ir_intrinsic_atomic_counter_read:
3897 case ir_intrinsic_atomic_counter_increment:
3898 case ir_intrinsic_atomic_counter_predecrement:
3899 case ir_intrinsic_atomic_counter_add:
3900 case ir_intrinsic_atomic_counter_min:
3901 case ir_intrinsic_atomic_counter_max:
3902 case ir_intrinsic_atomic_counter_and:
3903 case ir_intrinsic_atomic_counter_or:
3904 case ir_intrinsic_atomic_counter_xor:
3905 case ir_intrinsic_atomic_counter_exchange:
3906 case ir_intrinsic_atomic_counter_comp_swap:
3907 visit_atomic_counter_intrinsic(ir);
3908 return;
3909
3910 case ir_intrinsic_ssbo_load:
3911 case ir_intrinsic_ssbo_store:
3912 case ir_intrinsic_ssbo_atomic_add:
3913 case ir_intrinsic_ssbo_atomic_min:
3914 case ir_intrinsic_ssbo_atomic_max:
3915 case ir_intrinsic_ssbo_atomic_and:
3916 case ir_intrinsic_ssbo_atomic_or:
3917 case ir_intrinsic_ssbo_atomic_xor:
3918 case ir_intrinsic_ssbo_atomic_exchange:
3919 case ir_intrinsic_ssbo_atomic_comp_swap:
3920 visit_ssbo_intrinsic(ir);
3921 return;
3922
3923 case ir_intrinsic_memory_barrier:
3924 case ir_intrinsic_memory_barrier_atomic_counter:
3925 case ir_intrinsic_memory_barrier_buffer:
3926 case ir_intrinsic_memory_barrier_image:
3927 case ir_intrinsic_memory_barrier_shared:
3928 case ir_intrinsic_group_memory_barrier:
3929 visit_membar_intrinsic(ir);
3930 return;
3931
3932 case ir_intrinsic_shared_load:
3933 case ir_intrinsic_shared_store:
3934 case ir_intrinsic_shared_atomic_add:
3935 case ir_intrinsic_shared_atomic_min:
3936 case ir_intrinsic_shared_atomic_max:
3937 case ir_intrinsic_shared_atomic_and:
3938 case ir_intrinsic_shared_atomic_or:
3939 case ir_intrinsic_shared_atomic_xor:
3940 case ir_intrinsic_shared_atomic_exchange:
3941 case ir_intrinsic_shared_atomic_comp_swap:
3942 visit_shared_intrinsic(ir);
3943 return;
3944
3945 case ir_intrinsic_image_load:
3946 case ir_intrinsic_image_store:
3947 case ir_intrinsic_image_atomic_add:
3948 case ir_intrinsic_image_atomic_min:
3949 case ir_intrinsic_image_atomic_max:
3950 case ir_intrinsic_image_atomic_and:
3951 case ir_intrinsic_image_atomic_or:
3952 case ir_intrinsic_image_atomic_xor:
3953 case ir_intrinsic_image_atomic_exchange:
3954 case ir_intrinsic_image_atomic_comp_swap:
3955 case ir_intrinsic_image_size:
3956 case ir_intrinsic_image_samples:
3957 visit_image_intrinsic(ir);
3958 return;
3959
3960 case ir_intrinsic_shader_clock:
3961 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
3962 return;
3963
3964 case ir_intrinsic_vote_all:
3965 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
3966 return;
3967 case ir_intrinsic_vote_any:
3968 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
3969 return;
3970 case ir_intrinsic_vote_eq:
3971 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
3972 return;
3973 case ir_intrinsic_ballot:
3974 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
3975 return;
3976 case ir_intrinsic_read_first_invocation:
3977 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
3978 return;
3979 case ir_intrinsic_read_invocation:
3980 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
3981 return;
3982
3983 case ir_intrinsic_invalid:
3984 case ir_intrinsic_generic_load:
3985 case ir_intrinsic_generic_store:
3986 case ir_intrinsic_generic_atomic_add:
3987 case ir_intrinsic_generic_atomic_and:
3988 case ir_intrinsic_generic_atomic_or:
3989 case ir_intrinsic_generic_atomic_xor:
3990 case ir_intrinsic_generic_atomic_min:
3991 case ir_intrinsic_generic_atomic_max:
3992 case ir_intrinsic_generic_atomic_exchange:
3993 case ir_intrinsic_generic_atomic_comp_swap:
3994 unreachable("Invalid intrinsic");
3995 }
3996 }
3997
3998 void
3999 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4000 unsigned *array_elements,
4001 uint16_t *index,
4002 st_src_reg *indirect,
4003 unsigned *location)
4004 {
4005 switch (tail->ir_type) {
4006 case ir_type_dereference_record: {
4007 ir_dereference_record *deref_record = tail->as_dereference_record();
4008 const glsl_type *struct_type = deref_record->record->type;
4009 int field_index = deref_record->field_idx;
4010
4011 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4012
4013 assert(field_index >= 0);
4014 *location += struct_type->record_location_offset(field_index);
4015 break;
4016 }
4017
4018 case ir_type_dereference_array: {
4019 ir_dereference_array *deref_arr = tail->as_dereference_array();
4020
4021 void *mem_ctx = ralloc_parent(deref_arr);
4022 ir_constant *array_index =
4023 deref_arr->array_index->constant_expression_value(mem_ctx);
4024
4025 if (!array_index) {
4026 st_src_reg temp_reg;
4027 st_dst_reg temp_dst;
4028
4029 temp_reg = get_temp(glsl_type::uint_type);
4030 temp_dst = st_dst_reg(temp_reg);
4031 temp_dst.writemask = 1;
4032
4033 deref_arr->array_index->accept(this);
4034 if (*array_elements != 1)
4035 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4036 else
4037 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4038
4039 if (indirect->file == PROGRAM_UNDEFINED)
4040 *indirect = temp_reg;
4041 else {
4042 temp_dst = st_dst_reg(*indirect);
4043 temp_dst.writemask = 1;
4044 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4045 }
4046 } else
4047 *index += array_index->value.u[0] * *array_elements;
4048
4049 *array_elements *= deref_arr->array->type->length;
4050
4051 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4052 break;
4053 }
4054 default:
4055 break;
4056 }
4057 }
4058
4059 void
4060 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4061 unsigned *array_size,
4062 unsigned *base,
4063 uint16_t *index,
4064 st_src_reg *reladdr,
4065 bool opaque)
4066 {
4067 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4068 unsigned location = 0;
4069 ir_variable *var = ir->variable_referenced();
4070
4071 memset(reladdr, 0, sizeof(*reladdr));
4072 reladdr->file = PROGRAM_UNDEFINED;
4073
4074 *base = 0;
4075 *array_size = 1;
4076
4077 assert(var);
4078 location = var->data.location;
4079 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4080
4081 /*
4082 * If we end up with no indirect then adjust the base to the index,
4083 * and set the array size to 1.
4084 */
4085 if (reladdr->file == PROGRAM_UNDEFINED) {
4086 *base = *index;
4087 *array_size = 1;
4088 }
4089
4090 if (opaque) {
4091 assert(location != 0xffffffff);
4092 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4093 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4094 }
4095 }
4096
4097 st_src_reg
4098 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4099 {
4100 if (offset.reladdr || offset.reladdr2) {
4101 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4102 st_dst_reg tmp_dst = st_dst_reg(tmp);
4103 tmp_dst.writemask = WRITEMASK_XY;
4104 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4105 return tmp;
4106 }
4107
4108 return offset;
4109 }
4110
4111 void
4112 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4113 {
4114 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4115 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4116 st_src_reg levels_src, reladdr;
4117 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4118 glsl_to_tgsi_instruction *inst = NULL;
4119 unsigned opcode = TGSI_OPCODE_NOP;
4120 const glsl_type *sampler_type = ir->sampler->type;
4121 unsigned sampler_array_size = 1, sampler_base = 0;
4122 bool is_cube_array = false, is_cube_shadow = false;
4123 ir_variable *var = ir->sampler->variable_referenced();
4124 unsigned i;
4125
4126 /* if we are a cube array sampler or a cube shadow */
4127 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4128 is_cube_array = sampler_type->sampler_array;
4129 is_cube_shadow = sampler_type->sampler_shadow;
4130 }
4131
4132 if (ir->coordinate) {
4133 ir->coordinate->accept(this);
4134
4135 /* Put our coords in a temp. We'll need to modify them for shadow,
4136 * projection, or LOD, so the only case we'd use it as-is is if
4137 * we're doing plain old texturing. The optimization passes on
4138 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4139 */
4140 coord = get_temp(glsl_type::vec4_type);
4141 coord_dst = st_dst_reg(coord);
4142 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4143 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4144 }
4145
4146 if (ir->projector) {
4147 ir->projector->accept(this);
4148 projector = this->result;
4149 }
4150
4151 /* Storage for our result. Ideally for an assignment we'd be using
4152 * the actual storage for the result here, instead.
4153 */
4154 result_src = get_temp(ir->type);
4155 result_dst = st_dst_reg(result_src);
4156 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4157
4158 switch (ir->op) {
4159 case ir_tex:
4160 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4161 if (ir->offset) {
4162 ir->offset->accept(this);
4163 offset[0] = this->result;
4164 }
4165 break;
4166 case ir_txb:
4167 if (is_cube_array || is_cube_shadow) {
4168 opcode = TGSI_OPCODE_TXB2;
4169 }
4170 else {
4171 opcode = TGSI_OPCODE_TXB;
4172 }
4173 ir->lod_info.bias->accept(this);
4174 lod_info = this->result;
4175 if (ir->offset) {
4176 ir->offset->accept(this);
4177 offset[0] = this->result;
4178 }
4179 break;
4180 case ir_txl:
4181 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4182 opcode = TGSI_OPCODE_TEX_LZ;
4183 } else {
4184 opcode = is_cube_array ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4185 ir->lod_info.lod->accept(this);
4186 lod_info = this->result;
4187 }
4188 if (ir->offset) {
4189 ir->offset->accept(this);
4190 offset[0] = this->result;
4191 }
4192 break;
4193 case ir_txd:
4194 opcode = TGSI_OPCODE_TXD;
4195 ir->lod_info.grad.dPdx->accept(this);
4196 dx = this->result;
4197 ir->lod_info.grad.dPdy->accept(this);
4198 dy = this->result;
4199 if (ir->offset) {
4200 ir->offset->accept(this);
4201 offset[0] = this->result;
4202 }
4203 break;
4204 case ir_txs:
4205 opcode = TGSI_OPCODE_TXQ;
4206 ir->lod_info.lod->accept(this);
4207 lod_info = this->result;
4208 break;
4209 case ir_query_levels:
4210 opcode = TGSI_OPCODE_TXQ;
4211 lod_info = undef_src;
4212 levels_src = get_temp(ir->type);
4213 break;
4214 case ir_txf:
4215 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4216 opcode = TGSI_OPCODE_TXF_LZ;
4217 } else {
4218 opcode = TGSI_OPCODE_TXF;
4219 ir->lod_info.lod->accept(this);
4220 lod_info = this->result;
4221 }
4222 if (ir->offset) {
4223 ir->offset->accept(this);
4224 offset[0] = this->result;
4225 }
4226 break;
4227 case ir_txf_ms:
4228 opcode = TGSI_OPCODE_TXF;
4229 ir->lod_info.sample_index->accept(this);
4230 sample_index = this->result;
4231 break;
4232 case ir_tg4:
4233 opcode = TGSI_OPCODE_TG4;
4234 ir->lod_info.component->accept(this);
4235 component = this->result;
4236 if (ir->offset) {
4237 ir->offset->accept(this);
4238 if (ir->offset->type->is_array()) {
4239 const glsl_type *elt_type = ir->offset->type->fields.array;
4240 for (i = 0; i < ir->offset->type->length; i++) {
4241 offset[i] = this->result;
4242 offset[i].index += i * type_size(elt_type);
4243 offset[i].type = elt_type->base_type;
4244 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4245 offset[i] = canonicalize_gather_offset(offset[i]);
4246 }
4247 } else {
4248 offset[0] = canonicalize_gather_offset(this->result);
4249 }
4250 }
4251 break;
4252 case ir_lod:
4253 opcode = TGSI_OPCODE_LODQ;
4254 break;
4255 case ir_texture_samples:
4256 opcode = TGSI_OPCODE_TXQS;
4257 break;
4258 case ir_samples_identical:
4259 unreachable("Unexpected ir_samples_identical opcode");
4260 }
4261
4262 if (ir->projector) {
4263 if (opcode == TGSI_OPCODE_TEX) {
4264 /* Slot the projector in as the last component of the coord. */
4265 coord_dst.writemask = WRITEMASK_W;
4266 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4267 coord_dst.writemask = WRITEMASK_XYZW;
4268 opcode = TGSI_OPCODE_TXP;
4269 } else {
4270 st_src_reg coord_w = coord;
4271 coord_w.swizzle = SWIZZLE_WWWW;
4272
4273 /* For the other TEX opcodes there's no projective version
4274 * since the last slot is taken up by LOD info. Do the
4275 * projective divide now.
4276 */
4277 coord_dst.writemask = WRITEMASK_W;
4278 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4279
4280 /* In the case where we have to project the coordinates "by hand,"
4281 * the shadow comparator value must also be projected.
4282 */
4283 st_src_reg tmp_src = coord;
4284 if (ir->shadow_comparator) {
4285 /* Slot the shadow value in as the second to last component of the
4286 * coord.
4287 */
4288 ir->shadow_comparator->accept(this);
4289
4290 tmp_src = get_temp(glsl_type::vec4_type);
4291 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4292
4293 /* Projective division not allowed for array samplers. */
4294 assert(!sampler_type->sampler_array);
4295
4296 tmp_dst.writemask = WRITEMASK_Z;
4297 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4298
4299 tmp_dst.writemask = WRITEMASK_XY;
4300 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4301 }
4302
4303 coord_dst.writemask = WRITEMASK_XYZ;
4304 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4305
4306 coord_dst.writemask = WRITEMASK_XYZW;
4307 coord.swizzle = SWIZZLE_XYZW;
4308 }
4309 }
4310
4311 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4312 * shadow comparator was put in the correct place (and projected) by the
4313 * code, above, that handles by-hand projection.
4314 */
4315 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4316 /* Slot the shadow value in as the second to last component of the
4317 * coord.
4318 */
4319 ir->shadow_comparator->accept(this);
4320
4321 if (is_cube_array) {
4322 cube_sc = get_temp(glsl_type::float_type);
4323 cube_sc_dst = st_dst_reg(cube_sc);
4324 cube_sc_dst.writemask = WRITEMASK_X;
4325 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4326 cube_sc_dst.writemask = WRITEMASK_X;
4327 }
4328 else {
4329 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4330 sampler_type->sampler_array) ||
4331 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4332 coord_dst.writemask = WRITEMASK_W;
4333 } else {
4334 coord_dst.writemask = WRITEMASK_Z;
4335 }
4336 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4337 coord_dst.writemask = WRITEMASK_XYZW;
4338 }
4339 }
4340
4341 if (ir->op == ir_txf_ms) {
4342 coord_dst.writemask = WRITEMASK_W;
4343 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4344 coord_dst.writemask = WRITEMASK_XYZW;
4345 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4346 opcode == TGSI_OPCODE_TXF) {
4347 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4348 coord_dst.writemask = WRITEMASK_W;
4349 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4350 coord_dst.writemask = WRITEMASK_XYZW;
4351 }
4352
4353 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4354
4355 uint16_t index = 0;
4356 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4357 &index, &reladdr, !var->contains_bindless());
4358
4359 sampler.index = index;
4360 if (reladdr.file != PROGRAM_UNDEFINED) {
4361 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4362 *sampler.reladdr = reladdr;
4363 emit_arl(ir, sampler_reladdr, reladdr);
4364 }
4365
4366 st_src_reg bindless;
4367 if (var->contains_bindless()) {
4368 ir->sampler->accept(this);
4369 bindless = this->result;
4370 }
4371
4372 if (opcode == TGSI_OPCODE_TXD)
4373 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4374 else if (opcode == TGSI_OPCODE_TXQ) {
4375 if (ir->op == ir_query_levels) {
4376 /* the level is stored in W */
4377 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4378 result_dst.writemask = WRITEMASK_X;
4379 levels_src.swizzle = SWIZZLE_WWWW;
4380 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4381 } else
4382 inst = emit_asm(ir, opcode, result_dst, lod_info);
4383 } else if (opcode == TGSI_OPCODE_TXQS) {
4384 inst = emit_asm(ir, opcode, result_dst);
4385 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4386 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4387 } else if (opcode == TGSI_OPCODE_TEX2) {
4388 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4389 } else if (opcode == TGSI_OPCODE_TG4) {
4390 if (is_cube_array && ir->shadow_comparator) {
4391 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4392 } else {
4393 inst = emit_asm(ir, opcode, result_dst, coord, component);
4394 }
4395 } else
4396 inst = emit_asm(ir, opcode, result_dst, coord);
4397
4398 if (ir->shadow_comparator)
4399 inst->tex_shadow = GL_TRUE;
4400
4401 if (var->contains_bindless()) {
4402 inst->resource = bindless;
4403 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4404 SWIZZLE_X, SWIZZLE_Y);
4405 } else {
4406 inst->resource = sampler;
4407 inst->sampler_array_size = sampler_array_size;
4408 inst->sampler_base = sampler_base;
4409 }
4410
4411 if (ir->offset) {
4412 if (!inst->tex_offsets)
4413 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4414 MAX_GLSL_TEXTURE_OFFSET);
4415
4416 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4417 offset[i].file != PROGRAM_UNDEFINED; i++)
4418 inst->tex_offsets[i] = offset[i];
4419 inst->tex_offset_num_offset = i;
4420 }
4421
4422 inst->tex_target = sampler_type->sampler_index();
4423 inst->tex_type = ir->type->base_type;
4424
4425 this->result = result_src;
4426 }
4427
4428 void
4429 glsl_to_tgsi_visitor::visit(ir_return *ir)
4430 {
4431 assert(!ir->get_value());
4432
4433 emit_asm(ir, TGSI_OPCODE_RET);
4434 }
4435
4436 void
4437 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4438 {
4439 if (ir->condition) {
4440 ir->condition->accept(this);
4441 st_src_reg condition = this->result;
4442
4443 /* Convert the bool condition to a float so we can negate. */
4444 if (native_integers) {
4445 st_src_reg temp = get_temp(ir->condition->type);
4446 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4447 condition, st_src_reg_for_float(1.0));
4448 condition = temp;
4449 }
4450
4451 condition.negate = ~condition.negate;
4452 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4453 } else {
4454 /* unconditional kil */
4455 emit_asm(ir, TGSI_OPCODE_KILL);
4456 }
4457 }
4458
4459 void
4460 glsl_to_tgsi_visitor::visit(ir_if *ir)
4461 {
4462 unsigned if_opcode;
4463 glsl_to_tgsi_instruction *if_inst;
4464
4465 ir->condition->accept(this);
4466 assert(this->result.file != PROGRAM_UNDEFINED);
4467
4468 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4469
4470 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4471
4472 this->instructions.push_tail(if_inst);
4473
4474 visit_exec_list(&ir->then_instructions, this);
4475
4476 if (!ir->else_instructions.is_empty()) {
4477 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4478 visit_exec_list(&ir->else_instructions, this);
4479 }
4480
4481 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4482 }
4483
4484
4485 void
4486 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4487 {
4488 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4489
4490 ir->stream->accept(this);
4491 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4492 }
4493
4494 void
4495 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4496 {
4497 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4498
4499 ir->stream->accept(this);
4500 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4501 }
4502
4503 void
4504 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4505 {
4506 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4507 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4508
4509 emit_asm(ir, TGSI_OPCODE_BARRIER);
4510 }
4511
4512 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4513 {
4514 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4515
4516 result.file = PROGRAM_UNDEFINED;
4517 next_temp = 1;
4518 array_sizes = NULL;
4519 max_num_arrays = 0;
4520 next_array = 0;
4521 num_inputs = 0;
4522 num_outputs = 0;
4523 num_input_arrays = 0;
4524 num_output_arrays = 0;
4525 num_atomics = 0;
4526 num_atomic_arrays = 0;
4527 num_immediates = 0;
4528 num_address_regs = 0;
4529 samplers_used = 0;
4530 images_used = 0;
4531 indirect_addr_consts = false;
4532 wpos_transform_const = -1;
4533 native_integers = false;
4534 mem_ctx = ralloc_context(NULL);
4535 ctx = NULL;
4536 prog = NULL;
4537 precise = 0;
4538 shader_program = NULL;
4539 shader = NULL;
4540 options = NULL;
4541 have_sqrt = false;
4542 have_fma = false;
4543 use_shared_memory = false;
4544 has_tex_txf_lz = false;
4545 variables = NULL;
4546 }
4547
4548 static void var_destroy(struct hash_entry *entry)
4549 {
4550 variable_storage *storage = (variable_storage *)entry->data;
4551
4552 delete storage;
4553 }
4554
4555 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4556 {
4557 _mesa_hash_table_destroy(variables, var_destroy);
4558 free(array_sizes);
4559 ralloc_free(mem_ctx);
4560 }
4561
4562 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4563 {
4564 delete v;
4565 }
4566
4567
4568 /**
4569 * Count resources used by the given gpu program (number of texture
4570 * samplers, etc).
4571 */
4572 static void
4573 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4574 {
4575 v->samplers_used = 0;
4576 v->images_used = 0;
4577 prog->info.textures_used_by_txf = 0;
4578
4579 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4580 if (inst->info->is_tex) {
4581 for (int i = 0; i < inst->sampler_array_size; i++) {
4582 unsigned idx = inst->sampler_base + i;
4583 v->samplers_used |= 1u << idx;
4584
4585 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4586 v->sampler_types[idx] = inst->tex_type;
4587 v->sampler_targets[idx] =
4588 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4589
4590 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4591 prog->info.textures_used_by_txf |= 1u << idx;
4592 }
4593 }
4594 }
4595
4596 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4597 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4598
4599 if (inst->resource.file != PROGRAM_UNDEFINED && (
4600 is_resource_instruction(inst->op) ||
4601 inst->op == TGSI_OPCODE_STORE)) {
4602 if (inst->resource.file == PROGRAM_MEMORY) {
4603 v->use_shared_memory = true;
4604 } else if (inst->resource.file == PROGRAM_IMAGE) {
4605 for (int i = 0; i < inst->sampler_array_size; i++) {
4606 unsigned idx = inst->sampler_base + i;
4607 v->images_used |= 1 << idx;
4608 v->image_targets[idx] =
4609 st_translate_texture_target(inst->tex_target, false);
4610 v->image_formats[idx] = inst->image_format;
4611 }
4612 }
4613 }
4614 }
4615 prog->SamplersUsed = v->samplers_used;
4616
4617 if (v->shader_program != NULL)
4618 _mesa_update_shader_textures_used(v->shader_program, prog);
4619 }
4620
4621 /**
4622 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4623 * are read from the given src in this instruction
4624 */
4625 static int
4626 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4627 {
4628 int read_mask = 0, comp;
4629
4630 /* Now, given the src swizzle and the written channels, find which
4631 * components are actually read
4632 */
4633 for (comp = 0; comp < 4; ++comp) {
4634 const unsigned coord = GET_SWZ(src.swizzle, comp);
4635 assert(coord < 4);
4636 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4637 read_mask |= 1 << coord;
4638 }
4639
4640 return read_mask;
4641 }
4642
4643 /**
4644 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4645 * instruction is the first instruction to write to register T0. There are
4646 * several lowering passes done in GLSL IR (e.g. branches and
4647 * relative addressing) that create a large number of conditional assignments
4648 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4649 *
4650 * Here is why this conversion is safe:
4651 * CMP T0, T1 T2 T0 can be expanded to:
4652 * if (T1 < 0.0)
4653 * MOV T0, T2;
4654 * else
4655 * MOV T0, T0;
4656 *
4657 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4658 * as the original program. If (T1 < 0.0) evaluates to false, executing
4659 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4660 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4661 * because any instruction that was going to read from T0 after this was going
4662 * to read a garbage value anyway.
4663 */
4664 void
4665 glsl_to_tgsi_visitor::simplify_cmp(void)
4666 {
4667 int tempWritesSize = 0;
4668 unsigned *tempWrites = NULL;
4669 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4670
4671 memset(outputWrites, 0, sizeof(outputWrites));
4672
4673 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4674 unsigned prevWriteMask = 0;
4675
4676 /* Give up if we encounter relative addressing or flow control. */
4677 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4678 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4679 inst->info->is_branch ||
4680 inst->op == TGSI_OPCODE_CONT ||
4681 inst->op == TGSI_OPCODE_END ||
4682 inst->op == TGSI_OPCODE_RET) {
4683 break;
4684 }
4685
4686 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4687 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4688 prevWriteMask = outputWrites[inst->dst[0].index];
4689 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4690 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4691 if (inst->dst[0].index >= tempWritesSize) {
4692 const int inc = 4096;
4693
4694 tempWrites = (unsigned*)
4695 realloc(tempWrites,
4696 (tempWritesSize + inc) * sizeof(unsigned));
4697 if (!tempWrites)
4698 return;
4699
4700 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4701 tempWritesSize += inc;
4702 }
4703
4704 prevWriteMask = tempWrites[inst->dst[0].index];
4705 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4706 } else
4707 continue;
4708
4709 /* For a CMP to be considered a conditional write, the destination
4710 * register and source register two must be the same. */
4711 if (inst->op == TGSI_OPCODE_CMP
4712 && !(inst->dst[0].writemask & prevWriteMask)
4713 && inst->src[2].file == inst->dst[0].file
4714 && inst->src[2].index == inst->dst[0].index
4715 && inst->dst[0].writemask ==
4716 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4717
4718 inst->op = TGSI_OPCODE_MOV;
4719 inst->info = tgsi_get_opcode_info(inst->op);
4720 inst->src[0] = inst->src[1];
4721 }
4722 }
4723
4724 free(tempWrites);
4725 }
4726
4727 static void
4728 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4729 {
4730 if (src && src->file == PROGRAM_TEMPORARY) {
4731 int old_idx = src->index;
4732 if (renames[old_idx].valid)
4733 src->index = renames[old_idx].new_reg;
4734 }
4735 }
4736
4737 /* Replaces all references to a temporary register index with another index. */
4738 void
4739 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4740 {
4741 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4742 unsigned j;
4743 for (j = 0; j < num_inst_src_regs(inst); j++) {
4744 rename_temp_handle_src(renames, &inst->src[j]);
4745 rename_temp_handle_src(renames, inst->src[j].reladdr);
4746 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4747 }
4748
4749 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4750 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4751 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4752 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4753 }
4754
4755 rename_temp_handle_src(renames, &inst->resource);
4756 rename_temp_handle_src(renames, inst->resource.reladdr);
4757 rename_temp_handle_src(renames, inst->resource.reladdr2);
4758
4759 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4760 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4761 int old_idx = inst->dst[j].index;
4762 if (renames[old_idx].valid)
4763 inst->dst[j].index = renames[old_idx].new_reg;
4764 }
4765 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4766 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4767 }
4768 }
4769 }
4770
4771 void
4772 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4773 {
4774 int depth = 0; /* loop depth */
4775 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4776 unsigned i = 0, j;
4777
4778 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4779 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4780 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4781 if (first_writes[inst->dst[j].index] == -1)
4782 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4783 }
4784 }
4785
4786 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4787 if (depth++ == 0)
4788 loop_start = i;
4789 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4790 if (--depth == 0)
4791 loop_start = -1;
4792 }
4793 assert(depth >= 0);
4794 i++;
4795 }
4796 }
4797
4798 void
4799 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
4800 {
4801 int depth = 0; /* loop depth */
4802 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4803 unsigned i = 0, j;
4804
4805 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4806 for (j = 0; j < num_inst_src_regs(inst); j++) {
4807 if (inst->src[j].file == PROGRAM_TEMPORARY) {
4808 if (first_reads[inst->src[j].index] == -1)
4809 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
4810 }
4811 }
4812 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4813 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
4814 if (first_reads[inst->tex_offsets[j].index] == -1)
4815 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
4816 }
4817 }
4818 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4819 if (depth++ == 0)
4820 loop_start = i;
4821 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4822 if (--depth == 0)
4823 loop_start = -1;
4824 }
4825 assert(depth >= 0);
4826 i++;
4827 }
4828 }
4829
4830 void
4831 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
4832 {
4833 int depth = 0; /* loop depth */
4834 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4835 unsigned i = 0, j;
4836 int k;
4837 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4838 for (j = 0; j < num_inst_src_regs(inst); j++) {
4839 if (inst->src[j].file == PROGRAM_TEMPORARY)
4840 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
4841 }
4842 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4843 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4844 if (first_writes[inst->dst[j].index] == -1)
4845 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4846 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
4847 }
4848 }
4849 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4850 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
4851 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
4852 }
4853 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4854 if (depth++ == 0)
4855 loop_start = i;
4856 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4857 if (--depth == 0) {
4858 loop_start = -1;
4859 for (k = 0; k < this->next_temp; k++) {
4860 if (last_reads[k] == -2) {
4861 last_reads[k] = i;
4862 }
4863 }
4864 }
4865 }
4866 assert(depth >= 0);
4867 i++;
4868 }
4869 }
4870
4871 void
4872 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
4873 {
4874 int depth = 0; /* loop depth */
4875 int i = 0, k;
4876 unsigned j;
4877
4878 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4879 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4880 if (inst->dst[j].file == PROGRAM_TEMPORARY)
4881 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
4882 }
4883
4884 if (inst->op == TGSI_OPCODE_BGNLOOP)
4885 depth++;
4886 else if (inst->op == TGSI_OPCODE_ENDLOOP)
4887 if (--depth == 0) {
4888 for (k = 0; k < this->next_temp; k++) {
4889 if (last_writes[k] == -2) {
4890 last_writes[k] = i;
4891 }
4892 }
4893 }
4894 assert(depth >= 0);
4895 i++;
4896 }
4897 }
4898
4899 /*
4900 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4901 * channels for copy propagation and updates following instructions to
4902 * use the original versions.
4903 *
4904 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4905 * will occur. As an example, a TXP production before this pass:
4906 *
4907 * 0: MOV TEMP[1], INPUT[4].xyyy;
4908 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4909 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4910 *
4911 * and after:
4912 *
4913 * 0: MOV TEMP[1], INPUT[4].xyyy;
4914 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4915 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4916 *
4917 * which allows for dead code elimination on TEMP[1]'s writes.
4918 */
4919 void
4920 glsl_to_tgsi_visitor::copy_propagate(void)
4921 {
4922 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
4923 glsl_to_tgsi_instruction *,
4924 this->next_temp * 4);
4925 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
4926 int level = 0;
4927
4928 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4929 assert(inst->dst[0].file != PROGRAM_TEMPORARY
4930 || inst->dst[0].index < this->next_temp);
4931
4932 /* First, do any copy propagation possible into the src regs. */
4933 for (int r = 0; r < 3; r++) {
4934 glsl_to_tgsi_instruction *first = NULL;
4935 bool good = true;
4936 int acp_base = inst->src[r].index * 4;
4937
4938 if (inst->src[r].file != PROGRAM_TEMPORARY ||
4939 inst->src[r].reladdr ||
4940 inst->src[r].reladdr2)
4941 continue;
4942
4943 /* See if we can find entries in the ACP consisting of MOVs
4944 * from the same src register for all the swizzled channels
4945 * of this src register reference.
4946 */
4947 for (int i = 0; i < 4; i++) {
4948 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
4949 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
4950
4951 if (!copy_chan) {
4952 good = false;
4953 break;
4954 }
4955
4956 assert(acp_level[acp_base + src_chan] <= level);
4957
4958 if (!first) {
4959 first = copy_chan;
4960 } else {
4961 if (first->src[0].file != copy_chan->src[0].file ||
4962 first->src[0].index != copy_chan->src[0].index ||
4963 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
4964 first->src[0].index2D != copy_chan->src[0].index2D) {
4965 good = false;
4966 break;
4967 }
4968 }
4969 }
4970
4971 if (good) {
4972 /* We've now validated that we can copy-propagate to
4973 * replace this src register reference. Do it.
4974 */
4975 inst->src[r].file = first->src[0].file;
4976 inst->src[r].index = first->src[0].index;
4977 inst->src[r].index2D = first->src[0].index2D;
4978 inst->src[r].has_index2 = first->src[0].has_index2;
4979 inst->src[r].double_reg2 = first->src[0].double_reg2;
4980 inst->src[r].array_id = first->src[0].array_id;
4981
4982 int swizzle = 0;
4983 for (int i = 0; i < 4; i++) {
4984 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
4985 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
4986 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
4987 }
4988 inst->src[r].swizzle = swizzle;
4989 }
4990 }
4991
4992 switch (inst->op) {
4993 case TGSI_OPCODE_BGNLOOP:
4994 case TGSI_OPCODE_ENDLOOP:
4995 /* End of a basic block, clear the ACP entirely. */
4996 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
4997 break;
4998
4999 case TGSI_OPCODE_IF:
5000 case TGSI_OPCODE_UIF:
5001 ++level;
5002 break;
5003
5004 case TGSI_OPCODE_ENDIF:
5005 case TGSI_OPCODE_ELSE:
5006 /* Clear all channels written inside the block from the ACP, but
5007 * leaving those that were not touched.
5008 */
5009 for (int r = 0; r < this->next_temp; r++) {
5010 for (int c = 0; c < 4; c++) {
5011 if (!acp[4 * r + c])
5012 continue;
5013
5014 if (acp_level[4 * r + c] >= level)
5015 acp[4 * r + c] = NULL;
5016 }
5017 }
5018 if (inst->op == TGSI_OPCODE_ENDIF)
5019 --level;
5020 break;
5021
5022 default:
5023 /* Continuing the block, clear any written channels from
5024 * the ACP.
5025 */
5026 for (int d = 0; d < 2; d++) {
5027 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5028 /* Any temporary might be written, so no copy propagation
5029 * across this instruction.
5030 */
5031 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5032 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5033 inst->dst[d].reladdr) {
5034 /* Any output might be written, so no copy propagation
5035 * from outputs across this instruction.
5036 */
5037 for (int r = 0; r < this->next_temp; r++) {
5038 for (int c = 0; c < 4; c++) {
5039 if (!acp[4 * r + c])
5040 continue;
5041
5042 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5043 acp[4 * r + c] = NULL;
5044 }
5045 }
5046 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5047 inst->dst[d].file == PROGRAM_OUTPUT) {
5048 /* Clear where it's used as dst. */
5049 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5050 for (int c = 0; c < 4; c++) {
5051 if (inst->dst[d].writemask & (1 << c))
5052 acp[4 * inst->dst[d].index + c] = NULL;
5053 }
5054 }
5055
5056 /* Clear where it's used as src. */
5057 for (int r = 0; r < this->next_temp; r++) {
5058 for (int c = 0; c < 4; c++) {
5059 if (!acp[4 * r + c])
5060 continue;
5061
5062 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5063
5064 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5065 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5066 inst->dst[d].writemask & (1 << src_chan)) {
5067 acp[4 * r + c] = NULL;
5068 }
5069 }
5070 }
5071 }
5072 }
5073 break;
5074 }
5075
5076 /* If this is a copy, add it to the ACP. */
5077 if (inst->op == TGSI_OPCODE_MOV &&
5078 inst->dst[0].file == PROGRAM_TEMPORARY &&
5079 !(inst->dst[0].file == inst->src[0].file &&
5080 inst->dst[0].index == inst->src[0].index) &&
5081 !inst->dst[0].reladdr &&
5082 !inst->dst[0].reladdr2 &&
5083 !inst->saturate &&
5084 inst->src[0].file != PROGRAM_ARRAY &&
5085 (inst->src[0].file != PROGRAM_OUTPUT ||
5086 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5087 !inst->src[0].reladdr &&
5088 !inst->src[0].reladdr2 &&
5089 !inst->src[0].negate &&
5090 !inst->src[0].abs) {
5091 for (int i = 0; i < 4; i++) {
5092 if (inst->dst[0].writemask & (1 << i)) {
5093 acp[4 * inst->dst[0].index + i] = inst;
5094 acp_level[4 * inst->dst[0].index + i] = level;
5095 }
5096 }
5097 }
5098 }
5099
5100 ralloc_free(acp_level);
5101 ralloc_free(acp);
5102 }
5103
5104 static void
5105 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5106 {
5107 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5108 /* Clear where it's used as src. */
5109 int swz = GET_SWZ(reladdr->swizzle, 0);
5110 writes[4 * reladdr->index + swz] = NULL;
5111 }
5112 }
5113
5114 /*
5115 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5116 * code elimination.
5117 *
5118 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5119 * will occur. As an example, a TXP production after copy propagation but
5120 * before this pass:
5121 *
5122 * 0: MOV TEMP[1], INPUT[4].xyyy;
5123 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5124 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5125 *
5126 * and after this pass:
5127 *
5128 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5129 */
5130 int
5131 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5132 {
5133 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5134 glsl_to_tgsi_instruction *,
5135 this->next_temp * 4);
5136 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5137 int level = 0;
5138 int removed = 0;
5139
5140 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5141 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5142 || inst->dst[0].index < this->next_temp);
5143
5144 switch (inst->op) {
5145 case TGSI_OPCODE_BGNLOOP:
5146 case TGSI_OPCODE_ENDLOOP:
5147 case TGSI_OPCODE_CONT:
5148 case TGSI_OPCODE_BRK:
5149 /* End of a basic block, clear the write array entirely.
5150 *
5151 * This keeps us from killing dead code when the writes are
5152 * on either side of a loop, even when the register isn't touched
5153 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5154 * dead code of this type, so it shouldn't make a difference as long as
5155 * the dead code elimination pass in the GLSL compiler does its job.
5156 */
5157 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5158 break;
5159
5160 case TGSI_OPCODE_ENDIF:
5161 case TGSI_OPCODE_ELSE:
5162 /* Promote the recorded level of all channels written inside the
5163 * preceding if or else block to the level above the if/else block.
5164 */
5165 for (int r = 0; r < this->next_temp; r++) {
5166 for (int c = 0; c < 4; c++) {
5167 if (!writes[4 * r + c])
5168 continue;
5169
5170 if (write_level[4 * r + c] == level)
5171 write_level[4 * r + c] = level-1;
5172 }
5173 }
5174 if (inst->op == TGSI_OPCODE_ENDIF)
5175 --level;
5176 break;
5177
5178 case TGSI_OPCODE_IF:
5179 case TGSI_OPCODE_UIF:
5180 ++level;
5181 /* fallthrough to default case to mark the condition as read */
5182 default:
5183 /* Continuing the block, clear any channels from the write array that
5184 * are read by this instruction.
5185 */
5186 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5187 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5188 /* Any temporary might be read, so no dead code elimination
5189 * across this instruction.
5190 */
5191 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5192 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5193 /* Clear where it's used as src. */
5194 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5195 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5196 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5197 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5198
5199 for (int c = 0; c < 4; c++) {
5200 if (src_chans & (1 << c))
5201 writes[4 * inst->src[i].index + c] = NULL;
5202 }
5203 }
5204 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5205 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5206 }
5207 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5208 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5209 /* Any temporary might be read, so no dead code elimination
5210 * across this instruction.
5211 */
5212 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5213 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5214 /* Clear where it's used as src. */
5215 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5216 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5217 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5218 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5219
5220 for (int c = 0; c < 4; c++) {
5221 if (src_chans & (1 << c))
5222 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5223 }
5224 }
5225 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5226 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5227 }
5228
5229 if (inst->resource.file == PROGRAM_TEMPORARY) {
5230 int src_chans;
5231
5232 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5233 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5234 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5235 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5236
5237 for (int c = 0; c < 4; c++) {
5238 if (src_chans & (1 << c))
5239 writes[4 * inst->resource.index + c] = NULL;
5240 }
5241 }
5242 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5243 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5244
5245 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5246 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5247 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5248 }
5249 break;
5250 }
5251
5252 /* If this instruction writes to a temporary, add it to the write array.
5253 * If there is already an instruction in the write array for one or more
5254 * of the channels, flag that channel write as dead.
5255 */
5256 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5257 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5258 !inst->dst[i].reladdr) {
5259 for (int c = 0; c < 4; c++) {
5260 if (inst->dst[i].writemask & (1 << c)) {
5261 if (writes[4 * inst->dst[i].index + c]) {
5262 if (write_level[4 * inst->dst[i].index + c] < level)
5263 continue;
5264 else
5265 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5266 }
5267 writes[4 * inst->dst[i].index + c] = inst;
5268 write_level[4 * inst->dst[i].index + c] = level;
5269 }
5270 }
5271 }
5272 }
5273 }
5274
5275 /* Anything still in the write array at this point is dead code. */
5276 for (int r = 0; r < this->next_temp; r++) {
5277 for (int c = 0; c < 4; c++) {
5278 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5279 if (inst)
5280 inst->dead_mask |= (1 << c);
5281 }
5282 }
5283
5284 /* Now actually remove the instructions that are completely dead and update
5285 * the writemask of other instructions with dead channels.
5286 */
5287 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5288 if (!inst->dead_mask || !inst->dst[0].writemask)
5289 continue;
5290 /* No amount of dead masks should remove memory stores */
5291 if (inst->info->is_store)
5292 continue;
5293
5294 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5295 inst->remove();
5296 delete inst;
5297 removed++;
5298 } else {
5299 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5300 if (inst->dead_mask == WRITEMASK_XY ||
5301 inst->dead_mask == WRITEMASK_ZW)
5302 inst->dst[0].writemask &= ~(inst->dead_mask);
5303 } else
5304 inst->dst[0].writemask &= ~(inst->dead_mask);
5305 }
5306 }
5307
5308 ralloc_free(write_level);
5309 ralloc_free(writes);
5310
5311 return removed;
5312 }
5313
5314 /* merge DFRACEXP instructions into one. */
5315 void
5316 glsl_to_tgsi_visitor::merge_two_dsts(void)
5317 {
5318 /* We never delete inst, but we may delete its successor. */
5319 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5320 glsl_to_tgsi_instruction *inst2;
5321 unsigned defined;
5322
5323 if (num_inst_dst_regs(inst) != 2)
5324 continue;
5325
5326 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5327 inst->dst[1].file != PROGRAM_UNDEFINED)
5328 continue;
5329
5330 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5331 inst->dst[1].file != PROGRAM_UNDEFINED);
5332
5333 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5334 defined = 1;
5335 else
5336 defined = 0;
5337
5338 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5339 while (!inst2->is_tail_sentinel()) {
5340 if (inst->op == inst2->op &&
5341 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5342 inst->src[0].file == inst2->src[0].file &&
5343 inst->src[0].index == inst2->src[0].index &&
5344 inst->src[0].type == inst2->src[0].type &&
5345 inst->src[0].swizzle == inst2->src[0].swizzle)
5346 break;
5347 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5348 }
5349
5350 if (inst2->is_tail_sentinel()) {
5351 /* Undefined destinations are not allowed, substitute with an unused
5352 * temporary register.
5353 */
5354 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5355 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5356 inst->dst[defined ^ 1].writemask = 0;
5357 continue;
5358 }
5359
5360 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5361 inst2->remove();
5362 delete inst2;
5363 }
5364 }
5365
5366 /* Merges temporary registers together where possible to reduce the number of
5367 * registers needed to run a program.
5368 *
5369 * Produces optimal code only after copy propagation and dead code elimination
5370 * have been run. */
5371 void
5372 glsl_to_tgsi_visitor::merge_registers(void)
5373 {
5374 struct lifetime *lifetimes =
5375 rzalloc_array(mem_ctx, struct lifetime, this->next_temp);
5376
5377 if (get_temp_registers_required_lifetimes(mem_ctx, &this->instructions,
5378 this->next_temp, lifetimes)) {
5379 struct rename_reg_pair *renames =
5380 rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5381 get_temp_registers_remapping(mem_ctx, this->next_temp, lifetimes, renames);
5382 rename_temp_registers(renames);
5383 ralloc_free(renames);
5384 }
5385
5386 ralloc_free(lifetimes);
5387 }
5388
5389 /* Reassign indices to temporary registers by reusing unused indices created
5390 * by optimization passes. */
5391 void
5392 glsl_to_tgsi_visitor::renumber_registers(void)
5393 {
5394 int i = 0;
5395 int new_index = 0;
5396 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5397 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5398
5399 for (i = 0; i < this->next_temp; i++) {
5400 first_writes[i] = -1;
5401 }
5402 get_first_temp_write(first_writes);
5403
5404 for (i = 0; i < this->next_temp; i++) {
5405 if (first_writes[i] < 0) continue;
5406 if (i != new_index) {
5407 renames[i].new_reg = new_index;
5408 renames[i].valid = true;
5409 }
5410 new_index++;
5411 }
5412
5413 rename_temp_registers(renames);
5414 this->next_temp = new_index;
5415 ralloc_free(renames);
5416 ralloc_free(first_writes);
5417 }
5418
5419 /* ------------------------- TGSI conversion stuff -------------------------- */
5420
5421 /**
5422 * Intermediate state used during shader translation.
5423 */
5424 struct st_translate {
5425 struct ureg_program *ureg;
5426
5427 unsigned temps_size;
5428 struct ureg_dst *temps;
5429
5430 struct ureg_dst *arrays;
5431 unsigned num_temp_arrays;
5432 struct ureg_src *constants;
5433 int num_constants;
5434 struct ureg_src *immediates;
5435 int num_immediates;
5436 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5437 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5438 struct ureg_dst address[3];
5439 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5440 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5441 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5442 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5443 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5444 struct ureg_src shared_memory;
5445 unsigned *array_sizes;
5446 struct inout_decl *input_decls;
5447 unsigned num_input_decls;
5448 struct inout_decl *output_decls;
5449 unsigned num_output_decls;
5450
5451 const ubyte *inputMapping;
5452 const ubyte *outputMapping;
5453
5454 unsigned procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5455 bool need_uarl;
5456 };
5457
5458 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5459 enum tgsi_semantic
5460 _mesa_sysval_to_semantic(unsigned sysval)
5461 {
5462 switch (sysval) {
5463 /* Vertex shader */
5464 case SYSTEM_VALUE_VERTEX_ID:
5465 return TGSI_SEMANTIC_VERTEXID;
5466 case SYSTEM_VALUE_INSTANCE_ID:
5467 return TGSI_SEMANTIC_INSTANCEID;
5468 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
5469 return TGSI_SEMANTIC_VERTEXID_NOBASE;
5470 case SYSTEM_VALUE_BASE_VERTEX:
5471 return TGSI_SEMANTIC_BASEVERTEX;
5472 case SYSTEM_VALUE_BASE_INSTANCE:
5473 return TGSI_SEMANTIC_BASEINSTANCE;
5474 case SYSTEM_VALUE_DRAW_ID:
5475 return TGSI_SEMANTIC_DRAWID;
5476
5477 /* Geometry shader */
5478 case SYSTEM_VALUE_INVOCATION_ID:
5479 return TGSI_SEMANTIC_INVOCATIONID;
5480
5481 /* Fragment shader */
5482 case SYSTEM_VALUE_FRAG_COORD:
5483 return TGSI_SEMANTIC_POSITION;
5484 case SYSTEM_VALUE_FRONT_FACE:
5485 return TGSI_SEMANTIC_FACE;
5486 case SYSTEM_VALUE_SAMPLE_ID:
5487 return TGSI_SEMANTIC_SAMPLEID;
5488 case SYSTEM_VALUE_SAMPLE_POS:
5489 return TGSI_SEMANTIC_SAMPLEPOS;
5490 case SYSTEM_VALUE_SAMPLE_MASK_IN:
5491 return TGSI_SEMANTIC_SAMPLEMASK;
5492 case SYSTEM_VALUE_HELPER_INVOCATION:
5493 return TGSI_SEMANTIC_HELPER_INVOCATION;
5494
5495 /* Tessellation shader */
5496 case SYSTEM_VALUE_TESS_COORD:
5497 return TGSI_SEMANTIC_TESSCOORD;
5498 case SYSTEM_VALUE_VERTICES_IN:
5499 return TGSI_SEMANTIC_VERTICESIN;
5500 case SYSTEM_VALUE_PRIMITIVE_ID:
5501 return TGSI_SEMANTIC_PRIMID;
5502 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
5503 return TGSI_SEMANTIC_TESSOUTER;
5504 case SYSTEM_VALUE_TESS_LEVEL_INNER:
5505 return TGSI_SEMANTIC_TESSINNER;
5506
5507 /* Compute shader */
5508 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
5509 return TGSI_SEMANTIC_THREAD_ID;
5510 case SYSTEM_VALUE_WORK_GROUP_ID:
5511 return TGSI_SEMANTIC_BLOCK_ID;
5512 case SYSTEM_VALUE_NUM_WORK_GROUPS:
5513 return TGSI_SEMANTIC_GRID_SIZE;
5514 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
5515 return TGSI_SEMANTIC_BLOCK_SIZE;
5516
5517 /* ARB_shader_ballot */
5518 case SYSTEM_VALUE_SUBGROUP_SIZE:
5519 return TGSI_SEMANTIC_SUBGROUP_SIZE;
5520 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
5521 return TGSI_SEMANTIC_SUBGROUP_INVOCATION;
5522 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
5523 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
5524 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
5525 return TGSI_SEMANTIC_SUBGROUP_GE_MASK;
5526 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
5527 return TGSI_SEMANTIC_SUBGROUP_GT_MASK;
5528 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
5529 return TGSI_SEMANTIC_SUBGROUP_LE_MASK;
5530 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
5531 return TGSI_SEMANTIC_SUBGROUP_LT_MASK;
5532
5533 /* Unhandled */
5534 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
5535 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
5536 case SYSTEM_VALUE_VERTEX_CNT:
5537 default:
5538 assert(!"Unexpected SYSTEM_VALUE_ enum");
5539 return TGSI_SEMANTIC_COUNT;
5540 }
5541 }
5542
5543 /**
5544 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5545 */
5546 static struct ureg_src
5547 emit_immediate(struct st_translate *t,
5548 gl_constant_value values[4],
5549 GLenum type, int size)
5550 {
5551 struct ureg_program *ureg = t->ureg;
5552
5553 switch (type) {
5554 case GL_FLOAT:
5555 return ureg_DECL_immediate(ureg, &values[0].f, size);
5556 case GL_DOUBLE:
5557 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5558 case GL_INT64_ARB:
5559 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5560 case GL_UNSIGNED_INT64_ARB:
5561 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5562 case GL_INT:
5563 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5564 case GL_UNSIGNED_INT:
5565 case GL_BOOL:
5566 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5567 default:
5568 assert(!"should not get here - type must be float, int, uint, or bool");
5569 return ureg_src_undef();
5570 }
5571 }
5572
5573 /**
5574 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5575 */
5576 static struct ureg_dst
5577 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5578 unsigned array_id)
5579 {
5580 unsigned array;
5581
5582 switch (file) {
5583 case PROGRAM_UNDEFINED:
5584 return ureg_dst_undef();
5585
5586 case PROGRAM_TEMPORARY:
5587 /* Allocate space for temporaries on demand. */
5588 if (index >= t->temps_size) {
5589 const int inc = align(index - t->temps_size + 1, 4096);
5590
5591 t->temps = (struct ureg_dst*)
5592 realloc(t->temps,
5593 (t->temps_size + inc) * sizeof(struct ureg_dst));
5594 if (!t->temps)
5595 return ureg_dst_undef();
5596
5597 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5598 t->temps_size += inc;
5599 }
5600
5601 if (ureg_dst_is_undef(t->temps[index]))
5602 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5603
5604 return t->temps[index];
5605
5606 case PROGRAM_ARRAY:
5607 assert(array_id && array_id <= t->num_temp_arrays);
5608 array = array_id - 1;
5609
5610 if (ureg_dst_is_undef(t->arrays[array]))
5611 t->arrays[array] = ureg_DECL_array_temporary(
5612 t->ureg, t->array_sizes[array], TRUE);
5613
5614 return ureg_dst_array_offset(t->arrays[array], index);
5615
5616 case PROGRAM_OUTPUT:
5617 if (!array_id) {
5618 if (t->procType == PIPE_SHADER_FRAGMENT)
5619 assert(index < 2 * FRAG_RESULT_MAX);
5620 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5621 t->procType == PIPE_SHADER_TESS_EVAL)
5622 assert(index < VARYING_SLOT_TESS_MAX);
5623 else
5624 assert(index < VARYING_SLOT_MAX);
5625
5626 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5627 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5628 return t->outputs[t->outputMapping[index]];
5629 }
5630 else {
5631 struct inout_decl *decl =
5632 find_inout_array(t->output_decls,
5633 t->num_output_decls, array_id);
5634 unsigned mesa_index = decl->mesa_index;
5635 int slot = t->outputMapping[mesa_index];
5636
5637 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5638
5639 struct ureg_dst dst = t->outputs[slot];
5640 dst.ArrayID = array_id;
5641 return ureg_dst_array_offset(dst, index - mesa_index);
5642 }
5643
5644 case PROGRAM_ADDRESS:
5645 return t->address[index];
5646
5647 default:
5648 assert(!"unknown dst register file");
5649 return ureg_dst_undef();
5650 }
5651 }
5652
5653 static struct ureg_src
5654 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5655
5656 static struct ureg_src
5657 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5658 unsigned addr_index)
5659 {
5660 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5661 return ureg_src(t->address[addr_index]);
5662
5663 return translate_src(t, reladdr);
5664 }
5665
5666 /**
5667 * Create a TGSI ureg_dst register from an st_dst_reg.
5668 */
5669 static struct ureg_dst
5670 translate_dst(struct st_translate *t,
5671 const st_dst_reg *dst_reg,
5672 bool saturate)
5673 {
5674 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5675 dst_reg->array_id);
5676
5677 if (dst.File == TGSI_FILE_NULL)
5678 return dst;
5679
5680 dst = ureg_writemask(dst, dst_reg->writemask);
5681
5682 if (saturate)
5683 dst = ureg_saturate(dst);
5684
5685 if (dst_reg->reladdr != NULL) {
5686 assert(dst_reg->file != PROGRAM_TEMPORARY);
5687 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5688 }
5689
5690 if (dst_reg->has_index2) {
5691 if (dst_reg->reladdr2)
5692 dst = ureg_dst_dimension_indirect(dst,
5693 translate_addr(t, dst_reg->reladdr2, 1),
5694 dst_reg->index2D);
5695 else
5696 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5697 }
5698
5699 return dst;
5700 }
5701
5702 /**
5703 * Create a TGSI ureg_src register from an st_src_reg.
5704 */
5705 static struct ureg_src
5706 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5707 {
5708 struct ureg_src src;
5709 int index = src_reg->index;
5710 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5711
5712 switch (src_reg->file) {
5713 case PROGRAM_UNDEFINED:
5714 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5715 break;
5716
5717 case PROGRAM_TEMPORARY:
5718 case PROGRAM_ARRAY:
5719 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5720 src_reg->array_id));
5721 break;
5722
5723 case PROGRAM_OUTPUT: {
5724 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5725 src_reg->array_id);
5726 assert(dst.WriteMask != 0);
5727 unsigned shift = ffs(dst.WriteMask) - 1;
5728 src = ureg_swizzle(ureg_src(dst),
5729 shift,
5730 MIN2(shift + 1, 3),
5731 MIN2(shift + 2, 3),
5732 MIN2(shift + 3, 3));
5733 break;
5734 }
5735
5736 case PROGRAM_UNIFORM:
5737 assert(src_reg->index >= 0);
5738 src = src_reg->index < t->num_constants ?
5739 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
5740 break;
5741 case PROGRAM_STATE_VAR:
5742 case PROGRAM_CONSTANT: /* ie, immediate */
5743 if (src_reg->has_index2)
5744 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
5745 else
5746 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
5747 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
5748 break;
5749
5750 case PROGRAM_IMMEDIATE:
5751 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
5752 src = t->immediates[src_reg->index];
5753 break;
5754
5755 case PROGRAM_INPUT:
5756 /* GLSL inputs are 64-bit containers, so we have to
5757 * map back to the original index and add the offset after
5758 * mapping. */
5759 index -= double_reg2;
5760 if (!src_reg->array_id) {
5761 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
5762 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
5763 src = t->inputs[t->inputMapping[index] + double_reg2];
5764 }
5765 else {
5766 struct inout_decl *decl = find_inout_array(t->input_decls,
5767 t->num_input_decls,
5768 src_reg->array_id);
5769 unsigned mesa_index = decl->mesa_index;
5770 int slot = t->inputMapping[mesa_index];
5771
5772 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
5773
5774 src = t->inputs[slot];
5775 src.ArrayID = src_reg->array_id;
5776 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
5777 }
5778 break;
5779
5780 case PROGRAM_ADDRESS:
5781 src = ureg_src(t->address[src_reg->index]);
5782 break;
5783
5784 case PROGRAM_SYSTEM_VALUE:
5785 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
5786 src = t->systemValues[src_reg->index];
5787 break;
5788
5789 case PROGRAM_HW_ATOMIC:
5790 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
5791 src_reg->array_id);
5792 break;
5793
5794 default:
5795 assert(!"unknown src register file");
5796 return ureg_src_undef();
5797 }
5798
5799 if (src_reg->has_index2) {
5800 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5801 * and UBO constant buffers (buffer, position).
5802 */
5803 if (src_reg->reladdr2)
5804 src = ureg_src_dimension_indirect(src,
5805 translate_addr(t, src_reg->reladdr2, 1),
5806 src_reg->index2D);
5807 else
5808 src = ureg_src_dimension(src, src_reg->index2D);
5809 }
5810
5811 src = ureg_swizzle(src,
5812 GET_SWZ(src_reg->swizzle, 0) & 0x3,
5813 GET_SWZ(src_reg->swizzle, 1) & 0x3,
5814 GET_SWZ(src_reg->swizzle, 2) & 0x3,
5815 GET_SWZ(src_reg->swizzle, 3) & 0x3);
5816
5817 if (src_reg->abs)
5818 src = ureg_abs(src);
5819
5820 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
5821 src = ureg_negate(src);
5822
5823 if (src_reg->reladdr != NULL) {
5824 assert(src_reg->file != PROGRAM_TEMPORARY);
5825 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
5826 }
5827
5828 return src;
5829 }
5830
5831 static struct tgsi_texture_offset
5832 translate_tex_offset(struct st_translate *t,
5833 const st_src_reg *in_offset)
5834 {
5835 struct tgsi_texture_offset offset;
5836 struct ureg_src src = translate_src(t, in_offset);
5837
5838 offset.File = src.File;
5839 offset.Index = src.Index;
5840 offset.SwizzleX = src.SwizzleX;
5841 offset.SwizzleY = src.SwizzleY;
5842 offset.SwizzleZ = src.SwizzleZ;
5843 offset.Padding = 0;
5844
5845 assert(!src.Indirect);
5846 assert(!src.DimIndirect);
5847 assert(!src.Dimension);
5848 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
5849 assert(!src.Negate);
5850
5851 return offset;
5852 }
5853
5854 static void
5855 compile_tgsi_instruction(struct st_translate *t,
5856 const glsl_to_tgsi_instruction *inst)
5857 {
5858 struct ureg_program *ureg = t->ureg;
5859 int i;
5860 struct ureg_dst dst[2];
5861 struct ureg_src src[4];
5862 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
5863
5864 int num_dst;
5865 int num_src;
5866 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
5867
5868 num_dst = num_inst_dst_regs(inst);
5869 num_src = num_inst_src_regs(inst);
5870
5871 for (i = 0; i < num_dst; i++)
5872 dst[i] = translate_dst(t,
5873 &inst->dst[i],
5874 inst->saturate);
5875
5876 for (i = 0; i < num_src; i++)
5877 src[i] = translate_src(t, &inst->src[i]);
5878
5879 switch (inst->op) {
5880 case TGSI_OPCODE_BGNLOOP:
5881 case TGSI_OPCODE_ELSE:
5882 case TGSI_OPCODE_ENDLOOP:
5883 case TGSI_OPCODE_IF:
5884 case TGSI_OPCODE_UIF:
5885 assert(num_dst == 0);
5886 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
5887 return;
5888
5889 case TGSI_OPCODE_TEX:
5890 case TGSI_OPCODE_TEX_LZ:
5891 case TGSI_OPCODE_TXB:
5892 case TGSI_OPCODE_TXD:
5893 case TGSI_OPCODE_TXL:
5894 case TGSI_OPCODE_TXP:
5895 case TGSI_OPCODE_TXQ:
5896 case TGSI_OPCODE_TXQS:
5897 case TGSI_OPCODE_TXF:
5898 case TGSI_OPCODE_TXF_LZ:
5899 case TGSI_OPCODE_TEX2:
5900 case TGSI_OPCODE_TXB2:
5901 case TGSI_OPCODE_TXL2:
5902 case TGSI_OPCODE_TG4:
5903 case TGSI_OPCODE_LODQ:
5904 if (inst->resource.file == PROGRAM_SAMPLER) {
5905 src[num_src] = t->samplers[inst->resource.index];
5906 } else {
5907 /* Bindless samplers. */
5908 src[num_src] = translate_src(t, &inst->resource);
5909 }
5910 assert(src[num_src].File != TGSI_FILE_NULL);
5911 if (inst->resource.reladdr)
5912 src[num_src] =
5913 ureg_src_indirect(src[num_src],
5914 translate_addr(t, inst->resource.reladdr, 2));
5915 num_src++;
5916 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
5917 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
5918 }
5919 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5920
5921 ureg_tex_insn(ureg,
5922 inst->op,
5923 dst, num_dst,
5924 tex_target,
5925 st_translate_texture_type(inst->tex_type),
5926 texoffsets, inst->tex_offset_num_offset,
5927 src, num_src);
5928 return;
5929
5930 case TGSI_OPCODE_RESQ:
5931 case TGSI_OPCODE_LOAD:
5932 case TGSI_OPCODE_ATOMUADD:
5933 case TGSI_OPCODE_ATOMXCHG:
5934 case TGSI_OPCODE_ATOMCAS:
5935 case TGSI_OPCODE_ATOMAND:
5936 case TGSI_OPCODE_ATOMOR:
5937 case TGSI_OPCODE_ATOMXOR:
5938 case TGSI_OPCODE_ATOMUMIN:
5939 case TGSI_OPCODE_ATOMUMAX:
5940 case TGSI_OPCODE_ATOMIMIN:
5941 case TGSI_OPCODE_ATOMIMAX:
5942 for (i = num_src - 1; i >= 0; i--)
5943 src[i + 1] = src[i];
5944 num_src++;
5945 if (inst->resource.file == PROGRAM_MEMORY) {
5946 src[0] = t->shared_memory;
5947 } else if (inst->resource.file == PROGRAM_BUFFER) {
5948 src[0] = t->buffers[inst->resource.index];
5949 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
5950 src[0] = translate_src(t, &inst->resource);
5951 } else if (inst->resource.file == PROGRAM_CONSTANT) {
5952 assert(inst->resource.has_index2);
5953 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
5954 } else {
5955 assert(inst->resource.file != PROGRAM_UNDEFINED);
5956 if (inst->resource.file == PROGRAM_IMAGE) {
5957 src[0] = t->images[inst->resource.index];
5958 } else {
5959 /* Bindless images. */
5960 src[0] = translate_src(t, &inst->resource);
5961 }
5962 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5963 }
5964 if (inst->resource.reladdr)
5965 src[0] = ureg_src_indirect(src[0],
5966 translate_addr(t, inst->resource.reladdr, 2));
5967 assert(src[0].File != TGSI_FILE_NULL);
5968 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
5969 inst->buffer_access,
5970 tex_target, inst->image_format);
5971 break;
5972
5973 case TGSI_OPCODE_STORE:
5974 if (inst->resource.file == PROGRAM_MEMORY) {
5975 dst[0] = ureg_dst(t->shared_memory);
5976 } else if (inst->resource.file == PROGRAM_BUFFER) {
5977 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
5978 } else {
5979 if (inst->resource.file == PROGRAM_IMAGE) {
5980 dst[0] = ureg_dst(t->images[inst->resource.index]);
5981 } else {
5982 /* Bindless images. */
5983 dst[0] = ureg_dst(translate_src(t, &inst->resource));
5984 }
5985 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5986 }
5987 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
5988 if (inst->resource.reladdr)
5989 dst[0] = ureg_dst_indirect(dst[0],
5990 translate_addr(t, inst->resource.reladdr, 2));
5991 assert(dst[0].File != TGSI_FILE_NULL);
5992 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
5993 inst->buffer_access,
5994 tex_target, inst->image_format);
5995 break;
5996
5997 default:
5998 ureg_insn(ureg,
5999 inst->op,
6000 dst, num_dst,
6001 src, num_src, inst->precise);
6002 break;
6003 }
6004 }
6005
6006 /**
6007 * Emit the TGSI instructions for inverting and adjusting WPOS.
6008 * This code is unavoidable because it also depends on whether
6009 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6010 */
6011 static void
6012 emit_wpos_adjustment(struct gl_context *ctx,
6013 struct st_translate *t,
6014 int wpos_transform_const,
6015 boolean invert,
6016 GLfloat adjX, GLfloat adjY[2])
6017 {
6018 struct ureg_program *ureg = t->ureg;
6019
6020 assert(wpos_transform_const >= 0);
6021
6022 /* Fragment program uses fragment position input.
6023 * Need to replace instances of INPUT[WPOS] with temp T
6024 * where T = INPUT[WPOS] is inverted by Y.
6025 */
6026 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6027 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6028 struct ureg_src *wpos =
6029 ctx->Const.GLSLFragCoordIsSysVal ?
6030 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6031 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6032 struct ureg_src wpos_input = *wpos;
6033
6034 /* First, apply the coordinate shift: */
6035 if (adjX || adjY[0] || adjY[1]) {
6036 if (adjY[0] != adjY[1]) {
6037 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6038 * depending on whether inversion is actually going to be applied
6039 * or not, which is determined by testing against the inversion
6040 * state variable used below, which will be either +1 or -1.
6041 */
6042 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6043
6044 ureg_CMP(ureg, adj_temp,
6045 ureg_scalar(wpostrans, invert ? 2 : 0),
6046 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6047 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6048 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6049 } else {
6050 ureg_ADD(ureg, wpos_temp, wpos_input,
6051 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6052 }
6053 wpos_input = ureg_src(wpos_temp);
6054 } else {
6055 /* MOV wpos_temp, input[wpos]
6056 */
6057 ureg_MOV(ureg, wpos_temp, wpos_input);
6058 }
6059
6060 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6061 * inversion/identity, or the other way around if we're drawing to an FBO.
6062 */
6063 if (invert) {
6064 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6065 */
6066 ureg_MAD(ureg,
6067 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6068 wpos_input,
6069 ureg_scalar(wpostrans, 0),
6070 ureg_scalar(wpostrans, 1));
6071 } else {
6072 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6073 */
6074 ureg_MAD(ureg,
6075 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6076 wpos_input,
6077 ureg_scalar(wpostrans, 2),
6078 ureg_scalar(wpostrans, 3));
6079 }
6080
6081 /* Use wpos_temp as position input from here on:
6082 */
6083 *wpos = ureg_src(wpos_temp);
6084 }
6085
6086
6087 /**
6088 * Emit fragment position/ooordinate code.
6089 */
6090 static void
6091 emit_wpos(struct st_context *st,
6092 struct st_translate *t,
6093 const struct gl_program *program,
6094 struct ureg_program *ureg,
6095 int wpos_transform_const)
6096 {
6097 struct pipe_screen *pscreen = st->pipe->screen;
6098 GLfloat adjX = 0.0f;
6099 GLfloat adjY[2] = { 0.0f, 0.0f };
6100 boolean invert = FALSE;
6101
6102 /* Query the pixel center conventions supported by the pipe driver and set
6103 * adjX, adjY to help out if it cannot handle the requested one internally.
6104 *
6105 * The bias of the y-coordinate depends on whether y-inversion takes place
6106 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6107 * drawing to an FBO (causes additional inversion), and whether the pipe
6108 * driver origin and the requested origin differ (the latter condition is
6109 * stored in the 'invert' variable).
6110 *
6111 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6112 *
6113 * center shift only:
6114 * i -> h: +0.5
6115 * h -> i: -0.5
6116 *
6117 * inversion only:
6118 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6119 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6120 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6121 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6122 *
6123 * inversion and center shift:
6124 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6125 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6126 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6127 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6128 */
6129 if (program->OriginUpperLeft) {
6130 /* Fragment shader wants origin in upper-left */
6131 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6132 /* the driver supports upper-left origin */
6133 }
6134 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6135 /* the driver supports lower-left origin, need to invert Y */
6136 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6137 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6138 invert = TRUE;
6139 }
6140 else
6141 assert(0);
6142 }
6143 else {
6144 /* Fragment shader wants origin in lower-left */
6145 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6146 /* the driver supports lower-left origin */
6147 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6148 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6149 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6150 /* the driver supports upper-left origin, need to invert Y */
6151 invert = TRUE;
6152 else
6153 assert(0);
6154 }
6155
6156 if (program->PixelCenterInteger) {
6157 /* Fragment shader wants pixel center integer */
6158 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6159 /* the driver supports pixel center integer */
6160 adjY[1] = 1.0f;
6161 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6162 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6163 }
6164 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6165 /* the driver supports pixel center half integer, need to bias X,Y */
6166 adjX = -0.5f;
6167 adjY[0] = -0.5f;
6168 adjY[1] = 0.5f;
6169 }
6170 else
6171 assert(0);
6172 }
6173 else {
6174 /* Fragment shader wants pixel center half integer */
6175 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6176 /* the driver supports pixel center half integer */
6177 }
6178 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6179 /* the driver supports pixel center integer, need to bias X,Y */
6180 adjX = adjY[0] = adjY[1] = 0.5f;
6181 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6182 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6183 }
6184 else
6185 assert(0);
6186 }
6187
6188 /* we invert after adjustment so that we avoid the MOV to temporary,
6189 * and reuse the adjustment ADD instead */
6190 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6191 }
6192
6193 /**
6194 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6195 * TGSI uses +1 for front, -1 for back.
6196 * This function converts the TGSI value to the GL value. Simply clamping/
6197 * saturating the value to [0,1] does the job.
6198 */
6199 static void
6200 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6201 {
6202 struct ureg_program *ureg = t->ureg;
6203 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6204 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6205
6206 if (ctx->Const.NativeIntegers) {
6207 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6208 }
6209 else {
6210 /* MOV_SAT face_temp, input[face] */
6211 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6212 }
6213
6214 /* Use face_temp as face input from here on: */
6215 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6216 }
6217
6218 static void
6219 emit_compute_block_size(const struct gl_program *prog,
6220 struct ureg_program *ureg) {
6221 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6222 prog->info.cs.local_size[0]);
6223 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6224 prog->info.cs.local_size[1]);
6225 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6226 prog->info.cs.local_size[2]);
6227 }
6228
6229 struct sort_inout_decls {
6230 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6231 return mapping[a.mesa_index] < mapping[b.mesa_index];
6232 }
6233
6234 const ubyte *mapping;
6235 };
6236
6237 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6238 *
6239 * This is for the benefit of older drivers which are broken when the
6240 * declarations aren't sorted in this way.
6241 */
6242 static void
6243 sort_inout_decls_by_slot(struct inout_decl *decls,
6244 unsigned count,
6245 const ubyte mapping[])
6246 {
6247 sort_inout_decls sorter;
6248 sorter.mapping = mapping;
6249 std::sort(decls, decls + count, sorter);
6250 }
6251
6252 static enum tgsi_interpolate_mode
6253 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6254 {
6255 switch (glsl_qual) {
6256 case INTERP_MODE_NONE:
6257 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6258 return TGSI_INTERPOLATE_COLOR;
6259 return TGSI_INTERPOLATE_PERSPECTIVE;
6260 case INTERP_MODE_SMOOTH:
6261 return TGSI_INTERPOLATE_PERSPECTIVE;
6262 case INTERP_MODE_FLAT:
6263 return TGSI_INTERPOLATE_CONSTANT;
6264 case INTERP_MODE_NOPERSPECTIVE:
6265 return TGSI_INTERPOLATE_LINEAR;
6266 default:
6267 assert(0 && "unexpected interp mode in st_translate_interp()");
6268 return TGSI_INTERPOLATE_PERSPECTIVE;
6269 }
6270 }
6271
6272 /**
6273 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6274 * \param program the program to translate
6275 * \param numInputs number of input registers used
6276 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6277 * input indexes
6278 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6279 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6280 * each input
6281 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6282 * \param numOutputs number of output registers used
6283 * \param outputMapping maps Mesa fragment program outputs to TGSI
6284 * generic outputs
6285 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6286 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6287 * each output
6288 *
6289 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6290 */
6291 extern "C" enum pipe_error
6292 st_translate_program(
6293 struct gl_context *ctx,
6294 uint procType,
6295 struct ureg_program *ureg,
6296 glsl_to_tgsi_visitor *program,
6297 const struct gl_program *proginfo,
6298 GLuint numInputs,
6299 const ubyte inputMapping[],
6300 const ubyte inputSlotToAttr[],
6301 const ubyte inputSemanticName[],
6302 const ubyte inputSemanticIndex[],
6303 const ubyte interpMode[],
6304 GLuint numOutputs,
6305 const ubyte outputMapping[],
6306 const ubyte outputSemanticName[],
6307 const ubyte outputSemanticIndex[])
6308 {
6309 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6310 struct st_translate *t;
6311 unsigned i;
6312 struct gl_program_constants *frag_const =
6313 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6314 enum pipe_error ret = PIPE_OK;
6315
6316 assert(numInputs <= ARRAY_SIZE(t->inputs));
6317 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6318
6319 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6320 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6321 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6322 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6323 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6324 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6325 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6326 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6327 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op, TGSI_OPCODE_LAST - 1);
6328
6329 t = CALLOC_STRUCT(st_translate);
6330 if (!t) {
6331 ret = PIPE_ERROR_OUT_OF_MEMORY;
6332 goto out;
6333 }
6334
6335 t->procType = procType;
6336 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6337 t->inputMapping = inputMapping;
6338 t->outputMapping = outputMapping;
6339 t->ureg = ureg;
6340 t->num_temp_arrays = program->next_array;
6341 if (t->num_temp_arrays)
6342 t->arrays = (struct ureg_dst*)
6343 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6344
6345 /*
6346 * Declare input attributes.
6347 */
6348 switch (procType) {
6349 case PIPE_SHADER_FRAGMENT:
6350 case PIPE_SHADER_GEOMETRY:
6351 case PIPE_SHADER_TESS_EVAL:
6352 case PIPE_SHADER_TESS_CTRL:
6353 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6354
6355 for (i = 0; i < program->num_inputs; ++i) {
6356 struct inout_decl *decl = &program->inputs[i];
6357 unsigned slot = inputMapping[decl->mesa_index];
6358 struct ureg_src src;
6359 ubyte tgsi_usage_mask = decl->usage_mask;
6360
6361 if (glsl_base_type_is_64bit(decl->base_type)) {
6362 if (tgsi_usage_mask == 1)
6363 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6364 else if (tgsi_usage_mask == 2)
6365 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6366 else
6367 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6368 }
6369
6370 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6371 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6372 if (procType == PIPE_SHADER_FRAGMENT) {
6373 assert(interpMode);
6374 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6375 (enum tgsi_interpolate_mode) interpMode[slot] :
6376 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6377
6378 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6379 }
6380
6381 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6382 (enum tgsi_semantic) inputSemanticName[slot],
6383 inputSemanticIndex[slot],
6384 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6385 decl->array_id, decl->size);
6386
6387 for (unsigned j = 0; j < decl->size; ++j) {
6388 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6389 /* The ArrayID is set up in dst_register */
6390 t->inputs[slot + j] = src;
6391 t->inputs[slot + j].ArrayID = 0;
6392 t->inputs[slot + j].Index += j;
6393 }
6394 }
6395 }
6396 break;
6397 case PIPE_SHADER_VERTEX:
6398 for (i = 0; i < numInputs; i++) {
6399 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6400 }
6401 break;
6402 case PIPE_SHADER_COMPUTE:
6403 break;
6404 default:
6405 assert(0);
6406 }
6407
6408 /*
6409 * Declare output attributes.
6410 */
6411 switch (procType) {
6412 case PIPE_SHADER_FRAGMENT:
6413 case PIPE_SHADER_COMPUTE:
6414 break;
6415 case PIPE_SHADER_GEOMETRY:
6416 case PIPE_SHADER_TESS_EVAL:
6417 case PIPE_SHADER_TESS_CTRL:
6418 case PIPE_SHADER_VERTEX:
6419 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6420
6421 for (i = 0; i < program->num_outputs; ++i) {
6422 struct inout_decl *decl = &program->outputs[i];
6423 unsigned slot = outputMapping[decl->mesa_index];
6424 struct ureg_dst dst;
6425 ubyte tgsi_usage_mask = decl->usage_mask;
6426
6427 if (glsl_base_type_is_64bit(decl->base_type)) {
6428 if (tgsi_usage_mask == 1)
6429 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6430 else if (tgsi_usage_mask == 2)
6431 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6432 else
6433 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6434 }
6435
6436 dst = ureg_DECL_output_layout(ureg,
6437 (enum tgsi_semantic) outputSemanticName[slot],
6438 outputSemanticIndex[slot],
6439 decl->gs_out_streams,
6440 slot, tgsi_usage_mask, decl->array_id, decl->size);
6441
6442 for (unsigned j = 0; j < decl->size; ++j) {
6443 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6444 /* The ArrayID is set up in dst_register */
6445 t->outputs[slot + j] = dst;
6446 t->outputs[slot + j].ArrayID = 0;
6447 t->outputs[slot + j].Index += j;
6448 }
6449 }
6450 }
6451 break;
6452 default:
6453 assert(0);
6454 }
6455
6456 if (procType == PIPE_SHADER_FRAGMENT) {
6457 if (program->shader->Program->info.fs.early_fragment_tests ||
6458 program->shader->Program->info.fs.post_depth_coverage) {
6459 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6460
6461 if (program->shader->Program->info.fs.post_depth_coverage)
6462 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6463 }
6464
6465 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6466 /* Must do this after setting up t->inputs. */
6467 emit_wpos(st_context(ctx), t, proginfo, ureg,
6468 program->wpos_transform_const);
6469 }
6470
6471 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6472 emit_face_var(ctx, t);
6473
6474 for (i = 0; i < numOutputs; i++) {
6475 switch (outputSemanticName[i]) {
6476 case TGSI_SEMANTIC_POSITION:
6477 t->outputs[i] = ureg_DECL_output(ureg,
6478 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6479 outputSemanticIndex[i]);
6480 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6481 break;
6482 case TGSI_SEMANTIC_STENCIL:
6483 t->outputs[i] = ureg_DECL_output(ureg,
6484 TGSI_SEMANTIC_STENCIL, /* Stencil */
6485 outputSemanticIndex[i]);
6486 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6487 break;
6488 case TGSI_SEMANTIC_COLOR:
6489 t->outputs[i] = ureg_DECL_output(ureg,
6490 TGSI_SEMANTIC_COLOR,
6491 outputSemanticIndex[i]);
6492 break;
6493 case TGSI_SEMANTIC_SAMPLEMASK:
6494 t->outputs[i] = ureg_DECL_output(ureg,
6495 TGSI_SEMANTIC_SAMPLEMASK,
6496 outputSemanticIndex[i]);
6497 /* TODO: If we ever support more than 32 samples, this will have
6498 * to become an array.
6499 */
6500 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6501 break;
6502 default:
6503 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6504 ret = PIPE_ERROR_BAD_INPUT;
6505 goto out;
6506 }
6507 }
6508 }
6509 else if (procType == PIPE_SHADER_VERTEX) {
6510 for (i = 0; i < numOutputs; i++) {
6511 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6512 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6513 ureg_MOV(ureg,
6514 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6515 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6516 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6517 }
6518 }
6519 }
6520
6521 if (procType == PIPE_SHADER_COMPUTE) {
6522 emit_compute_block_size(proginfo, ureg);
6523 }
6524
6525 /* Declare address register.
6526 */
6527 if (program->num_address_regs > 0) {
6528 assert(program->num_address_regs <= 3);
6529 for (int i = 0; i < program->num_address_regs; i++)
6530 t->address[i] = ureg_DECL_address(ureg);
6531 }
6532
6533 /* Declare misc input registers
6534 */
6535 {
6536 GLbitfield sysInputs = proginfo->info.system_values_read;
6537
6538 for (i = 0; sysInputs; i++) {
6539 if (sysInputs & (1 << i)) {
6540 enum tgsi_semantic semName = _mesa_sysval_to_semantic(i);
6541
6542 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6543
6544 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6545 semName == TGSI_SEMANTIC_VERTEXID) {
6546 /* From Gallium perspective, these system values are always
6547 * integer, and require native integer support. However, if
6548 * native integer is supported on the vertex stage but not the
6549 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6550 * assumes these system values are floats. To resolve the
6551 * inconsistency, we insert a U2F.
6552 */
6553 struct st_context *st = st_context(ctx);
6554 struct pipe_screen *pscreen = st->pipe->screen;
6555 assert(procType == PIPE_SHADER_VERTEX);
6556 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6557 (void) pscreen;
6558 if (!ctx->Const.NativeIntegers) {
6559 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6560 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6561 t->systemValues[i]);
6562 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6563 }
6564 }
6565
6566 if (procType == PIPE_SHADER_FRAGMENT &&
6567 semName == TGSI_SEMANTIC_POSITION)
6568 emit_wpos(st_context(ctx), t, proginfo, ureg,
6569 program->wpos_transform_const);
6570
6571 sysInputs &= ~(1 << i);
6572 }
6573 }
6574 }
6575
6576 t->array_sizes = program->array_sizes;
6577 t->input_decls = program->inputs;
6578 t->num_input_decls = program->num_inputs;
6579 t->output_decls = program->outputs;
6580 t->num_output_decls = program->num_outputs;
6581
6582 /* Emit constants and uniforms. TGSI uses a single index space for these,
6583 * so we put all the translated regs in t->constants.
6584 */
6585 if (proginfo->Parameters) {
6586 t->constants = (struct ureg_src *)
6587 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6588 if (t->constants == NULL) {
6589 ret = PIPE_ERROR_OUT_OF_MEMORY;
6590 goto out;
6591 }
6592 t->num_constants = proginfo->Parameters->NumParameters;
6593
6594 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6595 switch (proginfo->Parameters->Parameters[i].Type) {
6596 case PROGRAM_STATE_VAR:
6597 case PROGRAM_UNIFORM:
6598 t->constants[i] = ureg_DECL_constant(ureg, i);
6599 break;
6600
6601 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6602 * addressing of the const buffer.
6603 * FIXME: Be smarter and recognize param arrays:
6604 * indirect addressing is only valid within the referenced
6605 * array.
6606 */
6607 case PROGRAM_CONSTANT:
6608 if (program->indirect_addr_consts)
6609 t->constants[i] = ureg_DECL_constant(ureg, i);
6610 else
6611 t->constants[i] = emit_immediate(t,
6612 proginfo->Parameters->ParameterValues[i],
6613 proginfo->Parameters->Parameters[i].DataType,
6614 4);
6615 break;
6616 default:
6617 break;
6618 }
6619 }
6620 }
6621
6622 for (i = 0; i < proginfo->info.num_ubos; i++) {
6623 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6624 unsigned num_const_vecs = (size + 15) / 16;
6625 unsigned first, last;
6626 assert(num_const_vecs > 0);
6627 first = 0;
6628 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6629 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6630 }
6631
6632 /* Emit immediate values.
6633 */
6634 t->immediates = (struct ureg_src *)
6635 calloc(program->num_immediates, sizeof(struct ureg_src));
6636 if (t->immediates == NULL) {
6637 ret = PIPE_ERROR_OUT_OF_MEMORY;
6638 goto out;
6639 }
6640 t->num_immediates = program->num_immediates;
6641
6642 i = 0;
6643 foreach_in_list(immediate_storage, imm, &program->immediates) {
6644 assert(i < program->num_immediates);
6645 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6646 }
6647 assert(i == program->num_immediates);
6648
6649 /* texture samplers */
6650 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6651 if (program->samplers_used & (1u << i)) {
6652 enum tgsi_return_type type =
6653 st_translate_texture_type(program->sampler_types[i]);
6654
6655 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6656
6657 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6658 type, type, type, type);
6659 }
6660 }
6661
6662 /* Declare atomic and shader storage buffers. */
6663 {
6664 struct gl_program *prog = program->prog;
6665
6666 if (!st_context(ctx)->has_hw_atomics) {
6667 for (i = 0; i < prog->info.num_abos; i++) {
6668 unsigned index = prog->sh.AtomicBuffers[i]->Binding;
6669 assert(index < frag_const->MaxAtomicBuffers);
6670 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6671 }
6672 } else {
6673 for (i = 0; i < program->num_atomics; i++) {
6674 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6675 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6676 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6677 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6678 ainfo->array_id);
6679 }
6680 }
6681
6682 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6683 for (i = 0; i < prog->info.num_ssbos; i++) {
6684 unsigned index = i;
6685 if (!st_context(ctx)->has_hw_atomics)
6686 index += frag_const->MaxAtomicBuffers;
6687
6688 t->buffers[index] = ureg_DECL_buffer(ureg, index, false);
6689 }
6690 }
6691
6692 if (program->use_shared_memory)
6693 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
6694
6695 for (i = 0; i < program->shader->Program->info.num_images; i++) {
6696 if (program->images_used & (1 << i)) {
6697 t->images[i] = ureg_DECL_image(ureg, i,
6698 program->image_targets[i],
6699 program->image_formats[i],
6700 true, false);
6701 }
6702 }
6703
6704 /* Emit each instruction in turn:
6705 */
6706 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
6707 compile_tgsi_instruction(t, inst);
6708
6709 /* Set the next shader stage hint for VS and TES. */
6710 switch (procType) {
6711 case PIPE_SHADER_VERTEX:
6712 case PIPE_SHADER_TESS_EVAL:
6713 if (program->shader_program->SeparateShader)
6714 break;
6715
6716 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
6717 if (program->shader_program->_LinkedShaders[i]) {
6718 ureg_set_next_shader_processor(
6719 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
6720 break;
6721 }
6722 }
6723 break;
6724 }
6725
6726 out:
6727 if (t) {
6728 free(t->arrays);
6729 free(t->temps);
6730 free(t->constants);
6731 t->num_constants = 0;
6732 free(t->immediates);
6733 t->num_immediates = 0;
6734 FREE(t);
6735 }
6736
6737 return ret;
6738 }
6739 /* ----------------------------- End TGSI code ------------------------------ */
6740
6741
6742 /**
6743 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6744 * generating Mesa IR.
6745 */
6746 static struct gl_program *
6747 get_mesa_program_tgsi(struct gl_context *ctx,
6748 struct gl_shader_program *shader_program,
6749 struct gl_linked_shader *shader)
6750 {
6751 glsl_to_tgsi_visitor* v;
6752 struct gl_program *prog;
6753 struct gl_shader_compiler_options *options =
6754 &ctx->Const.ShaderCompilerOptions[shader->Stage];
6755 struct pipe_screen *pscreen = ctx->st->pipe->screen;
6756 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
6757 unsigned skip_merge_registers;
6758
6759 validate_ir_tree(shader->ir);
6760
6761 prog = shader->Program;
6762
6763 prog->Parameters = _mesa_new_parameter_list();
6764 v = new glsl_to_tgsi_visitor();
6765 v->ctx = ctx;
6766 v->prog = prog;
6767 v->shader_program = shader_program;
6768 v->shader = shader;
6769 v->options = options;
6770 v->native_integers = ctx->Const.NativeIntegers;
6771
6772 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
6773 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
6774 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
6775 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
6776 v->has_tex_txf_lz = pscreen->get_param(pscreen,
6777 PIPE_CAP_TGSI_TEX_TXF_LZ);
6778 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6779
6780 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
6781 _mesa_key_pointer_equal);
6782 skip_merge_registers =
6783 pscreen->get_shader_param(pscreen, ptarget,
6784 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
6785
6786 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
6787 prog->Parameters);
6788
6789 /* Remove reads from output registers. */
6790 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
6791 lower_output_reads(shader->Stage, shader->ir);
6792
6793 /* Emit intermediate IR for main(). */
6794 visit_exec_list(shader->ir, v);
6795
6796 #if 0
6797 /* Print out some information (for debugging purposes) used by the
6798 * optimization passes. */
6799 {
6800 int i;
6801 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
6802 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
6803 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
6804 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
6805
6806 for (i = 0; i < v->next_temp; i++) {
6807 first_writes[i] = -1;
6808 first_reads[i] = -1;
6809 last_writes[i] = -1;
6810 last_reads[i] = -1;
6811 }
6812 v->get_first_temp_read(first_reads);
6813 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
6814 v->get_last_temp_write(last_writes);
6815 for (i = 0; i < v->next_temp; i++)
6816 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
6817 first_writes[i],
6818 last_reads[i],
6819 last_writes[i]);
6820 ralloc_free(first_writes);
6821 ralloc_free(first_reads);
6822 ralloc_free(last_writes);
6823 ralloc_free(last_reads);
6824 }
6825 #endif
6826
6827 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6828 v->simplify_cmp();
6829 v->copy_propagate();
6830
6831 while (v->eliminate_dead_code());
6832
6833 v->merge_two_dsts();
6834 if (!skip_merge_registers)
6835 v->merge_registers();
6836 v->renumber_registers();
6837
6838 /* Write the END instruction. */
6839 v->emit_asm(NULL, TGSI_OPCODE_END);
6840
6841 if (ctx->_Shader->Flags & GLSL_DUMP) {
6842 _mesa_log("\n");
6843 _mesa_log("GLSL IR for linked %s program %d:\n",
6844 _mesa_shader_stage_to_string(shader->Stage),
6845 shader_program->Name);
6846 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
6847 _mesa_log("\n\n");
6848 }
6849
6850 do_set_program_inouts(shader->ir, prog, shader->Stage);
6851 _mesa_copy_linked_program_data(shader_program, shader);
6852 shrink_array_declarations(v->inputs, v->num_inputs,
6853 &prog->info.inputs_read,
6854 prog->info.vs.double_inputs_read,
6855 &prog->info.patch_inputs_read);
6856 shrink_array_declarations(v->outputs, v->num_outputs,
6857 &prog->info.outputs_written, 0ULL,
6858 &prog->info.patch_outputs_written);
6859 count_resources(v, prog);
6860
6861 /* The GLSL IR won't be needed anymore. */
6862 ralloc_free(shader->ir);
6863 shader->ir = NULL;
6864
6865 /* This must be done before the uniform storage is associated. */
6866 if (shader->Stage == MESA_SHADER_FRAGMENT &&
6867 (prog->info.inputs_read & VARYING_BIT_POS ||
6868 prog->info.system_values_read & (1 << SYSTEM_VALUE_FRAG_COORD))) {
6869 static const gl_state_index wposTransformState[STATE_LENGTH] = {
6870 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
6871 };
6872
6873 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
6874 wposTransformState);
6875 }
6876
6877 /* Avoid reallocation of the program parameter list, because the uniform
6878 * storage is only associated with the original parameter list.
6879 * This should be enough for Bitmap and DrawPixels constants.
6880 */
6881 _mesa_reserve_parameter_storage(prog->Parameters, 8);
6882
6883 /* This has to be done last. Any operation the can cause
6884 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6885 * program constant) has to happen before creating this linkage.
6886 */
6887 _mesa_associate_uniform_storage(ctx, shader_program, prog, true);
6888 if (!shader_program->data->LinkStatus) {
6889 free_glsl_to_tgsi_visitor(v);
6890 _mesa_reference_program(ctx, &shader->Program, NULL);
6891 return NULL;
6892 }
6893
6894 struct st_vertex_program *stvp;
6895 struct st_fragment_program *stfp;
6896 struct st_common_program *stp;
6897 struct st_compute_program *stcp;
6898
6899 switch (shader->Stage) {
6900 case MESA_SHADER_VERTEX:
6901 stvp = (struct st_vertex_program *)prog;
6902 stvp->glsl_to_tgsi = v;
6903 break;
6904 case MESA_SHADER_FRAGMENT:
6905 stfp = (struct st_fragment_program *)prog;
6906 stfp->glsl_to_tgsi = v;
6907 break;
6908 case MESA_SHADER_TESS_CTRL:
6909 case MESA_SHADER_TESS_EVAL:
6910 case MESA_SHADER_GEOMETRY:
6911 stp = st_common_program(prog);
6912 stp->glsl_to_tgsi = v;
6913 break;
6914 case MESA_SHADER_COMPUTE:
6915 stcp = (struct st_compute_program *)prog;
6916 stcp->glsl_to_tgsi = v;
6917 break;
6918 default:
6919 assert(!"should not be reached");
6920 return NULL;
6921 }
6922
6923 return prog;
6924 }
6925
6926 /* See if there are unsupported control flow statements. */
6927 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
6928 private:
6929 const struct gl_shader_compiler_options *options;
6930 public:
6931 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
6932 : options(options),
6933 unsupported(false)
6934 {
6935 }
6936
6937 virtual ir_visitor_status visit_enter(ir_function *ir)
6938 {
6939 /* Other functions are skipped (same as glsl_to_tgsi). */
6940 if (strcmp(ir->name, "main") == 0)
6941 return visit_continue;
6942
6943 return visit_continue_with_parent;
6944 }
6945
6946 virtual ir_visitor_status visit_enter(ir_call *ir)
6947 {
6948 if (!ir->callee->is_intrinsic()) {
6949 unsupported = true; /* it's a function call */
6950 return visit_stop;
6951 }
6952 return visit_continue;
6953 }
6954
6955 virtual ir_visitor_status visit_enter(ir_return *ir)
6956 {
6957 if (options->EmitNoMainReturn) {
6958 unsupported = true;
6959 return visit_stop;
6960 }
6961 return visit_continue;
6962 }
6963
6964 bool unsupported;
6965 };
6966
6967 static bool
6968 has_unsupported_control_flow(exec_list *ir,
6969 const struct gl_shader_compiler_options *options)
6970 {
6971 ir_control_flow_info_visitor visitor(options);
6972 visit_list_elements(&visitor, ir);
6973 return visitor.unsupported;
6974 }
6975
6976 extern "C" {
6977
6978 /**
6979 * Link a shader.
6980 * Called via ctx->Driver.LinkShader()
6981 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6982 * with code lowering and other optimizations.
6983 */
6984 GLboolean
6985 st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
6986 {
6987 struct pipe_screen *pscreen = ctx->st->pipe->screen;
6988
6989 enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
6990 pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
6991 PIPE_SHADER_CAP_PREFERRED_IR);
6992 bool use_nir = preferred_ir == PIPE_SHADER_IR_NIR;
6993
6994 /* Return early if we are loading the shader from on-disk cache */
6995 if (st_load_ir_from_disk_cache(ctx, prog, use_nir)) {
6996 return GL_TRUE;
6997 }
6998
6999 assert(prog->data->LinkStatus);
7000
7001 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7002 if (prog->_LinkedShaders[i] == NULL)
7003 continue;
7004
7005 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7006 exec_list *ir = shader->ir;
7007 gl_shader_stage stage = shader->Stage;
7008 const struct gl_shader_compiler_options *options =
7009 &ctx->Const.ShaderCompilerOptions[stage];
7010 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7011 bool have_dround = pscreen->get_shader_param(pscreen, ptarget,
7012 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED);
7013 bool have_dfrexp = pscreen->get_shader_param(pscreen, ptarget,
7014 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED);
7015 bool have_ldexp = pscreen->get_shader_param(pscreen, ptarget,
7016 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED);
7017 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7018 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7019
7020 /* If there are forms of indirect addressing that the driver
7021 * cannot handle, perform the lowering pass.
7022 */
7023 if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput ||
7024 options->EmitNoIndirectTemp || options->EmitNoIndirectUniform) {
7025 lower_variable_index_to_cond_assign(stage, ir,
7026 options->EmitNoIndirectInput,
7027 options->EmitNoIndirectOutput,
7028 options->EmitNoIndirectTemp,
7029 options->EmitNoIndirectUniform);
7030 }
7031
7032 if (!pscreen->get_param(pscreen, PIPE_CAP_INT64_DIVMOD))
7033 lower_64bit_integer_instructions(ir, DIV64 | MOD64);
7034
7035 if (ctx->Extensions.ARB_shading_language_packing) {
7036 unsigned lower_inst = LOWER_PACK_SNORM_2x16 |
7037 LOWER_UNPACK_SNORM_2x16 |
7038 LOWER_PACK_UNORM_2x16 |
7039 LOWER_UNPACK_UNORM_2x16 |
7040 LOWER_PACK_SNORM_4x8 |
7041 LOWER_UNPACK_SNORM_4x8 |
7042 LOWER_UNPACK_UNORM_4x8 |
7043 LOWER_PACK_UNORM_4x8;
7044
7045 if (ctx->Extensions.ARB_gpu_shader5)
7046 lower_inst |= LOWER_PACK_USE_BFI |
7047 LOWER_PACK_USE_BFE;
7048 if (!ctx->st->has_half_float_packing)
7049 lower_inst |= LOWER_PACK_HALF_2x16 |
7050 LOWER_UNPACK_HALF_2x16;
7051
7052 lower_packing_builtins(ir, lower_inst);
7053 }
7054
7055 if (!pscreen->get_param(pscreen, PIPE_CAP_TEXTURE_GATHER_OFFSETS))
7056 lower_offset_arrays(ir);
7057 do_mat_op_to_vec(ir);
7058
7059 if (stage == MESA_SHADER_FRAGMENT)
7060 lower_blend_equation_advanced(shader);
7061
7062 lower_instructions(ir,
7063 MOD_TO_FLOOR |
7064 FDIV_TO_MUL_RCP |
7065 EXP_TO_EXP2 |
7066 LOG_TO_LOG2 |
7067 (have_ldexp ? 0 : LDEXP_TO_ARITH) |
7068 (have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) |
7069 CARRY_TO_ARITH |
7070 BORROW_TO_ARITH |
7071 (have_dround ? 0 : DOPS_TO_DFRAC) |
7072 (options->EmitNoPow ? POW_TO_EXP2 : 0) |
7073 (!ctx->Const.NativeIntegers ? INT_DIV_TO_MUL_RCP : 0) |
7074 (options->EmitNoSat ? SAT_TO_CLAMP : 0) |
7075 (ctx->Const.ForceGLSLAbsSqrt ? SQRT_TO_ABS_SQRT : 0) |
7076 /* Assume that if ARB_gpu_shader5 is not supported
7077 * then all of the extended integer functions need
7078 * lowering. It may be necessary to add some caps
7079 * for individual instructions.
7080 */
7081 (!ctx->Extensions.ARB_gpu_shader5
7082 ? BIT_COUNT_TO_MATH |
7083 EXTRACT_TO_SHIFTS |
7084 INSERT_TO_SHIFTS |
7085 REVERSE_TO_SHIFTS |
7086 FIND_LSB_TO_FLOAT_CAST |
7087 FIND_MSB_TO_FLOAT_CAST |
7088 IMUL_HIGH_TO_MUL
7089 : 0));
7090
7091 do_vec_index_to_cond_assign(ir);
7092 lower_vector_insert(ir, true);
7093 lower_quadop_vector(ir, false);
7094 lower_noise(ir);
7095 if (options->MaxIfDepth == 0) {
7096 lower_discard(ir);
7097 }
7098
7099 if (ctx->Const.GLSLOptimizeConservatively) {
7100 /* Do it once and repeat only if there's unsupported control flow. */
7101 do {
7102 do_common_optimization(ir, true, true, options,
7103 ctx->Const.NativeIntegers);
7104 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7105 options->MaxIfDepth, if_threshold);
7106 } while (has_unsupported_control_flow(ir, options));
7107 } else {
7108 /* Repeat it until it stops making changes. */
7109 bool progress;
7110 do {
7111 progress = do_common_optimization(ir, true, true, options,
7112 ctx->Const.NativeIntegers);
7113 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7114 options->MaxIfDepth, if_threshold);
7115 } while (progress);
7116 }
7117
7118 validate_ir_tree(ir);
7119 }
7120
7121 build_program_resource_list(ctx, prog);
7122
7123 if (use_nir)
7124 return st_link_nir(ctx, prog);
7125
7126 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7127 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7128 if (shader == NULL)
7129 continue;
7130
7131 struct gl_program *linked_prog =
7132 get_mesa_program_tgsi(ctx, prog, shader);
7133 st_set_prog_affected_state_flags(linked_prog);
7134
7135 if (linked_prog) {
7136 if (!ctx->Driver.ProgramStringNotify(ctx,
7137 _mesa_shader_stage_to_program(i),
7138 linked_prog)) {
7139 _mesa_reference_program(ctx, &shader->Program, NULL);
7140 return GL_FALSE;
7141 }
7142 }
7143 }
7144
7145 return GL_TRUE;
7146 }
7147
7148 void
7149 st_translate_stream_output_info(glsl_to_tgsi_visitor *glsl_to_tgsi,
7150 const ubyte outputMapping[],
7151 struct pipe_stream_output_info *so)
7152 {
7153 if (!glsl_to_tgsi->shader_program->last_vert_prog)
7154 return;
7155
7156 struct gl_transform_feedback_info *info =
7157 glsl_to_tgsi->shader_program->last_vert_prog->sh.LinkedTransformFeedback;
7158 st_translate_stream_output_info2(info, outputMapping, so);
7159 }
7160
7161 void
7162 st_translate_stream_output_info2(struct gl_transform_feedback_info *info,
7163 const ubyte outputMapping[],
7164 struct pipe_stream_output_info *so)
7165 {
7166 unsigned i;
7167
7168 for (i = 0; i < info->NumOutputs; i++) {
7169 so->output[i].register_index =
7170 outputMapping[info->Outputs[i].OutputRegister];
7171 so->output[i].start_component = info->Outputs[i].ComponentOffset;
7172 so->output[i].num_components = info->Outputs[i].NumComponents;
7173 so->output[i].output_buffer = info->Outputs[i].OutputBuffer;
7174 so->output[i].dst_offset = info->Outputs[i].DstOffset;
7175 so->output[i].stream = info->Outputs[i].StreamId;
7176 }
7177
7178 for (i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
7179 so->stride[i] = info->Buffers[i].Stride;
7180 }
7181 so->num_outputs = info->NumOutputs;
7182 }
7183
7184 } /* extern "C" */