2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_to_tgsi_temprename.h"
57 #include "util/hash_table.h"
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
64 #define MAX_GLSL_TEXTURE_OFFSET 4
67 #include "util/u_atomic.h"
68 #include "util/simple_mtx.h"
72 /* Prepare to make it possible to specify log file */
73 static std::ofstream stats_log
;
75 /* Helper function to check whether we want to write some statistics
76 * of the shader conversion.
79 static simple_mtx_t print_stats_mutex
= _SIMPLE_MTX_INITIALIZER_NP
;
81 static inline bool print_stats_enabled ()
83 static int stats_enabled
= 0;
86 simple_mtx_lock(&print_stats_mutex
);
88 const char *stats_filename
= getenv("GLSL_TO_TGSI_PRINT_STATS");
90 bool write_header
= std::ifstream(stats_filename
).fail();
91 stats_log
.open(stats_filename
, std::ios_base::out
| std::ios_base::app
);
92 stats_enabled
= stats_log
.good() ? 1 : -1;
94 stats_log
<< "arrays,temps,temps in arrays,total,instructions\n";
99 simple_mtx_unlock(&print_stats_mutex
);
101 return stats_enabled
> 0;
103 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
105 #define PRINT_STATS(X)
109 static unsigned is_precise(const ir_variable
*ir
)
113 return ir
->data
.precise
|| ir
->data
.invariant
;
116 class variable_storage
{
117 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
120 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
121 unsigned array_id
= 0)
122 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
124 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
127 gl_register_file file
;
130 /* Explicit component location. This is given in terms of the GLSL-style
131 * swizzles where each double is a single component, i.e. for 64-bit types
132 * it can only be 0 or 1.
135 ir_variable
*var
; /* variable that maps to this, if any */
139 class immediate_storage
: public exec_node
{
141 immediate_storage(gl_constant_value
*values
, int size32
, GLenum type
)
143 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
144 this->size32
= size32
;
148 /* doubles are stored across 2 gl_constant_values */
149 gl_constant_value values
[4];
150 int size32
; /**< Number of 32-bit components (1-4) */
151 GLenum type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
154 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
155 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
159 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
162 unsigned gs_out_streams
;
163 enum glsl_interp_mode interp
;
164 enum glsl_base_type base_type
;
165 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
169 static struct inout_decl
*
170 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
172 assert(array_id
!= 0);
174 for (unsigned i
= 0; i
< count
; i
++) {
175 struct inout_decl
*decl
= &decls
[i
];
177 if (array_id
== decl
->array_id
) {
185 static enum glsl_base_type
186 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
189 return GLSL_TYPE_ERROR
;
190 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
192 return decl
->base_type
;
193 return GLSL_TYPE_ERROR
;
196 struct hwatomic_decl
{
203 struct glsl_to_tgsi_visitor
: public ir_visitor
{
205 glsl_to_tgsi_visitor();
206 ~glsl_to_tgsi_visitor();
208 struct gl_context
*ctx
;
209 struct gl_program
*prog
;
210 struct gl_shader_program
*shader_program
;
211 struct gl_linked_shader
*shader
;
212 struct gl_shader_compiler_options
*options
;
216 unsigned *array_sizes
;
217 unsigned max_num_arrays
;
220 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
222 unsigned num_input_arrays
;
223 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
224 unsigned num_outputs
;
225 unsigned num_output_arrays
;
227 struct hwatomic_decl atomic_info
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
228 unsigned num_atomics
;
229 unsigned num_atomic_arrays
;
230 int num_address_regs
;
231 uint32_t samplers_used
;
232 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
233 enum tgsi_texture_type sampler_targets
[PIPE_MAX_SAMPLERS
];
235 enum tgsi_texture_type image_targets
[PIPE_MAX_SHADER_IMAGES
];
236 enum pipe_format image_formats
[PIPE_MAX_SHADER_IMAGES
];
237 bool image_wr
[PIPE_MAX_SHADER_IMAGES
];
238 bool indirect_addr_consts
;
239 int wpos_transform_const
;
241 bool native_integers
;
244 bool use_shared_memory
;
248 bool tg4_component_in_swizzle
;
250 variable_storage
*find_variable_storage(ir_variable
*var
);
252 int add_constant(gl_register_file file
, gl_constant_value values
[8],
253 int size
, GLenum datatype
, uint16_t *swizzle_out
);
255 st_src_reg
get_temp(const glsl_type
*type
);
256 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
258 st_src_reg
st_src_reg_for_double(double val
);
259 st_src_reg
st_src_reg_for_float(float val
);
260 st_src_reg
st_src_reg_for_int(int val
);
261 st_src_reg
st_src_reg_for_int64(int64_t val
);
262 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
265 * \name Visit methods
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
272 virtual void visit(ir_variable
*);
273 virtual void visit(ir_loop
*);
274 virtual void visit(ir_loop_jump
*);
275 virtual void visit(ir_function_signature
*);
276 virtual void visit(ir_function
*);
277 virtual void visit(ir_expression
*);
278 virtual void visit(ir_swizzle
*);
279 virtual void visit(ir_dereference_variable
*);
280 virtual void visit(ir_dereference_array
*);
281 virtual void visit(ir_dereference_record
*);
282 virtual void visit(ir_assignment
*);
283 virtual void visit(ir_constant
*);
284 virtual void visit(ir_call
*);
285 virtual void visit(ir_return
*);
286 virtual void visit(ir_discard
*);
287 virtual void visit(ir_demote
*);
288 virtual void visit(ir_texture
*);
289 virtual void visit(ir_if
*);
290 virtual void visit(ir_emit_vertex
*);
291 virtual void visit(ir_end_primitive
*);
292 virtual void visit(ir_barrier
*);
295 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
297 void visit_atomic_counter_intrinsic(ir_call
*);
298 void visit_ssbo_intrinsic(ir_call
*);
299 void visit_membar_intrinsic(ir_call
*);
300 void visit_shared_intrinsic(ir_call
*);
301 void visit_image_intrinsic(ir_call
*);
302 void visit_generic_intrinsic(ir_call
*, enum tgsi_opcode op
);
306 /** List of variable_storage */
307 struct hash_table
*variables
;
309 /** List of immediate_storage */
310 exec_list immediates
;
311 unsigned num_immediates
;
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions
;
316 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
317 st_dst_reg dst
= undef_dst
,
318 st_src_reg src0
= undef_src
,
319 st_src_reg src1
= undef_src
,
320 st_src_reg src2
= undef_src
,
321 st_src_reg src3
= undef_src
);
323 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
324 st_dst_reg dst
, st_dst_reg dst1
,
325 st_src_reg src0
= undef_src
,
326 st_src_reg src1
= undef_src
,
327 st_src_reg src2
= undef_src
,
328 st_src_reg src3
= undef_src
);
330 enum tgsi_opcode
get_opcode(enum tgsi_opcode op
,
332 st_src_reg src0
, st_src_reg src1
);
335 * Emit the correct dot-product instruction for the type of arguments
337 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
343 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
344 st_dst_reg dst
, st_src_reg src0
);
346 void emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
347 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
349 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
351 void get_deref_offsets(ir_dereference
*ir
,
352 unsigned *array_size
,
357 void calc_deref_offsets(ir_dereference
*tail
,
358 unsigned *array_elements
,
360 st_src_reg
*indirect
,
362 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
363 bool handle_bound_deref(ir_dereference
*ir
);
365 bool try_emit_mad(ir_expression
*ir
,
367 bool try_emit_mad_for_and_not(ir_expression
*ir
,
370 void emit_swz(ir_expression
*ir
);
372 bool process_move_condition(ir_rvalue
*ir
);
374 void simplify_cmp(void);
376 void rename_temp_registers(struct rename_reg_pair
*renames
);
377 void get_first_temp_read(int *first_reads
);
378 void get_first_temp_write(int *first_writes
);
379 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
380 void get_last_temp_write(int *last_writes
);
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
390 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
391 st_dst_reg
*l
, st_src_reg
*r
,
392 st_src_reg
*cond
, bool cond_swap
);
399 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
401 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
403 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
,
407 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
411 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
415 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
418 prog
->data
->LinkStatus
= LINKING_FAILURE
;
422 swizzle_for_size(int size
)
424 static const int size_swizzles
[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
426 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
427 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
428 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
431 assert((size
>= 1) && (size
<= 4));
432 return size_swizzles
[size
- 1];
436 glsl_to_tgsi_instruction
*
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
438 st_dst_reg dst
, st_dst_reg dst1
,
439 st_src_reg src0
, st_src_reg src1
,
440 st_src_reg src2
, st_src_reg src3
)
442 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
443 int num_reladdr
= 0, i
, j
;
444 bool dst_is_64bit
[2];
446 op
= get_opcode(op
, dst
, src0
, src1
);
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
452 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
453 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
454 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
455 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
456 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
457 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
459 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
460 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
461 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
462 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
464 if (dst
.reladdr
|| dst
.reladdr2
) {
466 emit_arl(ir
, address_reg
, *dst
.reladdr
);
468 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
472 assert(num_reladdr
== 0);
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
478 inst
->precise
= this->precise
;
479 inst
->info
= tgsi_get_opcode_info(op
);
486 inst
->is_64bit_expanded
= false;
489 inst
->tex_offsets
= NULL
;
490 inst
->tex_offset_num_offset
= 0;
492 inst
->tex_shadow
= 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
496 inst
->tex_type
= GLSL_TYPE_FLOAT
;
498 /* Update indirect addressing status used by TGSI */
499 if (dst
.reladdr
|| dst
.reladdr2
) {
501 case PROGRAM_STATE_VAR
:
502 case PROGRAM_CONSTANT
:
503 case PROGRAM_UNIFORM
:
504 this->indirect_addr_consts
= true;
506 case PROGRAM_IMMEDIATE
:
507 assert(!"immediates should not have indirect addressing");
514 for (i
= 0; i
< 4; i
++) {
515 if (inst
->src
[i
].reladdr
) {
516 switch (inst
->src
[i
].file
) {
517 case PROGRAM_STATE_VAR
:
518 case PROGRAM_CONSTANT
:
519 case PROGRAM_UNIFORM
:
520 this->indirect_addr_consts
= true;
522 case PROGRAM_IMMEDIATE
:
523 assert(!"immediates should not have indirect addressing");
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
550 for (j
= 0; j
< 2; j
++) {
551 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
552 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&&
553 inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
554 enum glsl_base_type type
= find_array_type(this->outputs
,
556 inst
->dst
[j
].array_id
);
557 if (glsl_base_type_is_64bit(type
))
558 dst_is_64bit
[j
] = true;
562 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
563 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
564 glsl_to_tgsi_instruction
*dinst
= NULL
;
565 int initial_src_swz
[4], initial_src_idx
[4];
566 int initial_dst_idx
[2], initial_dst_writemask
[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
569 ? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j
= 0; j
< 2; j
++) {
573 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
574 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
577 for (j
= 0; j
< 4; j
++) {
578 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
579 initial_src_idx
[j
] = inst
->src
[j
].index
;
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
589 int i
= u_bit_scan(&writemask
);
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
||
594 inst
->op
== TGSI_OPCODE_STORE
) &&
595 addr
.file
== PROGRAM_UNDEFINED
) {
596 /* We have to advance the buffer address by 16 */
597 addr
= get_temp(glsl_type::uint_type
);
598 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
599 inst
->src
[0], st_src_reg_for_int(16));
602 /* first time use previous instruction */
606 /* create a new instructions for subsequent attempts */
607 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
612 this->instructions
.push_tail(dinst
);
613 dinst
->is_64bit_expanded
= true;
615 /* modify the destination if we are splitting */
616 for (j
= 0; j
< 2; j
++) {
617 if (dst_is_64bit
[j
]) {
618 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
619 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
621 if (dinst
->op
== TGSI_OPCODE_LOAD
||
622 dinst
->op
== TGSI_OPCODE_STORE
)
623 dinst
->src
[0] = addr
;
624 if (dinst
->op
!= TGSI_OPCODE_STORE
)
625 dinst
->dst
[j
].index
++;
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
631 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
635 /* modify the src registers */
636 for (j
= 0; j
< 4; j
++) {
637 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
639 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
640 dinst
->src
[j
].index
= initial_src_idx
[j
];
642 dinst
->src
[j
].double_reg2
= true;
643 dinst
->src
[j
].index
++;
647 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
,
648 SWIZZLE_Z
, SWIZZLE_W
);
650 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
651 SWIZZLE_X
, SWIZZLE_Y
);
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
658 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
||
659 op
== TGSI_OPCODE_I2D
||
660 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
661 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
662 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
663 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
670 this->instructions
.push_tail(inst
);
677 glsl_to_tgsi_instruction
*
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, enum tgsi_opcode op
,
680 st_src_reg src0
, st_src_reg src1
,
681 st_src_reg src2
, st_src_reg src3
)
683 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op
,
693 st_src_reg src0
, st_src_reg src1
)
695 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
697 if (op
== TGSI_OPCODE_MOV
)
700 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
701 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
702 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
703 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
705 if (is_resource_instruction(op
))
707 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
708 type
= GLSL_TYPE_INT64
;
709 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
710 type
= GLSL_TYPE_UINT64
;
711 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
712 type
= GLSL_TYPE_DOUBLE
;
713 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
714 type
= GLSL_TYPE_FLOAT
;
715 else if (native_integers
)
716 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
731 op = TGSI_OPCODE_##f; \
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
749 op = TGSI_OPCODE_##c; \
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
758 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
759 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
760 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
761 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
762 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
763 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
764 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
765 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
766 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
767 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
768 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
769 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
770 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
771 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
772 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
773 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
775 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
776 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
777 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
778 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
779 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
780 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
781 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
782 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
783 case7(ATOMUADD
,ATOMFADD
,ATOMUADD
,ATOMUADD
,LAST
, LAST
, LAST
);
785 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
786 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
787 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
788 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
794 assert(op
!= TGSI_OPCODE_LAST
);
798 glsl_to_tgsi_instruction
*
799 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
800 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
803 static const enum tgsi_opcode dot_opcodes
[] = {
804 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
807 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
821 st_src_reg orig_src0
, st_src_reg orig_src1
)
824 int done_mask
= ~dst
.writemask
;
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
830 for (i
= 0; i
< 4; i
++) {
831 GLuint this_mask
= (1 << i
);
832 st_src_reg src0
= orig_src0
;
833 st_src_reg src1
= orig_src1
;
835 if (done_mask
& this_mask
)
838 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
839 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
840 for (j
= i
+ 1; j
< 4; j
++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
845 if (!(done_mask
& (1 << j
)) &&
846 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
847 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
848 this_mask
|= (1 << j
);
851 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
852 src0_swiz
, src0_swiz
);
853 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
854 src1_swiz
, src1_swiz
);
856 dst
.writemask
= this_mask
;
857 emit_asm(ir
, op
, dst
, src0
, src1
);
858 done_mask
|= this_mask
;
863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, enum tgsi_opcode op
,
864 st_dst_reg dst
, st_src_reg src0
)
866 st_src_reg undef
= undef_src
;
868 undef
.swizzle
= SWIZZLE_XXXX
;
870 emit_scalar(ir
, op
, dst
, src0
, undef
);
874 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
875 st_dst_reg dst
, st_src_reg src0
)
877 enum tgsi_opcode op
= TGSI_OPCODE_ARL
;
879 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
880 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
883 op
= TGSI_OPCODE_UARL
;
886 assert(dst
.file
== PROGRAM_ADDRESS
);
887 if (dst
.index
>= this->num_address_regs
)
888 this->num_address_regs
= dst
.index
+ 1;
890 emit_asm(NULL
, op
, dst
, src0
);
894 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
895 gl_constant_value values
[8], int size
,
897 uint16_t *swizzle_out
)
899 if (file
== PROGRAM_CONSTANT
) {
900 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
901 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
,
902 values
, size
, datatype
,
905 *swizzle_out
= swizzle
;
909 assert(file
== PROGRAM_IMMEDIATE
);
912 immediate_storage
*entry
;
913 int size32
= size
* ((datatype
== GL_DOUBLE
||
914 datatype
== GL_INT64_ARB
||
915 datatype
== GL_UNSIGNED_INT64_ARB
) ? 2 : 1);
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
921 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
922 immediate_storage
*tmp
= entry
;
924 for (i
= 0; i
* 4 < size32
; i
++) {
925 int slot_size
= MIN2(size32
- (i
* 4), 4);
926 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
928 if (memcmp(tmp
->values
, &values
[i
* 4],
929 slot_size
* sizeof(gl_constant_value
)))
932 /* Everything matches, keep going until the full size is matched */
933 tmp
= (immediate_storage
*)tmp
->next
;
936 /* The full value matched */
943 for (i
= 0; i
* 4 < size32
; i
++) {
944 int slot_size
= MIN2(size32
- (i
* 4), 4);
945 /* Add this immediate to the list. */
946 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4],
947 slot_size
, datatype
);
948 this->immediates
.push_tail(entry
);
949 this->num_immediates
++;
955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
957 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
958 union gl_constant_value uval
;
961 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
969 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
970 union gl_constant_value uval
[2];
972 memcpy(uval
, &val
, sizeof(uval
));
973 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
974 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
981 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
982 union gl_constant_value uval
;
984 assert(native_integers
);
987 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
995 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
996 union gl_constant_value uval
[2];
998 memcpy(uval
, &val
, sizeof(uval
));
999 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1000 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1008 if (native_integers
)
1009 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1010 st_src_reg_for_int(val
);
1012 return st_src_reg_for_float(val
);
1016 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1018 return type
->count_attribute_slots(is_vs_input
);
1022 type_size(const struct glsl_type
*type
)
1024 return type
->count_attribute_slots(false);
1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
1029 exec_list
*instructions
, ir_constant
*access
)
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1035 enum tgsi_opcode op
= inst
->op
;
1037 inst
->resource
= *buf
;
1039 inst
->buffer_access
= access
->value
.u
[0];
1041 if (inst
== instructions
->get_head_raw())
1043 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1045 if (inst
->op
== TGSI_OPCODE_UADD
) {
1046 if (inst
== instructions
->get_head_raw())
1048 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
1050 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1063 type_has_array_or_matrix(const glsl_type
*type
)
1065 if (type
->is_array() || type
->is_matrix())
1068 if (type
->is_struct()) {
1069 for (unsigned i
= 0; i
< type
->length
; i
++) {
1070 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1086 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1090 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1095 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1096 if (next_array
>= max_num_arrays
) {
1097 max_num_arrays
+= 32;
1098 array_sizes
= (unsigned*)
1099 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1102 src
.file
= PROGRAM_ARRAY
;
1104 src
.array_id
= next_array
+ 1;
1105 array_sizes
[next_array
] = type_size(type
);
1109 src
.file
= PROGRAM_TEMPORARY
;
1110 src
.index
= next_temp
;
1111 next_temp
+= type_size(type
);
1114 if (type
->is_array() || type
->is_struct()) {
1115 src
.swizzle
= SWIZZLE_NOOP
;
1117 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1126 struct hash_entry
*entry
;
1128 entry
= _mesa_hash_table_search(this->variables
, var
);
1132 return (variable_storage
*)entry
->data
;
1136 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1138 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1140 const ir_state_slot
*const slots
= ir
->get_state_slots();
1141 assert(slots
!= NULL
);
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1149 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1150 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1155 variable_storage
*storage
;
1157 if (i
== ir
->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1161 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1169 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1171 dst
= st_dst_reg(get_temp(ir
->type
));
1173 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1176 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1180 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1181 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1184 if (storage
->file
== PROGRAM_STATE_VAR
) {
1185 if (storage
->index
== -1) {
1186 storage
->index
= index
;
1188 assert(index
== storage
->index
+ (int)i
);
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1196 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1197 src
.swizzle
= slots
[i
].swizzle
;
1198 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1204 if (storage
->file
== PROGRAM_TEMPORARY
&&
1205 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1206 fail_link(this->shader_program
,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir
->name
, dst
.index
- storage
->index
,
1209 type_size(ir
->type
));
1215 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1217 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1219 visit_exec_list(&ir
->body_instructions
, this);
1221 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1228 case ir_loop_jump::jump_break
:
1229 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1231 case ir_loop_jump::jump_continue
:
1232 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1239 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1246 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1251 if (strcmp(ir
->name
, "main") == 0) {
1252 const ir_function_signature
*sig
;
1255 sig
= ir
->matching_signature(NULL
, &empty
, false);
1259 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1268 int nonmul_operand
= 1 - mul_operand
;
1270 st_dst_reg result_dst
;
1272 // there is no TGSI opcode for this
1273 if (ir
->type
->is_integer_64())
1276 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1277 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1280 expr
->operands
[0]->accept(this);
1282 expr
->operands
[1]->accept(this);
1284 ir
->operands
[nonmul_operand
]->accept(this);
1287 this->result
= get_temp(ir
->type
);
1288 result_dst
= st_dst_reg(this->result
);
1289 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1290 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1305 * - (a * 1) - (a * b)
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
,
1316 const int other_operand
= 1 - try_operand
;
1319 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1320 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1323 ir
->operands
[other_operand
]->accept(this);
1325 expr
->operands
[0]->accept(this);
1328 b
.negate
= ~b
.negate
;
1330 this->result
= get_temp(ir
->type
);
1331 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1338 st_src_reg
*reg
, int *num_reladdr
)
1340 if (!reg
->reladdr
&& !reg
->reladdr2
)
1344 emit_arl(ir
, address_reg
, *reg
->reladdr
);
1346 emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1348 if (*num_reladdr
!= 1) {
1349 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1351 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1359 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1361 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1365 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1366 if (try_emit_mad(ir
, 1))
1368 if (try_emit_mad(ir
, 0))
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1374 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1375 if (try_emit_mad_for_and_not(ir
, 1))
1377 if (try_emit_mad_for_and_not(ir
, 0))
1381 if (ir
->operation
== ir_quadop_vector
)
1382 assert(!"ir_quadop_vector should have been lowered");
1384 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1385 this->result
.file
= PROGRAM_UNDEFINED
;
1386 ir
->operands
[operand
]->accept(this);
1387 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir
->operands
[operand
]->print();
1393 op
[operand
] = this->result
;
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1398 assert(!ir
->operands
[operand
]->type
->is_matrix());
1401 visit_expression(ir
, op
);
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1411 st_src_reg result_src
;
1412 st_dst_reg result_dst
;
1414 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1415 if (ir
->operands
[1] &&
1416 ir
->operation
!= ir_binop_interpolate_at_offset
&&
1417 ir
->operation
!= ir_binop_interpolate_at_sample
) {
1418 st_src_reg
*swz_op
= NULL
;
1419 if (vector_elements
> ir
->operands
[1]->type
->vector_elements
) {
1420 assert(ir
->operands
[1]->type
->vector_elements
== 1);
1422 } else if (vector_elements
< ir
->operands
[1]->type
->vector_elements
) {
1423 assert(ir
->operands
[0]->type
->vector_elements
== 1);
1427 uint16_t swizzle_x
= GET_SWZ(swz_op
->swizzle
, 0);
1428 swz_op
->swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1429 swizzle_x
, swizzle_x
);
1431 vector_elements
= MAX2(vector_elements
,
1432 ir
->operands
[1]->type
->vector_elements
);
1434 if (ir
->operands
[2] &&
1435 ir
->operands
[2]->type
->vector_elements
!= vector_elements
) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir
->operands
[2]->type
->vector_elements
== 1);
1438 uint16_t swizzle_x
= GET_SWZ(op
[2].swizzle
, 0);
1439 op
[2].swizzle
= MAKE_SWIZZLE4(swizzle_x
, swizzle_x
,
1440 swizzle_x
, swizzle_x
);
1443 this->result
.file
= PROGRAM_UNDEFINED
;
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1448 result_src
= get_temp(ir
->type
);
1449 /* convenience for the emit functions below. */
1450 result_dst
= st_dst_reg(result_src
);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1455 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1457 switch (ir
->operation
) {
1458 case ir_unop_logic_not
:
1459 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1460 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1467 op
[0].negate
= ~op
[0].negate
;
1468 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0],
1469 st_src_reg_for_float(1.0));
1473 if (result_dst
.type
== GLSL_TYPE_INT64
||
1474 result_dst
.type
== GLSL_TYPE_UINT64
)
1475 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1476 else if (result_dst
.type
== GLSL_TYPE_INT
||
1477 result_dst
.type
== GLSL_TYPE_UINT
)
1478 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1479 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1480 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1482 op
[0].negate
= ~op
[0].negate
;
1486 case ir_unop_subroutine_to_int
:
1487 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1490 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1491 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1492 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1493 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1494 else if (result_dst
.type
== GLSL_TYPE_INT64
||
1495 result_dst
.type
== GLSL_TYPE_UINT64
)
1496 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1498 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1501 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1504 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1508 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1511 assert(!"not reached: should be handled by exp_to_exp2");
1514 assert(!"not reached: should be handled by log_to_log2");
1517 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1520 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1523 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1525 case ir_unop_saturate
: {
1526 glsl_to_tgsi_instruction
*inst
;
1527 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1528 inst
->saturate
= true;
1533 case ir_unop_dFdx_coarse
:
1534 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1536 case ir_unop_dFdx_fine
:
1537 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1540 case ir_unop_dFdy_coarse
:
1541 case ir_unop_dFdy_fine
:
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1547 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
1548 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1550 unsigned transform_y_index
=
1551 _mesa_add_state_reference(this->prog
->Parameters
,
1554 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1556 glsl_type::vec4_type
);
1557 transform_y
.swizzle
= SWIZZLE_XXXX
;
1559 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1561 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1562 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1563 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1567 case ir_unop_frexp_sig
:
1568 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1571 case ir_unop_frexp_exp
:
1572 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1575 case ir_unop_noise
: {
1576 /* At some point, a motivated person could add a better
1577 * implementation of noise. Currently not even the nvidia
1578 * binary drivers do anything more than this. In any case, the
1579 * place to do this is in the GL state tracker, not the poor
1582 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1587 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1590 op
[1].negate
= ~op
[1].negate
;
1591 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1595 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1598 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1601 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1602 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1604 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1608 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1610 case ir_binop_gequal
:
1611 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1613 case ir_binop_equal
:
1614 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1616 case ir_binop_nequal
:
1617 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1619 case ir_binop_all_equal
:
1620 /* "==" operator producing a scalar boolean. */
1621 if (ir
->operands
[0]->type
->is_vector() ||
1622 ir
->operands
[1]->type
->is_vector()) {
1623 st_src_reg temp
= get_temp(native_integers
?
1624 glsl_type::uvec4_type
:
1625 glsl_type::vec4_type
);
1627 if (native_integers
) {
1628 st_dst_reg temp_dst
= st_dst_reg(temp
);
1629 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1631 if (ir
->operands
[0]->type
->is_boolean() &&
1632 ir
->operands
[1]->as_constant() &&
1633 ir
->operands
[1]->as_constant()->is_one()) {
1634 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1636 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1639 /* Emit 1-3 AND operations to combine the SEQ results. */
1640 switch (ir
->operands
[0]->type
->vector_elements
) {
1644 temp_dst
.writemask
= WRITEMASK_Y
;
1645 temp1
.swizzle
= SWIZZLE_YYYY
;
1646 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1647 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1650 temp_dst
.writemask
= WRITEMASK_X
;
1651 temp1
.swizzle
= SWIZZLE_XXXX
;
1652 temp2
.swizzle
= SWIZZLE_YYYY
;
1653 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1654 temp_dst
.writemask
= WRITEMASK_Y
;
1655 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1656 temp2
.swizzle
= SWIZZLE_WWWW
;
1657 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1660 temp1
.swizzle
= SWIZZLE_XXXX
;
1661 temp2
.swizzle
= SWIZZLE_YYYY
;
1662 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1664 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1666 /* After the dot-product, the value will be an integer on the
1667 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1669 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1671 /* Negating the result of the dot-product gives values on the range
1672 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1673 * This is achieved using SGE.
1675 st_src_reg sge_src
= result_src
;
1676 sge_src
.negate
= ~sge_src
.negate
;
1677 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
,
1678 st_src_reg_for_float(0.0));
1681 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1684 case ir_binop_any_nequal
:
1685 /* "!=" operator producing a scalar boolean. */
1686 if (ir
->operands
[0]->type
->is_vector() ||
1687 ir
->operands
[1]->type
->is_vector()) {
1688 st_src_reg temp
= get_temp(native_integers
?
1689 glsl_type::uvec4_type
:
1690 glsl_type::vec4_type
);
1691 if (ir
->operands
[0]->type
->is_boolean() &&
1692 ir
->operands
[1]->as_constant() &&
1693 ir
->operands
[1]->as_constant()->is_zero()) {
1694 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1696 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1699 if (native_integers
) {
1700 st_dst_reg temp_dst
= st_dst_reg(temp
);
1701 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1703 /* Emit 1-3 OR operations to combine the SNE results. */
1704 switch (ir
->operands
[0]->type
->vector_elements
) {
1708 temp_dst
.writemask
= WRITEMASK_Y
;
1709 temp1
.swizzle
= SWIZZLE_YYYY
;
1710 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1711 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1714 temp_dst
.writemask
= WRITEMASK_X
;
1715 temp1
.swizzle
= SWIZZLE_XXXX
;
1716 temp2
.swizzle
= SWIZZLE_YYYY
;
1717 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1718 temp_dst
.writemask
= WRITEMASK_Y
;
1719 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1720 temp2
.swizzle
= SWIZZLE_WWWW
;
1721 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1724 temp1
.swizzle
= SWIZZLE_XXXX
;
1725 temp2
.swizzle
= SWIZZLE_YYYY
;
1726 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1728 /* After the dot-product, the value will be an integer on the
1729 * range [0,4]. Zero stays zero, and positive values become 1.0.
1731 glsl_to_tgsi_instruction
*const dp
=
1732 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1733 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1734 /* The clamping to [0,1] can be done for free in the fragment
1735 * shader with a saturate.
1737 dp
->saturate
= true;
1739 /* Negating the result of the dot-product gives values on the
1740 * range [-4, 0]. Zero stays zero, and negative values become
1741 * 1.0. This achieved using SLT.
1743 st_src_reg slt_src
= result_src
;
1744 slt_src
.negate
= ~slt_src
.negate
;
1745 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1746 st_src_reg_for_float(0.0));
1750 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1754 case ir_binop_logic_xor
:
1755 if (native_integers
)
1756 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1758 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1761 case ir_binop_logic_or
: {
1762 if (native_integers
) {
1763 /* If integers are used as booleans, we can use an actual "or"
1766 assert(native_integers
);
1767 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1769 /* After the addition, the value will be an integer on the
1770 * range [0,2]. Zero stays zero, and positive values become 1.0.
1772 glsl_to_tgsi_instruction
*add
=
1773 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1774 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1775 /* The clamping to [0,1] can be done for free in the fragment
1776 * shader with a saturate if floats are being used as boolean
1779 add
->saturate
= true;
1781 /* Negating the result of the addition gives values on the range
1782 * [-2, 0]. Zero stays zero, and negative values become 1.0
1783 * This is achieved using SLT.
1785 st_src_reg slt_src
= result_src
;
1786 slt_src
.negate
= ~slt_src
.negate
;
1787 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
,
1788 st_src_reg_for_float(0.0));
1794 case ir_binop_logic_and
:
1795 /* If native integers are disabled, the bool args are stored as float 0.0
1796 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1797 * actual AND opcode.
1799 if (native_integers
)
1800 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1802 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1806 assert(ir
->operands
[0]->type
->is_vector());
1807 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1808 emit_dp(ir
, result_dst
, op
[0], op
[1],
1809 ir
->operands
[0]->type
->vector_elements
);
1814 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1816 /* This is the only instruction sequence that makes the game "Risen"
1817 * render correctly. ABS is not required for the game, but since GLSL
1818 * declares negative values as "undefined", allowing us to do whatever
1819 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1822 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1823 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1827 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1830 if (native_integers
) {
1831 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1834 /* fallthrough to next case otherwise */
1836 if (native_integers
) {
1837 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1838 st_src_reg_for_float(1.0));
1841 /* fallthrough to next case otherwise */
1844 case ir_unop_i642u64
:
1845 case ir_unop_u642i64
:
1846 /* Converting between signed and unsigned integers is a no-op. */
1848 result_src
.type
= result_dst
.type
;
1851 if (native_integers
) {
1852 /* Booleans are stored as integers using ~0 for true and 0 for false.
1853 * GLSL requires that int(bool) return 1 for true and 0 for false.
1854 * This conversion is done with AND, but it could be done with NEG.
1856 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0],
1857 st_src_reg_for_int(1));
1859 /* Booleans and integers are both stored as floats when native
1860 * integers are disabled.
1866 if (native_integers
)
1867 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1869 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1872 if (native_integers
)
1873 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1875 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1877 case ir_unop_bitcast_f2i
:
1878 case ir_unop_bitcast_f2u
:
1879 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1880 if (op
[0].negate
|| op
[0].abs
)
1881 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1884 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1887 case ir_unop_bitcast_i2f
:
1888 case ir_unop_bitcast_u2f
:
1890 result_src
.type
= GLSL_TYPE_FLOAT
;
1893 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1894 st_src_reg_for_float(0.0));
1897 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1898 st_src_reg_for_double(0.0));
1901 if (native_integers
)
1902 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0],
1903 st_src_reg_for_int(0));
1905 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0],
1906 st_src_reg_for_float(0.0));
1908 case ir_unop_bitcast_u642d
:
1909 case ir_unop_bitcast_i642d
:
1911 result_src
.type
= GLSL_TYPE_DOUBLE
;
1913 case ir_unop_bitcast_d2i64
:
1915 result_src
.type
= GLSL_TYPE_INT64
;
1917 case ir_unop_bitcast_d2u64
:
1919 result_src
.type
= GLSL_TYPE_UINT64
;
1922 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1925 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1928 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1930 case ir_unop_round_even
:
1931 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1934 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1938 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1941 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1944 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1947 case ir_unop_bit_not
:
1948 if (native_integers
) {
1949 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1953 if (native_integers
) {
1954 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1957 case ir_binop_lshift
:
1958 case ir_binop_rshift
:
1959 if (native_integers
) {
1960 enum tgsi_opcode opcode
= ir
->operation
== ir_binop_lshift
1961 ? TGSI_OPCODE_SHL
: TGSI_OPCODE_ISHR
;
1964 if (glsl_base_type_is_64bit(op
[0].type
)) {
1965 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1968 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]
1969 ->type
->components()));
1970 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1975 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1978 case ir_binop_bit_and
:
1979 if (native_integers
) {
1980 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1983 case ir_binop_bit_xor
:
1984 if (native_integers
) {
1985 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1988 case ir_binop_bit_or
:
1989 if (native_integers
) {
1990 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1994 assert(!"GLSL 1.30 features unsupported");
1997 case ir_binop_ubo_load
: {
1998 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1999 ir_rvalue
*block
= ir
->operands
[0];
2000 ir_rvalue
*offset
= ir
->operands
[1];
2001 ir_constant
*const_block
= block
->as_constant();
2003 st_src_reg
cbuf(PROGRAM_CONSTANT
,
2004 (const_block
? const_block
->value
.u
[0] + 1 : 1),
2005 ir
->type
->base_type
);
2007 cbuf
.has_index2
= true;
2010 block
->accept(this);
2011 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2012 *cbuf
.reladdr
= this->result
;
2013 emit_arl(ir
, sampler_reladdr
, this->result
);
2016 /* Calculate the surface offset */
2017 offset
->accept(this);
2018 st_src_reg off
= this->result
;
2020 glsl_to_tgsi_instruction
*inst
=
2021 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
2023 if (result_dst
.type
== GLSL_TYPE_BOOL
)
2024 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
2025 st_src_reg_for_int(0));
2027 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
2030 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2031 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2032 unsigned const_offset
= const_offset_ir
?
2033 const_offset_ir
->value
.u
[0] : 0;
2034 unsigned const_block
= const_uniform_block
?
2035 const_uniform_block
->value
.u
[0] + 1 : 1;
2036 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2039 cbuf
.type
= ir
->type
->base_type
;
2040 cbuf
.file
= PROGRAM_CONSTANT
;
2042 cbuf
.reladdr
= NULL
;
2045 cbuf
.index2D
= const_block
;
2047 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2049 if (const_offset_ir
) {
2050 /* Constant index into constant buffer */
2051 cbuf
.reladdr
= NULL
;
2052 cbuf
.index
= const_offset
/ 16;
2054 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2055 st_src_reg offset
= op
[1];
2057 /* The OpenGL spec is written in such a way that accesses with
2058 * non-constant offset are almost always vec4-aligned. The only
2059 * exception to this are members of structs in arrays of structs:
2060 * each struct in an array of structs is at least vec4-aligned,
2061 * but single-element and [ui]vec2 members of the struct may be at
2062 * an offset that is not a multiple of 16 bytes.
2064 * Here, we extract that offset, relying on previous passes to
2065 * always generate offset expressions of the form
2066 * (+ expr constant_offset).
2068 * Note that the std430 layout, which allows more cases of
2069 * alignment less than vec4 in arrays, is not supported for
2070 * uniform blocks, so we do not have to deal with it here.
2072 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2073 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2074 if (const_offset_ir
) {
2075 const_offset
= const_offset_ir
->value
.u
[0];
2076 cbuf
.index
= const_offset
/ 16;
2077 offset_expr
->operands
[0]->accept(this);
2078 offset
= this->result
;
2082 /* Relative/variable index into constant buffer */
2083 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2084 st_src_reg_for_int(4));
2085 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2086 *cbuf
.reladdr
= index_reg
;
2089 if (const_uniform_block
) {
2090 /* Constant constant buffer */
2091 cbuf
.reladdr2
= NULL
;
2093 /* Relative/variable constant buffer */
2094 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2095 *cbuf
.reladdr2
= op
[0];
2097 cbuf
.has_index2
= true;
2099 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2100 if (glsl_base_type_is_64bit(cbuf
.type
))
2101 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2102 const_offset
% 16 / 8,
2103 const_offset
% 16 / 8,
2104 const_offset
% 16 / 8);
2106 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2107 const_offset
% 16 / 4,
2108 const_offset
% 16 / 4,
2109 const_offset
% 16 / 4);
2111 if (ir
->type
->is_boolean()) {
2112 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2113 st_src_reg_for_int(0));
2115 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2121 /* note: we have to reorder the three args here */
2122 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2125 if (this->ctx
->Const
.NativeIntegers
)
2126 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2128 op
[0].negate
= ~op
[0].negate
;
2129 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2132 case ir_triop_bitfield_extract
:
2133 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2135 case ir_quadop_bitfield_insert
:
2136 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2138 case ir_unop_bitfield_reverse
:
2139 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2141 case ir_unop_bit_count
:
2142 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2144 case ir_unop_find_msb
:
2145 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2147 case ir_unop_find_lsb
:
2148 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2150 case ir_binop_imul_high
:
2151 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2154 /* In theory, MAD is incorrect here. */
2156 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2158 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2160 case ir_unop_interpolate_at_centroid
:
2161 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2163 case ir_binop_interpolate_at_offset
: {
2164 /* The y coordinate needs to be flipped for the default fb */
2165 static const gl_state_index16 transform_y_state
[STATE_LENGTH
]
2166 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2168 unsigned transform_y_index
=
2169 _mesa_add_state_reference(this->prog
->Parameters
,
2172 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2174 glsl_type::vec4_type
);
2175 transform_y
.swizzle
= SWIZZLE_XXXX
;
2177 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2178 st_dst_reg temp_dst
= st_dst_reg(temp
);
2180 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2181 temp_dst
.writemask
= WRITEMASK_Y
;
2182 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2183 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2186 case ir_binop_interpolate_at_sample
:
2187 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2191 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2194 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2197 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2200 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2203 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2206 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2208 case ir_unop_unpack_double_2x32
:
2209 case ir_unop_pack_double_2x32
:
2210 case ir_unop_unpack_int_2x32
:
2211 case ir_unop_pack_int_2x32
:
2212 case ir_unop_unpack_uint_2x32
:
2213 case ir_unop_pack_uint_2x32
:
2214 case ir_unop_unpack_sampler_2x32
:
2215 case ir_unop_pack_sampler_2x32
:
2216 case ir_unop_unpack_image_2x32
:
2217 case ir_unop_pack_image_2x32
:
2218 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2221 case ir_binop_ldexp
:
2222 if (ir
->operands
[0]->type
->is_double()) {
2223 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2224 } else if (ir
->operands
[0]->type
->is_float()) {
2225 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2227 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2231 case ir_unop_pack_half_2x16
:
2232 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2234 case ir_unop_unpack_half_2x16
:
2235 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2238 case ir_unop_get_buffer_size
: {
2239 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2242 const_offset
? const_offset
->value
.u
[0] : 0,
2244 if (!const_offset
) {
2245 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2246 *buffer
.reladdr
= op
[0];
2247 emit_arl(ir
, sampler_reladdr
, op
[0]);
2249 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2255 case ir_unop_b2i64
: {
2256 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2257 st_dst_reg temp_dst
= st_dst_reg(temp
);
2258 unsigned orig_swz
= op
[0].swizzle
;
2260 * To convert unsigned to 64-bit:
2261 * zero Y channel, copy X channel.
2263 temp_dst
.writemask
= WRITEMASK_Y
;
2264 if (vector_elements
> 1)
2265 temp_dst
.writemask
|= WRITEMASK_W
;
2266 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2267 temp_dst
.writemask
= WRITEMASK_X
;
2268 if (vector_elements
> 1)
2269 temp_dst
.writemask
|= WRITEMASK_Z
;
2270 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2271 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2272 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2273 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2275 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2277 result_src
.type
= GLSL_TYPE_UINT64
;
2278 if (vector_elements
> 2) {
2279 /* Subtle: We rely on the fact that get_temp here returns the next
2280 * TGSI temporary register directly after the temp register used for
2281 * the first two components, so that the result gets picked up
2284 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2285 st_dst_reg temp_dst
= st_dst_reg(temp
);
2286 temp_dst
.writemask
= WRITEMASK_Y
;
2287 if (vector_elements
> 3)
2288 temp_dst
.writemask
|= WRITEMASK_W
;
2289 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2291 temp_dst
.writemask
= WRITEMASK_X
;
2292 if (vector_elements
> 3)
2293 temp_dst
.writemask
|= WRITEMASK_Z
;
2294 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2),
2295 GET_SWZ(orig_swz
, 2),
2296 GET_SWZ(orig_swz
, 3),
2297 GET_SWZ(orig_swz
, 3));
2298 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2299 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2301 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0],
2302 st_src_reg_for_int(1));
2309 case ir_unop_i642u
: {
2310 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2311 st_dst_reg temp_dst
= st_dst_reg(temp
);
2312 unsigned orig_swz
= op
[0].swizzle
;
2313 unsigned orig_idx
= op
[0].index
;
2315 temp_dst
.writemask
= WRITEMASK_X
;
2317 for (el
= 0; el
< vector_elements
; el
++) {
2318 unsigned swz
= GET_SWZ(orig_swz
, el
);
2320 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
,
2321 SWIZZLE_Z
, SWIZZLE_Z
);
2323 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
2324 SWIZZLE_X
, SWIZZLE_X
);
2326 op
[0].index
= orig_idx
+ 1;
2327 op
[0].type
= GLSL_TYPE_UINT
;
2328 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2329 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2332 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2333 result_src
.type
= GLSL_TYPE_UINT
;
2335 result_src
.type
= GLSL_TYPE_INT
;
2339 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0],
2340 st_src_reg_for_int64(0));
2343 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2346 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2349 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2352 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2355 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2358 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2361 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2364 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2367 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2370 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2372 /* these might be needed */
2373 case ir_unop_pack_snorm_2x16
:
2374 case ir_unop_pack_unorm_2x16
:
2375 case ir_unop_pack_snorm_4x8
:
2376 case ir_unop_pack_unorm_4x8
:
2378 case ir_unop_unpack_snorm_2x16
:
2379 case ir_unop_unpack_unorm_2x16
:
2380 case ir_unop_unpack_snorm_4x8
:
2381 case ir_unop_unpack_unorm_4x8
:
2383 case ir_quadop_vector
:
2384 case ir_binop_vector_extract
:
2385 case ir_triop_vector_insert
:
2386 case ir_binop_carry
:
2387 case ir_binop_borrow
:
2388 case ir_unop_ssbo_unsized_array_length
:
2390 case ir_binop_atan2
:
2391 /* This operation is not supported, or should have already been handled.
2393 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2397 this->result
= result_src
;
2402 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2408 /* Note that this is only swizzles in expressions, not those on the left
2409 * hand side of an assignment, which do write masking. See ir_assignment
2413 ir
->val
->accept(this);
2415 assert(src
.file
!= PROGRAM_UNDEFINED
);
2416 assert(ir
->type
->vector_elements
> 0);
2418 for (i
= 0; i
< 4; i
++) {
2419 if (i
< ir
->type
->vector_elements
) {
2422 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2425 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2428 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2431 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2435 /* If the type is smaller than a vec4, replicate the last
2438 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2442 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2447 /* Test if the variable is an array. Note that geometry and
2448 * tessellation shader inputs are outputs are always arrays (except
2449 * for patch inputs), so only the array element type is considered.
2452 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2454 const glsl_type
*type
= var
->type
;
2456 *remove_array
= false;
2458 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2459 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2462 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2463 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2464 stage
== MESA_SHADER_TESS_CTRL
) &&
2466 if (!var
->type
->is_array())
2467 return false; /* a system value probably */
2469 type
= var
->type
->fields
.array
;
2470 *remove_array
= true;
2473 return type
->is_array() || type
->is_matrix();
2477 st_translate_interp_loc(ir_variable
*var
)
2479 if (var
->data
.centroid
)
2480 return TGSI_INTERPOLATE_LOC_CENTROID
;
2481 else if (var
->data
.sample
)
2482 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2484 return TGSI_INTERPOLATE_LOC_CENTER
;
2488 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2490 variable_storage
*entry
;
2491 ir_variable
*var
= ir
->var
;
2494 if (handle_bound_deref(ir
->as_dereference()))
2497 entry
= find_variable_storage(ir
->var
);
2500 switch (var
->data
.mode
) {
2501 case ir_var_uniform
:
2502 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2503 var
->data
.param_index
);
2504 _mesa_hash_table_insert(this->variables
, var
, entry
);
2506 case ir_var_shader_in
: {
2507 /* The linker assigns locations for varyings and attributes,
2508 * including deprecated builtins (like gl_Color), user-assign
2509 * generic attributes (glBindVertexLocation), and
2510 * user-defined varyings.
2512 assert(var
->data
.location
!= -1);
2514 const glsl_type
*type_without_array
= var
->type
->without_array();
2515 struct inout_decl
*decl
= &inputs
[num_inputs
];
2516 unsigned component
= var
->data
.location_frac
;
2517 unsigned num_components
;
2520 if (type_without_array
->is_64bit())
2521 component
= component
/ 2;
2522 if (type_without_array
->vector_elements
)
2523 num_components
= type_without_array
->vector_elements
;
2527 decl
->mesa_index
= var
->data
.location
;
2528 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2529 decl
->interp_loc
= st_translate_interp_loc(var
);
2530 decl
->base_type
= type_without_array
->base_type
;
2531 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2533 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2534 decl
->array_id
= num_input_arrays
+ 1;
2541 decl
->size
= type_size(var
->type
->fields
.array
);
2543 decl
->size
= type_size(var
->type
);
2545 entry
= new(mem_ctx
) variable_storage(var
,
2549 entry
->component
= component
;
2551 _mesa_hash_table_insert(this->variables
, var
, entry
);
2555 case ir_var_shader_out
: {
2556 assert(var
->data
.location
!= -1);
2558 const glsl_type
*type_without_array
= var
->type
->without_array();
2559 struct inout_decl
*decl
= &outputs
[num_outputs
];
2560 unsigned component
= var
->data
.location_frac
;
2561 unsigned num_components
;
2564 decl
->invariant
= var
->data
.invariant
;
2566 if (type_without_array
->is_64bit())
2567 component
= component
/ 2;
2568 if (type_without_array
->vector_elements
)
2569 num_components
= type_without_array
->vector_elements
;
2573 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2574 decl
->base_type
= type_without_array
->base_type
;
2575 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2576 if (var
->data
.stream
& (1u << 31)) {
2577 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2579 assert(var
->data
.stream
< 4);
2580 decl
->gs_out_streams
= 0;
2581 for (unsigned i
= 0; i
< num_components
; ++i
)
2582 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2585 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2586 decl
->array_id
= num_output_arrays
+ 1;
2587 num_output_arrays
++;
2593 decl
->size
= type_size(var
->type
->fields
.array
);
2595 decl
->size
= type_size(var
->type
);
2597 if (var
->data
.fb_fetch_output
) {
2598 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2599 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2600 var
->type
, component
, decl
->array_id
);
2601 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2602 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2605 entry
= new(mem_ctx
) variable_storage(var
,
2610 entry
->component
= component
;
2612 _mesa_hash_table_insert(this->variables
, var
, entry
);
2616 case ir_var_system_value
:
2617 entry
= new(mem_ctx
) variable_storage(var
,
2618 PROGRAM_SYSTEM_VALUE
,
2619 var
->data
.location
);
2622 case ir_var_temporary
:
2623 st_src_reg src
= get_temp(var
->type
);
2625 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2627 _mesa_hash_table_insert(this->variables
, var
, entry
);
2633 printf("Failed to make storage for %s\n", var
->name
);
2638 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2639 entry
->component
, entry
->array_id
);
2640 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2641 var
->data
.mode
== ir_var_shader_in
&&
2642 var
->type
->without_array()->is_double())
2643 this->result
.is_double_vertex_input
= true;
2644 if (!native_integers
)
2645 this->result
.type
= GLSL_TYPE_FLOAT
;
2649 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2650 GLbitfield64
* usage_mask
,
2651 GLbitfield64 double_usage_mask
,
2652 GLbitfield
* patch_usage_mask
)
2657 /* Fix array declarations by removing unused array elements at both ends
2658 * of the arrays. For example, mat4[3] where only mat[1] is used.
2660 for (i
= 0; i
< count
; i
++) {
2661 struct inout_decl
*decl
= &decls
[i
];
2662 if (!decl
->array_id
)
2665 /* Shrink the beginning. */
2666 for (j
= 0; j
< (int)decl
->size
; j
++) {
2667 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2668 if (*patch_usage_mask
&
2669 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2673 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2675 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2684 /* Shrink the end. */
2685 for (j
= decl
->size
-1; j
>= 0; j
--) {
2686 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2687 if (*patch_usage_mask
&
2688 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2692 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2694 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2701 /* When not all entries of an array are accessed, we mark them as used
2702 * here anyway, to ensure that the input/output mapping logic doesn't get
2705 * TODO This happens when an array isn't used via indirect access, which
2706 * some game ports do (at least eON-based). There is an optimization
2707 * opportunity here by replacing the array declaration with non-array
2708 * declarations of those slots that are actually used.
2710 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2711 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2712 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2714 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2721 mark_array_io(struct inout_decl
*decls
, unsigned count
,
2722 GLbitfield64
* usage_mask
,
2723 GLbitfield64 double_usage_mask
,
2724 GLbitfield
* patch_usage_mask
)
2729 /* Fix array declarations by removing unused array elements at both ends
2730 * of the arrays. For example, mat4[3] where only mat[1] is used.
2732 for (i
= 0; i
< count
; i
++) {
2733 struct inout_decl
*decl
= &decls
[i
];
2734 if (!decl
->array_id
)
2737 /* When not all entries of an array are accessed, we mark them as used
2738 * here anyway, to ensure that the input/output mapping logic doesn't get
2741 * TODO This happens when an array isn't used via indirect access, which
2742 * some game ports do (at least eON-based). There is an optimization
2743 * opportunity here by replacing the array declaration with non-array
2744 * declarations of those slots that are actually used.
2746 for (j
= 0; j
< (int)decl
->size
; ++j
) {
2747 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2748 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2750 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2756 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2761 ir_variable
*var
= ir
->variable_referenced();
2763 if (handle_bound_deref(ir
->as_dereference()))
2766 /* We only need the logic provided by count_vec4_slots()
2767 * for arrays of structs. Indirect sampler and image indexing is handled
2770 int element_size
= ir
->type
->without_array()->is_struct() ?
2771 ir
->type
->count_vec4_slots(false, var
->data
.bindless
) :
2772 type_size(ir
->type
);
2774 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2776 ir
->array
->accept(this);
2779 if (!src
.has_index2
) {
2780 switch (this->prog
->Target
) {
2781 case GL_TESS_CONTROL_PROGRAM_NV
:
2782 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2783 !ir
->variable_referenced()->data
.patch
;
2785 case GL_TESS_EVALUATION_PROGRAM_NV
:
2786 is_2D
= src
.file
== PROGRAM_INPUT
&&
2787 !ir
->variable_referenced()->data
.patch
;
2789 case GL_GEOMETRY_PROGRAM_NV
:
2790 is_2D
= src
.file
== PROGRAM_INPUT
;
2800 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2801 src
.file
== PROGRAM_INPUT
)
2802 element_size
= attrib_type_size(ir
->type
, true);
2804 src
.index2D
= index
->value
.i
[0];
2805 src
.has_index2
= true;
2807 src
.index
+= index
->value
.i
[0] * element_size
;
2809 /* Variable index array dereference. It eats the "vec4" of the
2810 * base of the array and an index that offsets the TGSI register
2813 ir
->array_index
->accept(this);
2815 st_src_reg index_reg
;
2817 if (element_size
== 1) {
2818 index_reg
= this->result
;
2820 index_reg
= get_temp(native_integers
?
2821 glsl_type::int_type
: glsl_type::float_type
);
2823 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2824 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2827 /* If there was already a relative address register involved, add the
2828 * new and the old together to get the new offset.
2830 if (!is_2D
&& src
.reladdr
!= NULL
) {
2831 st_src_reg accum_reg
= get_temp(native_integers
?
2832 glsl_type::int_type
: glsl_type::float_type
);
2834 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2835 index_reg
, *src
.reladdr
);
2837 index_reg
= accum_reg
;
2841 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2842 *src
.reladdr2
= index_reg
;
2844 src
.has_index2
= true;
2846 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2847 *src
.reladdr
= index_reg
;
2851 /* Change the register type to the element type of the array. */
2852 src
.type
= ir
->type
->base_type
;
2858 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2861 const glsl_type
*struct_type
= ir
->record
->type
;
2862 ir_variable
*var
= ir
->record
->variable_referenced();
2865 if (handle_bound_deref(ir
->as_dereference()))
2868 ir
->record
->accept(this);
2870 assert(ir
->field_idx
>= 0);
2872 for (i
= 0; i
< struct_type
->length
; i
++) {
2873 if (i
== (unsigned) ir
->field_idx
)
2875 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2876 offset
+= member_type
->count_vec4_slots(false, var
->data
.bindless
);
2879 /* If the type is smaller than a vec4, replicate the last channel out. */
2880 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2881 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2883 this->result
.swizzle
= SWIZZLE_NOOP
;
2885 this->result
.index
+= offset
;
2886 this->result
.type
= ir
->type
->base_type
;
2890 * We want to be careful in assignment setup to hit the actual storage
2891 * instead of potentially using a temporary like we might with the
2892 * ir_dereference handler.
2895 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2897 /* The LHS must be a dereference. If the LHS is a variable indexed array
2898 * access of a vector, it must be separated into a series conditional moves
2899 * before reaching this point (see ir_vec_index_to_cond_assign).
2901 assert(ir
->as_dereference());
2902 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2904 assert(!deref_array
->array
->type
->is_vector());
2907 /* Use the rvalue deref handler for the most part. We write swizzles using
2908 * the writemask, but we do extract the base component for enhanced layouts
2909 * from the source swizzle.
2912 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2913 return st_dst_reg(v
->result
);
2917 * Process the condition of a conditional assignment
2919 * Examines the condition of a conditional assignment to generate the optimal
2920 * first operand of a \c CMP instruction. If the condition is a relational
2921 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2922 * used as the source for the \c CMP instruction. Otherwise the comparison
2923 * is processed to a boolean result, and the boolean result is used as the
2924 * operand to the CMP instruction.
2927 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2929 ir_rvalue
*src_ir
= ir
;
2931 bool switch_order
= false;
2933 ir_expression
*const expr
= ir
->as_expression();
2935 if (native_integers
) {
2936 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2937 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2938 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2939 type
== GLSL_TYPE_BOOL
) {
2940 if (expr
->operation
== ir_binop_equal
) {
2941 if (expr
->operands
[0]->is_zero()) {
2942 src_ir
= expr
->operands
[1];
2943 switch_order
= true;
2945 else if (expr
->operands
[1]->is_zero()) {
2946 src_ir
= expr
->operands
[0];
2947 switch_order
= true;
2950 else if (expr
->operation
== ir_binop_nequal
) {
2951 if (expr
->operands
[0]->is_zero()) {
2952 src_ir
= expr
->operands
[1];
2954 else if (expr
->operands
[1]->is_zero()) {
2955 src_ir
= expr
->operands
[0];
2961 src_ir
->accept(this);
2962 return switch_order
;
2965 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2966 bool zero_on_left
= false;
2968 if (expr
->operands
[0]->is_zero()) {
2969 src_ir
= expr
->operands
[1];
2970 zero_on_left
= true;
2971 } else if (expr
->operands
[1]->is_zero()) {
2972 src_ir
= expr
->operands
[0];
2973 zero_on_left
= false;
2977 * (a < 0) T F F ( a < 0) T F F
2978 * (0 < a) F F T (-a < 0) F F T
2979 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2980 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2982 * Note that exchanging the order of 0 and 'a' in the comparison simply
2983 * means that the value of 'a' should be negated.
2986 switch (expr
->operation
) {
2988 switch_order
= false;
2989 negate
= zero_on_left
;
2992 case ir_binop_gequal
:
2993 switch_order
= true;
2994 negate
= zero_on_left
;
2998 /* This isn't the right kind of comparison afterall, so make sure
2999 * the whole condition is visited.
3007 src_ir
->accept(this);
3009 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3010 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3011 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3012 * computing the condition.
3015 this->result
.negate
= ~this->result
.negate
;
3017 return switch_order
;
3021 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3022 st_dst_reg
*l
, st_src_reg
*r
,
3023 st_src_reg
*cond
, bool cond_swap
)
3025 if (type
->is_struct()) {
3026 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3027 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3033 if (type
->is_array()) {
3034 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3035 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3040 if (type
->is_matrix()) {
3041 const struct glsl_type
*vec_type
;
3043 vec_type
= glsl_type::get_instance(type
->is_double()
3044 ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3045 type
->vector_elements
, 1);
3047 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3048 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3053 assert(type
->is_scalar() || type
->is_vector());
3055 l
->type
= type
->base_type
;
3056 r
->type
= type
->base_type
;
3058 st_src_reg l_src
= st_src_reg(*l
);
3060 if (l_src
.file
== PROGRAM_OUTPUT
&&
3061 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
3062 (l_src
.index
== FRAG_RESULT_DEPTH
||
3063 l_src
.index
== FRAG_RESULT_STENCIL
)) {
3064 /* This is a special case because the source swizzles will be shifted
3065 * later to account for the difference between GLSL (where they're
3066 * plain floats) and TGSI (where they're Z and Y components). */
3067 l_src
.swizzle
= SWIZZLE_XXXX
;
3070 if (native_integers
) {
3071 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3072 cond_swap
? l_src
: *r
,
3073 cond_swap
? *r
: l_src
);
3075 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3076 cond_swap
? l_src
: *r
,
3077 cond_swap
? *r
: l_src
);
3080 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3084 if (type
->is_dual_slot()) {
3086 if (r
->is_double_vertex_input
== false)
3092 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3098 /* all generated instructions need to be flaged as precise */
3099 this->precise
= is_precise(ir
->lhs
->variable_referenced());
3100 ir
->rhs
->accept(this);
3103 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3107 int first_enabled_chan
= 0;
3109 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3111 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3112 variable
->data
.mode
== ir_var_shader_out
&&
3113 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3114 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3115 assert(ir
->lhs
->type
->is_scalar());
3116 assert(ir
->write_mask
== WRITEMASK_X
);
3118 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3119 l
.writemask
= WRITEMASK_Z
;
3121 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3122 l
.writemask
= WRITEMASK_Y
;
3124 } else if (ir
->write_mask
== 0) {
3125 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3127 unsigned num_elements
=
3128 ir
->lhs
->type
->without_array()->vector_elements
;
3131 l
.writemask
= u_bit_consecutive(0, num_elements
);
3133 /* The type is a struct or an array of (array of) structs. */
3134 l
.writemask
= WRITEMASK_XYZW
;
3137 l
.writemask
= ir
->write_mask
;
3140 for (int i
= 0; i
< 4; i
++) {
3141 if (l
.writemask
& (1 << i
)) {
3142 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3147 l
.writemask
= l
.writemask
<< dst_component
;
3149 /* Swizzle a small RHS vector into the channels being written.
3151 * glsl ir treats write_mask as dictating how many channels are
3152 * present on the RHS while TGSI treats write_mask as just
3153 * showing which channels of the vec4 RHS get written.
3155 for (int i
= 0; i
< 4; i
++) {
3156 if (l
.writemask
& (1 << i
))
3157 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3159 swizzles
[i
] = first_enabled_chan
;
3161 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3162 swizzles
[2], swizzles
[3]);
3165 assert(l
.file
!= PROGRAM_UNDEFINED
);
3166 assert(r
.file
!= PROGRAM_UNDEFINED
);
3168 if (ir
->condition
) {
3169 const bool switch_order
= this->process_move_condition(ir
->condition
);
3170 st_src_reg condition
= this->result
;
3172 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3173 } else if (ir
->rhs
->as_expression() &&
3174 this->instructions
.get_tail() &&
3175 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3176 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3177 type_size(ir
->lhs
->type
) == 1 &&
3178 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3179 /* To avoid emitting an extra MOV when assigning an expression to a
3180 * variable, emit the last instruction of the expression again, but
3181 * replace the destination register with the target of the assignment.
3182 * Dead code elimination will remove the original instruction.
3184 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3185 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3186 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3187 new_inst
->saturate
= inst
->saturate
;
3188 new_inst
->resource
= inst
->resource
;
3189 inst
->dead_mask
= inst
->dst
[0].writemask
;
3191 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3198 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3201 GLdouble stack_vals
[4] = { 0 };
3202 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3203 GLenum gl_type
= GL_NONE
;
3204 unsigned int i
, elements
;
3205 static int in_array
= 0;
3206 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3208 /* Unfortunately, 4 floats is all we can get into
3209 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3210 * aggregate constant and move each constant value into it. If we
3211 * get lucky, copy propagation will eliminate the extra moves.
3213 if (ir
->type
->is_struct()) {
3214 st_src_reg temp_base
= get_temp(ir
->type
);
3215 st_dst_reg temp
= st_dst_reg(temp_base
);
3217 for (i
= 0; i
< ir
->type
->length
; i
++) {
3218 ir_constant
*const field_value
= ir
->get_record_field(i
);
3219 int size
= type_size(field_value
->type
);
3223 field_value
->accept(this);
3226 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3227 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3233 this->result
= temp_base
;
3237 if (ir
->type
->is_array()) {
3238 st_src_reg temp_base
= get_temp(ir
->type
);
3239 st_dst_reg temp
= st_dst_reg(temp_base
);
3240 int size
= type_size(ir
->type
->fields
.array
);
3245 for (i
= 0; i
< ir
->type
->length
; i
++) {
3246 ir
->const_elements
[i
]->accept(this);
3248 for (int j
= 0; j
< size
; j
++) {
3249 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3255 this->result
= temp_base
;
3260 if (ir
->type
->is_matrix()) {
3261 st_src_reg mat
= get_temp(ir
->type
);
3262 st_dst_reg mat_column
= st_dst_reg(mat
);
3264 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3265 switch (ir
->type
->base_type
) {
3266 case GLSL_TYPE_FLOAT
:
3267 values
= (gl_constant_value
*)
3268 &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3270 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3271 src
.index
= add_constant(file
,
3273 ir
->type
->vector_elements
,
3276 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3278 case GLSL_TYPE_DOUBLE
:
3279 values
= (gl_constant_value
*)
3280 &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3281 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3282 src
.index
= add_constant(file
,
3284 ir
->type
->vector_elements
,
3287 if (ir
->type
->vector_elements
>= 2) {
3288 mat_column
.writemask
= WRITEMASK_XY
;
3289 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3290 SWIZZLE_X
, SWIZZLE_Y
);
3291 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3293 mat_column
.writemask
= WRITEMASK_X
;
3294 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
,
3295 SWIZZLE_X
, SWIZZLE_X
);
3296 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3299 if (ir
->type
->vector_elements
> 2) {
3300 if (ir
->type
->vector_elements
== 4) {
3301 mat_column
.writemask
= WRITEMASK_ZW
;
3302 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3303 SWIZZLE_X
, SWIZZLE_Y
);
3304 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3306 mat_column
.writemask
= WRITEMASK_Z
;
3307 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
,
3308 SWIZZLE_Y
, SWIZZLE_Y
);
3309 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3310 mat_column
.writemask
= WRITEMASK_XYZW
;
3311 src
.swizzle
= SWIZZLE_XYZW
;
3317 unreachable("Illegal matrix constant type.\n");
3326 elements
= ir
->type
->vector_elements
;
3327 switch (ir
->type
->base_type
) {
3328 case GLSL_TYPE_FLOAT
:
3330 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3331 values
[i
].f
= ir
->value
.f
[i
];
3334 case GLSL_TYPE_DOUBLE
:
3335 gl_type
= GL_DOUBLE
;
3336 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3337 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3340 case GLSL_TYPE_INT64
:
3341 gl_type
= GL_INT64_ARB
;
3342 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3343 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3346 case GLSL_TYPE_UINT64
:
3347 gl_type
= GL_UNSIGNED_INT64_ARB
;
3348 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3349 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3352 case GLSL_TYPE_UINT
:
3353 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3354 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3355 if (native_integers
)
3356 values
[i
].u
= ir
->value
.u
[i
];
3358 values
[i
].f
= ir
->value
.u
[i
];
3362 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3363 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3364 if (native_integers
)
3365 values
[i
].i
= ir
->value
.i
[i
];
3367 values
[i
].f
= ir
->value
.i
[i
];
3370 case GLSL_TYPE_BOOL
:
3371 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3372 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3373 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3376 case GLSL_TYPE_SAMPLER
:
3377 case GLSL_TYPE_IMAGE
:
3378 gl_type
= GL_UNSIGNED_INT
;
3380 values
[0].u
= ir
->value
.u64
[0] & 0xffffffff;
3381 values
[1].u
= ir
->value
.u64
[0] >> 32;
3384 assert(!"Non-float/uint/int/bool/sampler/image constant");
3387 this->result
= st_src_reg(file
, -1, ir
->type
);
3388 this->result
.index
= add_constant(file
,
3392 &this->result
.swizzle
);
3396 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3398 exec_node
*param
= ir
->actual_parameters
.get_head();
3399 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3400 ir_variable
*location
= deref
->variable_referenced();
3401 bool has_hw_atomics
= st_context(ctx
)->has_hw_atomics
;
3402 /* Calculate the surface offset */
3404 unsigned array_size
= 0, base
= 0;
3406 st_src_reg resource
;
3408 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3410 if (has_hw_atomics
) {
3411 variable_storage
*entry
= find_variable_storage(location
);
3412 st_src_reg
buffer(PROGRAM_HW_ATOMIC
, 0, GLSL_TYPE_ATOMIC_UINT
,
3413 location
->data
.binding
);
3416 entry
= new(mem_ctx
) variable_storage(location
, PROGRAM_HW_ATOMIC
,
3418 _mesa_hash_table_insert(this->variables
, location
, entry
);
3420 atomic_info
[num_atomics
].location
= location
->data
.location
;
3421 atomic_info
[num_atomics
].binding
= location
->data
.binding
;
3422 atomic_info
[num_atomics
].size
= location
->type
->arrays_of_arrays_size();
3423 if (atomic_info
[num_atomics
].size
== 0)
3424 atomic_info
[num_atomics
].size
= 1;
3425 atomic_info
[num_atomics
].array_id
= 0;
3429 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3430 if (atomic_info
[entry
->index
].array_id
== 0) {
3431 num_atomic_arrays
++;
3432 atomic_info
[entry
->index
].array_id
= num_atomic_arrays
;
3434 buffer
.array_id
= atomic_info
[entry
->index
].array_id
;
3437 buffer
.index
= index
;
3438 buffer
.index
+= location
->data
.offset
/ ATOMIC_COUNTER_SIZE
;
3439 buffer
.has_index2
= true;
3441 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3442 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3443 *buffer
.reladdr
= offset
;
3444 emit_arl(ir
, sampler_reladdr
, offset
);
3446 offset
= st_src_reg_for_int(0);
3450 st_src_reg
buffer(PROGRAM_BUFFER
,
3451 prog
->info
.num_ssbos
+
3452 location
->data
.binding
,
3453 GLSL_TYPE_ATOMIC_UINT
);
3455 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3456 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3457 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3458 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3459 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3461 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3466 ir
->return_deref
->accept(this);
3467 st_dst_reg
dst(this->result
);
3468 dst
.writemask
= WRITEMASK_X
;
3470 glsl_to_tgsi_instruction
*inst
;
3472 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3473 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3474 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3475 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3476 st_src_reg_for_int(1));
3477 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3478 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3479 st_src_reg_for_int(-1));
3480 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3482 param
= param
->get_next();
3483 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3486 st_src_reg data
= this->result
, data2
= undef_src
;
3487 enum tgsi_opcode opcode
;
3488 switch (ir
->callee
->intrinsic_id
) {
3489 case ir_intrinsic_atomic_counter_add
:
3490 opcode
= TGSI_OPCODE_ATOMUADD
;
3492 case ir_intrinsic_atomic_counter_min
:
3493 opcode
= TGSI_OPCODE_ATOMIMIN
;
3495 case ir_intrinsic_atomic_counter_max
:
3496 opcode
= TGSI_OPCODE_ATOMIMAX
;
3498 case ir_intrinsic_atomic_counter_and
:
3499 opcode
= TGSI_OPCODE_ATOMAND
;
3501 case ir_intrinsic_atomic_counter_or
:
3502 opcode
= TGSI_OPCODE_ATOMOR
;
3504 case ir_intrinsic_atomic_counter_xor
:
3505 opcode
= TGSI_OPCODE_ATOMXOR
;
3507 case ir_intrinsic_atomic_counter_exchange
:
3508 opcode
= TGSI_OPCODE_ATOMXCHG
;
3510 case ir_intrinsic_atomic_counter_comp_swap
: {
3511 opcode
= TGSI_OPCODE_ATOMCAS
;
3512 param
= param
->get_next();
3513 val
= ((ir_instruction
*)param
)->as_rvalue();
3515 data2
= this->result
;
3519 assert(!"Unexpected intrinsic");
3523 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3526 inst
->resource
= resource
;
3530 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3532 exec_node
*param
= ir
->actual_parameters
.get_head();
3534 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3536 param
= param
->get_next();
3537 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3539 ir_constant
*const_block
= block
->as_constant();
3542 const_block
? const_block
->value
.u
[0] : 0,
3546 block
->accept(this);
3547 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3548 *buffer
.reladdr
= this->result
;
3549 emit_arl(ir
, sampler_reladdr
, this->result
);
3552 /* Calculate the surface offset */
3553 offset
->accept(this);
3554 st_src_reg off
= this->result
;
3556 st_dst_reg dst
= undef_dst
;
3557 if (ir
->return_deref
) {
3558 ir
->return_deref
->accept(this);
3559 dst
= st_dst_reg(this->result
);
3560 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3563 glsl_to_tgsi_instruction
*inst
;
3565 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3566 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3567 if (dst
.type
== GLSL_TYPE_BOOL
)
3568 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
),
3569 st_src_reg_for_int(0));
3570 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3571 param
= param
->get_next();
3572 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3575 param
= param
->get_next();
3576 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3578 dst
.writemask
= write_mask
->value
.u
[0];
3580 dst
.type
= this->result
.type
;
3581 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3583 param
= param
->get_next();
3584 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3587 st_src_reg data
= this->result
, data2
= undef_src
;
3588 enum tgsi_opcode opcode
;
3589 switch (ir
->callee
->intrinsic_id
) {
3590 case ir_intrinsic_ssbo_atomic_add
:
3591 opcode
= TGSI_OPCODE_ATOMUADD
;
3593 case ir_intrinsic_ssbo_atomic_min
:
3594 opcode
= TGSI_OPCODE_ATOMIMIN
;
3596 case ir_intrinsic_ssbo_atomic_max
:
3597 opcode
= TGSI_OPCODE_ATOMIMAX
;
3599 case ir_intrinsic_ssbo_atomic_and
:
3600 opcode
= TGSI_OPCODE_ATOMAND
;
3602 case ir_intrinsic_ssbo_atomic_or
:
3603 opcode
= TGSI_OPCODE_ATOMOR
;
3605 case ir_intrinsic_ssbo_atomic_xor
:
3606 opcode
= TGSI_OPCODE_ATOMXOR
;
3608 case ir_intrinsic_ssbo_atomic_exchange
:
3609 opcode
= TGSI_OPCODE_ATOMXCHG
;
3611 case ir_intrinsic_ssbo_atomic_comp_swap
:
3612 opcode
= TGSI_OPCODE_ATOMCAS
;
3613 param
= param
->get_next();
3614 val
= ((ir_instruction
*)param
)->as_rvalue();
3616 data2
= this->result
;
3619 assert(!"Unexpected intrinsic");
3623 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3626 param
= param
->get_next();
3627 ir_constant
*access
= NULL
;
3628 if (!param
->is_tail_sentinel()) {
3629 access
= ((ir_instruction
*)param
)->as_constant();
3633 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3637 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3639 switch (ir
->callee
->intrinsic_id
) {
3640 case ir_intrinsic_memory_barrier
:
3641 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3642 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3643 TGSI_MEMBAR_ATOMIC_BUFFER
|
3644 TGSI_MEMBAR_SHADER_IMAGE
|
3645 TGSI_MEMBAR_SHARED
));
3647 case ir_intrinsic_memory_barrier_atomic_counter
:
3648 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3649 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3651 case ir_intrinsic_memory_barrier_buffer
:
3652 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3653 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3655 case ir_intrinsic_memory_barrier_image
:
3656 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3657 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3659 case ir_intrinsic_memory_barrier_shared
:
3660 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3661 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3663 case ir_intrinsic_group_memory_barrier
:
3664 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3665 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3666 TGSI_MEMBAR_ATOMIC_BUFFER
|
3667 TGSI_MEMBAR_SHADER_IMAGE
|
3668 TGSI_MEMBAR_SHARED
|
3669 TGSI_MEMBAR_THREAD_GROUP
));
3672 assert(!"Unexpected memory barrier intrinsic");
3677 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3679 exec_node
*param
= ir
->actual_parameters
.get_head();
3681 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3683 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3685 /* Calculate the surface offset */
3686 offset
->accept(this);
3687 st_src_reg off
= this->result
;
3689 st_dst_reg dst
= undef_dst
;
3690 if (ir
->return_deref
) {
3691 ir
->return_deref
->accept(this);
3692 dst
= st_dst_reg(this->result
);
3693 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3696 glsl_to_tgsi_instruction
*inst
;
3698 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3699 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3700 inst
->resource
= buffer
;
3701 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3702 param
= param
->get_next();
3703 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3706 param
= param
->get_next();
3707 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3709 dst
.writemask
= write_mask
->value
.u
[0];
3711 dst
.type
= this->result
.type
;
3712 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3713 inst
->resource
= buffer
;
3715 param
= param
->get_next();
3716 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3719 st_src_reg data
= this->result
, data2
= undef_src
;
3720 enum tgsi_opcode opcode
;
3721 switch (ir
->callee
->intrinsic_id
) {
3722 case ir_intrinsic_shared_atomic_add
:
3723 opcode
= TGSI_OPCODE_ATOMUADD
;
3725 case ir_intrinsic_shared_atomic_min
:
3726 opcode
= TGSI_OPCODE_ATOMIMIN
;
3728 case ir_intrinsic_shared_atomic_max
:
3729 opcode
= TGSI_OPCODE_ATOMIMAX
;
3731 case ir_intrinsic_shared_atomic_and
:
3732 opcode
= TGSI_OPCODE_ATOMAND
;
3734 case ir_intrinsic_shared_atomic_or
:
3735 opcode
= TGSI_OPCODE_ATOMOR
;
3737 case ir_intrinsic_shared_atomic_xor
:
3738 opcode
= TGSI_OPCODE_ATOMXOR
;
3740 case ir_intrinsic_shared_atomic_exchange
:
3741 opcode
= TGSI_OPCODE_ATOMXCHG
;
3743 case ir_intrinsic_shared_atomic_comp_swap
:
3744 opcode
= TGSI_OPCODE_ATOMCAS
;
3745 param
= param
->get_next();
3746 val
= ((ir_instruction
*)param
)->as_rvalue();
3748 data2
= this->result
;
3751 assert(!"Unexpected intrinsic");
3755 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3756 inst
->resource
= buffer
;
3761 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3762 bool *memory_coherent
, bool *memory_volatile
,
3763 bool *memory_restrict
, bool *memory_read_only
,
3764 unsigned *image_format
)
3767 switch (ir
->ir_type
) {
3768 case ir_type_dereference_record
: {
3769 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3770 const glsl_type
*struct_type
= deref_record
->record
->type
;
3771 int fild_idx
= deref_record
->field_idx
;
3773 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3775 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3777 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3779 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3781 struct_type
->fields
.structure
[fild_idx
].memory_read_only
;
3783 struct_type
->fields
.structure
[fild_idx
].image_format
;
3787 case ir_type_dereference_array
: {
3788 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3789 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3790 memory_coherent
, memory_volatile
, memory_restrict
,
3791 memory_read_only
, image_format
);
3795 case ir_type_dereference_variable
: {
3796 ir_variable
*var
= ir
->variable_referenced();
3798 *type
= var
->type
->without_array();
3799 *memory_coherent
= var
->data
.memory_coherent
;
3800 *memory_volatile
= var
->data
.memory_volatile
;
3801 *memory_restrict
= var
->data
.memory_restrict
;
3802 *memory_read_only
= var
->data
.memory_read_only
;
3803 *image_format
= var
->data
.image_format
;
3813 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3815 exec_node
*param
= ir
->actual_parameters
.get_head();
3817 ir_dereference
*img
= (ir_dereference
*)param
;
3818 const ir_variable
*imgvar
= img
->variable_referenced();
3819 unsigned sampler_array_size
= 1, sampler_base
= 0;
3820 bool memory_coherent
= false, memory_volatile
= false,
3821 memory_restrict
= false, memory_read_only
= false;
3822 unsigned image_format
= 0;
3823 const glsl_type
*type
= NULL
;
3825 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3826 &memory_restrict
, &memory_read_only
, &image_format
);
3829 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3831 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3832 &index
, &reladdr
, !imgvar
->contains_bindless());
3834 image
.index
= index
;
3835 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3836 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3837 *image
.reladdr
= reladdr
;
3838 emit_arl(ir
, sampler_reladdr
, reladdr
);
3841 st_dst_reg dst
= undef_dst
;
3842 if (ir
->return_deref
) {
3843 ir
->return_deref
->accept(this);
3844 dst
= st_dst_reg(this->result
);
3845 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3848 glsl_to_tgsi_instruction
*inst
;
3850 st_src_reg bindless
;
3851 if (imgvar
->contains_bindless()) {
3853 bindless
= this->result
;
3856 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3857 dst
.writemask
= WRITEMASK_XYZ
;
3858 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3859 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3860 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3861 st_dst_reg dstres
= st_dst_reg(res
);
3862 dstres
.writemask
= WRITEMASK_W
;
3863 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3864 res
.swizzle
= SWIZZLE_WWWW
;
3865 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3867 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3869 st_dst_reg coord_dst
;
3870 coord
= get_temp(glsl_type::ivec4_type
);
3871 coord_dst
= st_dst_reg(coord
);
3872 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3873 param
= param
->get_next();
3874 ((ir_dereference
*)param
)->accept(this);
3875 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3876 coord
.swizzle
= SWIZZLE_XXXX
;
3877 switch (type
->coordinate_components()) {
3878 case 4: assert(!"unexpected coord count");
3880 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3882 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3885 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3886 param
= param
->get_next();
3887 ((ir_dereference
*)param
)->accept(this);
3888 st_src_reg sample
= this->result
;
3889 sample
.swizzle
= SWIZZLE_XXXX
;
3890 coord_dst
.writemask
= WRITEMASK_W
;
3891 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3892 coord
.swizzle
|= SWIZZLE_W
<< 9;
3895 param
= param
->get_next();
3896 if (!param
->is_tail_sentinel()) {
3897 ((ir_dereference
*)param
)->accept(this);
3898 arg1
= this->result
;
3899 param
= param
->get_next();
3902 if (!param
->is_tail_sentinel()) {
3903 ((ir_dereference
*)param
)->accept(this);
3904 arg2
= this->result
;
3905 param
= param
->get_next();
3908 assert(param
->is_tail_sentinel());
3910 enum tgsi_opcode opcode
;
3911 switch (ir
->callee
->intrinsic_id
) {
3912 case ir_intrinsic_image_load
:
3913 opcode
= TGSI_OPCODE_LOAD
;
3915 case ir_intrinsic_image_store
:
3916 opcode
= TGSI_OPCODE_STORE
;
3918 case ir_intrinsic_image_atomic_add
:
3919 opcode
= TGSI_OPCODE_ATOMUADD
;
3921 case ir_intrinsic_image_atomic_min
:
3922 opcode
= TGSI_OPCODE_ATOMIMIN
;
3924 case ir_intrinsic_image_atomic_max
:
3925 opcode
= TGSI_OPCODE_ATOMIMAX
;
3927 case ir_intrinsic_image_atomic_and
:
3928 opcode
= TGSI_OPCODE_ATOMAND
;
3930 case ir_intrinsic_image_atomic_or
:
3931 opcode
= TGSI_OPCODE_ATOMOR
;
3933 case ir_intrinsic_image_atomic_xor
:
3934 opcode
= TGSI_OPCODE_ATOMXOR
;
3936 case ir_intrinsic_image_atomic_exchange
:
3937 opcode
= TGSI_OPCODE_ATOMXCHG
;
3939 case ir_intrinsic_image_atomic_comp_swap
:
3940 opcode
= TGSI_OPCODE_ATOMCAS
;
3942 case ir_intrinsic_image_atomic_inc_wrap
: {
3943 /* There's a bit of disagreement between GLSL and the hardware. The
3944 * hardware wants to wrap after the given wrap value, while GLSL
3945 * wants to wrap at the value. Subtract 1 to make up the difference.
3947 st_src_reg wrap
= get_temp(glsl_type::uint_type
);
3948 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(wrap
),
3949 arg1
, st_src_reg_for_int(-1));
3951 opcode
= TGSI_OPCODE_ATOMINC_WRAP
;
3954 case ir_intrinsic_image_atomic_dec_wrap
:
3955 opcode
= TGSI_OPCODE_ATOMDEC_WRAP
;
3958 assert(!"Unexpected intrinsic");
3962 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3963 if (opcode
== TGSI_OPCODE_STORE
)
3964 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3967 if (imgvar
->contains_bindless()) {
3968 inst
->resource
= bindless
;
3969 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3970 SWIZZLE_X
, SWIZZLE_Y
);
3972 inst
->resource
= image
;
3973 inst
->sampler_array_size
= sampler_array_size
;
3974 inst
->sampler_base
= sampler_base
;
3977 inst
->tex_target
= type
->sampler_index();
3978 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3979 _mesa_get_shader_image_format(image_format
));
3980 inst
->read_only
= memory_read_only
;
3982 if (memory_coherent
)
3983 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3984 if (memory_restrict
)
3985 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3986 if (memory_volatile
)
3987 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3991 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, enum tgsi_opcode op
)
3993 ir
->return_deref
->accept(this);
3994 st_dst_reg dst
= st_dst_reg(this->result
);
3996 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3998 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3999 unsigned num_src
= 0;
4000 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
4001 assert(num_src
< ARRAY_SIZE(src
));
4003 this->result
.file
= PROGRAM_UNDEFINED
;
4004 param
->accept(this);
4005 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4007 src
[num_src
] = this->result
;
4011 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
4015 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
4017 ir_function_signature
*sig
= ir
->callee
;
4019 /* Filter out intrinsics */
4020 switch (sig
->intrinsic_id
) {
4021 case ir_intrinsic_atomic_counter_read
:
4022 case ir_intrinsic_atomic_counter_increment
:
4023 case ir_intrinsic_atomic_counter_predecrement
:
4024 case ir_intrinsic_atomic_counter_add
:
4025 case ir_intrinsic_atomic_counter_min
:
4026 case ir_intrinsic_atomic_counter_max
:
4027 case ir_intrinsic_atomic_counter_and
:
4028 case ir_intrinsic_atomic_counter_or
:
4029 case ir_intrinsic_atomic_counter_xor
:
4030 case ir_intrinsic_atomic_counter_exchange
:
4031 case ir_intrinsic_atomic_counter_comp_swap
:
4032 visit_atomic_counter_intrinsic(ir
);
4035 case ir_intrinsic_ssbo_load
:
4036 case ir_intrinsic_ssbo_store
:
4037 case ir_intrinsic_ssbo_atomic_add
:
4038 case ir_intrinsic_ssbo_atomic_min
:
4039 case ir_intrinsic_ssbo_atomic_max
:
4040 case ir_intrinsic_ssbo_atomic_and
:
4041 case ir_intrinsic_ssbo_atomic_or
:
4042 case ir_intrinsic_ssbo_atomic_xor
:
4043 case ir_intrinsic_ssbo_atomic_exchange
:
4044 case ir_intrinsic_ssbo_atomic_comp_swap
:
4045 visit_ssbo_intrinsic(ir
);
4048 case ir_intrinsic_memory_barrier
:
4049 case ir_intrinsic_memory_barrier_atomic_counter
:
4050 case ir_intrinsic_memory_barrier_buffer
:
4051 case ir_intrinsic_memory_barrier_image
:
4052 case ir_intrinsic_memory_barrier_shared
:
4053 case ir_intrinsic_group_memory_barrier
:
4054 visit_membar_intrinsic(ir
);
4057 case ir_intrinsic_shared_load
:
4058 case ir_intrinsic_shared_store
:
4059 case ir_intrinsic_shared_atomic_add
:
4060 case ir_intrinsic_shared_atomic_min
:
4061 case ir_intrinsic_shared_atomic_max
:
4062 case ir_intrinsic_shared_atomic_and
:
4063 case ir_intrinsic_shared_atomic_or
:
4064 case ir_intrinsic_shared_atomic_xor
:
4065 case ir_intrinsic_shared_atomic_exchange
:
4066 case ir_intrinsic_shared_atomic_comp_swap
:
4067 visit_shared_intrinsic(ir
);
4070 case ir_intrinsic_image_load
:
4071 case ir_intrinsic_image_store
:
4072 case ir_intrinsic_image_atomic_add
:
4073 case ir_intrinsic_image_atomic_min
:
4074 case ir_intrinsic_image_atomic_max
:
4075 case ir_intrinsic_image_atomic_and
:
4076 case ir_intrinsic_image_atomic_or
:
4077 case ir_intrinsic_image_atomic_xor
:
4078 case ir_intrinsic_image_atomic_exchange
:
4079 case ir_intrinsic_image_atomic_comp_swap
:
4080 case ir_intrinsic_image_size
:
4081 case ir_intrinsic_image_samples
:
4082 case ir_intrinsic_image_atomic_inc_wrap
:
4083 case ir_intrinsic_image_atomic_dec_wrap
:
4084 visit_image_intrinsic(ir
);
4087 case ir_intrinsic_shader_clock
:
4088 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4091 case ir_intrinsic_vote_all
:
4092 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4094 case ir_intrinsic_vote_any
:
4095 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4097 case ir_intrinsic_vote_eq
:
4098 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4100 case ir_intrinsic_ballot
:
4101 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4103 case ir_intrinsic_read_first_invocation
:
4104 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4106 case ir_intrinsic_read_invocation
:
4107 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4110 case ir_intrinsic_helper_invocation
:
4111 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_HELPER
);
4114 case ir_intrinsic_invalid
:
4115 case ir_intrinsic_generic_load
:
4116 case ir_intrinsic_generic_store
:
4117 case ir_intrinsic_generic_atomic_add
:
4118 case ir_intrinsic_generic_atomic_and
:
4119 case ir_intrinsic_generic_atomic_or
:
4120 case ir_intrinsic_generic_atomic_xor
:
4121 case ir_intrinsic_generic_atomic_min
:
4122 case ir_intrinsic_generic_atomic_max
:
4123 case ir_intrinsic_generic_atomic_exchange
:
4124 case ir_intrinsic_generic_atomic_comp_swap
:
4125 case ir_intrinsic_begin_invocation_interlock
:
4126 case ir_intrinsic_end_invocation_interlock
:
4127 unreachable("Invalid intrinsic");
4132 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4133 unsigned *array_elements
,
4135 st_src_reg
*indirect
,
4138 switch (tail
->ir_type
) {
4139 case ir_type_dereference_record
: {
4140 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4141 const glsl_type
*struct_type
= deref_record
->record
->type
;
4142 int field_index
= deref_record
->field_idx
;
4144 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4146 assert(field_index
>= 0);
4147 *location
+= struct_type
->struct_location_offset(field_index
);
4151 case ir_type_dereference_array
: {
4152 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4154 void *mem_ctx
= ralloc_parent(deref_arr
);
4155 ir_constant
*array_index
=
4156 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
4159 st_src_reg temp_reg
;
4160 st_dst_reg temp_dst
;
4162 temp_reg
= get_temp(glsl_type::uint_type
);
4163 temp_dst
= st_dst_reg(temp_reg
);
4164 temp_dst
.writemask
= 1;
4166 deref_arr
->array_index
->accept(this);
4167 if (*array_elements
!= 1)
4168 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4170 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4172 if (indirect
->file
== PROGRAM_UNDEFINED
)
4173 *indirect
= temp_reg
;
4175 temp_dst
= st_dst_reg(*indirect
);
4176 temp_dst
.writemask
= 1;
4177 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4180 *index
+= array_index
->value
.u
[0] * *array_elements
;
4182 *array_elements
*= deref_arr
->array
->type
->length
;
4184 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4193 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4194 unsigned *array_size
,
4197 st_src_reg
*reladdr
,
4200 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4201 unsigned location
= 0;
4202 ir_variable
*var
= ir
->variable_referenced();
4210 location
= var
->data
.location
;
4211 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4214 * If we end up with no indirect then adjust the base to the index,
4215 * and set the array size to 1.
4217 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4223 assert(location
!= 0xffffffff);
4224 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4225 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4230 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4232 if (offset
.reladdr
|| offset
.reladdr2
||
4233 offset
.has_index2
||
4234 offset
.file
== PROGRAM_UNIFORM
||
4235 offset
.file
== PROGRAM_CONSTANT
||
4236 offset
.file
== PROGRAM_STATE_VAR
) {
4237 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4238 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4239 tmp_dst
.writemask
= WRITEMASK_XY
;
4240 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4248 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference
*ir
)
4250 ir_variable
*var
= ir
->variable_referenced();
4252 if (!var
|| var
->data
.mode
!= ir_var_uniform
|| var
->data
.bindless
||
4253 !(ir
->type
->is_image() || ir
->type
->is_sampler()))
4256 /* Convert from bound sampler/image to bindless handle. */
4257 bool is_image
= ir
->type
->is_image();
4258 st_src_reg
resource(is_image
? PROGRAM_IMAGE
: PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4260 unsigned array_size
= 1, base
= 0;
4262 get_deref_offsets(ir
, &array_size
, &base
, &index
, &reladdr
, true);
4264 resource
.index
= index
;
4265 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4266 resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4267 *resource
.reladdr
= reladdr
;
4268 emit_arl(ir
, sampler_reladdr
, reladdr
);
4271 this->result
= get_temp(glsl_type::uvec2_type
);
4272 st_dst_reg
dst(this->result
);
4273 dst
.writemask
= WRITEMASK_XY
;
4275 glsl_to_tgsi_instruction
*inst
= emit_asm(
4276 ir
, is_image
? TGSI_OPCODE_IMG2HND
: TGSI_OPCODE_SAMP2HND
, dst
);
4278 inst
->tex_target
= ir
->type
->sampler_index();
4279 inst
->resource
= resource
;
4280 inst
->sampler_array_size
= array_size
;
4281 inst
->sampler_base
= base
;
4287 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4289 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4290 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4291 st_src_reg levels_src
, reladdr
;
4292 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4293 glsl_to_tgsi_instruction
*inst
= NULL
;
4294 enum tgsi_opcode opcode
= TGSI_OPCODE_NOP
;
4295 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4296 unsigned sampler_array_size
= 1, sampler_base
= 0;
4297 bool is_cube_array
= false, is_cube_shadow
= false;
4298 ir_variable
*var
= ir
->sampler
->variable_referenced();
4301 /* if we are a cube array sampler or a cube shadow */
4302 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4303 is_cube_array
= sampler_type
->sampler_array
;
4304 is_cube_shadow
= sampler_type
->sampler_shadow
;
4307 if (ir
->coordinate
) {
4308 ir
->coordinate
->accept(this);
4310 /* Put our coords in a temp. We'll need to modify them for shadow,
4311 * projection, or LOD, so the only case we'd use it as-is is if
4312 * we're doing plain old texturing. The optimization passes on
4313 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4315 coord
= get_temp(glsl_type::vec4_type
);
4316 coord_dst
= st_dst_reg(coord
);
4317 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4318 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4321 if (ir
->projector
) {
4322 ir
->projector
->accept(this);
4323 projector
= this->result
;
4326 /* Storage for our result. Ideally for an assignment we'd be using
4327 * the actual storage for the result here, instead.
4329 result_src
= get_temp(ir
->type
);
4330 result_dst
= st_dst_reg(result_src
);
4331 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4335 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4337 ir
->offset
->accept(this);
4338 offset
[0] = this->result
;
4342 if (is_cube_array
|| is_cube_shadow
) {
4343 opcode
= TGSI_OPCODE_TXB2
;
4346 opcode
= TGSI_OPCODE_TXB
;
4348 ir
->lod_info
.bias
->accept(this);
4349 lod_info
= this->result
;
4351 ir
->offset
->accept(this);
4352 offset
[0] = this->result
;
4356 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4357 opcode
= TGSI_OPCODE_TEX_LZ
;
4359 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4360 ir
->lod_info
.lod
->accept(this);
4361 lod_info
= this->result
;
4364 ir
->offset
->accept(this);
4365 offset
[0] = this->result
;
4369 opcode
= TGSI_OPCODE_TXD
;
4370 ir
->lod_info
.grad
.dPdx
->accept(this);
4372 ir
->lod_info
.grad
.dPdy
->accept(this);
4375 ir
->offset
->accept(this);
4376 offset
[0] = this->result
;
4380 opcode
= TGSI_OPCODE_TXQ
;
4381 ir
->lod_info
.lod
->accept(this);
4382 lod_info
= this->result
;
4384 case ir_query_levels
:
4385 opcode
= TGSI_OPCODE_TXQ
;
4386 lod_info
= undef_src
;
4387 levels_src
= get_temp(ir
->type
);
4390 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4391 opcode
= TGSI_OPCODE_TXF_LZ
;
4393 opcode
= TGSI_OPCODE_TXF
;
4394 ir
->lod_info
.lod
->accept(this);
4395 lod_info
= this->result
;
4398 ir
->offset
->accept(this);
4399 offset
[0] = this->result
;
4403 opcode
= TGSI_OPCODE_TXF
;
4404 ir
->lod_info
.sample_index
->accept(this);
4405 sample_index
= this->result
;
4408 opcode
= TGSI_OPCODE_TG4
;
4409 ir
->lod_info
.component
->accept(this);
4410 component
= this->result
;
4412 ir
->offset
->accept(this);
4413 if (ir
->offset
->type
->is_array()) {
4414 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4415 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4416 offset
[i
] = this->result
;
4417 offset
[i
].index
+= i
* type_size(elt_type
);
4418 offset
[i
].type
= elt_type
->base_type
;
4419 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4420 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4423 offset
[0] = canonicalize_gather_offset(this->result
);
4428 opcode
= TGSI_OPCODE_LODQ
;
4430 case ir_texture_samples
:
4431 opcode
= TGSI_OPCODE_TXQS
;
4433 case ir_samples_identical
:
4434 unreachable("Unexpected ir_samples_identical opcode");
4437 if (ir
->projector
) {
4438 if (opcode
== TGSI_OPCODE_TEX
) {
4439 /* Slot the projector in as the last component of the coord. */
4440 coord_dst
.writemask
= WRITEMASK_W
;
4441 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4442 coord_dst
.writemask
= WRITEMASK_XYZW
;
4443 opcode
= TGSI_OPCODE_TXP
;
4445 st_src_reg coord_w
= coord
;
4446 coord_w
.swizzle
= SWIZZLE_WWWW
;
4448 /* For the other TEX opcodes there's no projective version
4449 * since the last slot is taken up by LOD info. Do the
4450 * projective divide now.
4452 coord_dst
.writemask
= WRITEMASK_W
;
4453 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4455 /* In the case where we have to project the coordinates "by hand,"
4456 * the shadow comparator value must also be projected.
4458 st_src_reg tmp_src
= coord
;
4459 if (ir
->shadow_comparator
) {
4460 /* Slot the shadow value in as the second to last component of the
4463 ir
->shadow_comparator
->accept(this);
4465 tmp_src
= get_temp(glsl_type::vec4_type
);
4466 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4468 /* Projective division not allowed for array samplers. */
4469 assert(!sampler_type
->sampler_array
);
4471 tmp_dst
.writemask
= WRITEMASK_Z
;
4472 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4474 tmp_dst
.writemask
= WRITEMASK_XY
;
4475 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4478 coord_dst
.writemask
= WRITEMASK_XYZ
;
4479 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4481 coord_dst
.writemask
= WRITEMASK_XYZW
;
4482 coord
.swizzle
= SWIZZLE_XYZW
;
4486 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4487 * shadow comparator was put in the correct place (and projected) by the
4488 * code, above, that handles by-hand projection.
4490 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4491 /* Slot the shadow value in as the second to last component of the
4494 ir
->shadow_comparator
->accept(this);
4496 if (is_cube_array
) {
4497 cube_sc
= get_temp(glsl_type::float_type
);
4498 cube_sc_dst
= st_dst_reg(cube_sc
);
4499 cube_sc_dst
.writemask
= WRITEMASK_X
;
4500 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4501 cube_sc_dst
.writemask
= WRITEMASK_X
;
4504 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4505 sampler_type
->sampler_array
) ||
4506 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4507 coord_dst
.writemask
= WRITEMASK_W
;
4509 coord_dst
.writemask
= WRITEMASK_Z
;
4511 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4512 coord_dst
.writemask
= WRITEMASK_XYZW
;
4516 if (ir
->op
== ir_txf_ms
) {
4517 coord_dst
.writemask
= WRITEMASK_W
;
4518 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4519 coord_dst
.writemask
= WRITEMASK_XYZW
;
4520 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4521 opcode
== TGSI_OPCODE_TXF
) {
4522 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4523 coord_dst
.writemask
= WRITEMASK_W
;
4524 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4525 coord_dst
.writemask
= WRITEMASK_XYZW
;
4528 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4531 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4532 &index
, &reladdr
, !var
->contains_bindless());
4534 sampler
.index
= index
;
4535 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4536 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4537 *sampler
.reladdr
= reladdr
;
4538 emit_arl(ir
, sampler_reladdr
, reladdr
);
4541 st_src_reg bindless
;
4542 if (var
->contains_bindless()) {
4543 ir
->sampler
->accept(this);
4544 bindless
= this->result
;
4547 if (opcode
== TGSI_OPCODE_TXD
)
4548 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4549 else if (opcode
== TGSI_OPCODE_TXQ
) {
4550 if (ir
->op
== ir_query_levels
) {
4551 /* the level is stored in W */
4552 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4553 result_dst
.writemask
= WRITEMASK_X
;
4554 levels_src
.swizzle
= SWIZZLE_WWWW
;
4555 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4557 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4558 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4559 inst
= emit_asm(ir
, opcode
, result_dst
);
4560 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4561 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4562 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4563 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4564 } else if (opcode
== TGSI_OPCODE_TG4
) {
4565 if (is_cube_array
&& ir
->shadow_comparator
) {
4566 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4568 if (this->tg4_component_in_swizzle
) {
4569 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4571 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
4572 if (component
.index
== idx
) {
4573 gl_constant_value value
= entry
->values
[component
.swizzle
];
4574 inst
->gather_component
= value
.i
;
4580 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4584 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4586 if (ir
->shadow_comparator
)
4587 inst
->tex_shadow
= GL_TRUE
;
4589 if (var
->contains_bindless()) {
4590 inst
->resource
= bindless
;
4591 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4592 SWIZZLE_X
, SWIZZLE_Y
);
4594 inst
->resource
= sampler
;
4595 inst
->sampler_array_size
= sampler_array_size
;
4596 inst
->sampler_base
= sampler_base
;
4600 if (!inst
->tex_offsets
)
4601 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
,
4602 MAX_GLSL_TEXTURE_OFFSET
);
4604 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&&
4605 offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4606 inst
->tex_offsets
[i
] = offset
[i
];
4607 inst
->tex_offset_num_offset
= i
;
4610 inst
->tex_target
= sampler_type
->sampler_index();
4611 inst
->tex_type
= ir
->type
->base_type
;
4613 this->result
= result_src
;
4617 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4619 assert(!ir
->get_value());
4621 emit_asm(ir
, TGSI_OPCODE_RET
);
4625 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4627 if (ir
->condition
) {
4628 ir
->condition
->accept(this);
4629 st_src_reg condition
= this->result
;
4631 /* Convert the bool condition to a float so we can negate. */
4632 if (native_integers
) {
4633 st_src_reg temp
= get_temp(ir
->condition
->type
);
4634 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4635 condition
, st_src_reg_for_float(1.0));
4639 condition
.negate
= ~condition
.negate
;
4640 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4642 /* unconditional kil */
4643 emit_asm(ir
, TGSI_OPCODE_KILL
);
4648 glsl_to_tgsi_visitor::visit(ir_demote
*ir
)
4650 emit_asm(ir
, TGSI_OPCODE_DEMOTE
);
4654 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4656 enum tgsi_opcode if_opcode
;
4657 glsl_to_tgsi_instruction
*if_inst
;
4659 ir
->condition
->accept(this);
4660 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4662 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4664 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4666 this->instructions
.push_tail(if_inst
);
4668 visit_exec_list(&ir
->then_instructions
, this);
4670 if (!ir
->else_instructions
.is_empty()) {
4671 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4672 visit_exec_list(&ir
->else_instructions
, this);
4675 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4680 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4682 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4684 ir
->stream
->accept(this);
4685 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4689 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4691 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4693 ir
->stream
->accept(this);
4694 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4698 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4700 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4701 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4703 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4706 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4708 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4710 result
.file
= PROGRAM_UNDEFINED
;
4717 num_input_arrays
= 0;
4718 num_output_arrays
= 0;
4720 num_atomic_arrays
= 0;
4722 num_address_regs
= 0;
4725 indirect_addr_consts
= false;
4726 wpos_transform_const
= -1;
4727 native_integers
= false;
4728 mem_ctx
= ralloc_context(NULL
);
4733 tg4_component_in_swizzle
= false;
4734 shader_program
= NULL
;
4739 use_shared_memory
= false;
4740 has_tex_txf_lz
= false;
4744 static void var_destroy(struct hash_entry
*entry
)
4746 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4751 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4753 _mesa_hash_table_destroy(variables
, var_destroy
);
4755 ralloc_free(mem_ctx
);
4758 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4765 * Count resources used by the given gpu program (number of texture
4769 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4771 v
->samplers_used
= 0;
4773 prog
->info
.textures_used_by_txf
= 0;
4775 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4776 if (inst
->info
->is_tex
) {
4777 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4778 unsigned idx
= inst
->sampler_base
+ i
;
4779 v
->samplers_used
|= 1u << idx
;
4781 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4782 v
->sampler_types
[idx
] = inst
->tex_type
;
4783 v
->sampler_targets
[idx
] =
4784 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4786 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4787 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4792 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4793 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4795 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4796 is_resource_instruction(inst
->op
) ||
4797 inst
->op
== TGSI_OPCODE_STORE
)) {
4798 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4799 v
->use_shared_memory
= true;
4800 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4801 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4802 unsigned idx
= inst
->sampler_base
+ i
;
4803 v
->images_used
|= 1 << idx
;
4804 v
->image_targets
[idx
] =
4805 st_translate_texture_target(inst
->tex_target
, false);
4806 v
->image_formats
[idx
] = inst
->image_format
;
4807 v
->image_wr
[idx
] = !inst
->read_only
;
4812 prog
->SamplersUsed
= v
->samplers_used
;
4814 if (v
->shader_program
!= NULL
)
4815 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4819 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4820 * are read from the given src in this instruction
4823 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4825 int read_mask
= 0, comp
;
4827 /* Now, given the src swizzle and the written channels, find which
4828 * components are actually read
4830 for (comp
= 0; comp
< 4; ++comp
) {
4831 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4833 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4834 read_mask
|= 1 << coord
;
4841 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4842 * instruction is the first instruction to write to register T0. There are
4843 * several lowering passes done in GLSL IR (e.g. branches and
4844 * relative addressing) that create a large number of conditional assignments
4845 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4847 * Here is why this conversion is safe:
4848 * CMP T0, T1 T2 T0 can be expanded to:
4854 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4855 * as the original program. If (T1 < 0.0) evaluates to false, executing
4856 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4857 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4858 * because any instruction that was going to read from T0 after this was going
4859 * to read a garbage value anyway.
4862 glsl_to_tgsi_visitor::simplify_cmp(void)
4864 int tempWritesSize
= 0;
4865 unsigned *tempWrites
= NULL
;
4866 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4868 memset(outputWrites
, 0, sizeof(outputWrites
));
4870 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4871 unsigned prevWriteMask
= 0;
4873 /* Give up if we encounter relative addressing or flow control. */
4874 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4875 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4876 inst
->info
->is_branch
||
4877 inst
->op
== TGSI_OPCODE_CONT
||
4878 inst
->op
== TGSI_OPCODE_END
||
4879 inst
->op
== TGSI_OPCODE_RET
) {
4883 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4884 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4885 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4886 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4887 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4888 if (inst
->dst
[0].index
>= tempWritesSize
) {
4889 const int inc
= 4096;
4891 tempWrites
= (unsigned*)
4893 (tempWritesSize
+ inc
) * sizeof(unsigned));
4897 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4898 tempWritesSize
+= inc
;
4901 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4902 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4906 /* For a CMP to be considered a conditional write, the destination
4907 * register and source register two must be the same. */
4908 if (inst
->op
== TGSI_OPCODE_CMP
4909 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4910 && inst
->src
[2].file
== inst
->dst
[0].file
4911 && inst
->src
[2].index
== inst
->dst
[0].index
4912 && inst
->dst
[0].writemask
==
4913 get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4915 inst
->op
= TGSI_OPCODE_MOV
;
4916 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4917 inst
->src
[0] = inst
->src
[1];
4925 rename_temp_handle_src(struct rename_reg_pair
*renames
, st_src_reg
*src
)
4927 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4928 int old_idx
= src
->index
;
4929 if (renames
[old_idx
].valid
)
4930 src
->index
= renames
[old_idx
].new_reg
;
4934 /* Replaces all references to a temporary register index with another index. */
4936 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4938 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4940 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4941 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4942 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4943 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4946 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4947 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4948 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4949 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4952 rename_temp_handle_src(renames
, &inst
->resource
);
4953 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4954 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4956 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4957 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4958 int old_idx
= inst
->dst
[j
].index
;
4959 if (renames
[old_idx
].valid
)
4960 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4962 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4963 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4969 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4971 int depth
= 0; /* loop depth */
4972 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4975 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4976 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4977 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4978 if (first_writes
[inst
->dst
[j
].index
] == -1)
4979 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4983 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4986 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4996 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4998 int depth
= 0; /* loop depth */
4999 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
5002 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5003 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
5004 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
5005 if (first_reads
[inst
->src
[j
].index
] == -1)
5006 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5009 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
5010 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
5011 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
5012 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5015 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
5018 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
5028 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
5030 int depth
= 0; /* loop depth */
5031 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
5034 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5035 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
5036 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
5037 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
5039 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5040 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
5041 if (first_writes
[inst
->dst
[j
].index
] == -1)
5042 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
5043 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5046 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
5047 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
5048 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
5050 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
5053 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
5056 for (k
= 0; k
< this->next_temp
; k
++) {
5057 if (last_reads
[k
] == -2) {
5069 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
5071 int depth
= 0; /* loop depth */
5075 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5076 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5077 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
5078 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
5081 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
5083 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
5085 for (k
= 0; k
< this->next_temp
; k
++) {
5086 if (last_writes
[k
] == -2) {
5097 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5098 * channels for copy propagation and updates following instructions to
5099 * use the original versions.
5101 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5102 * will occur. As an example, a TXP production before this pass:
5104 * 0: MOV TEMP[1], INPUT[4].xyyy;
5105 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5106 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5110 * 0: MOV TEMP[1], INPUT[4].xyyy;
5111 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5112 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5114 * which allows for dead code elimination on TEMP[1]'s writes.
5117 glsl_to_tgsi_visitor::copy_propagate(void)
5119 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5120 glsl_to_tgsi_instruction
*,
5121 this->next_temp
* 4);
5122 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5125 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5126 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5127 || inst
->dst
[0].index
< this->next_temp
);
5129 /* First, do any copy propagation possible into the src regs. */
5130 for (int r
= 0; r
< 3; r
++) {
5131 glsl_to_tgsi_instruction
*first
= NULL
;
5133 int acp_base
= inst
->src
[r
].index
* 4;
5135 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5136 inst
->src
[r
].reladdr
||
5137 inst
->src
[r
].reladdr2
)
5140 /* See if we can find entries in the ACP consisting of MOVs
5141 * from the same src register for all the swizzled channels
5142 * of this src register reference.
5144 for (int i
= 0; i
< 4; i
++) {
5145 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5146 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5153 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5158 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5159 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5160 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5161 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5169 /* We've now validated that we can copy-propagate to
5170 * replace this src register reference. Do it.
5172 inst
->src
[r
].file
= first
->src
[0].file
;
5173 inst
->src
[r
].index
= first
->src
[0].index
;
5174 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5175 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5176 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5177 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5180 for (int i
= 0; i
< 4; i
++) {
5181 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5182 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5183 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5185 inst
->src
[r
].swizzle
= swizzle
;
5190 case TGSI_OPCODE_BGNLOOP
:
5191 case TGSI_OPCODE_ENDLOOP
:
5192 /* End of a basic block, clear the ACP entirely. */
5193 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5196 case TGSI_OPCODE_IF
:
5197 case TGSI_OPCODE_UIF
:
5201 case TGSI_OPCODE_ENDIF
:
5202 case TGSI_OPCODE_ELSE
:
5203 /* Clear all channels written inside the block from the ACP, but
5204 * leaving those that were not touched.
5206 for (int r
= 0; r
< this->next_temp
; r
++) {
5207 for (int c
= 0; c
< 4; c
++) {
5208 if (!acp
[4 * r
+ c
])
5211 if (acp_level
[4 * r
+ c
] >= level
)
5212 acp
[4 * r
+ c
] = NULL
;
5215 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5220 /* Continuing the block, clear any written channels from
5223 for (int d
= 0; d
< 2; d
++) {
5224 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5225 /* Any temporary might be written, so no copy propagation
5226 * across this instruction.
5228 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5229 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5230 inst
->dst
[d
].reladdr
) {
5231 /* Any output might be written, so no copy propagation
5232 * from outputs across this instruction.
5234 for (int r
= 0; r
< this->next_temp
; r
++) {
5235 for (int c
= 0; c
< 4; c
++) {
5236 if (!acp
[4 * r
+ c
])
5239 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5240 acp
[4 * r
+ c
] = NULL
;
5243 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5244 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5245 /* Clear where it's used as dst. */
5246 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5247 for (int c
= 0; c
< 4; c
++) {
5248 if (inst
->dst
[d
].writemask
& (1 << c
))
5249 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5253 /* Clear where it's used as src. */
5254 for (int r
= 0; r
< this->next_temp
; r
++) {
5255 for (int c
= 0; c
< 4; c
++) {
5256 if (!acp
[4 * r
+ c
])
5259 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5261 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5262 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5263 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5264 acp
[4 * r
+ c
] = NULL
;
5273 /* If this is a copy, add it to the ACP. */
5274 if (inst
->op
== TGSI_OPCODE_MOV
&&
5275 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5276 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5277 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5278 !inst
->dst
[0].reladdr
&&
5279 !inst
->dst
[0].reladdr2
&&
5281 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5282 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
5283 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
5284 !inst
->src
[0].reladdr
&&
5285 !inst
->src
[0].reladdr2
&&
5286 !inst
->src
[0].negate
&&
5287 !inst
->src
[0].abs
) {
5288 for (int i
= 0; i
< 4; i
++) {
5289 if (inst
->dst
[0].writemask
& (1 << i
)) {
5290 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5291 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5297 ralloc_free(acp_level
);
5302 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
5304 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
5305 /* Clear where it's used as src. */
5306 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
5307 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5312 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5315 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5316 * will occur. As an example, a TXP production after copy propagation but
5319 * 0: MOV TEMP[1], INPUT[4].xyyy;
5320 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5321 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5323 * and after this pass:
5325 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5328 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5330 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5331 glsl_to_tgsi_instruction
*,
5332 this->next_temp
* 4);
5333 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5337 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5338 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5339 || inst
->dst
[0].index
< this->next_temp
);
5342 case TGSI_OPCODE_BGNLOOP
:
5343 case TGSI_OPCODE_ENDLOOP
:
5344 case TGSI_OPCODE_CONT
:
5345 case TGSI_OPCODE_BRK
:
5346 /* End of a basic block, clear the write array entirely.
5348 * This keeps us from killing dead code when the writes are
5349 * on either side of a loop, even when the register isn't touched
5350 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5351 * dead code of this type, so it shouldn't make a difference as long as
5352 * the dead code elimination pass in the GLSL compiler does its job.
5354 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5357 case TGSI_OPCODE_ENDIF
:
5358 case TGSI_OPCODE_ELSE
:
5359 /* Promote the recorded level of all channels written inside the
5360 * preceding if or else block to the level above the if/else block.
5362 for (int r
= 0; r
< this->next_temp
; r
++) {
5363 for (int c
= 0; c
< 4; c
++) {
5364 if (!writes
[4 * r
+ c
])
5367 if (write_level
[4 * r
+ c
] == level
)
5368 write_level
[4 * r
+ c
] = level
-1;
5371 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5375 case TGSI_OPCODE_IF
:
5376 case TGSI_OPCODE_UIF
:
5378 /* fallthrough to default case to mark the condition as read */
5380 /* Continuing the block, clear any channels from the write array that
5381 * are read by this instruction.
5383 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5384 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5385 /* Any temporary might be read, so no dead code elimination
5386 * across this instruction.
5388 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5389 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5390 /* Clear where it's used as src. */
5391 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5392 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5393 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5394 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5396 for (int c
= 0; c
< 4; c
++) {
5397 if (src_chans
& (1 << c
))
5398 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5401 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5402 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5404 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5405 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5406 /* Any temporary might be read, so no dead code elimination
5407 * across this instruction.
5409 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5410 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5411 /* Clear where it's used as src. */
5412 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5413 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5414 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5415 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5417 for (int c
= 0; c
< 4; c
++) {
5418 if (src_chans
& (1 << c
))
5419 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5422 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5423 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5426 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5429 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5430 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5431 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5432 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5434 for (int c
= 0; c
< 4; c
++) {
5435 if (src_chans
& (1 << c
))
5436 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5439 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5440 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5442 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5443 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5444 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5449 /* If this instruction writes to a temporary, add it to the write array.
5450 * If there is already an instruction in the write array for one or more
5451 * of the channels, flag that channel write as dead.
5453 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5454 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5455 !inst
->dst
[i
].reladdr
) {
5456 for (int c
= 0; c
< 4; c
++) {
5457 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5458 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5459 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5462 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5464 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5465 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5472 /* Anything still in the write array at this point is dead code. */
5473 for (int r
= 0; r
< this->next_temp
; r
++) {
5474 for (int c
= 0; c
< 4; c
++) {
5475 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5477 inst
->dead_mask
|= (1 << c
);
5481 /* Now actually remove the instructions that are completely dead and update
5482 * the writemask of other instructions with dead channels.
5484 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5485 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5487 /* No amount of dead masks should remove memory stores */
5488 if (inst
->info
->is_store
)
5491 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5496 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5497 if (inst
->dead_mask
== WRITEMASK_XY
||
5498 inst
->dead_mask
== WRITEMASK_ZW
)
5499 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5501 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5505 ralloc_free(write_level
);
5506 ralloc_free(writes
);
5511 /* merge DFRACEXP instructions into one. */
5513 glsl_to_tgsi_visitor::merge_two_dsts(void)
5515 /* We never delete inst, but we may delete its successor. */
5516 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5517 glsl_to_tgsi_instruction
*inst2
;
5520 if (num_inst_dst_regs(inst
) != 2)
5523 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5524 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5527 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5528 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5530 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5535 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5536 while (!inst2
->is_tail_sentinel()) {
5537 if (inst
->op
== inst2
->op
&&
5538 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5539 inst
->src
[0].file
== inst2
->src
[0].file
&&
5540 inst
->src
[0].index
== inst2
->src
[0].index
&&
5541 inst
->src
[0].type
== inst2
->src
[0].type
&&
5542 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5544 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5547 if (inst2
->is_tail_sentinel()) {
5548 /* Undefined destinations are not allowed, substitute with an unused
5549 * temporary register.
5551 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5552 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5553 inst
->dst
[defined
^ 1].writemask
= 0;
5557 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5563 template <typename st_reg
>
5564 void test_indirect_access(const st_reg
& reg
, bool *has_indirect_access
)
5566 if (reg
.file
== PROGRAM_ARRAY
) {
5567 if (reg
.reladdr
|| reg
.reladdr2
|| reg
.has_index2
) {
5568 has_indirect_access
[reg
.array_id
] = true;
5570 test_indirect_access(*reg
.reladdr
, has_indirect_access
);
5572 test_indirect_access(*reg
.reladdr2
, has_indirect_access
);
5577 template <typename st_reg
>
5578 void remap_array(st_reg
& reg
, const int *array_remap_info
,
5579 const bool *has_indirect_access
)
5581 if (reg
.file
== PROGRAM_ARRAY
) {
5582 if (!has_indirect_access
[reg
.array_id
]) {
5583 reg
.file
= PROGRAM_TEMPORARY
;
5584 reg
.index
= reg
.index
+ array_remap_info
[reg
.array_id
];
5587 reg
.array_id
= array_remap_info
[reg
.array_id
];
5591 remap_array(*reg
.reladdr
, array_remap_info
, has_indirect_access
);
5594 remap_array(*reg
.reladdr2
, array_remap_info
, has_indirect_access
);
5598 /* One-dimensional arrays whose elements are only accessed directly are
5599 * replaced by an according set of temporary registers that then can become
5600 * subject to further optimization steps like copy propagation and
5604 glsl_to_tgsi_visitor::split_arrays(void)
5609 bool *has_indirect_access
= rzalloc_array(mem_ctx
, bool, next_array
+ 1);
5611 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5612 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5613 test_indirect_access(inst
->src
[j
], has_indirect_access
);
5615 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5616 test_indirect_access(inst
->tex_offsets
[j
], has_indirect_access
);
5618 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++)
5619 test_indirect_access(inst
->dst
[j
], has_indirect_access
);
5621 test_indirect_access(inst
->resource
, has_indirect_access
);
5624 unsigned array_offset
= 0;
5625 unsigned n_remaining_arrays
= 0;
5627 /* Double use: For arrays that get split this value will contain
5628 * the base index of the temporary registers this array is replaced
5629 * with. For arrays that remain it contains the new array ID.
5631 int *array_remap_info
= rzalloc_array(has_indirect_access
, int,
5634 for (unsigned i
= 1; i
<= next_array
; ++i
) {
5635 if (!has_indirect_access
[i
]) {
5636 array_remap_info
[i
] = this->next_temp
+ array_offset
;
5637 array_offset
+= array_sizes
[i
- 1];
5639 array_sizes
[n_remaining_arrays
] = array_sizes
[i
-1];
5640 array_remap_info
[i
] = ++n_remaining_arrays
;
5644 if (next_array
!= n_remaining_arrays
) {
5645 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5646 for (unsigned j
= 0; j
< num_inst_src_regs(inst
); j
++)
5647 remap_array(inst
->src
[j
], array_remap_info
, has_indirect_access
);
5649 for (unsigned j
= 0; j
< inst
->tex_offset_num_offset
; j
++)
5650 remap_array(inst
->tex_offsets
[j
], array_remap_info
, has_indirect_access
);
5652 for (unsigned j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
5653 remap_array(inst
->dst
[j
], array_remap_info
, has_indirect_access
);
5655 remap_array(inst
->resource
, array_remap_info
, has_indirect_access
);
5659 ralloc_free(has_indirect_access
);
5660 this->next_temp
+= array_offset
;
5661 next_array
= n_remaining_arrays
;
5664 /* Merges temporary registers together where possible to reduce the number of
5665 * registers needed to run a program.
5667 * Produces optimal code only after copy propagation and dead code elimination
5670 glsl_to_tgsi_visitor::merge_registers(void)
5672 class array_live_range
*arr_live_ranges
= NULL
;
5674 struct register_live_range
*reg_live_ranges
=
5675 rzalloc_array(mem_ctx
, struct register_live_range
, this->next_temp
);
5677 if (this->next_array
> 0) {
5678 arr_live_ranges
= new array_live_range
[this->next_array
];
5679 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5680 arr_live_ranges
[i
] = array_live_range(i
+1, this->array_sizes
[i
]);
5684 if (get_temp_registers_required_live_ranges(reg_live_ranges
, &this->instructions
,
5685 this->next_temp
, reg_live_ranges
,
5686 this->next_array
, arr_live_ranges
)) {
5687 struct rename_reg_pair
*renames
=
5688 rzalloc_array(reg_live_ranges
, struct rename_reg_pair
, this->next_temp
);
5689 get_temp_registers_remapping(reg_live_ranges
, this->next_temp
,
5690 reg_live_ranges
, renames
);
5691 rename_temp_registers(renames
);
5693 this->next_array
= merge_arrays(this->next_array
, this->array_sizes
,
5694 &this->instructions
, arr_live_ranges
);
5697 if (arr_live_ranges
)
5698 delete[] arr_live_ranges
;
5700 ralloc_free(reg_live_ranges
);
5703 /* Reassign indices to temporary registers by reusing unused indices created
5704 * by optimization passes. */
5706 glsl_to_tgsi_visitor::renumber_registers(void)
5710 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5711 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5713 for (i
= 0; i
< this->next_temp
; i
++) {
5714 first_writes
[i
] = -1;
5716 get_first_temp_write(first_writes
);
5718 for (i
= 0; i
< this->next_temp
; i
++) {
5719 if (first_writes
[i
] < 0) continue;
5720 if (i
!= new_index
) {
5721 renames
[i
].new_reg
= new_index
;
5722 renames
[i
].valid
= true;
5727 rename_temp_registers(renames
);
5728 this->next_temp
= new_index
;
5729 ralloc_free(renames
);
5730 ralloc_free(first_writes
);
5734 void glsl_to_tgsi_visitor::print_stats()
5736 int narray_registers
= 0;
5737 for (unsigned i
= 0; i
< this->next_array
; ++i
)
5738 narray_registers
+= this->array_sizes
[i
];
5740 int ninstructions
= 0;
5741 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &instructions
) {
5745 simple_mtx_lock(&print_stats_mutex
);
5746 stats_log
<< next_array
<< ", "
5747 << next_temp
<< ", "
5748 << narray_registers
<< ", "
5749 << next_temp
+ narray_registers
<< ", "
5750 << ninstructions
<< "\n";
5751 simple_mtx_unlock(&print_stats_mutex
);
5754 /* ------------------------- TGSI conversion stuff -------------------------- */
5757 * Intermediate state used during shader translation.
5759 struct st_translate
{
5760 struct ureg_program
*ureg
;
5762 unsigned temps_size
;
5763 struct ureg_dst
*temps
;
5765 struct ureg_dst
*arrays
;
5766 unsigned num_temp_arrays
;
5767 struct ureg_src
*constants
;
5769 struct ureg_src
*immediates
;
5771 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5772 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5773 struct ureg_dst address
[3];
5774 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5775 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5776 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5777 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5778 struct ureg_src hw_atomics
[PIPE_MAX_HW_ATOMIC_BUFFERS
];
5779 struct ureg_src shared_memory
;
5780 unsigned *array_sizes
;
5781 struct inout_decl
*input_decls
;
5782 unsigned num_input_decls
;
5783 struct inout_decl
*output_decls
;
5784 unsigned num_output_decls
;
5786 const ubyte
*inputMapping
;
5787 const ubyte
*outputMapping
;
5789 enum pipe_shader_type procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5791 bool tg4_component_in_swizzle
;
5794 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5796 _mesa_sysval_to_semantic(unsigned sysval
)
5800 case SYSTEM_VALUE_VERTEX_ID
:
5801 return TGSI_SEMANTIC_VERTEXID
;
5802 case SYSTEM_VALUE_INSTANCE_ID
:
5803 return TGSI_SEMANTIC_INSTANCEID
;
5804 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5805 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5806 case SYSTEM_VALUE_BASE_VERTEX
:
5807 return TGSI_SEMANTIC_BASEVERTEX
;
5808 case SYSTEM_VALUE_BASE_INSTANCE
:
5809 return TGSI_SEMANTIC_BASEINSTANCE
;
5810 case SYSTEM_VALUE_DRAW_ID
:
5811 return TGSI_SEMANTIC_DRAWID
;
5813 /* Geometry shader */
5814 case SYSTEM_VALUE_INVOCATION_ID
:
5815 return TGSI_SEMANTIC_INVOCATIONID
;
5817 /* Fragment shader */
5818 case SYSTEM_VALUE_FRAG_COORD
:
5819 return TGSI_SEMANTIC_POSITION
;
5820 case SYSTEM_VALUE_POINT_COORD
:
5821 return TGSI_SEMANTIC_PCOORD
;
5822 case SYSTEM_VALUE_FRONT_FACE
:
5823 return TGSI_SEMANTIC_FACE
;
5824 case SYSTEM_VALUE_SAMPLE_ID
:
5825 return TGSI_SEMANTIC_SAMPLEID
;
5826 case SYSTEM_VALUE_SAMPLE_POS
:
5827 return TGSI_SEMANTIC_SAMPLEPOS
;
5828 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5829 return TGSI_SEMANTIC_SAMPLEMASK
;
5830 case SYSTEM_VALUE_HELPER_INVOCATION
:
5831 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5833 /* Tessellation shader */
5834 case SYSTEM_VALUE_TESS_COORD
:
5835 return TGSI_SEMANTIC_TESSCOORD
;
5836 case SYSTEM_VALUE_VERTICES_IN
:
5837 return TGSI_SEMANTIC_VERTICESIN
;
5838 case SYSTEM_VALUE_PRIMITIVE_ID
:
5839 return TGSI_SEMANTIC_PRIMID
;
5840 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5841 return TGSI_SEMANTIC_TESSOUTER
;
5842 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5843 return TGSI_SEMANTIC_TESSINNER
;
5845 /* Compute shader */
5846 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5847 return TGSI_SEMANTIC_THREAD_ID
;
5848 case SYSTEM_VALUE_WORK_GROUP_ID
:
5849 return TGSI_SEMANTIC_BLOCK_ID
;
5850 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5851 return TGSI_SEMANTIC_GRID_SIZE
;
5852 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5853 return TGSI_SEMANTIC_BLOCK_SIZE
;
5855 /* ARB_shader_ballot */
5856 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5857 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5858 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5859 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5860 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5861 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5862 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5863 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5864 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5865 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5866 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5867 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5868 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5869 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5872 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5873 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5874 case SYSTEM_VALUE_VERTEX_CNT
:
5875 case SYSTEM_VALUE_BARYCENTRIC_PIXEL
:
5876 case SYSTEM_VALUE_BARYCENTRIC_SAMPLE
:
5877 case SYSTEM_VALUE_BARYCENTRIC_CENTROID
:
5878 case SYSTEM_VALUE_BARYCENTRIC_SIZE
:
5880 assert(!"Unexpected SYSTEM_VALUE_ enum");
5881 return TGSI_SEMANTIC_COUNT
;
5886 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5888 static struct ureg_src
5889 emit_immediate(struct st_translate
*t
,
5890 gl_constant_value values
[4],
5891 GLenum type
, int size
)
5893 struct ureg_program
*ureg
= t
->ureg
;
5897 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5899 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5901 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5902 case GL_UNSIGNED_INT64_ARB
:
5903 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5905 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5906 case GL_UNSIGNED_INT
:
5908 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5910 assert(!"should not get here - type must be float, int, uint, or bool");
5911 return ureg_src_undef();
5916 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5918 static struct ureg_dst
5919 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5925 case PROGRAM_UNDEFINED
:
5926 return ureg_dst_undef();
5928 case PROGRAM_TEMPORARY
:
5929 /* Allocate space for temporaries on demand. */
5930 if (index
>= t
->temps_size
) {
5931 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5933 t
->temps
= (struct ureg_dst
*)
5935 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5937 return ureg_dst_undef();
5939 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5940 t
->temps_size
+= inc
;
5943 if (ureg_dst_is_undef(t
->temps
[index
]))
5944 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5946 return t
->temps
[index
];
5949 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5950 array
= array_id
- 1;
5952 if (ureg_dst_is_undef(t
->arrays
[array
]))
5953 t
->arrays
[array
] = ureg_DECL_array_temporary(
5954 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5956 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5958 case PROGRAM_OUTPUT
:
5960 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5961 assert(index
< 2 * FRAG_RESULT_MAX
);
5962 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5963 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5964 assert(index
< VARYING_SLOT_TESS_MAX
);
5966 assert(index
< VARYING_SLOT_MAX
);
5968 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5969 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5970 return t
->outputs
[t
->outputMapping
[index
]];
5973 struct inout_decl
*decl
=
5974 find_inout_array(t
->output_decls
,
5975 t
->num_output_decls
, array_id
);
5976 unsigned mesa_index
= decl
->mesa_index
;
5977 int slot
= t
->outputMapping
[mesa_index
];
5979 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5981 struct ureg_dst dst
= t
->outputs
[slot
];
5982 dst
.ArrayID
= array_id
;
5983 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5986 case PROGRAM_ADDRESS
:
5987 return t
->address
[index
];
5990 assert(!"unknown dst register file");
5991 return ureg_dst_undef();
5995 static struct ureg_src
5996 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5998 static struct ureg_src
5999 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
6000 unsigned addr_index
)
6002 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
6003 return ureg_src(t
->address
[addr_index
]);
6005 return translate_src(t
, reladdr
);
6009 * Create a TGSI ureg_dst register from an st_dst_reg.
6011 static struct ureg_dst
6012 translate_dst(struct st_translate
*t
,
6013 const st_dst_reg
*dst_reg
,
6016 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
6019 if (dst
.File
== TGSI_FILE_NULL
)
6022 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
6025 dst
= ureg_saturate(dst
);
6027 if (dst_reg
->reladdr
!= NULL
) {
6028 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
6029 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
6032 if (dst_reg
->has_index2
) {
6033 if (dst_reg
->reladdr2
)
6034 dst
= ureg_dst_dimension_indirect(dst
,
6035 translate_addr(t
, dst_reg
->reladdr2
, 1),
6038 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
6045 * Create a TGSI ureg_src register from an st_src_reg.
6047 static struct ureg_src
6048 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
6050 struct ureg_src src
;
6051 int index
= src_reg
->index
;
6052 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
6054 switch (src_reg
->file
) {
6055 case PROGRAM_UNDEFINED
:
6056 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6059 case PROGRAM_TEMPORARY
:
6061 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
,
6062 src_reg
->array_id
));
6065 case PROGRAM_OUTPUT
: {
6066 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
,
6068 assert(dst
.WriteMask
!= 0);
6069 unsigned shift
= ffs(dst
.WriteMask
) - 1;
6070 src
= ureg_swizzle(ureg_src(dst
),
6074 MIN2(shift
+ 3, 3));
6078 case PROGRAM_UNIFORM
:
6079 assert(src_reg
->index
>= 0);
6080 src
= src_reg
->index
< t
->num_constants
?
6081 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6083 case PROGRAM_STATE_VAR
:
6084 case PROGRAM_CONSTANT
: /* ie, immediate */
6085 if (src_reg
->has_index2
)
6086 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
6088 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
6089 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
6092 case PROGRAM_IMMEDIATE
:
6093 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
6094 src
= t
->immediates
[src_reg
->index
];
6098 /* GLSL inputs are 64-bit containers, so we have to
6099 * map back to the original index and add the offset after
6101 index
-= double_reg2
;
6102 if (!src_reg
->array_id
) {
6103 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
6104 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
6105 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
6108 struct inout_decl
*decl
= find_inout_array(t
->input_decls
,
6111 unsigned mesa_index
= decl
->mesa_index
;
6112 int slot
= t
->inputMapping
[mesa_index
];
6114 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
6116 src
= t
->inputs
[slot
];
6117 src
.ArrayID
= src_reg
->array_id
;
6118 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
6122 case PROGRAM_ADDRESS
:
6123 src
= ureg_src(t
->address
[src_reg
->index
]);
6126 case PROGRAM_SYSTEM_VALUE
:
6127 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
6128 src
= t
->systemValues
[src_reg
->index
];
6131 case PROGRAM_HW_ATOMIC
:
6132 src
= ureg_src_array_register(TGSI_FILE_HW_ATOMIC
, src_reg
->index
,
6137 assert(!"unknown src register file");
6138 return ureg_src_undef();
6141 if (src_reg
->has_index2
) {
6142 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6143 * and UBO constant buffers (buffer, position).
6145 if (src_reg
->reladdr2
)
6146 src
= ureg_src_dimension_indirect(src
,
6147 translate_addr(t
, src_reg
->reladdr2
, 1),
6150 src
= ureg_src_dimension(src
, src_reg
->index2D
);
6153 src
= ureg_swizzle(src
,
6154 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
6155 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
6156 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
6157 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
6160 src
= ureg_abs(src
);
6162 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
6163 src
= ureg_negate(src
);
6165 if (src_reg
->reladdr
!= NULL
) {
6166 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
6167 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
6173 static struct tgsi_texture_offset
6174 translate_tex_offset(struct st_translate
*t
,
6175 const st_src_reg
*in_offset
)
6177 struct tgsi_texture_offset offset
;
6178 struct ureg_src src
= translate_src(t
, in_offset
);
6180 offset
.File
= src
.File
;
6181 offset
.Index
= src
.Index
;
6182 offset
.SwizzleX
= src
.SwizzleX
;
6183 offset
.SwizzleY
= src
.SwizzleY
;
6184 offset
.SwizzleZ
= src
.SwizzleZ
;
6187 assert(!src
.Indirect
);
6188 assert(!src
.DimIndirect
);
6189 assert(!src
.Dimension
);
6190 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
6191 assert(!src
.Negate
);
6197 compile_tgsi_instruction(struct st_translate
*t
,
6198 const glsl_to_tgsi_instruction
*inst
)
6200 struct ureg_program
*ureg
= t
->ureg
;
6202 struct ureg_dst dst
[2];
6203 struct ureg_src src
[4];
6204 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
6208 enum tgsi_texture_type tex_target
= TGSI_TEXTURE_BUFFER
;
6210 num_dst
= num_inst_dst_regs(inst
);
6211 num_src
= num_inst_src_regs(inst
);
6213 for (i
= 0; i
< num_dst
; i
++)
6214 dst
[i
] = translate_dst(t
,
6218 for (i
= 0; i
< num_src
; i
++)
6219 src
[i
] = translate_src(t
, &inst
->src
[i
]);
6222 case TGSI_OPCODE_BGNLOOP
:
6223 case TGSI_OPCODE_ELSE
:
6224 case TGSI_OPCODE_ENDLOOP
:
6225 case TGSI_OPCODE_IF
:
6226 case TGSI_OPCODE_UIF
:
6227 assert(num_dst
== 0);
6228 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
6231 case TGSI_OPCODE_TEX
:
6232 case TGSI_OPCODE_TEX_LZ
:
6233 case TGSI_OPCODE_TXB
:
6234 case TGSI_OPCODE_TXD
:
6235 case TGSI_OPCODE_TXL
:
6236 case TGSI_OPCODE_TXP
:
6237 case TGSI_OPCODE_TXQ
:
6238 case TGSI_OPCODE_TXQS
:
6239 case TGSI_OPCODE_TXF
:
6240 case TGSI_OPCODE_TXF_LZ
:
6241 case TGSI_OPCODE_TEX2
:
6242 case TGSI_OPCODE_TXB2
:
6243 case TGSI_OPCODE_TXL2
:
6244 case TGSI_OPCODE_TG4
:
6245 case TGSI_OPCODE_LODQ
:
6246 case TGSI_OPCODE_SAMP2HND
:
6247 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
6248 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
6249 if (t
->tg4_component_in_swizzle
&& inst
->op
== TGSI_OPCODE_TG4
)
6250 src
[num_src
].SwizzleX
= inst
->gather_component
;
6252 /* Bindless samplers. */
6253 src
[num_src
] = translate_src(t
, &inst
->resource
);
6255 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
6256 if (inst
->resource
.reladdr
)
6258 ureg_src_indirect(src
[num_src
],
6259 translate_addr(t
, inst
->resource
.reladdr
, 2));
6261 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
6262 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
6264 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6270 st_translate_texture_type(inst
->tex_type
),
6271 texoffsets
, inst
->tex_offset_num_offset
,
6275 case TGSI_OPCODE_RESQ
:
6276 case TGSI_OPCODE_LOAD
:
6277 case TGSI_OPCODE_ATOMUADD
:
6278 case TGSI_OPCODE_ATOMXCHG
:
6279 case TGSI_OPCODE_ATOMCAS
:
6280 case TGSI_OPCODE_ATOMAND
:
6281 case TGSI_OPCODE_ATOMOR
:
6282 case TGSI_OPCODE_ATOMXOR
:
6283 case TGSI_OPCODE_ATOMUMIN
:
6284 case TGSI_OPCODE_ATOMUMAX
:
6285 case TGSI_OPCODE_ATOMIMIN
:
6286 case TGSI_OPCODE_ATOMIMAX
:
6287 case TGSI_OPCODE_ATOMFADD
:
6288 case TGSI_OPCODE_IMG2HND
:
6289 case TGSI_OPCODE_ATOMINC_WRAP
:
6290 case TGSI_OPCODE_ATOMDEC_WRAP
:
6291 for (i
= num_src
- 1; i
>= 0; i
--)
6292 src
[i
+ 1] = src
[i
];
6294 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6295 src
[0] = t
->shared_memory
;
6296 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6297 src
[0] = t
->buffers
[inst
->resource
.index
];
6298 } else if (inst
->resource
.file
== PROGRAM_HW_ATOMIC
) {
6299 src
[0] = translate_src(t
, &inst
->resource
);
6300 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
6301 assert(inst
->resource
.has_index2
);
6302 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
6304 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
6305 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6306 src
[0] = t
->images
[inst
->resource
.index
];
6308 /* Bindless images. */
6309 src
[0] = translate_src(t
, &inst
->resource
);
6311 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6313 if (inst
->resource
.reladdr
)
6314 src
[0] = ureg_src_indirect(src
[0],
6315 translate_addr(t
, inst
->resource
.reladdr
, 2));
6316 assert(src
[0].File
!= TGSI_FILE_NULL
);
6317 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6318 inst
->buffer_access
,
6319 tex_target
, inst
->image_format
);
6322 case TGSI_OPCODE_STORE
:
6323 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6324 dst
[0] = ureg_dst(t
->shared_memory
);
6325 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6326 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6328 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6329 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6331 /* Bindless images. */
6332 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6334 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6336 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6337 if (inst
->resource
.reladdr
)
6338 dst
[0] = ureg_dst_indirect(dst
[0],
6339 translate_addr(t
, inst
->resource
.reladdr
, 2));
6340 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6341 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6342 inst
->buffer_access
,
6343 tex_target
, inst
->image_format
);
6350 src
, num_src
, inst
->precise
);
6355 /* Invert SamplePos.y when rendering to the default framebuffer. */
6357 emit_samplepos_adjustment(struct st_translate
*t
, int wpos_y_transform
)
6359 struct ureg_program
*ureg
= t
->ureg
;
6361 assert(wpos_y_transform
>= 0);
6362 struct ureg_src trans_const
= ureg_DECL_constant(ureg
, wpos_y_transform
);
6363 struct ureg_src samplepos_sysval
= t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
];
6364 struct ureg_dst samplepos_flipped
= ureg_DECL_temporary(ureg
);
6365 struct ureg_dst is_fbo
= ureg_DECL_temporary(ureg
);
6367 ureg_ADD(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6368 ureg_imm1f(ureg
, 1), ureg_negate(samplepos_sysval
));
6370 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6371 ureg_FSEQ(ureg
, ureg_writemask(is_fbo
, TGSI_WRITEMASK_Y
),
6372 ureg_scalar(trans_const
, TGSI_SWIZZLE_X
), ureg_imm1f(ureg
, 1));
6373 ureg_UCMP(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_Y
),
6374 ureg_src(is_fbo
), samplepos_sysval
, ureg_src(samplepos_flipped
));
6375 ureg_MOV(ureg
, ureg_writemask(samplepos_flipped
, TGSI_WRITEMASK_X
),
6378 /* Use the result in place of the system value. */
6379 t
->systemValues
[SYSTEM_VALUE_SAMPLE_POS
] = ureg_src(samplepos_flipped
);
6384 * Emit the TGSI instructions for inverting and adjusting WPOS.
6385 * This code is unavoidable because it also depends on whether
6386 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6389 emit_wpos_adjustment(struct gl_context
*ctx
,
6390 struct st_translate
*t
,
6391 int wpos_transform_const
,
6393 GLfloat adjX
, GLfloat adjY
[2])
6395 struct ureg_program
*ureg
= t
->ureg
;
6397 assert(wpos_transform_const
>= 0);
6399 /* Fragment program uses fragment position input.
6400 * Need to replace instances of INPUT[WPOS] with temp T
6401 * where T = INPUT[WPOS] is inverted by Y.
6403 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6404 struct ureg_dst wpos_temp
= ureg_DECL_temporary(ureg
);
6405 struct ureg_src
*wpos
=
6406 ctx
->Const
.GLSLFragCoordIsSysVal
?
6407 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6408 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6409 struct ureg_src wpos_input
= *wpos
;
6411 /* First, apply the coordinate shift: */
6412 if (adjX
|| adjY
[0] || adjY
[1]) {
6413 if (adjY
[0] != adjY
[1]) {
6414 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6415 * depending on whether inversion is actually going to be applied
6416 * or not, which is determined by testing against the inversion
6417 * state variable used below, which will be either +1 or -1.
6419 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6421 ureg_CMP(ureg
, adj_temp
,
6422 ureg_scalar(wpostrans
, invert
? 2 : 0),
6423 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6424 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6425 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6427 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6428 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6430 wpos_input
= ureg_src(wpos_temp
);
6432 /* MOV wpos_temp, input[wpos]
6434 ureg_MOV(ureg
, wpos_temp
, wpos_input
);
6437 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6438 * inversion/identity, or the other way around if we're drawing to an FBO.
6441 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6444 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6446 ureg_scalar(wpostrans
, 0),
6447 ureg_scalar(wpostrans
, 1));
6449 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6452 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6454 ureg_scalar(wpostrans
, 2),
6455 ureg_scalar(wpostrans
, 3));
6458 /* Use wpos_temp as position input from here on:
6460 *wpos
= ureg_src(wpos_temp
);
6465 * Emit fragment position/ooordinate code.
6468 emit_wpos(struct st_context
*st
,
6469 struct st_translate
*t
,
6470 const struct gl_program
*program
,
6471 struct ureg_program
*ureg
,
6472 int wpos_transform_const
)
6474 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6475 GLfloat adjX
= 0.0f
;
6476 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6477 boolean invert
= FALSE
;
6479 /* Query the pixel center conventions supported by the pipe driver and set
6480 * adjX, adjY to help out if it cannot handle the requested one internally.
6482 * The bias of the y-coordinate depends on whether y-inversion takes place
6483 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6484 * drawing to an FBO (causes additional inversion), and whether the pipe
6485 * driver origin and the requested origin differ (the latter condition is
6486 * stored in the 'invert' variable).
6488 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6490 * center shift only:
6495 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6496 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6497 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6498 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6500 * inversion and center shift:
6501 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6502 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6503 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6504 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6506 if (program
->info
.fs
.origin_upper_left
) {
6507 /* Fragment shader wants origin in upper-left */
6508 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6509 /* the driver supports upper-left origin */
6511 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6512 /* the driver supports lower-left origin, need to invert Y */
6513 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6514 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6521 /* Fragment shader wants origin in lower-left */
6522 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6523 /* the driver supports lower-left origin */
6524 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6525 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6526 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6527 /* the driver supports upper-left origin, need to invert Y */
6533 if (program
->info
.fs
.pixel_center_integer
) {
6534 /* Fragment shader wants pixel center integer */
6535 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6536 /* the driver supports pixel center integer */
6538 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6539 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6541 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6542 /* the driver supports pixel center half integer, need to bias X,Y */
6551 /* Fragment shader wants pixel center half integer */
6552 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6553 /* the driver supports pixel center half integer */
6555 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6556 /* the driver supports pixel center integer, need to bias X,Y */
6557 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6558 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6559 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6565 /* we invert after adjustment so that we avoid the MOV to temporary,
6566 * and reuse the adjustment ADD instead */
6567 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6571 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6572 * TGSI uses +1 for front, -1 for back.
6573 * This function converts the TGSI value to the GL value. Simply clamping/
6574 * saturating the value to [0,1] does the job.
6577 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6579 struct ureg_program
*ureg
= t
->ureg
;
6580 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6581 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6583 if (ctx
->Const
.NativeIntegers
) {
6584 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6587 /* MOV_SAT face_temp, input[face] */
6588 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6591 /* Use face_temp as face input from here on: */
6592 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6596 emit_compute_block_size(const struct gl_program
*prog
,
6597 struct ureg_program
*ureg
) {
6598 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6599 prog
->info
.cs
.local_size
[0]);
6600 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6601 prog
->info
.cs
.local_size
[1]);
6602 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6603 prog
->info
.cs
.local_size
[2]);
6606 struct sort_inout_decls
{
6607 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6608 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6611 const ubyte
*mapping
;
6614 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6616 * This is for the benefit of older drivers which are broken when the
6617 * declarations aren't sorted in this way.
6620 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6622 const ubyte mapping
[])
6624 sort_inout_decls sorter
;
6625 sorter
.mapping
= mapping
;
6626 std::sort(decls
, decls
+ count
, sorter
);
6629 static enum tgsi_interpolate_mode
6630 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6632 switch (glsl_qual
) {
6633 case INTERP_MODE_NONE
:
6634 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6635 return TGSI_INTERPOLATE_COLOR
;
6636 return TGSI_INTERPOLATE_PERSPECTIVE
;
6637 case INTERP_MODE_SMOOTH
:
6638 return TGSI_INTERPOLATE_PERSPECTIVE
;
6639 case INTERP_MODE_FLAT
:
6640 return TGSI_INTERPOLATE_CONSTANT
;
6641 case INTERP_MODE_NOPERSPECTIVE
:
6642 return TGSI_INTERPOLATE_LINEAR
;
6644 assert(0 && "unexpected interp mode in st_translate_interp()");
6645 return TGSI_INTERPOLATE_PERSPECTIVE
;
6650 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6651 * \param program the program to translate
6652 * \param numInputs number of input registers used
6653 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6655 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6656 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6658 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6659 * \param numOutputs number of output registers used
6660 * \param outputMapping maps Mesa fragment program outputs to TGSI
6662 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6663 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6666 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6668 extern "C" enum pipe_error
6669 st_translate_program(
6670 struct gl_context
*ctx
,
6671 enum pipe_shader_type procType
,
6672 struct ureg_program
*ureg
,
6673 glsl_to_tgsi_visitor
*program
,
6674 const struct gl_program
*proginfo
,
6676 const ubyte inputMapping
[],
6677 const ubyte inputSlotToAttr
[],
6678 const ubyte inputSemanticName
[],
6679 const ubyte inputSemanticIndex
[],
6680 const ubyte interpMode
[],
6682 const ubyte outputMapping
[],
6683 const ubyte outputSemanticName
[],
6684 const ubyte outputSemanticIndex
[])
6686 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6687 struct st_translate
*t
;
6689 struct gl_program_constants
*frag_const
=
6690 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6691 enum pipe_error ret
= PIPE_OK
;
6693 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6694 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6696 ASSERT_BITFIELD_SIZE(st_src_reg
, type
, GLSL_TYPE_ERROR
);
6697 ASSERT_BITFIELD_SIZE(st_dst_reg
, type
, GLSL_TYPE_ERROR
);
6698 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_type
, GLSL_TYPE_ERROR
);
6699 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
, PIPE_FORMAT_COUNT
);
6700 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, tex_target
,
6701 (gl_texture_index
) (NUM_TEXTURE_TARGETS
- 1));
6702 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, image_format
,
6703 (enum pipe_format
) (PIPE_FORMAT_COUNT
- 1));
6704 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction
, op
,
6705 (enum tgsi_opcode
) (TGSI_OPCODE_LAST
- 1));
6707 t
= CALLOC_STRUCT(st_translate
);
6709 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6713 t
->procType
= procType
;
6714 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6715 t
->tg4_component_in_swizzle
= screen
->get_param(screen
, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
);
6716 t
->inputMapping
= inputMapping
;
6717 t
->outputMapping
= outputMapping
;
6719 t
->num_temp_arrays
= program
->next_array
;
6720 if (t
->num_temp_arrays
)
6721 t
->arrays
= (struct ureg_dst
*)
6722 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6725 * Declare input attributes.
6728 case PIPE_SHADER_FRAGMENT
:
6729 case PIPE_SHADER_GEOMETRY
:
6730 case PIPE_SHADER_TESS_EVAL
:
6731 case PIPE_SHADER_TESS_CTRL
:
6732 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6734 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6735 struct inout_decl
*decl
= &program
->inputs
[i
];
6736 unsigned slot
= inputMapping
[decl
->mesa_index
];
6737 struct ureg_src src
;
6738 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6740 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6741 if (tgsi_usage_mask
== 1)
6742 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6743 else if (tgsi_usage_mask
== 2)
6744 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6746 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6749 enum tgsi_interpolate_mode interp_mode
= TGSI_INTERPOLATE_CONSTANT
;
6750 enum tgsi_interpolate_loc interp_location
= TGSI_INTERPOLATE_LOC_CENTER
;
6751 if (procType
== PIPE_SHADER_FRAGMENT
) {
6753 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6754 (enum tgsi_interpolate_mode
) interpMode
[slot
] :
6755 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6757 interp_location
= (enum tgsi_interpolate_loc
) decl
->interp_loc
;
6760 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6761 (enum tgsi_semantic
) inputSemanticName
[slot
],
6762 inputSemanticIndex
[slot
],
6763 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6764 decl
->array_id
, decl
->size
);
6766 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6767 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6768 /* The ArrayID is set up in dst_register */
6769 t
->inputs
[slot
+ j
] = src
;
6770 t
->inputs
[slot
+ j
].ArrayID
= 0;
6771 t
->inputs
[slot
+ j
].Index
+= j
;
6776 case PIPE_SHADER_VERTEX
:
6777 for (i
= 0; i
< numInputs
; i
++) {
6778 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6781 case PIPE_SHADER_COMPUTE
:
6788 * Declare output attributes.
6791 case PIPE_SHADER_FRAGMENT
:
6792 case PIPE_SHADER_COMPUTE
:
6794 case PIPE_SHADER_GEOMETRY
:
6795 case PIPE_SHADER_TESS_EVAL
:
6796 case PIPE_SHADER_TESS_CTRL
:
6797 case PIPE_SHADER_VERTEX
:
6798 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6800 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6801 struct inout_decl
*decl
= &program
->outputs
[i
];
6802 unsigned slot
= outputMapping
[decl
->mesa_index
];
6803 struct ureg_dst dst
;
6804 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6806 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6807 if (tgsi_usage_mask
== 1)
6808 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6809 else if (tgsi_usage_mask
== 2)
6810 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6812 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6815 dst
= ureg_DECL_output_layout(ureg
,
6816 (enum tgsi_semantic
) outputSemanticName
[slot
],
6817 outputSemanticIndex
[slot
],
6818 decl
->gs_out_streams
,
6819 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
, decl
->invariant
);
6820 dst
.Invariant
= decl
->invariant
;
6821 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6822 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6823 /* The ArrayID is set up in dst_register */
6824 t
->outputs
[slot
+ j
] = dst
;
6825 t
->outputs
[slot
+ j
].ArrayID
= 0;
6826 t
->outputs
[slot
+ j
].Index
+= j
;
6827 t
->outputs
[slot
+ j
].Invariant
= decl
->invariant
;
6836 if (procType
== PIPE_SHADER_FRAGMENT
) {
6837 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6838 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6839 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6841 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6842 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6845 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6846 /* Must do this after setting up t->inputs. */
6847 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6848 program
->wpos_transform_const
);
6851 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6852 emit_face_var(ctx
, t
);
6854 for (i
= 0; i
< numOutputs
; i
++) {
6855 switch (outputSemanticName
[i
]) {
6856 case TGSI_SEMANTIC_POSITION
:
6857 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6858 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6859 outputSemanticIndex
[i
]);
6860 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6862 case TGSI_SEMANTIC_STENCIL
:
6863 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6864 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6865 outputSemanticIndex
[i
]);
6866 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6868 case TGSI_SEMANTIC_COLOR
:
6869 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6870 TGSI_SEMANTIC_COLOR
,
6871 outputSemanticIndex
[i
]);
6873 case TGSI_SEMANTIC_SAMPLEMASK
:
6874 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6875 TGSI_SEMANTIC_SAMPLEMASK
,
6876 outputSemanticIndex
[i
]);
6877 /* TODO: If we ever support more than 32 samples, this will have
6878 * to become an array.
6880 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6883 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6884 ret
= PIPE_ERROR_BAD_INPUT
;
6889 else if (procType
== PIPE_SHADER_VERTEX
) {
6890 for (i
= 0; i
< numOutputs
; i
++) {
6891 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6892 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6894 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6895 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6896 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6901 if (procType
== PIPE_SHADER_COMPUTE
) {
6902 emit_compute_block_size(proginfo
, ureg
);
6905 /* Declare address register.
6907 if (program
->num_address_regs
> 0) {
6908 assert(program
->num_address_regs
<= 3);
6909 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6910 t
->address
[i
] = ureg_DECL_address(ureg
);
6913 /* Declare misc input registers
6916 GLbitfield64 sysInputs
= proginfo
->info
.system_values_read
;
6918 for (i
= 0; sysInputs
; i
++) {
6919 if (sysInputs
& (1ull << i
)) {
6920 enum tgsi_semantic semName
= _mesa_sysval_to_semantic(i
);
6922 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6924 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6925 semName
== TGSI_SEMANTIC_VERTEXID
) {
6926 /* From Gallium perspective, these system values are always
6927 * integer, and require native integer support. However, if
6928 * native integer is supported on the vertex stage but not the
6929 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6930 * assumes these system values are floats. To resolve the
6931 * inconsistency, we insert a U2F.
6933 struct st_context
*st
= st_context(ctx
);
6934 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6935 assert(procType
== PIPE_SHADER_VERTEX
);
6936 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6938 if (!ctx
->Const
.NativeIntegers
) {
6939 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6940 ureg_U2F(t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
),
6941 t
->systemValues
[i
]);
6942 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6946 if (procType
== PIPE_SHADER_FRAGMENT
&&
6947 semName
== TGSI_SEMANTIC_POSITION
)
6948 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6949 program
->wpos_transform_const
);
6951 if (procType
== PIPE_SHADER_FRAGMENT
&&
6952 semName
== TGSI_SEMANTIC_SAMPLEPOS
)
6953 emit_samplepos_adjustment(t
, program
->wpos_transform_const
);
6955 sysInputs
&= ~(1ull << i
);
6960 t
->array_sizes
= program
->array_sizes
;
6961 t
->input_decls
= program
->inputs
;
6962 t
->num_input_decls
= program
->num_inputs
;
6963 t
->output_decls
= program
->outputs
;
6964 t
->num_output_decls
= program
->num_outputs
;
6966 /* Emit constants and uniforms. TGSI uses a single index space for these,
6967 * so we put all the translated regs in t->constants.
6969 if (proginfo
->Parameters
) {
6970 t
->constants
= (struct ureg_src
*)
6971 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6972 if (t
->constants
== NULL
) {
6973 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6976 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6978 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6979 unsigned pvo
= proginfo
->Parameters
->ParameterValueOffset
[i
];
6981 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6982 case PROGRAM_STATE_VAR
:
6983 case PROGRAM_UNIFORM
:
6984 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6987 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6988 * addressing of the const buffer.
6989 * FIXME: Be smarter and recognize param arrays:
6990 * indirect addressing is only valid within the referenced
6993 case PROGRAM_CONSTANT
:
6994 if (program
->indirect_addr_consts
)
6995 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6997 t
->constants
[i
] = emit_immediate(t
,
6998 proginfo
->Parameters
->ParameterValues
+ pvo
,
6999 proginfo
->Parameters
->Parameters
[i
].DataType
,
7008 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
7009 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
7010 unsigned num_const_vecs
= (size
+ 15) / 16;
7011 unsigned first
, last
;
7012 assert(num_const_vecs
> 0);
7014 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
7015 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
7018 /* Emit immediate values.
7020 t
->immediates
= (struct ureg_src
*)
7021 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
7022 if (t
->immediates
== NULL
) {
7023 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
7026 t
->num_immediates
= program
->num_immediates
;
7029 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
7030 assert(i
< program
->num_immediates
);
7031 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
7033 assert(i
== program
->num_immediates
);
7035 /* texture samplers */
7036 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
7037 if (program
->samplers_used
& (1u << i
)) {
7038 enum tgsi_return_type type
=
7039 st_translate_texture_type(program
->sampler_types
[i
]);
7041 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
7043 ureg_DECL_sampler_view(ureg
, i
, program
->sampler_targets
[i
],
7044 type
, type
, type
, type
);
7048 /* Declare atomic and shader storage buffers. */
7050 struct gl_program
*prog
= program
->prog
;
7052 if (!st_context(ctx
)->has_hw_atomics
) {
7053 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
7054 unsigned index
= (prog
->info
.num_ssbos
+
7055 prog
->sh
.AtomicBuffers
[i
]->Binding
);
7056 assert(prog
->sh
.AtomicBuffers
[i
]->Binding
<
7057 frag_const
->MaxAtomicBuffers
);
7058 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
7061 for (i
= 0; i
< program
->num_atomics
; i
++) {
7062 struct hwatomic_decl
*ainfo
= &program
->atomic_info
[i
];
7063 gl_uniform_storage
*uni_storage
= &prog
->sh
.data
->UniformStorage
[ainfo
->location
];
7064 int base
= uni_storage
->offset
/ ATOMIC_COUNTER_SIZE
;
7065 ureg_DECL_hw_atomic(ureg
, base
, base
+ ainfo
->size
- 1, ainfo
->binding
,
7070 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
7071 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
7072 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
7076 if (program
->use_shared_memory
)
7077 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
7079 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
7080 if (program
->images_used
& (1 << i
)) {
7081 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
7082 program
->image_targets
[i
],
7083 program
->image_formats
[i
],
7084 program
->image_wr
[i
],
7089 /* Emit each instruction in turn:
7091 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
7092 compile_tgsi_instruction(t
, inst
);
7094 /* Set the next shader stage hint for VS and TES. */
7096 case PIPE_SHADER_VERTEX
:
7097 case PIPE_SHADER_TESS_EVAL
:
7098 if (program
->shader_program
->SeparateShader
)
7101 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
7102 if (program
->shader_program
->_LinkedShaders
[i
]) {
7103 ureg_set_next_shader_processor(
7104 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
7110 ; /* nothing - silence compiler warning */
7118 t
->num_constants
= 0;
7119 free(t
->immediates
);
7120 t
->num_immediates
= 0;
7126 /* ----------------------------- End TGSI code ------------------------------ */
7130 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7131 * generating Mesa IR.
7133 static struct gl_program
*
7134 get_mesa_program_tgsi(struct gl_context
*ctx
,
7135 struct gl_shader_program
*shader_program
,
7136 struct gl_linked_shader
*shader
)
7138 glsl_to_tgsi_visitor
* v
;
7139 struct gl_program
*prog
;
7140 struct gl_shader_compiler_options
*options
=
7141 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
7142 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7143 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
7144 unsigned skip_merge_registers
;
7146 validate_ir_tree(shader
->ir
);
7148 prog
= shader
->Program
;
7150 prog
->Parameters
= _mesa_new_parameter_list();
7151 v
= new glsl_to_tgsi_visitor();
7154 v
->shader_program
= shader_program
;
7156 v
->options
= options
;
7157 v
->native_integers
= ctx
->Const
.NativeIntegers
;
7159 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
7160 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
7161 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
7162 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
7163 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
7164 PIPE_CAP_TGSI_TEX_TXF_LZ
);
7165 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
7167 v
->tg4_component_in_swizzle
= pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
);
7168 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
7169 _mesa_key_pointer_equal
);
7170 skip_merge_registers
=
7171 pscreen
->get_shader_param(pscreen
, ptarget
,
7172 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
7174 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
7177 /* Remove reads from output registers. */
7178 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
7179 lower_output_reads(shader
->Stage
, shader
->ir
);
7181 /* Emit intermediate IR for main(). */
7182 visit_exec_list(shader
->ir
, v
);
7185 /* Print out some information (for debugging purposes) used by the
7186 * optimization passes. */
7189 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7190 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7191 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7192 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
7194 for (i
= 0; i
< v
->next_temp
; i
++) {
7195 first_writes
[i
] = -1;
7196 first_reads
[i
] = -1;
7197 last_writes
[i
] = -1;
7200 v
->get_first_temp_read(first_reads
);
7201 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
7202 v
->get_last_temp_write(last_writes
);
7203 for (i
= 0; i
< v
->next_temp
; i
++)
7204 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
7208 ralloc_free(first_writes
);
7209 ralloc_free(first_reads
);
7210 ralloc_free(last_writes
);
7211 ralloc_free(last_reads
);
7215 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7217 v
->copy_propagate();
7219 while (v
->eliminate_dead_code());
7221 v
->merge_two_dsts();
7223 if (!skip_merge_registers
) {
7225 v
->copy_propagate();
7226 while (v
->eliminate_dead_code());
7228 v
->merge_registers();
7229 v
->copy_propagate();
7230 while (v
->eliminate_dead_code());
7233 v
->renumber_registers();
7235 /* Write the END instruction. */
7236 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
7238 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
7240 _mesa_log("GLSL IR for linked %s program %d:\n",
7241 _mesa_shader_stage_to_string(shader
->Stage
),
7242 shader_program
->Name
);
7243 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
7247 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
7249 _mesa_copy_linked_program_data(shader_program
, shader
);
7251 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS
)) {
7252 mark_array_io(v
->inputs
, v
->num_inputs
,
7253 &prog
->info
.inputs_read
,
7254 prog
->DualSlotInputs
,
7255 &prog
->info
.patch_inputs_read
);
7257 mark_array_io(v
->outputs
, v
->num_outputs
,
7258 &prog
->info
.outputs_written
, 0ULL,
7259 &prog
->info
.patch_outputs_written
);
7261 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
7262 &prog
->info
.inputs_read
,
7263 prog
->DualSlotInputs
,
7264 &prog
->info
.patch_inputs_read
);
7265 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
7266 &prog
->info
.outputs_written
, 0ULL,
7267 &prog
->info
.patch_outputs_written
);
7270 count_resources(v
, prog
);
7272 /* The GLSL IR won't be needed anymore. */
7273 ralloc_free(shader
->ir
);
7276 /* This must be done before the uniform storage is associated. */
7277 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
7278 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
7279 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
) ||
7280 prog
->info
.system_values_read
& (1ull << SYSTEM_VALUE_SAMPLE_POS
))) {
7281 static const gl_state_index16 wposTransformState
[STATE_LENGTH
] = {
7282 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
7285 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
7286 wposTransformState
);
7289 /* Avoid reallocation of the program parameter list, because the uniform
7290 * storage is only associated with the original parameter list.
7291 * This should be enough for Bitmap and DrawPixels constants.
7293 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
7295 /* This has to be done last. Any operation the can cause
7296 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7297 * program constant) has to happen before creating this linkage.
7299 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
);
7300 if (!shader_program
->data
->LinkStatus
) {
7301 free_glsl_to_tgsi_visitor(v
);
7302 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7306 st_program(prog
)->glsl_to_tgsi
= v
;
7308 PRINT_STATS(v
->print_stats());
7313 /* See if there are unsupported control flow statements. */
7314 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
7316 const struct gl_shader_compiler_options
*options
;
7318 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
7324 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
7326 /* Other functions are skipped (same as glsl_to_tgsi). */
7327 if (strcmp(ir
->name
, "main") == 0)
7328 return visit_continue
;
7330 return visit_continue_with_parent
;
7333 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
7335 if (!ir
->callee
->is_intrinsic()) {
7336 unsupported
= true; /* it's a function call */
7339 return visit_continue
;
7342 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7344 if (options
->EmitNoMainReturn
) {
7348 return visit_continue
;
7355 has_unsupported_control_flow(exec_list
*ir
,
7356 const struct gl_shader_compiler_options
*options
)
7358 ir_control_flow_info_visitor
visitor(options
);
7359 visit_list_elements(&visitor
, ir
);
7360 return visitor
.unsupported
;
7365 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7366 * with code lowering and other optimizations.
7369 st_link_tgsi(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7371 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7373 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7374 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7378 exec_list
*ir
= shader
->ir
;
7379 gl_shader_stage stage
= shader
->Stage
;
7380 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
7381 const struct gl_shader_compiler_options
*options
=
7382 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7384 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7385 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7386 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7387 /* Do it once and repeat only if there's unsupported control flow. */
7389 do_common_optimization(ir
, true, true, options
,
7390 ctx
->Const
.NativeIntegers
);
7391 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7392 options
->MaxIfDepth
, if_threshold
);
7393 } while (has_unsupported_control_flow(ir
, options
));
7395 /* Repeat it until it stops making changes. */
7398 progress
= do_common_optimization(ir
, true, true, options
,
7399 ctx
->Const
.NativeIntegers
);
7400 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7401 options
->MaxIfDepth
, if_threshold
);
7405 /* Do this again to lower ir_binop_vector_extract introduced
7406 * by optimization passes.
7408 do_vec_index_to_cond_assign(ir
);
7410 validate_ir_tree(ir
);
7412 struct gl_program
*linked_prog
=
7413 get_mesa_program_tgsi(ctx
, prog
, shader
);
7414 st_set_prog_affected_state_flags(linked_prog
);
7417 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7418 _mesa_shader_stage_to_program(i
),
7420 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);