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glsl_to_tgsi: add fallthrough comments
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_to_tgsi_temprename.h"
56
57 #include "util/hash_table.h"
58 #include <algorithm>
59
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
63
64 #define MAX_GLSL_TEXTURE_OFFSET 4
65
66 #ifndef NDEBUG
67 #include "util/u_atomic.h"
68 #include "util/simple_mtx.h"
69 #include <fstream>
70 #include <ios>
71
72 /* Prepare to make it possible to specify log file */
73 static std::ofstream stats_log;
74
75 /* Helper function to check whether we want to write some statistics
76 * of the shader conversion.
77 */
78
79 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
80
81 static inline bool print_stats_enabled ()
82 {
83 static int stats_enabled = 0;
84
85 if (!stats_enabled) {
86 simple_mtx_lock(&print_stats_mutex);
87 if (!stats_enabled) {
88 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
89 if (stats_filename) {
90 bool write_header = std::ifstream(stats_filename).fail();
91 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
92 stats_enabled = stats_log.good() ? 1 : -1;
93 if (write_header)
94 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
95 } else {
96 stats_enabled = -1;
97 }
98 }
99 simple_mtx_unlock(&print_stats_mutex);
100 }
101 return stats_enabled > 0;
102 }
103 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
104 #else
105 #define PRINT_STATS(X)
106 #endif
107
108
109 static unsigned is_precise(const ir_variable *ir)
110 {
111 if (!ir)
112 return 0;
113 return ir->data.precise || ir->data.invariant;
114 }
115
116 class variable_storage {
117 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
118
119 public:
120 variable_storage(ir_variable *var, gl_register_file file, int index,
121 unsigned array_id = 0)
122 : file(file), index(index), component(0), var(var), array_id(array_id)
123 {
124 assert(file != PROGRAM_ARRAY || array_id != 0);
125 }
126
127 gl_register_file file;
128 int index;
129
130 /* Explicit component location. This is given in terms of the GLSL-style
131 * swizzles where each double is a single component, i.e. for 64-bit types
132 * it can only be 0 or 1.
133 */
134 int component;
135 ir_variable *var; /* variable that maps to this, if any */
136 unsigned array_id;
137 };
138
139 class immediate_storage : public exec_node {
140 public:
141 immediate_storage(gl_constant_value *values, int size32, GLenum type)
142 {
143 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
144 this->size32 = size32;
145 this->type = type;
146 }
147
148 /* doubles are stored across 2 gl_constant_values */
149 gl_constant_value values[4];
150 int size32; /**< Number of 32-bit components (1-4) */
151 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
152 };
153
154 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
155 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
156
157 struct inout_decl {
158 unsigned mesa_index;
159 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
160 unsigned size;
161 unsigned interp_loc;
162 unsigned gs_out_streams;
163 enum glsl_interp_mode interp;
164 enum glsl_base_type base_type;
165 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
166 bool invariant;
167 };
168
169 static struct inout_decl *
170 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
171 {
172 assert(array_id != 0);
173
174 for (unsigned i = 0; i < count; i++) {
175 struct inout_decl *decl = &decls[i];
176
177 if (array_id == decl->array_id) {
178 return decl;
179 }
180 }
181
182 return NULL;
183 }
184
185 static enum glsl_base_type
186 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
187 {
188 if (!array_id)
189 return GLSL_TYPE_ERROR;
190 struct inout_decl *decl = find_inout_array(decls, count, array_id);
191 if (decl)
192 return decl->base_type;
193 return GLSL_TYPE_ERROR;
194 }
195
196 struct hwatomic_decl {
197 unsigned location;
198 unsigned binding;
199 unsigned size;
200 unsigned array_id;
201 };
202
203 struct glsl_to_tgsi_visitor : public ir_visitor {
204 public:
205 glsl_to_tgsi_visitor();
206 ~glsl_to_tgsi_visitor();
207
208 struct gl_context *ctx;
209 struct gl_program *prog;
210 struct gl_shader_program *shader_program;
211 struct gl_linked_shader *shader;
212 struct gl_shader_compiler_options *options;
213
214 int next_temp;
215
216 unsigned *array_sizes;
217 unsigned max_num_arrays;
218 unsigned next_array;
219
220 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
221 unsigned num_inputs;
222 unsigned num_input_arrays;
223 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
224 unsigned num_outputs;
225 unsigned num_output_arrays;
226
227 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
228 unsigned num_atomics;
229 unsigned num_atomic_arrays;
230 int num_address_regs;
231 uint32_t samplers_used;
232 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
233 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
234 int images_used;
235 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
236 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
237 bool image_wr[PIPE_MAX_SHADER_IMAGES];
238 bool indirect_addr_consts;
239 int wpos_transform_const;
240
241 bool native_integers;
242 bool have_sqrt;
243 bool have_fma;
244 bool use_shared_memory;
245 bool has_tex_txf_lz;
246 bool precise;
247 bool need_uarl;
248 bool tg4_component_in_swizzle;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_demote *);
288 virtual void visit(ir_texture *);
289 virtual void visit(ir_if *);
290 virtual void visit(ir_emit_vertex *);
291 virtual void visit(ir_end_primitive *);
292 virtual void visit(ir_barrier *);
293 /*@}*/
294
295 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
296
297 void visit_atomic_counter_intrinsic(ir_call *);
298 void visit_ssbo_intrinsic(ir_call *);
299 void visit_membar_intrinsic(ir_call *);
300 void visit_shared_intrinsic(ir_call *);
301 void visit_image_intrinsic(ir_call *);
302 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
303
304 st_src_reg result;
305
306 /** List of variable_storage */
307 struct hash_table *variables;
308
309 /** List of immediate_storage */
310 exec_list immediates;
311 unsigned num_immediates;
312
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions;
315
316 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
317 st_dst_reg dst = undef_dst,
318 st_src_reg src0 = undef_src,
319 st_src_reg src1 = undef_src,
320 st_src_reg src2 = undef_src,
321 st_src_reg src3 = undef_src);
322
323 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
324 st_dst_reg dst, st_dst_reg dst1,
325 st_src_reg src0 = undef_src,
326 st_src_reg src1 = undef_src,
327 st_src_reg src2 = undef_src,
328 st_src_reg src3 = undef_src);
329
330 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
331 st_dst_reg dst,
332 st_src_reg src0, st_src_reg src1);
333
334 /**
335 * Emit the correct dot-product instruction for the type of arguments
336 */
337 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
338 st_dst_reg dst,
339 st_src_reg src0,
340 st_src_reg src1,
341 unsigned elements);
342
343 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
344 st_dst_reg dst, st_src_reg src0);
345
346 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
347 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
348
349 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
350
351 void get_deref_offsets(ir_dereference *ir,
352 unsigned *array_size,
353 unsigned *base,
354 uint16_t *index,
355 st_src_reg *reladdr,
356 bool opaque);
357 void calc_deref_offsets(ir_dereference *tail,
358 unsigned *array_elements,
359 uint16_t *index,
360 st_src_reg *indirect,
361 unsigned *location);
362 st_src_reg canonicalize_gather_offset(st_src_reg offset);
363 bool handle_bound_deref(ir_dereference *ir);
364
365 bool try_emit_mad(ir_expression *ir,
366 int mul_operand);
367 bool try_emit_mad_for_and_not(ir_expression *ir,
368 int mul_operand);
369
370 void emit_swz(ir_expression *ir);
371
372 bool process_move_condition(ir_rvalue *ir);
373
374 void simplify_cmp(void);
375
376 void rename_temp_registers(struct rename_reg_pair *renames);
377 void get_first_temp_read(int *first_reads);
378 void get_first_temp_write(int *first_writes);
379 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
380 void get_last_temp_write(int *last_writes);
381
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
384
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
389
390 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
391 st_dst_reg *l, st_src_reg *r,
392 st_src_reg *cond, bool cond_swap);
393
394 void print_stats();
395
396 void *mem_ctx;
397 };
398
399 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
400 GLSL_TYPE_FLOAT, 0);
401 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
402 GLSL_TYPE_FLOAT, 1);
403 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
404 GLSL_TYPE_FLOAT, 2);
405
406 static void
407 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
408 PRINTFLIKE(2, 3);
409
410 static void
411 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
412 {
413 va_list args;
414 va_start(args, fmt);
415 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
416 va_end(args);
417
418 prog->data->LinkStatus = LINKING_FAILURE;
419 }
420
421 int
422 swizzle_for_size(int size)
423 {
424 static const int size_swizzles[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
428 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
429 };
430
431 assert((size >= 1) && (size <= 4));
432 return size_swizzles[size - 1];
433 }
434
435
436 glsl_to_tgsi_instruction *
437 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
438 st_dst_reg dst, st_dst_reg dst1,
439 st_src_reg src0, st_src_reg src1,
440 st_src_reg src2, st_src_reg src3)
441 {
442 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
443 int num_reladdr = 0, i, j;
444 bool dst_is_64bit[2];
445
446 op = get_opcode(op, dst, src0, src1);
447
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
451 */
452 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
453 assert(!dst1.reladdr); /* should be lowered in earlier passes */
454 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
455 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
456 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
457 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
458
459 reladdr_to_temp(ir, &src3, &num_reladdr);
460 reladdr_to_temp(ir, &src2, &num_reladdr);
461 reladdr_to_temp(ir, &src1, &num_reladdr);
462 reladdr_to_temp(ir, &src0, &num_reladdr);
463
464 if (dst.reladdr || dst.reladdr2) {
465 if (dst.reladdr)
466 emit_arl(ir, address_reg, *dst.reladdr);
467 if (dst.reladdr2)
468 emit_arl(ir, address_reg2, *dst.reladdr2);
469 num_reladdr--;
470 }
471
472 assert(num_reladdr == 0);
473
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
476
477 inst->op = op;
478 inst->precise = this->precise;
479 inst->info = tgsi_get_opcode_info(op);
480 inst->dst[0] = dst;
481 inst->dst[1] = dst1;
482 inst->src[0] = src0;
483 inst->src[1] = src1;
484 inst->src[2] = src2;
485 inst->src[3] = src3;
486 inst->is_64bit_expanded = false;
487 inst->ir = ir;
488 inst->dead_mask = 0;
489 inst->tex_offsets = NULL;
490 inst->tex_offset_num_offset = 0;
491 inst->saturate = 0;
492 inst->tex_shadow = 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
495 */
496 inst->tex_type = GLSL_TYPE_FLOAT;
497
498 /* Update indirect addressing status used by TGSI */
499 if (dst.reladdr || dst.reladdr2) {
500 switch (dst.file) {
501 case PROGRAM_STATE_VAR:
502 case PROGRAM_CONSTANT:
503 case PROGRAM_UNIFORM:
504 this->indirect_addr_consts = true;
505 break;
506 case PROGRAM_IMMEDIATE:
507 assert(!"immediates should not have indirect addressing");
508 break;
509 default:
510 break;
511 }
512 }
513 else {
514 for (i = 0; i < 4; i++) {
515 if (inst->src[i].reladdr) {
516 switch (inst->src[i].file) {
517 case PROGRAM_STATE_VAR:
518 case PROGRAM_CONSTANT:
519 case PROGRAM_UNIFORM:
520 this->indirect_addr_consts = true;
521 break;
522 case PROGRAM_IMMEDIATE:
523 assert(!"immediates should not have indirect addressing");
524 break;
525 default:
526 break;
527 }
528 }
529 }
530 }
531
532 /*
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
536 *
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
541 *
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
544 *
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
549 */
550 for (j = 0; j < 2; j++) {
551 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
552 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
553 inst->dst[j].type == GLSL_TYPE_ARRAY) {
554 enum glsl_base_type type = find_array_type(this->outputs,
555 this->num_outputs,
556 inst->dst[j].array_id);
557 if (glsl_base_type_is_64bit(type))
558 dst_is_64bit[j] = true;
559 }
560 }
561
562 if (dst_is_64bit[0] || dst_is_64bit[1] ||
563 glsl_base_type_is_64bit(inst->src[0].type)) {
564 glsl_to_tgsi_instruction *dinst = NULL;
565 int initial_src_swz[4], initial_src_idx[4];
566 int initial_dst_idx[2], initial_dst_writemask[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
569 ? inst->dst[0].writemask : inst->dst[1].writemask;
570
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j = 0; j < 2; j++) {
573 initial_dst_writemask[j] = inst->dst[j].writemask;
574 initial_dst_idx[j] = inst->dst[j].index;
575 }
576
577 for (j = 0; j < 4; j++) {
578 initial_src_swz[j] = inst->src[j].swizzle;
579 initial_src_idx[j] = inst->src[j].index;
580 }
581
582 /*
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
585 */
586 st_src_reg addr;
587 while (writemask) {
588
589 int i = u_bit_scan(&writemask);
590
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
594 inst->op == TGSI_OPCODE_STORE) &&
595 addr.file == PROGRAM_UNDEFINED) {
596 /* We have to advance the buffer address by 16 */
597 addr = get_temp(glsl_type::uint_type);
598 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
599 inst->src[0], st_src_reg_for_int(16));
600 }
601
602 /* first time use previous instruction */
603 if (dinst == NULL) {
604 dinst = inst;
605 } else {
606 /* create a new instructions for subsequent attempts */
607 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
608 *dinst = *inst;
609 dinst->next = NULL;
610 dinst->prev = NULL;
611 }
612 this->instructions.push_tail(dinst);
613 dinst->is_64bit_expanded = true;
614
615 /* modify the destination if we are splitting */
616 for (j = 0; j < 2; j++) {
617 if (dst_is_64bit[j]) {
618 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
619 dinst->dst[j].index = initial_dst_idx[j];
620 if (i > 1) {
621 if (dinst->op == TGSI_OPCODE_LOAD ||
622 dinst->op == TGSI_OPCODE_STORE)
623 dinst->src[0] = addr;
624 if (dinst->op != TGSI_OPCODE_STORE)
625 dinst->dst[j].index++;
626 }
627 } else {
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
630 */
631 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
632 }
633 }
634
635 /* modify the src registers */
636 for (j = 0; j < 4; j++) {
637 int swz = GET_SWZ(initial_src_swz[j], i);
638
639 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
640 dinst->src[j].index = initial_src_idx[j];
641 if (swz > 1) {
642 dinst->src[j].double_reg2 = true;
643 dinst->src[j].index++;
644 }
645
646 if (swz & 1)
647 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
648 SWIZZLE_Z, SWIZZLE_W);
649 else
650 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
651 SWIZZLE_X, SWIZZLE_Y);
652
653 } else {
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
656 * integer src1
657 */
658 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
659 op == TGSI_OPCODE_I2D ||
660 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
661 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
662 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
663 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
664 }
665 }
666 }
667 }
668 inst = dinst;
669 } else {
670 this->instructions.push_tail(inst);
671 }
672
673
674 return inst;
675 }
676
677 glsl_to_tgsi_instruction *
678 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
679 st_dst_reg dst,
680 st_src_reg src0, st_src_reg src1,
681 st_src_reg src2, st_src_reg src3)
682 {
683 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
684 }
685
686 /**
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
689 */
690 enum tgsi_opcode
691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
692 st_dst_reg dst,
693 st_src_reg src0, st_src_reg src1)
694 {
695 enum glsl_base_type type = GLSL_TYPE_FLOAT;
696
697 if (op == TGSI_OPCODE_MOV)
698 return op;
699
700 assert(src0.type != GLSL_TYPE_ARRAY);
701 assert(src0.type != GLSL_TYPE_STRUCT);
702 assert(src1.type != GLSL_TYPE_ARRAY);
703 assert(src1.type != GLSL_TYPE_STRUCT);
704
705 if (is_resource_instruction(op))
706 type = src1.type;
707 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
708 type = GLSL_TYPE_INT64;
709 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
710 type = GLSL_TYPE_UINT64;
711 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
712 type = GLSL_TYPE_DOUBLE;
713 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
714 type = GLSL_TYPE_FLOAT;
715 else if (native_integers)
716 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
717
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
730 else \
731 op = TGSI_OPCODE_##f; \
732 break;
733
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
748 else \
749 op = TGSI_OPCODE_##c; \
750 break;
751
752 switch (op) {
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
755 *
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
757 */
758 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
759 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
760 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
761 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
762 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
763 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
764 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
765 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
766 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
767 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
768 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
769 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
770 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
771 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
772 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
773 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
774
775 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
776 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
777 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
778 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
779 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
780 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
781 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
782 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
783 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
784
785 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
786 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
787 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
788 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
789
790 default:
791 break;
792 }
793
794 assert(op != TGSI_OPCODE_LAST);
795 return op;
796 }
797
798 glsl_to_tgsi_instruction *
799 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
800 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
801 unsigned elements)
802 {
803 static const enum tgsi_opcode dot_opcodes[] = {
804 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
805 };
806
807 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
808 }
809
810 /**
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
812 *
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
817 */
818 void
819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
820 st_dst_reg dst,
821 st_src_reg orig_src0, st_src_reg orig_src1)
822 {
823 int i, j;
824 int done_mask = ~dst.writemask;
825
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
828 * dst channels.
829 */
830 for (i = 0; i < 4; i++) {
831 GLuint this_mask = (1 << i);
832 st_src_reg src0 = orig_src0;
833 st_src_reg src1 = orig_src1;
834
835 if (done_mask & this_mask)
836 continue;
837
838 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
839 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
840 for (j = i + 1; j < 4; j++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
843 * well.
844 */
845 if (!(done_mask & (1 << j)) &&
846 GET_SWZ(src0.swizzle, j) == src0_swiz &&
847 GET_SWZ(src1.swizzle, j) == src1_swiz) {
848 this_mask |= (1 << j);
849 }
850 }
851 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
852 src0_swiz, src0_swiz);
853 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
854 src1_swiz, src1_swiz);
855
856 dst.writemask = this_mask;
857 emit_asm(ir, op, dst, src0, src1);
858 done_mask |= this_mask;
859 }
860 }
861
862 void
863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
864 st_dst_reg dst, st_src_reg src0)
865 {
866 st_src_reg undef = undef_src;
867
868 undef.swizzle = SWIZZLE_XXXX;
869
870 emit_scalar(ir, op, dst, src0, undef);
871 }
872
873 void
874 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
875 st_dst_reg dst, st_src_reg src0)
876 {
877 enum tgsi_opcode op = TGSI_OPCODE_ARL;
878
879 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
880 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
881 return;
882
883 op = TGSI_OPCODE_UARL;
884 }
885
886 assert(dst.file == PROGRAM_ADDRESS);
887 if (dst.index >= this->num_address_regs)
888 this->num_address_regs = dst.index + 1;
889
890 emit_asm(NULL, op, dst, src0);
891 }
892
893 int
894 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
895 gl_constant_value values[8], int size,
896 GLenum datatype,
897 uint16_t *swizzle_out)
898 {
899 if (file == PROGRAM_CONSTANT) {
900 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
901 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
902 values, size, datatype,
903 &swizzle);
904 if (swizzle_out)
905 *swizzle_out = swizzle;
906 return result;
907 }
908
909 assert(file == PROGRAM_IMMEDIATE);
910
911 int index = 0;
912 immediate_storage *entry;
913 int size32 = size * ((datatype == GL_DOUBLE ||
914 datatype == GL_INT64_ARB ||
915 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
916 int i;
917
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
920 */
921 foreach_in_list(immediate_storage, entry, &this->immediates) {
922 immediate_storage *tmp = entry;
923
924 for (i = 0; i * 4 < size32; i++) {
925 int slot_size = MIN2(size32 - (i * 4), 4);
926 if (tmp->type != datatype || tmp->size32 != slot_size)
927 break;
928 if (memcmp(tmp->values, &values[i * 4],
929 slot_size * sizeof(gl_constant_value)))
930 break;
931
932 /* Everything matches, keep going until the full size is matched */
933 tmp = (immediate_storage *)tmp->next;
934 }
935
936 /* The full value matched */
937 if (i * 4 >= size32)
938 return index;
939
940 index++;
941 }
942
943 for (i = 0; i * 4 < size32; i++) {
944 int slot_size = MIN2(size32 - (i * 4), 4);
945 /* Add this immediate to the list. */
946 entry = new(mem_ctx) immediate_storage(&values[i * 4],
947 slot_size, datatype);
948 this->immediates.push_tail(entry);
949 this->num_immediates++;
950 }
951 return index;
952 }
953
954 st_src_reg
955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
956 {
957 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
958 union gl_constant_value uval;
959
960 uval.f = val;
961 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
962
963 return src;
964 }
965
966 st_src_reg
967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
968 {
969 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
970 union gl_constant_value uval[2];
971
972 memcpy(uval, &val, sizeof(uval));
973 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
974 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
975 return src;
976 }
977
978 st_src_reg
979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
980 {
981 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
982 union gl_constant_value uval;
983
984 assert(native_integers);
985
986 uval.i = val;
987 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
988
989 return src;
990 }
991
992 st_src_reg
993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
994 {
995 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
996 union gl_constant_value uval[2];
997
998 memcpy(uval, &val, sizeof(uval));
999 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
1000 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1001
1002 return src;
1003 }
1004
1005 st_src_reg
1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1007 {
1008 if (native_integers)
1009 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1010 st_src_reg_for_int(val);
1011 else
1012 return st_src_reg_for_float(val);
1013 }
1014
1015 static int
1016 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1017 {
1018 return type->count_attribute_slots(is_vs_input);
1019 }
1020
1021 static int
1022 type_size(const struct glsl_type *type)
1023 {
1024 return type->count_attribute_slots(false);
1025 }
1026
1027 static void
1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1029 exec_list *instructions, ir_constant *access)
1030 {
1031 /**
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1034 */
1035 enum tgsi_opcode op = inst->op;
1036 do {
1037 inst->resource = *buf;
1038 if (access)
1039 inst->buffer_access = access->value.u[0];
1040
1041 if (inst == instructions->get_head_raw())
1042 break;
1043 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1044
1045 if (inst->op == TGSI_OPCODE_UADD) {
1046 if (inst == instructions->get_head_raw())
1047 break;
1048 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1049 }
1050 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1051 }
1052
1053 /**
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1056 *
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1061 */
1062 static bool
1063 type_has_array_or_matrix(const glsl_type *type)
1064 {
1065 if (type->is_array() || type->is_matrix())
1066 return true;
1067
1068 if (type->is_struct()) {
1069 for (unsigned i = 0; i < type->length; i++) {
1070 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1071 return true;
1072 }
1073 }
1074 }
1075
1076 return false;
1077 }
1078
1079
1080 /**
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1083 * storage).
1084 */
1085 st_src_reg
1086 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1087 {
1088 st_src_reg src;
1089
1090 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1091 src.reladdr = NULL;
1092 src.negate = 0;
1093 src.abs = 0;
1094
1095 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1096 if (next_array >= max_num_arrays) {
1097 max_num_arrays += 32;
1098 array_sizes = (unsigned*)
1099 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1100 }
1101
1102 src.file = PROGRAM_ARRAY;
1103 src.index = 0;
1104 src.array_id = next_array + 1;
1105 array_sizes[next_array] = type_size(type);
1106 ++next_array;
1107
1108 } else {
1109 src.file = PROGRAM_TEMPORARY;
1110 src.index = next_temp;
1111 next_temp += type_size(type);
1112 }
1113
1114 if (type->is_array() || type->is_struct()) {
1115 src.swizzle = SWIZZLE_NOOP;
1116 } else {
1117 src.swizzle = swizzle_for_size(type->vector_elements);
1118 }
1119
1120 return src;
1121 }
1122
1123 variable_storage *
1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1125 {
1126 struct hash_entry *entry;
1127
1128 entry = _mesa_hash_table_search(this->variables, var);
1129 if (!entry)
1130 return NULL;
1131
1132 return (variable_storage *)entry->data;
1133 }
1134
1135 void
1136 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1137 {
1138 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1139 unsigned int i;
1140 const ir_state_slot *const slots = ir->get_state_slots();
1141 assert(slots != NULL);
1142
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1147 * out.
1148 */
1149 for (i = 0; i < ir->get_num_state_slots(); i++) {
1150 if (slots[i].swizzle != SWIZZLE_XYZW) {
1151 break;
1152 }
1153 }
1154
1155 variable_storage *storage;
1156 st_dst_reg dst;
1157 if (i == ir->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1160
1161 _mesa_hash_table_insert(this->variables, ir, storage);
1162
1163 dst = undef_dst;
1164 } else {
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1168 */
1169 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1170
1171 dst = st_dst_reg(get_temp(ir->type));
1172
1173 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1174 dst.array_id);
1175
1176 _mesa_hash_table_insert(this->variables, ir, storage);
1177 }
1178
1179
1180 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1181 int index = _mesa_add_state_reference(this->prog->Parameters,
1182 slots[i].tokens);
1183
1184 if (storage->file == PROGRAM_STATE_VAR) {
1185 if (storage->index == -1) {
1186 storage->index = index;
1187 } else {
1188 assert(index == storage->index + (int)i);
1189 }
1190 } else {
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1195 */
1196 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1197 src.swizzle = slots[i].swizzle;
1198 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1200 dst.index++;
1201 }
1202 }
1203
1204 if (storage->file == PROGRAM_TEMPORARY &&
1205 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1206 fail_link(this->shader_program,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir->name, dst.index - storage->index,
1209 type_size(ir->type));
1210 }
1211 }
1212 }
1213
1214 void
1215 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1216 {
1217 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1218
1219 visit_exec_list(&ir->body_instructions, this);
1220
1221 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1222 }
1223
1224 void
1225 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1226 {
1227 switch (ir->mode) {
1228 case ir_loop_jump::jump_break:
1229 emit_asm(NULL, TGSI_OPCODE_BRK);
1230 break;
1231 case ir_loop_jump::jump_continue:
1232 emit_asm(NULL, TGSI_OPCODE_CONT);
1233 break;
1234 }
1235 }
1236
1237
1238 void
1239 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1240 {
1241 assert(0);
1242 (void)ir;
1243 }
1244
1245 void
1246 glsl_to_tgsi_visitor::visit(ir_function *ir)
1247 {
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1250 */
1251 if (strcmp(ir->name, "main") == 0) {
1252 const ir_function_signature *sig;
1253 exec_list empty;
1254
1255 sig = ir->matching_signature(NULL, &empty, false);
1256
1257 assert(sig);
1258
1259 foreach_in_list(ir_instruction, ir, &sig->body) {
1260 ir->accept(this);
1261 }
1262 }
1263 }
1264
1265 bool
1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1267 {
1268 int nonmul_operand = 1 - mul_operand;
1269 st_src_reg a, b, c;
1270 st_dst_reg result_dst;
1271
1272 // there is no TGSI opcode for this
1273 if (ir->type->is_integer_64())
1274 return false;
1275
1276 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1277 if (!expr || expr->operation != ir_binop_mul)
1278 return false;
1279
1280 expr->operands[0]->accept(this);
1281 a = this->result;
1282 expr->operands[1]->accept(this);
1283 b = this->result;
1284 ir->operands[nonmul_operand]->accept(this);
1285 c = this->result;
1286
1287 this->result = get_temp(ir->type);
1288 result_dst = st_dst_reg(this->result);
1289 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1290 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1291
1292 return true;
1293 }
1294
1295 /**
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1297 *
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1302 *
1303 * - a * !b
1304 * - a * (1 - b)
1305 * - (a * 1) - (a * b)
1306 * - a + -(a * b)
1307 * - a + (a * -b)
1308 *
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1310 * instruction.
1311 */
1312 bool
1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1314 int try_operand)
1315 {
1316 const int other_operand = 1 - try_operand;
1317 st_src_reg a, b;
1318
1319 ir_expression *expr = ir->operands[try_operand]->as_expression();
1320 if (!expr || expr->operation != ir_unop_logic_not)
1321 return false;
1322
1323 ir->operands[other_operand]->accept(this);
1324 a = this->result;
1325 expr->operands[0]->accept(this);
1326 b = this->result;
1327
1328 b.negate = ~b.negate;
1329
1330 this->result = get_temp(ir->type);
1331 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1332
1333 return true;
1334 }
1335
1336 void
1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1338 st_src_reg *reg, int *num_reladdr)
1339 {
1340 if (!reg->reladdr && !reg->reladdr2)
1341 return;
1342
1343 if (reg->reladdr)
1344 emit_arl(ir, address_reg, *reg->reladdr);
1345 if (reg->reladdr2)
1346 emit_arl(ir, address_reg2, *reg->reladdr2);
1347
1348 if (*num_reladdr != 1) {
1349 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1350
1351 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1352 *reg = temp;
1353 }
1354
1355 (*num_reladdr)--;
1356 }
1357
1358 void
1359 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1360 {
1361 st_src_reg op[ARRAY_SIZE(ir->operands)];
1362
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1364 */
1365 if (!this->precise && ir->operation == ir_binop_add) {
1366 if (try_emit_mad(ir, 1))
1367 return;
1368 if (try_emit_mad(ir, 0))
1369 return;
1370 }
1371
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1373 */
1374 if (!native_integers && ir->operation == ir_binop_logic_and) {
1375 if (try_emit_mad_for_and_not(ir, 1))
1376 return;
1377 if (try_emit_mad_for_and_not(ir, 0))
1378 return;
1379 }
1380
1381 if (ir->operation == ir_quadop_vector)
1382 assert(!"ir_quadop_vector should have been lowered");
1383
1384 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1385 this->result.file = PROGRAM_UNDEFINED;
1386 ir->operands[operand]->accept(this);
1387 if (this->result.file == PROGRAM_UNDEFINED) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir->operands[operand]->print();
1390 printf("\n");
1391 exit(1);
1392 }
1393 op[operand] = this->result;
1394
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1397 */
1398 assert(!ir->operands[operand]->type->is_matrix());
1399 }
1400
1401 visit_expression(ir, op);
1402 }
1403
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1407 */
1408 void
1409 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1410 {
1411 st_src_reg result_src;
1412 st_dst_reg result_dst;
1413
1414 int vector_elements = ir->operands[0]->type->vector_elements;
1415 if (ir->operands[1] &&
1416 ir->operation != ir_binop_interpolate_at_offset &&
1417 ir->operation != ir_binop_interpolate_at_sample) {
1418 st_src_reg *swz_op = NULL;
1419 if (vector_elements > ir->operands[1]->type->vector_elements) {
1420 assert(ir->operands[1]->type->vector_elements == 1);
1421 swz_op = &op[1];
1422 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1423 assert(ir->operands[0]->type->vector_elements == 1);
1424 swz_op = &op[0];
1425 }
1426 if (swz_op) {
1427 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1428 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1429 swizzle_x, swizzle_x);
1430 }
1431 vector_elements = MAX2(vector_elements,
1432 ir->operands[1]->type->vector_elements);
1433 }
1434 if (ir->operands[2] &&
1435 ir->operands[2]->type->vector_elements != vector_elements) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir->operands[2]->type->vector_elements == 1);
1438 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1439 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1440 swizzle_x, swizzle_x);
1441 }
1442
1443 this->result.file = PROGRAM_UNDEFINED;
1444
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1447 */
1448 result_src = get_temp(ir->type);
1449 /* convenience for the emit functions below. */
1450 result_dst = st_dst_reg(result_src);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1453 * sequences.
1454 */
1455 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1456
1457 switch (ir->operation) {
1458 case ir_unop_logic_not:
1459 if (result_dst.type != GLSL_TYPE_FLOAT)
1460 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1461 else {
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1466 */
1467 op[0].negate = ~op[0].negate;
1468 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1469 st_src_reg_for_float(1.0));
1470 }
1471 break;
1472 case ir_unop_neg:
1473 if (result_dst.type == GLSL_TYPE_INT64 ||
1474 result_dst.type == GLSL_TYPE_UINT64)
1475 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1476 else if (result_dst.type == GLSL_TYPE_INT ||
1477 result_dst.type == GLSL_TYPE_UINT)
1478 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1479 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1480 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1481 else {
1482 op[0].negate = ~op[0].negate;
1483 result_src = op[0];
1484 }
1485 break;
1486 case ir_unop_subroutine_to_int:
1487 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1488 break;
1489 case ir_unop_abs:
1490 if (result_dst.type == GLSL_TYPE_FLOAT)
1491 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1492 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1493 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1494 else if (result_dst.type == GLSL_TYPE_INT64 ||
1495 result_dst.type == GLSL_TYPE_UINT64)
1496 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1497 else
1498 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1499 break;
1500 case ir_unop_sign:
1501 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1502 break;
1503 case ir_unop_rcp:
1504 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1505 break;
1506
1507 case ir_unop_exp2:
1508 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1509 break;
1510 case ir_unop_exp:
1511 assert(!"not reached: should be handled by exp_to_exp2");
1512 break;
1513 case ir_unop_log:
1514 assert(!"not reached: should be handled by log_to_log2");
1515 break;
1516 case ir_unop_log2:
1517 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1518 break;
1519 case ir_unop_sin:
1520 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1521 break;
1522 case ir_unop_cos:
1523 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1524 break;
1525 case ir_unop_saturate: {
1526 glsl_to_tgsi_instruction *inst;
1527 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1528 inst->saturate = true;
1529 break;
1530 }
1531
1532 case ir_unop_dFdx:
1533 case ir_unop_dFdx_coarse:
1534 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1535 break;
1536 case ir_unop_dFdx_fine:
1537 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1538 break;
1539 case ir_unop_dFdy:
1540 case ir_unop_dFdy_coarse:
1541 case ir_unop_dFdy_fine:
1542 {
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1546 */
1547 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1548 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1549
1550 unsigned transform_y_index =
1551 _mesa_add_state_reference(this->prog->Parameters,
1552 transform_y_state);
1553
1554 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1555 transform_y_index,
1556 glsl_type::vec4_type);
1557 transform_y.swizzle = SWIZZLE_XXXX;
1558
1559 st_src_reg temp = get_temp(glsl_type::vec4_type);
1560
1561 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1562 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1563 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1564 break;
1565 }
1566
1567 case ir_unop_frexp_sig:
1568 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1569 break;
1570
1571 case ir_unop_frexp_exp:
1572 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1573 break;
1574
1575 case ir_binop_add:
1576 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1577 break;
1578 case ir_binop_sub:
1579 op[1].negate = ~op[1].negate;
1580 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1581 break;
1582
1583 case ir_binop_mul:
1584 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1585 break;
1586 case ir_binop_div:
1587 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1588 break;
1589 case ir_binop_mod:
1590 if (result_dst.type == GLSL_TYPE_FLOAT)
1591 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1592 else
1593 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1594 break;
1595
1596 case ir_binop_less:
1597 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1598 break;
1599 case ir_binop_gequal:
1600 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1601 break;
1602 case ir_binop_equal:
1603 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1604 break;
1605 case ir_binop_nequal:
1606 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1607 break;
1608 case ir_binop_all_equal:
1609 /* "==" operator producing a scalar boolean. */
1610 if (ir->operands[0]->type->is_vector() ||
1611 ir->operands[1]->type->is_vector()) {
1612 st_src_reg temp = get_temp(native_integers ?
1613 glsl_type::uvec4_type :
1614 glsl_type::vec4_type);
1615
1616 if (native_integers) {
1617 st_dst_reg temp_dst = st_dst_reg(temp);
1618 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1619
1620 if (ir->operands[0]->type->is_boolean() &&
1621 ir->operands[1]->as_constant() &&
1622 ir->operands[1]->as_constant()->is_one()) {
1623 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1624 } else {
1625 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1626 }
1627
1628 /* Emit 1-3 AND operations to combine the SEQ results. */
1629 switch (ir->operands[0]->type->vector_elements) {
1630 case 2:
1631 break;
1632 case 3:
1633 temp_dst.writemask = WRITEMASK_Y;
1634 temp1.swizzle = SWIZZLE_YYYY;
1635 temp2.swizzle = SWIZZLE_ZZZZ;
1636 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1637 break;
1638 case 4:
1639 temp_dst.writemask = WRITEMASK_X;
1640 temp1.swizzle = SWIZZLE_XXXX;
1641 temp2.swizzle = SWIZZLE_YYYY;
1642 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1643 temp_dst.writemask = WRITEMASK_Y;
1644 temp1.swizzle = SWIZZLE_ZZZZ;
1645 temp2.swizzle = SWIZZLE_WWWW;
1646 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1647 }
1648
1649 temp1.swizzle = SWIZZLE_XXXX;
1650 temp2.swizzle = SWIZZLE_YYYY;
1651 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1652 } else {
1653 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1654
1655 /* After the dot-product, the value will be an integer on the
1656 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1657 */
1658 emit_dp(ir, result_dst, temp, temp, vector_elements);
1659
1660 /* Negating the result of the dot-product gives values on the range
1661 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1662 * This is achieved using SGE.
1663 */
1664 st_src_reg sge_src = result_src;
1665 sge_src.negate = ~sge_src.negate;
1666 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1667 st_src_reg_for_float(0.0));
1668 }
1669 } else {
1670 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1671 }
1672 break;
1673 case ir_binop_any_nequal:
1674 /* "!=" operator producing a scalar boolean. */
1675 if (ir->operands[0]->type->is_vector() ||
1676 ir->operands[1]->type->is_vector()) {
1677 st_src_reg temp = get_temp(native_integers ?
1678 glsl_type::uvec4_type :
1679 glsl_type::vec4_type);
1680 if (ir->operands[0]->type->is_boolean() &&
1681 ir->operands[1]->as_constant() &&
1682 ir->operands[1]->as_constant()->is_zero()) {
1683 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1684 } else {
1685 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1686 }
1687
1688 if (native_integers) {
1689 st_dst_reg temp_dst = st_dst_reg(temp);
1690 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1691
1692 /* Emit 1-3 OR operations to combine the SNE results. */
1693 switch (ir->operands[0]->type->vector_elements) {
1694 case 2:
1695 break;
1696 case 3:
1697 temp_dst.writemask = WRITEMASK_Y;
1698 temp1.swizzle = SWIZZLE_YYYY;
1699 temp2.swizzle = SWIZZLE_ZZZZ;
1700 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1701 break;
1702 case 4:
1703 temp_dst.writemask = WRITEMASK_X;
1704 temp1.swizzle = SWIZZLE_XXXX;
1705 temp2.swizzle = SWIZZLE_YYYY;
1706 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1707 temp_dst.writemask = WRITEMASK_Y;
1708 temp1.swizzle = SWIZZLE_ZZZZ;
1709 temp2.swizzle = SWIZZLE_WWWW;
1710 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1711 }
1712
1713 temp1.swizzle = SWIZZLE_XXXX;
1714 temp2.swizzle = SWIZZLE_YYYY;
1715 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1716 } else {
1717 /* After the dot-product, the value will be an integer on the
1718 * range [0,4]. Zero stays zero, and positive values become 1.0.
1719 */
1720 glsl_to_tgsi_instruction *const dp =
1721 emit_dp(ir, result_dst, temp, temp, vector_elements);
1722 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1723 /* The clamping to [0,1] can be done for free in the fragment
1724 * shader with a saturate.
1725 */
1726 dp->saturate = true;
1727 } else {
1728 /* Negating the result of the dot-product gives values on the
1729 * range [-4, 0]. Zero stays zero, and negative values become
1730 * 1.0. This achieved using SLT.
1731 */
1732 st_src_reg slt_src = result_src;
1733 slt_src.negate = ~slt_src.negate;
1734 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1735 st_src_reg_for_float(0.0));
1736 }
1737 }
1738 } else {
1739 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1740 }
1741 break;
1742
1743 case ir_binop_logic_xor:
1744 if (native_integers)
1745 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1746 else
1747 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1748 break;
1749
1750 case ir_binop_logic_or: {
1751 if (native_integers) {
1752 /* If integers are used as booleans, we can use an actual "or"
1753 * instruction.
1754 */
1755 assert(native_integers);
1756 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1757 } else {
1758 /* After the addition, the value will be an integer on the
1759 * range [0,2]. Zero stays zero, and positive values become 1.0.
1760 */
1761 glsl_to_tgsi_instruction *add =
1762 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1763 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1764 /* The clamping to [0,1] can be done for free in the fragment
1765 * shader with a saturate if floats are being used as boolean
1766 * values.
1767 */
1768 add->saturate = true;
1769 } else {
1770 /* Negating the result of the addition gives values on the range
1771 * [-2, 0]. Zero stays zero, and negative values become 1.0
1772 * This is achieved using SLT.
1773 */
1774 st_src_reg slt_src = result_src;
1775 slt_src.negate = ~slt_src.negate;
1776 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1777 st_src_reg_for_float(0.0));
1778 }
1779 }
1780 break;
1781 }
1782
1783 case ir_binop_logic_and:
1784 /* If native integers are disabled, the bool args are stored as float 0.0
1785 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1786 * actual AND opcode.
1787 */
1788 if (native_integers)
1789 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1790 else
1791 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1792 break;
1793
1794 case ir_binop_dot:
1795 assert(ir->operands[0]->type->is_vector());
1796 assert(ir->operands[0]->type == ir->operands[1]->type);
1797 emit_dp(ir, result_dst, op[0], op[1],
1798 ir->operands[0]->type->vector_elements);
1799 break;
1800
1801 case ir_unop_sqrt:
1802 if (have_sqrt) {
1803 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1804 } else {
1805 /* This is the only instruction sequence that makes the game "Risen"
1806 * render correctly. ABS is not required for the game, but since GLSL
1807 * declares negative values as "undefined", allowing us to do whatever
1808 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1809 * behavior.
1810 */
1811 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1812 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1813 }
1814 break;
1815 case ir_unop_rsq:
1816 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1817 break;
1818 case ir_unop_i2f:
1819 if (native_integers) {
1820 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1821 break;
1822 }
1823 /* fallthrough to next case otherwise */
1824 case ir_unop_b2f:
1825 if (native_integers) {
1826 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1827 st_src_reg_for_float(1.0));
1828 break;
1829 }
1830 /* fallthrough to next case otherwise */
1831 case ir_unop_i2u:
1832 case ir_unop_u2i:
1833 case ir_unop_i642u64:
1834 case ir_unop_u642i64:
1835 /* Converting between signed and unsigned integers is a no-op. */
1836 result_src = op[0];
1837 result_src.type = result_dst.type;
1838 break;
1839 case ir_unop_b2i:
1840 if (native_integers) {
1841 /* Booleans are stored as integers using ~0 for true and 0 for false.
1842 * GLSL requires that int(bool) return 1 for true and 0 for false.
1843 * This conversion is done with AND, but it could be done with NEG.
1844 */
1845 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1846 st_src_reg_for_int(1));
1847 } else {
1848 /* Booleans and integers are both stored as floats when native
1849 * integers are disabled.
1850 */
1851 result_src = op[0];
1852 }
1853 break;
1854 case ir_unop_f2i:
1855 if (native_integers)
1856 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1857 else
1858 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1859 break;
1860 case ir_unop_f2u:
1861 if (native_integers)
1862 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1863 else
1864 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1865 break;
1866 case ir_unop_bitcast_f2i:
1867 case ir_unop_bitcast_f2u:
1868 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1869 if (op[0].negate || op[0].abs)
1870 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1871 else
1872 result_src = op[0];
1873 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1874 GLSL_TYPE_UINT;
1875 break;
1876 case ir_unop_bitcast_i2f:
1877 case ir_unop_bitcast_u2f:
1878 result_src = op[0];
1879 result_src.type = GLSL_TYPE_FLOAT;
1880 break;
1881 case ir_unop_f2b:
1882 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1883 st_src_reg_for_float(0.0));
1884 break;
1885 case ir_unop_d2b:
1886 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1887 st_src_reg_for_double(0.0));
1888 break;
1889 case ir_unop_i2b:
1890 if (native_integers)
1891 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1892 st_src_reg_for_int(0));
1893 else
1894 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1895 st_src_reg_for_float(0.0));
1896 break;
1897 case ir_unop_bitcast_u642d:
1898 case ir_unop_bitcast_i642d:
1899 result_src = op[0];
1900 result_src.type = GLSL_TYPE_DOUBLE;
1901 break;
1902 case ir_unop_bitcast_d2i64:
1903 result_src = op[0];
1904 result_src.type = GLSL_TYPE_INT64;
1905 break;
1906 case ir_unop_bitcast_d2u64:
1907 result_src = op[0];
1908 result_src.type = GLSL_TYPE_UINT64;
1909 break;
1910 case ir_unop_trunc:
1911 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1912 break;
1913 case ir_unop_ceil:
1914 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1915 break;
1916 case ir_unop_floor:
1917 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1918 break;
1919 case ir_unop_round_even:
1920 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1921 break;
1922 case ir_unop_fract:
1923 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1924 break;
1925
1926 case ir_binop_min:
1927 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1928 break;
1929 case ir_binop_max:
1930 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1931 break;
1932 case ir_binop_pow:
1933 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1934 break;
1935
1936 case ir_unop_bit_not:
1937 if (native_integers) {
1938 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1939 break;
1940 }
1941 /* fallthrough */
1942 case ir_unop_u2f:
1943 if (native_integers) {
1944 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1945 break;
1946 }
1947 /* fallthrough */
1948 case ir_binop_lshift:
1949 case ir_binop_rshift:
1950 if (native_integers) {
1951 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1952 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1953 st_src_reg count;
1954
1955 if (glsl_base_type_is_64bit(op[0].type)) {
1956 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1957 * 64 bits.
1958 */
1959 count = get_temp(glsl_type::u64vec(ir->operands[1]
1960 ->type->components()));
1961 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1962 } else {
1963 count = op[1];
1964 }
1965
1966 emit_asm(ir, opcode, result_dst, op[0], count);
1967 break;
1968 }
1969 /* fallthrough */
1970 case ir_binop_bit_and:
1971 if (native_integers) {
1972 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1973 break;
1974 }
1975 /* fallthrough */
1976 case ir_binop_bit_xor:
1977 if (native_integers) {
1978 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1979 break;
1980 }
1981 /* fallthrough */
1982 case ir_binop_bit_or:
1983 if (native_integers) {
1984 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1985 break;
1986 }
1987
1988 assert(!"GLSL 1.30 features unsupported");
1989 break;
1990
1991 case ir_binop_ubo_load: {
1992 if (ctx->Const.UseSTD430AsDefaultPacking) {
1993 ir_rvalue *block = ir->operands[0];
1994 ir_rvalue *offset = ir->operands[1];
1995 ir_constant *const_block = block->as_constant();
1996
1997 st_src_reg cbuf(PROGRAM_CONSTANT,
1998 (const_block ? const_block->value.u[0] + 1 : 1),
1999 ir->type->base_type);
2000
2001 cbuf.has_index2 = true;
2002
2003 if (!const_block) {
2004 block->accept(this);
2005 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2006 *cbuf.reladdr = this->result;
2007 emit_arl(ir, sampler_reladdr, this->result);
2008 }
2009
2010 /* Calculate the surface offset */
2011 offset->accept(this);
2012 st_src_reg off = this->result;
2013
2014 glsl_to_tgsi_instruction *inst =
2015 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2016
2017 if (result_dst.type == GLSL_TYPE_BOOL)
2018 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2019 st_src_reg_for_int(0));
2020
2021 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2022 NULL);
2023 } else {
2024 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2025 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2026 unsigned const_offset = const_offset_ir ?
2027 const_offset_ir->value.u[0] : 0;
2028 unsigned const_block = const_uniform_block ?
2029 const_uniform_block->value.u[0] + 1 : 1;
2030 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2031 st_src_reg cbuf;
2032
2033 cbuf.type = ir->type->base_type;
2034 cbuf.file = PROGRAM_CONSTANT;
2035 cbuf.index = 0;
2036 cbuf.reladdr = NULL;
2037 cbuf.negate = 0;
2038 cbuf.abs = 0;
2039 cbuf.index2D = const_block;
2040
2041 assert(ir->type->is_vector() || ir->type->is_scalar());
2042
2043 if (const_offset_ir) {
2044 /* Constant index into constant buffer */
2045 cbuf.reladdr = NULL;
2046 cbuf.index = const_offset / 16;
2047 } else {
2048 ir_expression *offset_expr = ir->operands[1]->as_expression();
2049 st_src_reg offset = op[1];
2050
2051 /* The OpenGL spec is written in such a way that accesses with
2052 * non-constant offset are almost always vec4-aligned. The only
2053 * exception to this are members of structs in arrays of structs:
2054 * each struct in an array of structs is at least vec4-aligned,
2055 * but single-element and [ui]vec2 members of the struct may be at
2056 * an offset that is not a multiple of 16 bytes.
2057 *
2058 * Here, we extract that offset, relying on previous passes to
2059 * always generate offset expressions of the form
2060 * (+ expr constant_offset).
2061 *
2062 * Note that the std430 layout, which allows more cases of
2063 * alignment less than vec4 in arrays, is not supported for
2064 * uniform blocks, so we do not have to deal with it here.
2065 */
2066 if (offset_expr && offset_expr->operation == ir_binop_add) {
2067 const_offset_ir = offset_expr->operands[1]->as_constant();
2068 if (const_offset_ir) {
2069 const_offset = const_offset_ir->value.u[0];
2070 cbuf.index = const_offset / 16;
2071 offset_expr->operands[0]->accept(this);
2072 offset = this->result;
2073 }
2074 }
2075
2076 /* Relative/variable index into constant buffer */
2077 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2078 st_src_reg_for_int(4));
2079 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2080 *cbuf.reladdr = index_reg;
2081 }
2082
2083 if (const_uniform_block) {
2084 /* Constant constant buffer */
2085 cbuf.reladdr2 = NULL;
2086 } else {
2087 /* Relative/variable constant buffer */
2088 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2089 *cbuf.reladdr2 = op[0];
2090 }
2091 cbuf.has_index2 = true;
2092
2093 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2094 if (glsl_base_type_is_64bit(cbuf.type))
2095 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2096 const_offset % 16 / 8,
2097 const_offset % 16 / 8,
2098 const_offset % 16 / 8);
2099 else
2100 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2101 const_offset % 16 / 4,
2102 const_offset % 16 / 4,
2103 const_offset % 16 / 4);
2104
2105 if (ir->type->is_boolean()) {
2106 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2107 st_src_reg_for_int(0));
2108 } else {
2109 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2110 }
2111 }
2112 break;
2113 }
2114 case ir_triop_lrp:
2115 /* note: we have to reorder the three args here */
2116 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2117 break;
2118 case ir_triop_csel:
2119 if (this->ctx->Const.NativeIntegers)
2120 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2121 else {
2122 op[0].negate = ~op[0].negate;
2123 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2124 }
2125 break;
2126 case ir_triop_bitfield_extract:
2127 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2128 break;
2129 case ir_quadop_bitfield_insert:
2130 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2131 break;
2132 case ir_unop_bitfield_reverse:
2133 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2134 break;
2135 case ir_unop_bit_count:
2136 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2137 break;
2138 case ir_unop_find_msb:
2139 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2140 break;
2141 case ir_unop_find_lsb:
2142 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2143 break;
2144 case ir_binop_imul_high:
2145 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2146 break;
2147 case ir_triop_fma:
2148 /* In theory, MAD is incorrect here. */
2149 if (have_fma)
2150 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2151 else
2152 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2153 break;
2154 case ir_unop_interpolate_at_centroid:
2155 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2156 break;
2157 case ir_binop_interpolate_at_offset: {
2158 /* The y coordinate needs to be flipped for the default fb */
2159 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2160 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2161
2162 unsigned transform_y_index =
2163 _mesa_add_state_reference(this->prog->Parameters,
2164 transform_y_state);
2165
2166 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2167 transform_y_index,
2168 glsl_type::vec4_type);
2169 transform_y.swizzle = SWIZZLE_XXXX;
2170
2171 st_src_reg temp = get_temp(glsl_type::vec2_type);
2172 st_dst_reg temp_dst = st_dst_reg(temp);
2173
2174 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2175 temp_dst.writemask = WRITEMASK_Y;
2176 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2177 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2178 break;
2179 }
2180 case ir_binop_interpolate_at_sample:
2181 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2182 break;
2183
2184 case ir_unop_d2f:
2185 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2186 break;
2187 case ir_unop_f2d:
2188 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2189 break;
2190 case ir_unop_d2i:
2191 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2192 break;
2193 case ir_unop_i2d:
2194 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2195 break;
2196 case ir_unop_d2u:
2197 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2198 break;
2199 case ir_unop_u2d:
2200 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2201 break;
2202 case ir_unop_unpack_double_2x32:
2203 case ir_unop_pack_double_2x32:
2204 case ir_unop_unpack_int_2x32:
2205 case ir_unop_pack_int_2x32:
2206 case ir_unop_unpack_uint_2x32:
2207 case ir_unop_pack_uint_2x32:
2208 case ir_unop_unpack_sampler_2x32:
2209 case ir_unop_pack_sampler_2x32:
2210 case ir_unop_unpack_image_2x32:
2211 case ir_unop_pack_image_2x32:
2212 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2213 break;
2214
2215 case ir_binop_ldexp:
2216 if (ir->operands[0]->type->is_double()) {
2217 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2218 } else if (ir->operands[0]->type->is_float()) {
2219 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2220 } else {
2221 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2222 }
2223 break;
2224
2225 case ir_unop_pack_half_2x16:
2226 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2227 break;
2228 case ir_unop_unpack_half_2x16:
2229 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2230 break;
2231
2232 case ir_unop_get_buffer_size: {
2233 ir_constant *const_offset = ir->operands[0]->as_constant();
2234 st_src_reg buffer(
2235 PROGRAM_BUFFER,
2236 const_offset ? const_offset->value.u[0] : 0,
2237 GLSL_TYPE_UINT);
2238 if (!const_offset) {
2239 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2240 *buffer.reladdr = op[0];
2241 emit_arl(ir, sampler_reladdr, op[0]);
2242 }
2243 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2244 break;
2245 }
2246
2247 case ir_unop_u2i64:
2248 case ir_unop_u2u64:
2249 case ir_unop_b2i64: {
2250 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2251 st_dst_reg temp_dst = st_dst_reg(temp);
2252 unsigned orig_swz = op[0].swizzle;
2253 /*
2254 * To convert unsigned to 64-bit:
2255 * zero Y channel, copy X channel.
2256 */
2257 temp_dst.writemask = WRITEMASK_Y;
2258 if (vector_elements > 1)
2259 temp_dst.writemask |= WRITEMASK_W;
2260 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2261 temp_dst.writemask = WRITEMASK_X;
2262 if (vector_elements > 1)
2263 temp_dst.writemask |= WRITEMASK_Z;
2264 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2265 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2266 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2267 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2268 else
2269 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2270 result_src = temp;
2271 result_src.type = GLSL_TYPE_UINT64;
2272 if (vector_elements > 2) {
2273 /* Subtle: We rely on the fact that get_temp here returns the next
2274 * TGSI temporary register directly after the temp register used for
2275 * the first two components, so that the result gets picked up
2276 * automatically.
2277 */
2278 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2279 st_dst_reg temp_dst = st_dst_reg(temp);
2280 temp_dst.writemask = WRITEMASK_Y;
2281 if (vector_elements > 3)
2282 temp_dst.writemask |= WRITEMASK_W;
2283 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2284
2285 temp_dst.writemask = WRITEMASK_X;
2286 if (vector_elements > 3)
2287 temp_dst.writemask |= WRITEMASK_Z;
2288 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2289 GET_SWZ(orig_swz, 2),
2290 GET_SWZ(orig_swz, 3),
2291 GET_SWZ(orig_swz, 3));
2292 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2293 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2294 else
2295 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2296 st_src_reg_for_int(1));
2297 }
2298 break;
2299 }
2300 case ir_unop_i642i:
2301 case ir_unop_u642i:
2302 case ir_unop_u642u:
2303 case ir_unop_i642u: {
2304 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2305 st_dst_reg temp_dst = st_dst_reg(temp);
2306 unsigned orig_swz = op[0].swizzle;
2307 unsigned orig_idx = op[0].index;
2308 int el;
2309 temp_dst.writemask = WRITEMASK_X;
2310
2311 for (el = 0; el < vector_elements; el++) {
2312 unsigned swz = GET_SWZ(orig_swz, el);
2313 if (swz & 1)
2314 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2315 SWIZZLE_Z, SWIZZLE_Z);
2316 else
2317 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2318 SWIZZLE_X, SWIZZLE_X);
2319 if (swz > 2)
2320 op[0].index = orig_idx + 1;
2321 op[0].type = GLSL_TYPE_UINT;
2322 temp_dst.writemask = WRITEMASK_X << el;
2323 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2324 }
2325 result_src = temp;
2326 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2327 result_src.type = GLSL_TYPE_UINT;
2328 else
2329 result_src.type = GLSL_TYPE_INT;
2330 break;
2331 }
2332 case ir_unop_i642b:
2333 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2334 st_src_reg_for_int64(0));
2335 break;
2336 case ir_unop_i642f:
2337 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2338 break;
2339 case ir_unop_u642f:
2340 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2341 break;
2342 case ir_unop_i642d:
2343 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2344 break;
2345 case ir_unop_u642d:
2346 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2347 break;
2348 case ir_unop_i2i64:
2349 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2350 break;
2351 case ir_unop_f2i64:
2352 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2353 break;
2354 case ir_unop_d2i64:
2355 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2356 break;
2357 case ir_unop_i2u64:
2358 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2359 break;
2360 case ir_unop_f2u64:
2361 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2362 break;
2363 case ir_unop_d2u64:
2364 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2365 break;
2366 /* these might be needed */
2367 case ir_unop_pack_snorm_2x16:
2368 case ir_unop_pack_unorm_2x16:
2369 case ir_unop_pack_snorm_4x8:
2370 case ir_unop_pack_unorm_4x8:
2371
2372 case ir_unop_unpack_snorm_2x16:
2373 case ir_unop_unpack_unorm_2x16:
2374 case ir_unop_unpack_snorm_4x8:
2375 case ir_unop_unpack_unorm_4x8:
2376
2377 case ir_quadop_vector:
2378 case ir_binop_vector_extract:
2379 case ir_triop_vector_insert:
2380 case ir_binop_carry:
2381 case ir_binop_borrow:
2382 case ir_unop_ssbo_unsized_array_length:
2383 case ir_unop_atan:
2384 case ir_binop_atan2:
2385 case ir_unop_clz:
2386 case ir_binop_add_sat:
2387 case ir_binop_sub_sat:
2388 case ir_binop_abs_sub:
2389 case ir_binop_avg:
2390 case ir_binop_avg_round:
2391 case ir_binop_mul_32x16:
2392 case ir_unop_f162f:
2393 case ir_unop_f2f16:
2394 case ir_unop_f2fmp:
2395 case ir_unop_f162b:
2396 case ir_unop_b2f16:
2397 /* This operation is not supported, or should have already been handled.
2398 */
2399 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2400 break;
2401 }
2402
2403 this->result = result_src;
2404 }
2405
2406
2407 void
2408 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2409 {
2410 st_src_reg src;
2411 int i;
2412 int swizzle[4] = {0};
2413
2414 /* Note that this is only swizzles in expressions, not those on the left
2415 * hand side of an assignment, which do write masking. See ir_assignment
2416 * for that.
2417 */
2418
2419 ir->val->accept(this);
2420 src = this->result;
2421 assert(src.file != PROGRAM_UNDEFINED);
2422 assert(ir->type->vector_elements > 0);
2423
2424 for (i = 0; i < 4; i++) {
2425 if (i < ir->type->vector_elements) {
2426 switch (i) {
2427 case 0:
2428 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2429 break;
2430 case 1:
2431 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2432 break;
2433 case 2:
2434 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2435 break;
2436 case 3:
2437 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2438 break;
2439 }
2440 } else {
2441 /* If the type is smaller than a vec4, replicate the last
2442 * channel out.
2443 */
2444 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2445 }
2446 }
2447
2448 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2449
2450 this->result = src;
2451 }
2452
2453 /* Test if the variable is an array. Note that geometry and
2454 * tessellation shader inputs are outputs are always arrays (except
2455 * for patch inputs), so only the array element type is considered.
2456 */
2457 static bool
2458 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2459 {
2460 const glsl_type *type = var->type;
2461
2462 *remove_array = false;
2463
2464 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2465 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2466 return false;
2467
2468 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2469 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2470 stage == MESA_SHADER_TESS_CTRL) &&
2471 !var->data.patch) {
2472 if (!var->type->is_array())
2473 return false; /* a system value probably */
2474
2475 type = var->type->fields.array;
2476 *remove_array = true;
2477 }
2478
2479 return type->is_array() || type->is_matrix();
2480 }
2481
2482 static unsigned
2483 st_translate_interp_loc(ir_variable *var)
2484 {
2485 if (var->data.centroid)
2486 return TGSI_INTERPOLATE_LOC_CENTROID;
2487 else if (var->data.sample)
2488 return TGSI_INTERPOLATE_LOC_SAMPLE;
2489 else
2490 return TGSI_INTERPOLATE_LOC_CENTER;
2491 }
2492
2493 void
2494 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2495 {
2496 variable_storage *entry;
2497 ir_variable *var = ir->var;
2498 bool remove_array;
2499
2500 if (handle_bound_deref(ir->as_dereference()))
2501 return;
2502
2503 entry = find_variable_storage(ir->var);
2504
2505 if (!entry) {
2506 switch (var->data.mode) {
2507 case ir_var_uniform:
2508 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2509 var->data.param_index);
2510 _mesa_hash_table_insert(this->variables, var, entry);
2511 break;
2512 case ir_var_shader_in: {
2513 /* The linker assigns locations for varyings and attributes,
2514 * including deprecated builtins (like gl_Color), user-assign
2515 * generic attributes (glBindVertexLocation), and
2516 * user-defined varyings.
2517 */
2518 assert(var->data.location != -1);
2519
2520 const glsl_type *type_without_array = var->type->without_array();
2521 struct inout_decl *decl = &inputs[num_inputs];
2522 unsigned component = var->data.location_frac;
2523 unsigned num_components;
2524 num_inputs++;
2525
2526 if (type_without_array->is_64bit())
2527 component = component / 2;
2528 if (type_without_array->vector_elements)
2529 num_components = type_without_array->vector_elements;
2530 else
2531 num_components = 4;
2532
2533 decl->mesa_index = var->data.location;
2534 decl->interp = (glsl_interp_mode) var->data.interpolation;
2535 decl->interp_loc = st_translate_interp_loc(var);
2536 decl->base_type = type_without_array->base_type;
2537 decl->usage_mask = u_bit_consecutive(component, num_components);
2538
2539 if (is_inout_array(shader->Stage, var, &remove_array)) {
2540 decl->array_id = num_input_arrays + 1;
2541 num_input_arrays++;
2542 } else {
2543 decl->array_id = 0;
2544 }
2545
2546 if (remove_array)
2547 decl->size = type_size(var->type->fields.array);
2548 else
2549 decl->size = type_size(var->type);
2550
2551 entry = new(mem_ctx) variable_storage(var,
2552 PROGRAM_INPUT,
2553 decl->mesa_index,
2554 decl->array_id);
2555 entry->component = component;
2556
2557 _mesa_hash_table_insert(this->variables, var, entry);
2558
2559 break;
2560 }
2561 case ir_var_shader_out: {
2562 assert(var->data.location != -1);
2563
2564 const glsl_type *type_without_array = var->type->without_array();
2565 struct inout_decl *decl = &outputs[num_outputs];
2566 unsigned component = var->data.location_frac;
2567 unsigned num_components;
2568 num_outputs++;
2569
2570 decl->invariant = var->data.invariant;
2571
2572 if (type_without_array->is_64bit())
2573 component = component / 2;
2574 if (type_without_array->vector_elements)
2575 num_components = type_without_array->vector_elements;
2576 else
2577 num_components = 4;
2578
2579 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2580 decl->base_type = type_without_array->base_type;
2581 decl->usage_mask = u_bit_consecutive(component, num_components);
2582 if (var->data.stream & (1u << 31)) {
2583 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2584 } else {
2585 assert(var->data.stream < 4);
2586 decl->gs_out_streams = 0;
2587 for (unsigned i = 0; i < num_components; ++i)
2588 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2589 }
2590
2591 if (is_inout_array(shader->Stage, var, &remove_array)) {
2592 decl->array_id = num_output_arrays + 1;
2593 num_output_arrays++;
2594 } else {
2595 decl->array_id = 0;
2596 }
2597
2598 if (remove_array)
2599 decl->size = type_size(var->type->fields.array);
2600 else
2601 decl->size = type_size(var->type);
2602
2603 if (var->data.fb_fetch_output) {
2604 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2605 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2606 var->type, component, decl->array_id);
2607 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2608 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2609 dst.array_id);
2610 } else {
2611 entry = new(mem_ctx) variable_storage(var,
2612 PROGRAM_OUTPUT,
2613 decl->mesa_index,
2614 decl->array_id);
2615 }
2616 entry->component = component;
2617
2618 _mesa_hash_table_insert(this->variables, var, entry);
2619
2620 break;
2621 }
2622 case ir_var_system_value:
2623 entry = new(mem_ctx) variable_storage(var,
2624 PROGRAM_SYSTEM_VALUE,
2625 var->data.location);
2626 break;
2627 case ir_var_auto:
2628 case ir_var_temporary:
2629 st_src_reg src = get_temp(var->type);
2630
2631 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2632 src.array_id);
2633 _mesa_hash_table_insert(this->variables, var, entry);
2634
2635 break;
2636 }
2637
2638 if (!entry) {
2639 printf("Failed to make storage for %s\n", var->name);
2640 exit(1);
2641 }
2642 }
2643
2644 this->result = st_src_reg(entry->file, entry->index, var->type,
2645 entry->component, entry->array_id);
2646 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2647 var->data.mode == ir_var_shader_in &&
2648 var->type->without_array()->is_double())
2649 this->result.is_double_vertex_input = true;
2650 if (!native_integers)
2651 this->result.type = GLSL_TYPE_FLOAT;
2652 }
2653
2654 static void
2655 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2656 GLbitfield64* usage_mask,
2657 GLbitfield64 double_usage_mask,
2658 GLbitfield* patch_usage_mask)
2659 {
2660 unsigned i;
2661 int j;
2662
2663 /* Fix array declarations by removing unused array elements at both ends
2664 * of the arrays. For example, mat4[3] where only mat[1] is used.
2665 */
2666 for (i = 0; i < count; i++) {
2667 struct inout_decl *decl = &decls[i];
2668 if (!decl->array_id)
2669 continue;
2670
2671 /* Shrink the beginning. */
2672 for (j = 0; j < (int)decl->size; j++) {
2673 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2674 if (*patch_usage_mask &
2675 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2676 break;
2677 }
2678 else {
2679 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2680 break;
2681 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2682 break;
2683 }
2684
2685 decl->mesa_index++;
2686 decl->size--;
2687 j--;
2688 }
2689
2690 /* Shrink the end. */
2691 for (j = decl->size-1; j >= 0; j--) {
2692 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2693 if (*patch_usage_mask &
2694 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2695 break;
2696 }
2697 else {
2698 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2699 break;
2700 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2701 break;
2702 }
2703
2704 decl->size--;
2705 }
2706
2707 /* When not all entries of an array are accessed, we mark them as used
2708 * here anyway, to ensure that the input/output mapping logic doesn't get
2709 * confused.
2710 *
2711 * TODO This happens when an array isn't used via indirect access, which
2712 * some game ports do (at least eON-based). There is an optimization
2713 * opportunity here by replacing the array declaration with non-array
2714 * declarations of those slots that are actually used.
2715 */
2716 for (j = 1; j < (int)decl->size; ++j) {
2717 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2718 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2719 else
2720 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2721 }
2722 }
2723 }
2724
2725
2726 static void
2727 mark_array_io(struct inout_decl *decls, unsigned count,
2728 GLbitfield64* usage_mask,
2729 GLbitfield64 double_usage_mask,
2730 GLbitfield* patch_usage_mask)
2731 {
2732 unsigned i;
2733 int j;
2734
2735 /* Fix array declarations by removing unused array elements at both ends
2736 * of the arrays. For example, mat4[3] where only mat[1] is used.
2737 */
2738 for (i = 0; i < count; i++) {
2739 struct inout_decl *decl = &decls[i];
2740 if (!decl->array_id)
2741 continue;
2742
2743 /* When not all entries of an array are accessed, we mark them as used
2744 * here anyway, to ensure that the input/output mapping logic doesn't get
2745 * confused.
2746 *
2747 * TODO This happens when an array isn't used via indirect access, which
2748 * some game ports do (at least eON-based). There is an optimization
2749 * opportunity here by replacing the array declaration with non-array
2750 * declarations of those slots that are actually used.
2751 */
2752 for (j = 0; j < (int)decl->size; ++j) {
2753 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2754 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2755 else
2756 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2757 }
2758 }
2759 }
2760
2761 void
2762 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2763 {
2764 ir_constant *index;
2765 st_src_reg src;
2766 bool is_2D = false;
2767 ir_variable *var = ir->variable_referenced();
2768
2769 if (handle_bound_deref(ir->as_dereference()))
2770 return;
2771
2772 /* We only need the logic provided by count_vec4_slots()
2773 * for arrays of structs. Indirect sampler and image indexing is handled
2774 * elsewhere.
2775 */
2776 int element_size = ir->type->without_array()->is_struct() ?
2777 ir->type->count_vec4_slots(false, var->data.bindless) :
2778 type_size(ir->type);
2779
2780 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2781
2782 ir->array->accept(this);
2783 src = this->result;
2784
2785 if (!src.has_index2) {
2786 switch (this->prog->Target) {
2787 case GL_TESS_CONTROL_PROGRAM_NV:
2788 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2789 !ir->variable_referenced()->data.patch;
2790 break;
2791 case GL_TESS_EVALUATION_PROGRAM_NV:
2792 is_2D = src.file == PROGRAM_INPUT &&
2793 !ir->variable_referenced()->data.patch;
2794 break;
2795 case GL_GEOMETRY_PROGRAM_NV:
2796 is_2D = src.file == PROGRAM_INPUT;
2797 break;
2798 }
2799 }
2800
2801 if (is_2D)
2802 element_size = 1;
2803
2804 if (index) {
2805
2806 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2807 src.file == PROGRAM_INPUT)
2808 element_size = attrib_type_size(ir->type, true);
2809 if (is_2D) {
2810 src.index2D = index->value.i[0];
2811 src.has_index2 = true;
2812 } else
2813 src.index += index->value.i[0] * element_size;
2814 } else {
2815 /* Variable index array dereference. It eats the "vec4" of the
2816 * base of the array and an index that offsets the TGSI register
2817 * index.
2818 */
2819 ir->array_index->accept(this);
2820
2821 st_src_reg index_reg;
2822
2823 if (element_size == 1) {
2824 index_reg = this->result;
2825 } else {
2826 index_reg = get_temp(native_integers ?
2827 glsl_type::int_type : glsl_type::float_type);
2828
2829 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2830 this->result, st_src_reg_for_type(index_reg.type, element_size));
2831 }
2832
2833 /* If there was already a relative address register involved, add the
2834 * new and the old together to get the new offset.
2835 */
2836 if (!is_2D && src.reladdr != NULL) {
2837 st_src_reg accum_reg = get_temp(native_integers ?
2838 glsl_type::int_type : glsl_type::float_type);
2839
2840 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2841 index_reg, *src.reladdr);
2842
2843 index_reg = accum_reg;
2844 }
2845
2846 if (is_2D) {
2847 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2848 *src.reladdr2 = index_reg;
2849 src.index2D = 0;
2850 src.has_index2 = true;
2851 } else {
2852 src.reladdr = ralloc(mem_ctx, st_src_reg);
2853 *src.reladdr = index_reg;
2854 }
2855 }
2856
2857 /* Change the register type to the element type of the array. */
2858 src.type = ir->type->base_type;
2859
2860 this->result = src;
2861 }
2862
2863 void
2864 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2865 {
2866 unsigned int i;
2867 const glsl_type *struct_type = ir->record->type;
2868 ir_variable *var = ir->record->variable_referenced();
2869 int offset = 0;
2870
2871 if (handle_bound_deref(ir->as_dereference()))
2872 return;
2873
2874 ir->record->accept(this);
2875
2876 assert(ir->field_idx >= 0);
2877 assert(var);
2878 for (i = 0; i < struct_type->length; i++) {
2879 if (i == (unsigned) ir->field_idx)
2880 break;
2881 const glsl_type *member_type = struct_type->fields.structure[i].type;
2882 offset += member_type->count_vec4_slots(false, var->data.bindless);
2883 }
2884
2885 /* If the type is smaller than a vec4, replicate the last channel out. */
2886 if (ir->type->is_scalar() || ir->type->is_vector())
2887 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2888 else
2889 this->result.swizzle = SWIZZLE_NOOP;
2890
2891 this->result.index += offset;
2892 this->result.type = ir->type->base_type;
2893 }
2894
2895 /**
2896 * We want to be careful in assignment setup to hit the actual storage
2897 * instead of potentially using a temporary like we might with the
2898 * ir_dereference handler.
2899 */
2900 static st_dst_reg
2901 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2902 {
2903 /* The LHS must be a dereference. If the LHS is a variable indexed array
2904 * access of a vector, it must be separated into a series conditional moves
2905 * before reaching this point (see ir_vec_index_to_cond_assign).
2906 */
2907 assert(ir->as_dereference());
2908 ir_dereference_array *deref_array = ir->as_dereference_array();
2909 if (deref_array) {
2910 assert(!deref_array->array->type->is_vector());
2911 }
2912
2913 /* Use the rvalue deref handler for the most part. We write swizzles using
2914 * the writemask, but we do extract the base component for enhanced layouts
2915 * from the source swizzle.
2916 */
2917 ir->accept(v);
2918 *component = GET_SWZ(v->result.swizzle, 0);
2919 return st_dst_reg(v->result);
2920 }
2921
2922 /**
2923 * Process the condition of a conditional assignment
2924 *
2925 * Examines the condition of a conditional assignment to generate the optimal
2926 * first operand of a \c CMP instruction. If the condition is a relational
2927 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2928 * used as the source for the \c CMP instruction. Otherwise the comparison
2929 * is processed to a boolean result, and the boolean result is used as the
2930 * operand to the CMP instruction.
2931 */
2932 bool
2933 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2934 {
2935 ir_rvalue *src_ir = ir;
2936 bool negate = true;
2937 bool switch_order = false;
2938
2939 ir_expression *const expr = ir->as_expression();
2940
2941 if (native_integers) {
2942 if ((expr != NULL) && (expr->num_operands == 2)) {
2943 enum glsl_base_type type = expr->operands[0]->type->base_type;
2944 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2945 type == GLSL_TYPE_BOOL) {
2946 if (expr->operation == ir_binop_equal) {
2947 if (expr->operands[0]->is_zero()) {
2948 src_ir = expr->operands[1];
2949 switch_order = true;
2950 }
2951 else if (expr->operands[1]->is_zero()) {
2952 src_ir = expr->operands[0];
2953 switch_order = true;
2954 }
2955 }
2956 else if (expr->operation == ir_binop_nequal) {
2957 if (expr->operands[0]->is_zero()) {
2958 src_ir = expr->operands[1];
2959 }
2960 else if (expr->operands[1]->is_zero()) {
2961 src_ir = expr->operands[0];
2962 }
2963 }
2964 }
2965 }
2966
2967 src_ir->accept(this);
2968 return switch_order;
2969 }
2970
2971 if ((expr != NULL) && (expr->num_operands == 2)) {
2972 bool zero_on_left = false;
2973
2974 if (expr->operands[0]->is_zero()) {
2975 src_ir = expr->operands[1];
2976 zero_on_left = true;
2977 } else if (expr->operands[1]->is_zero()) {
2978 src_ir = expr->operands[0];
2979 zero_on_left = false;
2980 }
2981
2982 /* a is - 0 + - 0 +
2983 * (a < 0) T F F ( a < 0) T F F
2984 * (0 < a) F F T (-a < 0) F F T
2985 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2986 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2987 *
2988 * Note that exchanging the order of 0 and 'a' in the comparison simply
2989 * means that the value of 'a' should be negated.
2990 */
2991 if (src_ir != ir) {
2992 switch (expr->operation) {
2993 case ir_binop_less:
2994 switch_order = false;
2995 negate = zero_on_left;
2996 break;
2997
2998 case ir_binop_gequal:
2999 switch_order = true;
3000 negate = zero_on_left;
3001 break;
3002
3003 default:
3004 /* This isn't the right kind of comparison afterall, so make sure
3005 * the whole condition is visited.
3006 */
3007 src_ir = ir;
3008 break;
3009 }
3010 }
3011 }
3012
3013 src_ir->accept(this);
3014
3015 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3016 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3017 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3018 * computing the condition.
3019 */
3020 if (negate)
3021 this->result.negate = ~this->result.negate;
3022
3023 return switch_order;
3024 }
3025
3026 void
3027 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
3028 st_dst_reg *l, st_src_reg *r,
3029 st_src_reg *cond, bool cond_swap)
3030 {
3031 if (type->is_struct()) {
3032 for (unsigned int i = 0; i < type->length; i++) {
3033 emit_block_mov(ir, type->fields.structure[i].type, l, r,
3034 cond, cond_swap);
3035 }
3036 return;
3037 }
3038
3039 if (type->is_array()) {
3040 for (unsigned int i = 0; i < type->length; i++) {
3041 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
3042 }
3043 return;
3044 }
3045
3046 if (type->is_matrix()) {
3047 const struct glsl_type *vec_type;
3048
3049 vec_type = glsl_type::get_instance(type->is_double()
3050 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3051 type->vector_elements, 1);
3052
3053 for (int i = 0; i < type->matrix_columns; i++) {
3054 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3055 }
3056 return;
3057 }
3058
3059 assert(type->is_scalar() || type->is_vector());
3060
3061 l->type = type->base_type;
3062 r->type = type->base_type;
3063 if (cond) {
3064 st_src_reg l_src = st_src_reg(*l);
3065
3066 if (l_src.file == PROGRAM_OUTPUT &&
3067 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3068 (l_src.index == FRAG_RESULT_DEPTH ||
3069 l_src.index == FRAG_RESULT_STENCIL)) {
3070 /* This is a special case because the source swizzles will be shifted
3071 * later to account for the difference between GLSL (where they're
3072 * plain floats) and TGSI (where they're Z and Y components). */
3073 l_src.swizzle = SWIZZLE_XXXX;
3074 }
3075
3076 if (native_integers) {
3077 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3078 cond_swap ? l_src : *r,
3079 cond_swap ? *r : l_src);
3080 } else {
3081 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3082 cond_swap ? l_src : *r,
3083 cond_swap ? *r : l_src);
3084 }
3085 } else {
3086 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3087 }
3088 l->index++;
3089 r->index++;
3090 if (type->is_dual_slot()) {
3091 l->index++;
3092 if (r->is_double_vertex_input == false)
3093 r->index++;
3094 }
3095 }
3096
3097 void
3098 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3099 {
3100 int dst_component;
3101 st_dst_reg l;
3102 st_src_reg r;
3103
3104 /* all generated instructions need to be flaged as precise */
3105 this->precise = is_precise(ir->lhs->variable_referenced());
3106 ir->rhs->accept(this);
3107 r = this->result;
3108
3109 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3110
3111 {
3112 int swizzles[4];
3113 int first_enabled_chan = 0;
3114 int rhs_chan = 0;
3115 ir_variable *variable = ir->lhs->variable_referenced();
3116
3117 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3118 variable->data.mode == ir_var_shader_out &&
3119 (variable->data.location == FRAG_RESULT_DEPTH ||
3120 variable->data.location == FRAG_RESULT_STENCIL)) {
3121 assert(ir->lhs->type->is_scalar());
3122 assert(ir->write_mask == WRITEMASK_X);
3123
3124 if (variable->data.location == FRAG_RESULT_DEPTH)
3125 l.writemask = WRITEMASK_Z;
3126 else {
3127 assert(variable->data.location == FRAG_RESULT_STENCIL);
3128 l.writemask = WRITEMASK_Y;
3129 }
3130 } else if (ir->write_mask == 0) {
3131 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3132
3133 unsigned num_elements =
3134 ir->lhs->type->without_array()->vector_elements;
3135
3136 if (num_elements) {
3137 l.writemask = u_bit_consecutive(0, num_elements);
3138 } else {
3139 /* The type is a struct or an array of (array of) structs. */
3140 l.writemask = WRITEMASK_XYZW;
3141 }
3142 } else {
3143 l.writemask = ir->write_mask;
3144 }
3145
3146 for (int i = 0; i < 4; i++) {
3147 if (l.writemask & (1 << i)) {
3148 first_enabled_chan = GET_SWZ(r.swizzle, i);
3149 break;
3150 }
3151 }
3152
3153 l.writemask = l.writemask << dst_component;
3154
3155 /* Swizzle a small RHS vector into the channels being written.
3156 *
3157 * glsl ir treats write_mask as dictating how many channels are
3158 * present on the RHS while TGSI treats write_mask as just
3159 * showing which channels of the vec4 RHS get written.
3160 */
3161 for (int i = 0; i < 4; i++) {
3162 if (l.writemask & (1 << i))
3163 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3164 else
3165 swizzles[i] = first_enabled_chan;
3166 }
3167 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3168 swizzles[2], swizzles[3]);
3169 }
3170
3171 assert(l.file != PROGRAM_UNDEFINED);
3172 assert(r.file != PROGRAM_UNDEFINED);
3173
3174 if (ir->condition) {
3175 const bool switch_order = this->process_move_condition(ir->condition);
3176 st_src_reg condition = this->result;
3177
3178 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3179 } else if (ir->rhs->as_expression() &&
3180 this->instructions.get_tail() &&
3181 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3182 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3183 type_size(ir->lhs->type) == 1 &&
3184 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3185 /* To avoid emitting an extra MOV when assigning an expression to a
3186 * variable, emit the last instruction of the expression again, but
3187 * replace the destination register with the target of the assignment.
3188 * Dead code elimination will remove the original instruction.
3189 */
3190 glsl_to_tgsi_instruction *inst, *new_inst;
3191 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3192 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3193 new_inst->saturate = inst->saturate;
3194 new_inst->resource = inst->resource;
3195 inst->dead_mask = inst->dst[0].writemask;
3196 } else {
3197 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3198 }
3199 this->precise = 0;
3200 }
3201
3202
3203 void
3204 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3205 {
3206 st_src_reg src;
3207 GLdouble stack_vals[4] = { 0 };
3208 gl_constant_value *values = (gl_constant_value *) stack_vals;
3209 GLenum gl_type = GL_NONE;
3210 unsigned int i, elements;
3211 static int in_array = 0;
3212 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3213
3214 /* Unfortunately, 4 floats is all we can get into
3215 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3216 * aggregate constant and move each constant value into it. If we
3217 * get lucky, copy propagation will eliminate the extra moves.
3218 */
3219 if (ir->type->is_struct()) {
3220 st_src_reg temp_base = get_temp(ir->type);
3221 st_dst_reg temp = st_dst_reg(temp_base);
3222
3223 for (i = 0; i < ir->type->length; i++) {
3224 ir_constant *const field_value = ir->get_record_field(i);
3225 int size = type_size(field_value->type);
3226
3227 assert(size > 0);
3228
3229 field_value->accept(this);
3230 src = this->result;
3231
3232 for (unsigned j = 0; j < (unsigned int)size; j++) {
3233 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3234
3235 src.index++;
3236 temp.index++;
3237 }
3238 }
3239 this->result = temp_base;
3240 return;
3241 }
3242
3243 if (ir->type->is_array()) {
3244 st_src_reg temp_base = get_temp(ir->type);
3245 st_dst_reg temp = st_dst_reg(temp_base);
3246 int size = type_size(ir->type->fields.array);
3247
3248 assert(size > 0);
3249 in_array++;
3250
3251 for (i = 0; i < ir->type->length; i++) {
3252 ir->const_elements[i]->accept(this);
3253 src = this->result;
3254 for (int j = 0; j < size; j++) {
3255 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3256
3257 src.index++;
3258 temp.index++;
3259 }
3260 }
3261 this->result = temp_base;
3262 in_array--;
3263 return;
3264 }
3265
3266 if (ir->type->is_matrix()) {
3267 st_src_reg mat = get_temp(ir->type);
3268 st_dst_reg mat_column = st_dst_reg(mat);
3269
3270 for (i = 0; i < ir->type->matrix_columns; i++) {
3271 switch (ir->type->base_type) {
3272 case GLSL_TYPE_FLOAT:
3273 values = (gl_constant_value *)
3274 &ir->value.f[i * ir->type->vector_elements];
3275
3276 src = st_src_reg(file, -1, ir->type->base_type);
3277 src.index = add_constant(file,
3278 values,
3279 ir->type->vector_elements,
3280 GL_FLOAT,
3281 &src.swizzle);
3282 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3283 break;
3284 case GLSL_TYPE_DOUBLE:
3285 values = (gl_constant_value *)
3286 &ir->value.d[i * ir->type->vector_elements];
3287 src = st_src_reg(file, -1, ir->type->base_type);
3288 src.index = add_constant(file,
3289 values,
3290 ir->type->vector_elements,
3291 GL_DOUBLE,
3292 &src.swizzle);
3293 if (ir->type->vector_elements >= 2) {
3294 mat_column.writemask = WRITEMASK_XY;
3295 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3296 SWIZZLE_X, SWIZZLE_Y);
3297 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3298 } else {
3299 mat_column.writemask = WRITEMASK_X;
3300 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3301 SWIZZLE_X, SWIZZLE_X);
3302 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3303 }
3304 src.index++;
3305 if (ir->type->vector_elements > 2) {
3306 if (ir->type->vector_elements == 4) {
3307 mat_column.writemask = WRITEMASK_ZW;
3308 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3309 SWIZZLE_X, SWIZZLE_Y);
3310 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3311 } else {
3312 mat_column.writemask = WRITEMASK_Z;
3313 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3314 SWIZZLE_Y, SWIZZLE_Y);
3315 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3316 mat_column.writemask = WRITEMASK_XYZW;
3317 src.swizzle = SWIZZLE_XYZW;
3318 }
3319 mat_column.index++;
3320 }
3321 break;
3322 default:
3323 unreachable("Illegal matrix constant type.\n");
3324 break;
3325 }
3326 mat_column.index++;
3327 }
3328 this->result = mat;
3329 return;
3330 }
3331
3332 elements = ir->type->vector_elements;
3333 switch (ir->type->base_type) {
3334 case GLSL_TYPE_FLOAT:
3335 gl_type = GL_FLOAT;
3336 for (i = 0; i < ir->type->vector_elements; i++) {
3337 values[i].f = ir->value.f[i];
3338 }
3339 break;
3340 case GLSL_TYPE_DOUBLE:
3341 gl_type = GL_DOUBLE;
3342 for (i = 0; i < ir->type->vector_elements; i++) {
3343 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3344 }
3345 break;
3346 case GLSL_TYPE_INT64:
3347 gl_type = GL_INT64_ARB;
3348 for (i = 0; i < ir->type->vector_elements; i++) {
3349 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3350 }
3351 break;
3352 case GLSL_TYPE_UINT64:
3353 gl_type = GL_UNSIGNED_INT64_ARB;
3354 for (i = 0; i < ir->type->vector_elements; i++) {
3355 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3356 }
3357 break;
3358 case GLSL_TYPE_UINT:
3359 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3360 for (i = 0; i < ir->type->vector_elements; i++) {
3361 if (native_integers)
3362 values[i].u = ir->value.u[i];
3363 else
3364 values[i].f = ir->value.u[i];
3365 }
3366 break;
3367 case GLSL_TYPE_INT:
3368 gl_type = native_integers ? GL_INT : GL_FLOAT;
3369 for (i = 0; i < ir->type->vector_elements; i++) {
3370 if (native_integers)
3371 values[i].i = ir->value.i[i];
3372 else
3373 values[i].f = ir->value.i[i];
3374 }
3375 break;
3376 case GLSL_TYPE_BOOL:
3377 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3378 for (i = 0; i < ir->type->vector_elements; i++) {
3379 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3380 }
3381 break;
3382 case GLSL_TYPE_SAMPLER:
3383 case GLSL_TYPE_IMAGE:
3384 gl_type = GL_UNSIGNED_INT;
3385 elements = 2;
3386 values[0].u = ir->value.u64[0] & 0xffffffff;
3387 values[1].u = ir->value.u64[0] >> 32;
3388 break;
3389 default:
3390 assert(!"Non-float/uint/int/bool/sampler/image constant");
3391 }
3392
3393 this->result = st_src_reg(file, -1, ir->type);
3394 this->result.index = add_constant(file,
3395 values,
3396 elements,
3397 gl_type,
3398 &this->result.swizzle);
3399 }
3400
3401 void
3402 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3403 {
3404 exec_node *param = ir->actual_parameters.get_head();
3405 ir_dereference *deref = static_cast<ir_dereference *>(param);
3406 ir_variable *location = deref->variable_referenced();
3407 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3408 /* Calculate the surface offset */
3409 st_src_reg offset;
3410 unsigned array_size = 0, base = 0;
3411 uint16_t index = 0;
3412 st_src_reg resource;
3413
3414 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3415
3416 if (has_hw_atomics) {
3417 variable_storage *entry = find_variable_storage(location);
3418 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3419 location->data.binding);
3420
3421 if (!entry) {
3422 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3423 num_atomics);
3424 _mesa_hash_table_insert(this->variables, location, entry);
3425
3426 atomic_info[num_atomics].location = location->data.location;
3427 atomic_info[num_atomics].binding = location->data.binding;
3428 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3429 if (atomic_info[num_atomics].size == 0)
3430 atomic_info[num_atomics].size = 1;
3431 atomic_info[num_atomics].array_id = 0;
3432 num_atomics++;
3433 }
3434
3435 if (offset.file != PROGRAM_UNDEFINED) {
3436 if (atomic_info[entry->index].array_id == 0) {
3437 num_atomic_arrays++;
3438 atomic_info[entry->index].array_id = num_atomic_arrays;
3439 }
3440 buffer.array_id = atomic_info[entry->index].array_id;
3441 }
3442
3443 buffer.index = index;
3444 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3445 buffer.has_index2 = true;
3446
3447 if (offset.file != PROGRAM_UNDEFINED) {
3448 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3449 *buffer.reladdr = offset;
3450 emit_arl(ir, sampler_reladdr, offset);
3451 }
3452 offset = st_src_reg_for_int(0);
3453
3454 resource = buffer;
3455 } else {
3456 st_src_reg buffer(PROGRAM_BUFFER,
3457 prog->info.num_ssbos +
3458 location->data.binding,
3459 GLSL_TYPE_ATOMIC_UINT);
3460
3461 if (offset.file != PROGRAM_UNDEFINED) {
3462 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3463 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3464 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3465 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3466 } else {
3467 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3468 }
3469 resource = buffer;
3470 }
3471
3472 ir->return_deref->accept(this);
3473 st_dst_reg dst(this->result);
3474 dst.writemask = WRITEMASK_X;
3475
3476 glsl_to_tgsi_instruction *inst;
3477
3478 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3479 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3480 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3481 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3482 st_src_reg_for_int(1));
3483 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3484 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3485 st_src_reg_for_int(-1));
3486 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3487 } else {
3488 param = param->get_next();
3489 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3490 val->accept(this);
3491
3492 st_src_reg data = this->result, data2 = undef_src;
3493 enum tgsi_opcode opcode;
3494 switch (ir->callee->intrinsic_id) {
3495 case ir_intrinsic_atomic_counter_add:
3496 opcode = TGSI_OPCODE_ATOMUADD;
3497 break;
3498 case ir_intrinsic_atomic_counter_min:
3499 opcode = TGSI_OPCODE_ATOMIMIN;
3500 break;
3501 case ir_intrinsic_atomic_counter_max:
3502 opcode = TGSI_OPCODE_ATOMIMAX;
3503 break;
3504 case ir_intrinsic_atomic_counter_and:
3505 opcode = TGSI_OPCODE_ATOMAND;
3506 break;
3507 case ir_intrinsic_atomic_counter_or:
3508 opcode = TGSI_OPCODE_ATOMOR;
3509 break;
3510 case ir_intrinsic_atomic_counter_xor:
3511 opcode = TGSI_OPCODE_ATOMXOR;
3512 break;
3513 case ir_intrinsic_atomic_counter_exchange:
3514 opcode = TGSI_OPCODE_ATOMXCHG;
3515 break;
3516 case ir_intrinsic_atomic_counter_comp_swap: {
3517 opcode = TGSI_OPCODE_ATOMCAS;
3518 param = param->get_next();
3519 val = ((ir_instruction *)param)->as_rvalue();
3520 val->accept(this);
3521 data2 = this->result;
3522 break;
3523 }
3524 default:
3525 assert(!"Unexpected intrinsic");
3526 return;
3527 }
3528
3529 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3530 }
3531
3532 inst->resource = resource;
3533 }
3534
3535 void
3536 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3537 {
3538 exec_node *param = ir->actual_parameters.get_head();
3539
3540 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3541
3542 param = param->get_next();
3543 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3544
3545 ir_constant *const_block = block->as_constant();
3546 st_src_reg buffer(
3547 PROGRAM_BUFFER,
3548 const_block ? const_block->value.u[0] : 0,
3549 GLSL_TYPE_UINT);
3550
3551 if (!const_block) {
3552 block->accept(this);
3553 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3554 *buffer.reladdr = this->result;
3555 emit_arl(ir, sampler_reladdr, this->result);
3556 }
3557
3558 /* Calculate the surface offset */
3559 offset->accept(this);
3560 st_src_reg off = this->result;
3561
3562 st_dst_reg dst = undef_dst;
3563 if (ir->return_deref) {
3564 ir->return_deref->accept(this);
3565 dst = st_dst_reg(this->result);
3566 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3567 }
3568
3569 glsl_to_tgsi_instruction *inst;
3570
3571 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3572 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3573 if (dst.type == GLSL_TYPE_BOOL)
3574 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3575 st_src_reg_for_int(0));
3576 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3577 param = param->get_next();
3578 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3579 val->accept(this);
3580
3581 param = param->get_next();
3582 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3583 assert(write_mask);
3584 dst.writemask = write_mask->value.u[0];
3585
3586 dst.type = this->result.type;
3587 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3588 } else {
3589 param = param->get_next();
3590 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3591 val->accept(this);
3592
3593 st_src_reg data = this->result, data2 = undef_src;
3594 enum tgsi_opcode opcode;
3595 switch (ir->callee->intrinsic_id) {
3596 case ir_intrinsic_ssbo_atomic_add:
3597 opcode = TGSI_OPCODE_ATOMUADD;
3598 break;
3599 case ir_intrinsic_ssbo_atomic_min:
3600 opcode = TGSI_OPCODE_ATOMIMIN;
3601 break;
3602 case ir_intrinsic_ssbo_atomic_max:
3603 opcode = TGSI_OPCODE_ATOMIMAX;
3604 break;
3605 case ir_intrinsic_ssbo_atomic_and:
3606 opcode = TGSI_OPCODE_ATOMAND;
3607 break;
3608 case ir_intrinsic_ssbo_atomic_or:
3609 opcode = TGSI_OPCODE_ATOMOR;
3610 break;
3611 case ir_intrinsic_ssbo_atomic_xor:
3612 opcode = TGSI_OPCODE_ATOMXOR;
3613 break;
3614 case ir_intrinsic_ssbo_atomic_exchange:
3615 opcode = TGSI_OPCODE_ATOMXCHG;
3616 break;
3617 case ir_intrinsic_ssbo_atomic_comp_swap:
3618 opcode = TGSI_OPCODE_ATOMCAS;
3619 param = param->get_next();
3620 val = ((ir_instruction *)param)->as_rvalue();
3621 val->accept(this);
3622 data2 = this->result;
3623 break;
3624 default:
3625 assert(!"Unexpected intrinsic");
3626 return;
3627 }
3628
3629 inst = emit_asm(ir, opcode, dst, off, data, data2);
3630 }
3631
3632 param = param->get_next();
3633 ir_constant *access = NULL;
3634 if (!param->is_tail_sentinel()) {
3635 access = ((ir_instruction *)param)->as_constant();
3636 assert(access);
3637 }
3638
3639 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3640 }
3641
3642 void
3643 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3644 {
3645 switch (ir->callee->intrinsic_id) {
3646 case ir_intrinsic_memory_barrier:
3647 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3648 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3649 TGSI_MEMBAR_ATOMIC_BUFFER |
3650 TGSI_MEMBAR_SHADER_IMAGE |
3651 TGSI_MEMBAR_SHARED));
3652 break;
3653 case ir_intrinsic_memory_barrier_atomic_counter:
3654 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3655 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3656 break;
3657 case ir_intrinsic_memory_barrier_buffer:
3658 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3659 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3660 break;
3661 case ir_intrinsic_memory_barrier_image:
3662 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3663 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3664 break;
3665 case ir_intrinsic_memory_barrier_shared:
3666 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3667 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3668 break;
3669 case ir_intrinsic_group_memory_barrier:
3670 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3671 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3672 TGSI_MEMBAR_ATOMIC_BUFFER |
3673 TGSI_MEMBAR_SHADER_IMAGE |
3674 TGSI_MEMBAR_SHARED |
3675 TGSI_MEMBAR_THREAD_GROUP));
3676 break;
3677 default:
3678 assert(!"Unexpected memory barrier intrinsic");
3679 }
3680 }
3681
3682 void
3683 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3684 {
3685 exec_node *param = ir->actual_parameters.get_head();
3686
3687 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3688
3689 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3690
3691 /* Calculate the surface offset */
3692 offset->accept(this);
3693 st_src_reg off = this->result;
3694
3695 st_dst_reg dst = undef_dst;
3696 if (ir->return_deref) {
3697 ir->return_deref->accept(this);
3698 dst = st_dst_reg(this->result);
3699 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3700 }
3701
3702 glsl_to_tgsi_instruction *inst;
3703
3704 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3705 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3706 inst->resource = buffer;
3707 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3708 param = param->get_next();
3709 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3710 val->accept(this);
3711
3712 param = param->get_next();
3713 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3714 assert(write_mask);
3715 dst.writemask = write_mask->value.u[0];
3716
3717 dst.type = this->result.type;
3718 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3719 inst->resource = buffer;
3720 } else {
3721 param = param->get_next();
3722 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3723 val->accept(this);
3724
3725 st_src_reg data = this->result, data2 = undef_src;
3726 enum tgsi_opcode opcode;
3727 switch (ir->callee->intrinsic_id) {
3728 case ir_intrinsic_shared_atomic_add:
3729 opcode = TGSI_OPCODE_ATOMUADD;
3730 break;
3731 case ir_intrinsic_shared_atomic_min:
3732 opcode = TGSI_OPCODE_ATOMIMIN;
3733 break;
3734 case ir_intrinsic_shared_atomic_max:
3735 opcode = TGSI_OPCODE_ATOMIMAX;
3736 break;
3737 case ir_intrinsic_shared_atomic_and:
3738 opcode = TGSI_OPCODE_ATOMAND;
3739 break;
3740 case ir_intrinsic_shared_atomic_or:
3741 opcode = TGSI_OPCODE_ATOMOR;
3742 break;
3743 case ir_intrinsic_shared_atomic_xor:
3744 opcode = TGSI_OPCODE_ATOMXOR;
3745 break;
3746 case ir_intrinsic_shared_atomic_exchange:
3747 opcode = TGSI_OPCODE_ATOMXCHG;
3748 break;
3749 case ir_intrinsic_shared_atomic_comp_swap:
3750 opcode = TGSI_OPCODE_ATOMCAS;
3751 param = param->get_next();
3752 val = ((ir_instruction *)param)->as_rvalue();
3753 val->accept(this);
3754 data2 = this->result;
3755 break;
3756 default:
3757 assert(!"Unexpected intrinsic");
3758 return;
3759 }
3760
3761 inst = emit_asm(ir, opcode, dst, off, data, data2);
3762 inst->resource = buffer;
3763 }
3764 }
3765
3766 static void
3767 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3768 bool *memory_coherent, bool *memory_volatile,
3769 bool *memory_restrict, bool *memory_read_only,
3770 enum pipe_format *image_format)
3771 {
3772
3773 switch (ir->ir_type) {
3774 case ir_type_dereference_record: {
3775 ir_dereference_record *deref_record = ir->as_dereference_record();
3776 const glsl_type *struct_type = deref_record->record->type;
3777 int fild_idx = deref_record->field_idx;
3778
3779 *type = struct_type->fields.structure[fild_idx].type->without_array();
3780 *memory_coherent =
3781 struct_type->fields.structure[fild_idx].memory_coherent;
3782 *memory_volatile =
3783 struct_type->fields.structure[fild_idx].memory_volatile;
3784 *memory_restrict =
3785 struct_type->fields.structure[fild_idx].memory_restrict;
3786 *memory_read_only =
3787 struct_type->fields.structure[fild_idx].memory_read_only;
3788 *image_format =
3789 struct_type->fields.structure[fild_idx].image_format;
3790 break;
3791 }
3792
3793 case ir_type_dereference_array: {
3794 ir_dereference_array *deref_arr = ir->as_dereference_array();
3795 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3796 memory_coherent, memory_volatile, memory_restrict,
3797 memory_read_only, image_format);
3798 break;
3799 }
3800
3801 case ir_type_dereference_variable: {
3802 ir_variable *var = ir->variable_referenced();
3803
3804 *type = var->type->without_array();
3805 *memory_coherent = var->data.memory_coherent;
3806 *memory_volatile = var->data.memory_volatile;
3807 *memory_restrict = var->data.memory_restrict;
3808 *memory_read_only = var->data.memory_read_only;
3809 *image_format = var->data.image_format;
3810 break;
3811 }
3812
3813 default:
3814 break;
3815 }
3816 }
3817
3818 void
3819 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3820 {
3821 exec_node *param = ir->actual_parameters.get_head();
3822
3823 ir_dereference *img = (ir_dereference *)param;
3824 const ir_variable *imgvar = img->variable_referenced();
3825 unsigned sampler_array_size = 1, sampler_base = 0;
3826 bool memory_coherent = false, memory_volatile = false,
3827 memory_restrict = false, memory_read_only = false;
3828 enum pipe_format image_format = PIPE_FORMAT_NONE;
3829 const glsl_type *type = NULL;
3830
3831 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3832 &memory_restrict, &memory_read_only, &image_format);
3833
3834 st_src_reg reladdr;
3835 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3836 uint16_t index = 0;
3837 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3838 &index, &reladdr, !imgvar->contains_bindless());
3839
3840 image.index = index;
3841 if (reladdr.file != PROGRAM_UNDEFINED) {
3842 image.reladdr = ralloc(mem_ctx, st_src_reg);
3843 *image.reladdr = reladdr;
3844 emit_arl(ir, sampler_reladdr, reladdr);
3845 }
3846
3847 st_dst_reg dst = undef_dst;
3848 if (ir->return_deref) {
3849 ir->return_deref->accept(this);
3850 dst = st_dst_reg(this->result);
3851 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3852 }
3853
3854 glsl_to_tgsi_instruction *inst;
3855
3856 st_src_reg bindless;
3857 if (imgvar->contains_bindless()) {
3858 img->accept(this);
3859 bindless = this->result;
3860 }
3861
3862 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3863 dst.writemask = WRITEMASK_XYZ;
3864 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3865 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3866 st_src_reg res = get_temp(glsl_type::ivec4_type);
3867 st_dst_reg dstres = st_dst_reg(res);
3868 dstres.writemask = WRITEMASK_W;
3869 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3870 res.swizzle = SWIZZLE_WWWW;
3871 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3872 } else {
3873 st_src_reg arg1 = undef_src, arg2 = undef_src;
3874 st_src_reg coord;
3875 st_dst_reg coord_dst;
3876 coord = get_temp(glsl_type::ivec4_type);
3877 coord_dst = st_dst_reg(coord);
3878 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3879 param = param->get_next();
3880 ((ir_dereference *)param)->accept(this);
3881 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3882 coord.swizzle = SWIZZLE_XXXX;
3883 switch (type->coordinate_components()) {
3884 case 4: assert(!"unexpected coord count");
3885 /* fallthrough */
3886 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3887 /* fallthrough */
3888 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3889 }
3890
3891 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3892 param = param->get_next();
3893 ((ir_dereference *)param)->accept(this);
3894 st_src_reg sample = this->result;
3895 sample.swizzle = SWIZZLE_XXXX;
3896 coord_dst.writemask = WRITEMASK_W;
3897 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3898 coord.swizzle |= SWIZZLE_W << 9;
3899 }
3900
3901 param = param->get_next();
3902 if (!param->is_tail_sentinel()) {
3903 ((ir_dereference *)param)->accept(this);
3904 arg1 = this->result;
3905 param = param->get_next();
3906 }
3907
3908 if (!param->is_tail_sentinel()) {
3909 ((ir_dereference *)param)->accept(this);
3910 arg2 = this->result;
3911 param = param->get_next();
3912 }
3913
3914 assert(param->is_tail_sentinel());
3915
3916 enum tgsi_opcode opcode;
3917 switch (ir->callee->intrinsic_id) {
3918 case ir_intrinsic_image_load:
3919 opcode = TGSI_OPCODE_LOAD;
3920 break;
3921 case ir_intrinsic_image_store:
3922 opcode = TGSI_OPCODE_STORE;
3923 break;
3924 case ir_intrinsic_image_atomic_add:
3925 opcode = TGSI_OPCODE_ATOMUADD;
3926 break;
3927 case ir_intrinsic_image_atomic_min:
3928 opcode = TGSI_OPCODE_ATOMIMIN;
3929 break;
3930 case ir_intrinsic_image_atomic_max:
3931 opcode = TGSI_OPCODE_ATOMIMAX;
3932 break;
3933 case ir_intrinsic_image_atomic_and:
3934 opcode = TGSI_OPCODE_ATOMAND;
3935 break;
3936 case ir_intrinsic_image_atomic_or:
3937 opcode = TGSI_OPCODE_ATOMOR;
3938 break;
3939 case ir_intrinsic_image_atomic_xor:
3940 opcode = TGSI_OPCODE_ATOMXOR;
3941 break;
3942 case ir_intrinsic_image_atomic_exchange:
3943 opcode = TGSI_OPCODE_ATOMXCHG;
3944 break;
3945 case ir_intrinsic_image_atomic_comp_swap:
3946 opcode = TGSI_OPCODE_ATOMCAS;
3947 break;
3948 case ir_intrinsic_image_atomic_inc_wrap: {
3949 /* There's a bit of disagreement between GLSL and the hardware. The
3950 * hardware wants to wrap after the given wrap value, while GLSL
3951 * wants to wrap at the value. Subtract 1 to make up the difference.
3952 */
3953 st_src_reg wrap = get_temp(glsl_type::uint_type);
3954 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(wrap),
3955 arg1, st_src_reg_for_int(-1));
3956 arg1 = wrap;
3957 opcode = TGSI_OPCODE_ATOMINC_WRAP;
3958 break;
3959 }
3960 case ir_intrinsic_image_atomic_dec_wrap:
3961 opcode = TGSI_OPCODE_ATOMDEC_WRAP;
3962 break;
3963 default:
3964 assert(!"Unexpected intrinsic");
3965 return;
3966 }
3967
3968 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3969 if (opcode == TGSI_OPCODE_STORE)
3970 inst->dst[0].writemask = WRITEMASK_XYZW;
3971 }
3972
3973 if (imgvar->contains_bindless()) {
3974 inst->resource = bindless;
3975 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3976 SWIZZLE_X, SWIZZLE_Y);
3977 } else {
3978 inst->resource = image;
3979 inst->sampler_array_size = sampler_array_size;
3980 inst->sampler_base = sampler_base;
3981 }
3982
3983 inst->tex_target = type->sampler_index();
3984 inst->image_format = image_format;
3985 inst->read_only = memory_read_only;
3986
3987 if (memory_coherent)
3988 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3989 if (memory_restrict)
3990 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3991 if (memory_volatile)
3992 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3993 }
3994
3995 void
3996 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
3997 {
3998 ir->return_deref->accept(this);
3999 st_dst_reg dst = st_dst_reg(this->result);
4000
4001 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
4002
4003 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
4004 unsigned num_src = 0;
4005 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
4006 assert(num_src < ARRAY_SIZE(src));
4007
4008 this->result.file = PROGRAM_UNDEFINED;
4009 param->accept(this);
4010 assert(this->result.file != PROGRAM_UNDEFINED);
4011
4012 src[num_src] = this->result;
4013 num_src++;
4014 }
4015
4016 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
4017 }
4018
4019 void
4020 glsl_to_tgsi_visitor::visit(ir_call *ir)
4021 {
4022 ir_function_signature *sig = ir->callee;
4023
4024 /* Filter out intrinsics */
4025 switch (sig->intrinsic_id) {
4026 case ir_intrinsic_atomic_counter_read:
4027 case ir_intrinsic_atomic_counter_increment:
4028 case ir_intrinsic_atomic_counter_predecrement:
4029 case ir_intrinsic_atomic_counter_add:
4030 case ir_intrinsic_atomic_counter_min:
4031 case ir_intrinsic_atomic_counter_max:
4032 case ir_intrinsic_atomic_counter_and:
4033 case ir_intrinsic_atomic_counter_or:
4034 case ir_intrinsic_atomic_counter_xor:
4035 case ir_intrinsic_atomic_counter_exchange:
4036 case ir_intrinsic_atomic_counter_comp_swap:
4037 visit_atomic_counter_intrinsic(ir);
4038 return;
4039
4040 case ir_intrinsic_ssbo_load:
4041 case ir_intrinsic_ssbo_store:
4042 case ir_intrinsic_ssbo_atomic_add:
4043 case ir_intrinsic_ssbo_atomic_min:
4044 case ir_intrinsic_ssbo_atomic_max:
4045 case ir_intrinsic_ssbo_atomic_and:
4046 case ir_intrinsic_ssbo_atomic_or:
4047 case ir_intrinsic_ssbo_atomic_xor:
4048 case ir_intrinsic_ssbo_atomic_exchange:
4049 case ir_intrinsic_ssbo_atomic_comp_swap:
4050 visit_ssbo_intrinsic(ir);
4051 return;
4052
4053 case ir_intrinsic_memory_barrier:
4054 case ir_intrinsic_memory_barrier_atomic_counter:
4055 case ir_intrinsic_memory_barrier_buffer:
4056 case ir_intrinsic_memory_barrier_image:
4057 case ir_intrinsic_memory_barrier_shared:
4058 case ir_intrinsic_group_memory_barrier:
4059 visit_membar_intrinsic(ir);
4060 return;
4061
4062 case ir_intrinsic_shared_load:
4063 case ir_intrinsic_shared_store:
4064 case ir_intrinsic_shared_atomic_add:
4065 case ir_intrinsic_shared_atomic_min:
4066 case ir_intrinsic_shared_atomic_max:
4067 case ir_intrinsic_shared_atomic_and:
4068 case ir_intrinsic_shared_atomic_or:
4069 case ir_intrinsic_shared_atomic_xor:
4070 case ir_intrinsic_shared_atomic_exchange:
4071 case ir_intrinsic_shared_atomic_comp_swap:
4072 visit_shared_intrinsic(ir);
4073 return;
4074
4075 case ir_intrinsic_image_load:
4076 case ir_intrinsic_image_store:
4077 case ir_intrinsic_image_atomic_add:
4078 case ir_intrinsic_image_atomic_min:
4079 case ir_intrinsic_image_atomic_max:
4080 case ir_intrinsic_image_atomic_and:
4081 case ir_intrinsic_image_atomic_or:
4082 case ir_intrinsic_image_atomic_xor:
4083 case ir_intrinsic_image_atomic_exchange:
4084 case ir_intrinsic_image_atomic_comp_swap:
4085 case ir_intrinsic_image_size:
4086 case ir_intrinsic_image_samples:
4087 case ir_intrinsic_image_atomic_inc_wrap:
4088 case ir_intrinsic_image_atomic_dec_wrap:
4089 visit_image_intrinsic(ir);
4090 return;
4091
4092 case ir_intrinsic_shader_clock:
4093 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4094 return;
4095
4096 case ir_intrinsic_vote_all:
4097 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4098 return;
4099 case ir_intrinsic_vote_any:
4100 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4101 return;
4102 case ir_intrinsic_vote_eq:
4103 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4104 return;
4105 case ir_intrinsic_ballot:
4106 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4107 return;
4108 case ir_intrinsic_read_first_invocation:
4109 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4110 return;
4111 case ir_intrinsic_read_invocation:
4112 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4113 return;
4114
4115 case ir_intrinsic_helper_invocation:
4116 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_HELPER);
4117 return;
4118
4119 case ir_intrinsic_invalid:
4120 case ir_intrinsic_generic_load:
4121 case ir_intrinsic_generic_store:
4122 case ir_intrinsic_generic_atomic_add:
4123 case ir_intrinsic_generic_atomic_and:
4124 case ir_intrinsic_generic_atomic_or:
4125 case ir_intrinsic_generic_atomic_xor:
4126 case ir_intrinsic_generic_atomic_min:
4127 case ir_intrinsic_generic_atomic_max:
4128 case ir_intrinsic_generic_atomic_exchange:
4129 case ir_intrinsic_generic_atomic_comp_swap:
4130 case ir_intrinsic_begin_invocation_interlock:
4131 case ir_intrinsic_end_invocation_interlock:
4132 unreachable("Invalid intrinsic");
4133 }
4134 }
4135
4136 void
4137 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4138 unsigned *array_elements,
4139 uint16_t *index,
4140 st_src_reg *indirect,
4141 unsigned *location)
4142 {
4143 switch (tail->ir_type) {
4144 case ir_type_dereference_record: {
4145 ir_dereference_record *deref_record = tail->as_dereference_record();
4146 const glsl_type *struct_type = deref_record->record->type;
4147 int field_index = deref_record->field_idx;
4148
4149 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4150
4151 assert(field_index >= 0);
4152 *location += struct_type->struct_location_offset(field_index);
4153 break;
4154 }
4155
4156 case ir_type_dereference_array: {
4157 ir_dereference_array *deref_arr = tail->as_dereference_array();
4158
4159 void *mem_ctx = ralloc_parent(deref_arr);
4160 ir_constant *array_index =
4161 deref_arr->array_index->constant_expression_value(mem_ctx);
4162
4163 if (!array_index) {
4164 st_src_reg temp_reg;
4165 st_dst_reg temp_dst;
4166
4167 temp_reg = get_temp(glsl_type::uint_type);
4168 temp_dst = st_dst_reg(temp_reg);
4169 temp_dst.writemask = 1;
4170
4171 deref_arr->array_index->accept(this);
4172 if (*array_elements != 1)
4173 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4174 else
4175 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4176
4177 if (indirect->file == PROGRAM_UNDEFINED)
4178 *indirect = temp_reg;
4179 else {
4180 temp_dst = st_dst_reg(*indirect);
4181 temp_dst.writemask = 1;
4182 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4183 }
4184 } else
4185 *index += array_index->value.u[0] * *array_elements;
4186
4187 *array_elements *= deref_arr->array->type->length;
4188
4189 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4190 break;
4191 }
4192 default:
4193 break;
4194 }
4195 }
4196
4197 void
4198 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4199 unsigned *array_size,
4200 unsigned *base,
4201 uint16_t *index,
4202 st_src_reg *reladdr,
4203 bool opaque)
4204 {
4205 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4206 unsigned location = 0;
4207 ir_variable *var = ir->variable_referenced();
4208
4209 reladdr->reset();
4210
4211 *base = 0;
4212 *array_size = 1;
4213
4214 assert(var);
4215 location = var->data.location;
4216 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4217
4218 /*
4219 * If we end up with no indirect then adjust the base to the index,
4220 * and set the array size to 1.
4221 */
4222 if (reladdr->file == PROGRAM_UNDEFINED) {
4223 *base = *index;
4224 *array_size = 1;
4225 }
4226
4227 if (opaque) {
4228 assert(location != 0xffffffff);
4229 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4230 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4231 }
4232 }
4233
4234 st_src_reg
4235 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4236 {
4237 if (offset.reladdr || offset.reladdr2 ||
4238 offset.has_index2 ||
4239 offset.file == PROGRAM_UNIFORM ||
4240 offset.file == PROGRAM_CONSTANT ||
4241 offset.file == PROGRAM_STATE_VAR) {
4242 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4243 st_dst_reg tmp_dst = st_dst_reg(tmp);
4244 tmp_dst.writemask = WRITEMASK_XY;
4245 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4246 return tmp;
4247 }
4248
4249 return offset;
4250 }
4251
4252 bool
4253 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4254 {
4255 ir_variable *var = ir->variable_referenced();
4256
4257 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4258 !(ir->type->is_image() || ir->type->is_sampler()))
4259 return false;
4260
4261 /* Convert from bound sampler/image to bindless handle. */
4262 bool is_image = ir->type->is_image();
4263 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4264 uint16_t index = 0;
4265 unsigned array_size = 1, base = 0;
4266 st_src_reg reladdr;
4267 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4268
4269 resource.index = index;
4270 if (reladdr.file != PROGRAM_UNDEFINED) {
4271 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4272 *resource.reladdr = reladdr;
4273 emit_arl(ir, sampler_reladdr, reladdr);
4274 }
4275
4276 this->result = get_temp(glsl_type::uvec2_type);
4277 st_dst_reg dst(this->result);
4278 dst.writemask = WRITEMASK_XY;
4279
4280 glsl_to_tgsi_instruction *inst = emit_asm(
4281 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4282
4283 inst->tex_target = ir->type->sampler_index();
4284 inst->resource = resource;
4285 inst->sampler_array_size = array_size;
4286 inst->sampler_base = base;
4287
4288 return true;
4289 }
4290
4291 void
4292 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4293 {
4294 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4295 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4296 st_src_reg levels_src, reladdr;
4297 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4298 glsl_to_tgsi_instruction *inst = NULL;
4299 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4300 const glsl_type *sampler_type = ir->sampler->type;
4301 unsigned sampler_array_size = 1, sampler_base = 0;
4302 bool is_cube_array = false;
4303 ir_variable *var = ir->sampler->variable_referenced();
4304 unsigned i;
4305
4306 /* if we are a cube array sampler or a cube shadow */
4307 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4308 is_cube_array = sampler_type->sampler_array;
4309 }
4310
4311 if (ir->coordinate) {
4312 ir->coordinate->accept(this);
4313
4314 /* Put our coords in a temp. We'll need to modify them for shadow,
4315 * projection, or LOD, so the only case we'd use it as-is is if
4316 * we're doing plain old texturing. The optimization passes on
4317 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4318 */
4319 coord = get_temp(glsl_type::vec4_type);
4320 coord_dst = st_dst_reg(coord);
4321 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4322 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4323 }
4324
4325 if (ir->projector) {
4326 ir->projector->accept(this);
4327 projector = this->result;
4328 }
4329
4330 /* Storage for our result. Ideally for an assignment we'd be using
4331 * the actual storage for the result here, instead.
4332 */
4333 result_src = get_temp(ir->type);
4334 result_dst = st_dst_reg(result_src);
4335 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4336
4337 switch (ir->op) {
4338 case ir_tex:
4339 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4340 if (ir->offset) {
4341 ir->offset->accept(this);
4342 offset[0] = this->result;
4343 }
4344 break;
4345 case ir_txb:
4346 if (is_cube_array ||
4347 (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) {
4348 opcode = TGSI_OPCODE_TXB2;
4349 }
4350 else {
4351 opcode = TGSI_OPCODE_TXB;
4352 }
4353 ir->lod_info.bias->accept(this);
4354 lod_info = this->result;
4355 if (ir->offset) {
4356 ir->offset->accept(this);
4357 offset[0] = this->result;
4358 }
4359 break;
4360 case ir_txl:
4361 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4362 opcode = TGSI_OPCODE_TEX_LZ;
4363 } else {
4364 opcode = (is_cube_array || (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4365 ir->lod_info.lod->accept(this);
4366 lod_info = this->result;
4367 }
4368 if (ir->offset) {
4369 ir->offset->accept(this);
4370 offset[0] = this->result;
4371 }
4372 break;
4373 case ir_txd:
4374 opcode = TGSI_OPCODE_TXD;
4375 ir->lod_info.grad.dPdx->accept(this);
4376 dx = this->result;
4377 ir->lod_info.grad.dPdy->accept(this);
4378 dy = this->result;
4379 if (ir->offset) {
4380 ir->offset->accept(this);
4381 offset[0] = this->result;
4382 }
4383 break;
4384 case ir_txs:
4385 opcode = TGSI_OPCODE_TXQ;
4386 ir->lod_info.lod->accept(this);
4387 lod_info = this->result;
4388 break;
4389 case ir_query_levels:
4390 opcode = TGSI_OPCODE_TXQ;
4391 lod_info = undef_src;
4392 levels_src = get_temp(ir->type);
4393 break;
4394 case ir_txf:
4395 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4396 opcode = TGSI_OPCODE_TXF_LZ;
4397 } else {
4398 opcode = TGSI_OPCODE_TXF;
4399 ir->lod_info.lod->accept(this);
4400 lod_info = this->result;
4401 }
4402 if (ir->offset) {
4403 ir->offset->accept(this);
4404 offset[0] = this->result;
4405 }
4406 break;
4407 case ir_txf_ms:
4408 opcode = TGSI_OPCODE_TXF;
4409 ir->lod_info.sample_index->accept(this);
4410 sample_index = this->result;
4411 break;
4412 case ir_tg4:
4413 opcode = TGSI_OPCODE_TG4;
4414 ir->lod_info.component->accept(this);
4415 component = this->result;
4416 if (ir->offset) {
4417 ir->offset->accept(this);
4418 if (ir->offset->type->is_array()) {
4419 const glsl_type *elt_type = ir->offset->type->fields.array;
4420 for (i = 0; i < ir->offset->type->length; i++) {
4421 offset[i] = this->result;
4422 offset[i].index += i * type_size(elt_type);
4423 offset[i].type = elt_type->base_type;
4424 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4425 offset[i] = canonicalize_gather_offset(offset[i]);
4426 }
4427 } else {
4428 offset[0] = canonicalize_gather_offset(this->result);
4429 }
4430 }
4431 break;
4432 case ir_lod:
4433 opcode = TGSI_OPCODE_LODQ;
4434 break;
4435 case ir_texture_samples:
4436 opcode = TGSI_OPCODE_TXQS;
4437 break;
4438 case ir_samples_identical:
4439 unreachable("Unexpected ir_samples_identical opcode");
4440 }
4441
4442 if (ir->projector) {
4443 if (opcode == TGSI_OPCODE_TEX) {
4444 /* Slot the projector in as the last component of the coord. */
4445 coord_dst.writemask = WRITEMASK_W;
4446 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4447 coord_dst.writemask = WRITEMASK_XYZW;
4448 opcode = TGSI_OPCODE_TXP;
4449 } else {
4450 st_src_reg coord_w = coord;
4451 coord_w.swizzle = SWIZZLE_WWWW;
4452
4453 /* For the other TEX opcodes there's no projective version
4454 * since the last slot is taken up by LOD info. Do the
4455 * projective divide now.
4456 */
4457 coord_dst.writemask = WRITEMASK_W;
4458 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4459
4460 /* In the case where we have to project the coordinates "by hand,"
4461 * the shadow comparator value must also be projected.
4462 */
4463 st_src_reg tmp_src = coord;
4464 if (ir->shadow_comparator) {
4465 /* Slot the shadow value in as the second to last component of the
4466 * coord.
4467 */
4468 ir->shadow_comparator->accept(this);
4469
4470 tmp_src = get_temp(glsl_type::vec4_type);
4471 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4472
4473 /* Projective division not allowed for array samplers. */
4474 assert(!sampler_type->sampler_array);
4475
4476 tmp_dst.writemask = WRITEMASK_Z;
4477 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4478
4479 tmp_dst.writemask = WRITEMASK_XY;
4480 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4481 }
4482
4483 coord_dst.writemask = WRITEMASK_XYZ;
4484 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4485
4486 coord_dst.writemask = WRITEMASK_XYZW;
4487 coord.swizzle = SWIZZLE_XYZW;
4488 }
4489 }
4490
4491 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4492 * shadow comparator was put in the correct place (and projected) by the
4493 * code, above, that handles by-hand projection.
4494 */
4495 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4496 /* Slot the shadow value in as the second to last component of the
4497 * coord.
4498 */
4499 ir->shadow_comparator->accept(this);
4500
4501 if (is_cube_array) {
4502 if (lod_info.file != PROGRAM_UNDEFINED) {
4503 // If we have both a cube array *and* a bias/lod, stick the
4504 // comparator into the .Y of the second argument.
4505 st_src_reg tmp = get_temp(glsl_type::vec2_type);
4506 cube_sc_dst = st_dst_reg(tmp);
4507 cube_sc_dst.writemask = WRITEMASK_X;
4508 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, lod_info);
4509 lod_info = tmp;
4510 cube_sc_dst.writemask = WRITEMASK_Y;
4511 } else {
4512 cube_sc = get_temp(glsl_type::float_type);
4513 cube_sc_dst = st_dst_reg(cube_sc);
4514 cube_sc_dst.writemask = WRITEMASK_X;
4515 }
4516 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4517 }
4518 else {
4519 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4520 sampler_type->sampler_array) ||
4521 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4522 coord_dst.writemask = WRITEMASK_W;
4523 } else {
4524 coord_dst.writemask = WRITEMASK_Z;
4525 }
4526 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4527 coord_dst.writemask = WRITEMASK_XYZW;
4528 }
4529 }
4530
4531 if (ir->op == ir_txf_ms) {
4532 coord_dst.writemask = WRITEMASK_W;
4533 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4534 coord_dst.writemask = WRITEMASK_XYZW;
4535 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4536 opcode == TGSI_OPCODE_TXF) {
4537 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4538 coord_dst.writemask = WRITEMASK_W;
4539 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4540 coord_dst.writemask = WRITEMASK_XYZW;
4541 }
4542
4543 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4544
4545 uint16_t index = 0;
4546 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4547 &index, &reladdr, !var->contains_bindless());
4548
4549 sampler.index = index;
4550 if (reladdr.file != PROGRAM_UNDEFINED) {
4551 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4552 *sampler.reladdr = reladdr;
4553 emit_arl(ir, sampler_reladdr, reladdr);
4554 }
4555
4556 st_src_reg bindless;
4557 if (var->contains_bindless()) {
4558 ir->sampler->accept(this);
4559 bindless = this->result;
4560 }
4561
4562 if (opcode == TGSI_OPCODE_TXD)
4563 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4564 else if (opcode == TGSI_OPCODE_TXQ) {
4565 if (ir->op == ir_query_levels) {
4566 /* the level is stored in W */
4567 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4568 result_dst.writemask = WRITEMASK_X;
4569 levels_src.swizzle = SWIZZLE_WWWW;
4570 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4571 } else
4572 inst = emit_asm(ir, opcode, result_dst, lod_info);
4573 } else if (opcode == TGSI_OPCODE_TXQS) {
4574 inst = emit_asm(ir, opcode, result_dst);
4575 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4576 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4577 } else if (opcode == TGSI_OPCODE_TEX2) {
4578 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4579 } else if (opcode == TGSI_OPCODE_TG4) {
4580 if (is_cube_array && ir->shadow_comparator) {
4581 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4582 } else {
4583 if (this->tg4_component_in_swizzle) {
4584 inst = emit_asm(ir, opcode, result_dst, coord);
4585 int idx = 0;
4586 foreach_in_list(immediate_storage, entry, &this->immediates) {
4587 if (component.index == idx) {
4588 gl_constant_value value = entry->values[component.swizzle];
4589 inst->gather_component = value.i;
4590 break;
4591 }
4592 idx++;
4593 }
4594 } else {
4595 inst = emit_asm(ir, opcode, result_dst, coord, component);
4596 }
4597 }
4598 } else
4599 inst = emit_asm(ir, opcode, result_dst, coord);
4600
4601 if (ir->shadow_comparator)
4602 inst->tex_shadow = GL_TRUE;
4603
4604 if (var->contains_bindless()) {
4605 inst->resource = bindless;
4606 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4607 SWIZZLE_X, SWIZZLE_Y);
4608 } else {
4609 inst->resource = sampler;
4610 inst->sampler_array_size = sampler_array_size;
4611 inst->sampler_base = sampler_base;
4612 }
4613
4614 if (ir->offset) {
4615 if (!inst->tex_offsets)
4616 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4617 MAX_GLSL_TEXTURE_OFFSET);
4618
4619 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4620 offset[i].file != PROGRAM_UNDEFINED; i++)
4621 inst->tex_offsets[i] = offset[i];
4622 inst->tex_offset_num_offset = i;
4623 }
4624
4625 inst->tex_target = sampler_type->sampler_index();
4626 inst->tex_type = ir->type->base_type;
4627
4628 this->result = result_src;
4629 }
4630
4631 void
4632 glsl_to_tgsi_visitor::visit(ir_return *ir)
4633 {
4634 assert(!ir->get_value());
4635
4636 emit_asm(ir, TGSI_OPCODE_RET);
4637 }
4638
4639 void
4640 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4641 {
4642 if (ir->condition) {
4643 ir->condition->accept(this);
4644 st_src_reg condition = this->result;
4645
4646 /* Convert the bool condition to a float so we can negate. */
4647 if (native_integers) {
4648 st_src_reg temp = get_temp(ir->condition->type);
4649 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4650 condition, st_src_reg_for_float(1.0));
4651 condition = temp;
4652 }
4653
4654 condition.negate = ~condition.negate;
4655 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4656 } else {
4657 /* unconditional kil */
4658 emit_asm(ir, TGSI_OPCODE_KILL);
4659 }
4660 }
4661
4662 void
4663 glsl_to_tgsi_visitor::visit(ir_demote *ir)
4664 {
4665 emit_asm(ir, TGSI_OPCODE_DEMOTE);
4666 }
4667
4668 void
4669 glsl_to_tgsi_visitor::visit(ir_if *ir)
4670 {
4671 enum tgsi_opcode if_opcode;
4672 glsl_to_tgsi_instruction *if_inst;
4673
4674 ir->condition->accept(this);
4675 assert(this->result.file != PROGRAM_UNDEFINED);
4676
4677 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4678
4679 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4680
4681 this->instructions.push_tail(if_inst);
4682
4683 visit_exec_list(&ir->then_instructions, this);
4684
4685 if (!ir->else_instructions.is_empty()) {
4686 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4687 visit_exec_list(&ir->else_instructions, this);
4688 }
4689
4690 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4691 }
4692
4693
4694 void
4695 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4696 {
4697 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4698
4699 ir->stream->accept(this);
4700 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4701 }
4702
4703 void
4704 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4705 {
4706 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4707
4708 ir->stream->accept(this);
4709 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4710 }
4711
4712 void
4713 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4714 {
4715 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4716 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4717
4718 emit_asm(ir, TGSI_OPCODE_BARRIER);
4719 }
4720
4721 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4722 {
4723 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4724
4725 result.file = PROGRAM_UNDEFINED;
4726 next_temp = 1;
4727 array_sizes = NULL;
4728 max_num_arrays = 0;
4729 next_array = 0;
4730 num_inputs = 0;
4731 num_outputs = 0;
4732 num_input_arrays = 0;
4733 num_output_arrays = 0;
4734 num_atomics = 0;
4735 num_atomic_arrays = 0;
4736 num_immediates = 0;
4737 num_address_regs = 0;
4738 samplers_used = 0;
4739 images_used = 0;
4740 indirect_addr_consts = false;
4741 wpos_transform_const = -1;
4742 native_integers = false;
4743 mem_ctx = ralloc_context(NULL);
4744 ctx = NULL;
4745 prog = NULL;
4746 precise = 0;
4747 need_uarl = false;
4748 tg4_component_in_swizzle = false;
4749 shader_program = NULL;
4750 shader = NULL;
4751 options = NULL;
4752 have_sqrt = false;
4753 have_fma = false;
4754 use_shared_memory = false;
4755 has_tex_txf_lz = false;
4756 variables = NULL;
4757 }
4758
4759 static void var_destroy(struct hash_entry *entry)
4760 {
4761 variable_storage *storage = (variable_storage *)entry->data;
4762
4763 delete storage;
4764 }
4765
4766 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4767 {
4768 _mesa_hash_table_destroy(variables, var_destroy);
4769 free(array_sizes);
4770 ralloc_free(mem_ctx);
4771 }
4772
4773 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4774 {
4775 delete v;
4776 }
4777
4778
4779 /**
4780 * Count resources used by the given gpu program (number of texture
4781 * samplers, etc).
4782 */
4783 static void
4784 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4785 {
4786 v->samplers_used = 0;
4787 v->images_used = 0;
4788 prog->info.textures_used_by_txf = 0;
4789
4790 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4791 if (inst->info->is_tex) {
4792 for (int i = 0; i < inst->sampler_array_size; i++) {
4793 unsigned idx = inst->sampler_base + i;
4794 v->samplers_used |= 1u << idx;
4795
4796 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4797 v->sampler_types[idx] = inst->tex_type;
4798 v->sampler_targets[idx] =
4799 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4800
4801 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4802 prog->info.textures_used_by_txf |= 1u << idx;
4803 }
4804 }
4805 }
4806
4807 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4808 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4809
4810 if (inst->resource.file != PROGRAM_UNDEFINED && (
4811 is_resource_instruction(inst->op) ||
4812 inst->op == TGSI_OPCODE_STORE)) {
4813 if (inst->resource.file == PROGRAM_MEMORY) {
4814 v->use_shared_memory = true;
4815 } else if (inst->resource.file == PROGRAM_IMAGE) {
4816 for (int i = 0; i < inst->sampler_array_size; i++) {
4817 unsigned idx = inst->sampler_base + i;
4818 v->images_used |= 1 << idx;
4819 v->image_targets[idx] =
4820 st_translate_texture_target(inst->tex_target, false);
4821 v->image_formats[idx] = inst->image_format;
4822 v->image_wr[idx] = !inst->read_only;
4823 }
4824 }
4825 }
4826 }
4827 prog->SamplersUsed = v->samplers_used;
4828
4829 if (v->shader_program != NULL)
4830 _mesa_update_shader_textures_used(v->shader_program, prog);
4831 }
4832
4833 /**
4834 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4835 * are read from the given src in this instruction
4836 */
4837 static int
4838 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4839 {
4840 int read_mask = 0, comp;
4841
4842 /* Now, given the src swizzle and the written channels, find which
4843 * components are actually read
4844 */
4845 for (comp = 0; comp < 4; ++comp) {
4846 const unsigned coord = GET_SWZ(src.swizzle, comp);
4847 assert(coord < 4);
4848 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4849 read_mask |= 1 << coord;
4850 }
4851
4852 return read_mask;
4853 }
4854
4855 /**
4856 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4857 * instruction is the first instruction to write to register T0. There are
4858 * several lowering passes done in GLSL IR (e.g. branches and
4859 * relative addressing) that create a large number of conditional assignments
4860 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4861 *
4862 * Here is why this conversion is safe:
4863 * CMP T0, T1 T2 T0 can be expanded to:
4864 * if (T1 < 0.0)
4865 * MOV T0, T2;
4866 * else
4867 * MOV T0, T0;
4868 *
4869 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4870 * as the original program. If (T1 < 0.0) evaluates to false, executing
4871 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4872 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4873 * because any instruction that was going to read from T0 after this was going
4874 * to read a garbage value anyway.
4875 */
4876 void
4877 glsl_to_tgsi_visitor::simplify_cmp(void)
4878 {
4879 int tempWritesSize = 0;
4880 unsigned *tempWrites = NULL;
4881 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4882
4883 memset(outputWrites, 0, sizeof(outputWrites));
4884
4885 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4886 unsigned prevWriteMask = 0;
4887
4888 /* Give up if we encounter relative addressing or flow control. */
4889 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4890 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4891 inst->info->is_branch ||
4892 inst->op == TGSI_OPCODE_CONT ||
4893 inst->op == TGSI_OPCODE_END ||
4894 inst->op == TGSI_OPCODE_RET) {
4895 break;
4896 }
4897
4898 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4899 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4900 prevWriteMask = outputWrites[inst->dst[0].index];
4901 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4902 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4903 if (inst->dst[0].index >= tempWritesSize) {
4904 const int inc = 4096;
4905
4906 tempWrites = (unsigned*)
4907 realloc(tempWrites,
4908 (tempWritesSize + inc) * sizeof(unsigned));
4909 if (!tempWrites)
4910 return;
4911
4912 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4913 tempWritesSize += inc;
4914 }
4915
4916 prevWriteMask = tempWrites[inst->dst[0].index];
4917 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4918 } else
4919 continue;
4920
4921 /* For a CMP to be considered a conditional write, the destination
4922 * register and source register two must be the same. */
4923 if (inst->op == TGSI_OPCODE_CMP
4924 && !(inst->dst[0].writemask & prevWriteMask)
4925 && inst->src[2].file == inst->dst[0].file
4926 && inst->src[2].index == inst->dst[0].index
4927 && inst->dst[0].writemask ==
4928 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4929
4930 inst->op = TGSI_OPCODE_MOV;
4931 inst->info = tgsi_get_opcode_info(inst->op);
4932 inst->src[0] = inst->src[1];
4933 }
4934 }
4935
4936 free(tempWrites);
4937 }
4938
4939 static void
4940 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4941 {
4942 if (src && src->file == PROGRAM_TEMPORARY) {
4943 int old_idx = src->index;
4944 if (renames[old_idx].valid)
4945 src->index = renames[old_idx].new_reg;
4946 }
4947 }
4948
4949 /* Replaces all references to a temporary register index with another index. */
4950 void
4951 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4952 {
4953 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4954 unsigned j;
4955 for (j = 0; j < num_inst_src_regs(inst); j++) {
4956 rename_temp_handle_src(renames, &inst->src[j]);
4957 rename_temp_handle_src(renames, inst->src[j].reladdr);
4958 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4959 }
4960
4961 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4962 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4963 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4964 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4965 }
4966
4967 rename_temp_handle_src(renames, &inst->resource);
4968 rename_temp_handle_src(renames, inst->resource.reladdr);
4969 rename_temp_handle_src(renames, inst->resource.reladdr2);
4970
4971 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4972 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4973 int old_idx = inst->dst[j].index;
4974 if (renames[old_idx].valid)
4975 inst->dst[j].index = renames[old_idx].new_reg;
4976 }
4977 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4978 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4979 }
4980 }
4981 }
4982
4983 void
4984 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4985 {
4986 int depth = 0; /* loop depth */
4987 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4988 unsigned i = 0, j;
4989
4990 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4991 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4992 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4993 if (first_writes[inst->dst[j].index] == -1)
4994 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4995 }
4996 }
4997
4998 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4999 if (depth++ == 0)
5000 loop_start = i;
5001 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5002 if (--depth == 0)
5003 loop_start = -1;
5004 }
5005 assert(depth >= 0);
5006 i++;
5007 }
5008 }
5009
5010 void
5011 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
5012 {
5013 int depth = 0; /* loop depth */
5014 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5015 unsigned i = 0, j;
5016
5017 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5018 for (j = 0; j < num_inst_src_regs(inst); j++) {
5019 if (inst->src[j].file == PROGRAM_TEMPORARY) {
5020 if (first_reads[inst->src[j].index] == -1)
5021 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
5022 }
5023 }
5024 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5025 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
5026 if (first_reads[inst->tex_offsets[j].index] == -1)
5027 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
5028 }
5029 }
5030 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5031 if (depth++ == 0)
5032 loop_start = i;
5033 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5034 if (--depth == 0)
5035 loop_start = -1;
5036 }
5037 assert(depth >= 0);
5038 i++;
5039 }
5040 }
5041
5042 void
5043 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
5044 {
5045 int depth = 0; /* loop depth */
5046 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5047 unsigned i = 0, j;
5048 int k;
5049 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5050 for (j = 0; j < num_inst_src_regs(inst); j++) {
5051 if (inst->src[j].file == PROGRAM_TEMPORARY)
5052 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
5053 }
5054 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5055 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
5056 if (first_writes[inst->dst[j].index] == -1)
5057 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5058 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
5059 }
5060 }
5061 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5062 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
5063 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
5064 }
5065 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5066 if (depth++ == 0)
5067 loop_start = i;
5068 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5069 if (--depth == 0) {
5070 loop_start = -1;
5071 for (k = 0; k < this->next_temp; k++) {
5072 if (last_reads[k] == -2) {
5073 last_reads[k] = i;
5074 }
5075 }
5076 }
5077 }
5078 assert(depth >= 0);
5079 i++;
5080 }
5081 }
5082
5083 void
5084 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
5085 {
5086 int depth = 0; /* loop depth */
5087 int i = 0, k;
5088 unsigned j;
5089
5090 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5091 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5092 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5093 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5094 }
5095
5096 if (inst->op == TGSI_OPCODE_BGNLOOP)
5097 depth++;
5098 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5099 if (--depth == 0) {
5100 for (k = 0; k < this->next_temp; k++) {
5101 if (last_writes[k] == -2) {
5102 last_writes[k] = i;
5103 }
5104 }
5105 }
5106 assert(depth >= 0);
5107 i++;
5108 }
5109 }
5110
5111 /*
5112 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5113 * channels for copy propagation and updates following instructions to
5114 * use the original versions.
5115 *
5116 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5117 * will occur. As an example, a TXP production before this pass:
5118 *
5119 * 0: MOV TEMP[1], INPUT[4].xyyy;
5120 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5121 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5122 *
5123 * and after:
5124 *
5125 * 0: MOV TEMP[1], INPUT[4].xyyy;
5126 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5127 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5128 *
5129 * which allows for dead code elimination on TEMP[1]'s writes.
5130 */
5131 void
5132 glsl_to_tgsi_visitor::copy_propagate(void)
5133 {
5134 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5135 glsl_to_tgsi_instruction *,
5136 this->next_temp * 4);
5137 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5138 int level = 0;
5139
5140 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5141 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5142 || inst->dst[0].index < this->next_temp);
5143
5144 /* First, do any copy propagation possible into the src regs. */
5145 for (int r = 0; r < 3; r++) {
5146 glsl_to_tgsi_instruction *first = NULL;
5147 bool good = true;
5148 int acp_base = inst->src[r].index * 4;
5149
5150 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5151 inst->src[r].reladdr ||
5152 inst->src[r].reladdr2)
5153 continue;
5154
5155 /* See if we can find entries in the ACP consisting of MOVs
5156 * from the same src register for all the swizzled channels
5157 * of this src register reference.
5158 */
5159 for (int i = 0; i < 4; i++) {
5160 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5161 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5162
5163 if (!copy_chan) {
5164 good = false;
5165 break;
5166 }
5167
5168 assert(acp_level[acp_base + src_chan] <= level);
5169
5170 if (!first) {
5171 first = copy_chan;
5172 } else {
5173 if (first->src[0].file != copy_chan->src[0].file ||
5174 first->src[0].index != copy_chan->src[0].index ||
5175 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5176 first->src[0].index2D != copy_chan->src[0].index2D) {
5177 good = false;
5178 break;
5179 }
5180 }
5181 }
5182
5183 if (good) {
5184 /* We've now validated that we can copy-propagate to
5185 * replace this src register reference. Do it.
5186 */
5187 inst->src[r].file = first->src[0].file;
5188 inst->src[r].index = first->src[0].index;
5189 inst->src[r].index2D = first->src[0].index2D;
5190 inst->src[r].has_index2 = first->src[0].has_index2;
5191 inst->src[r].double_reg2 = first->src[0].double_reg2;
5192 inst->src[r].array_id = first->src[0].array_id;
5193
5194 int swizzle = 0;
5195 for (int i = 0; i < 4; i++) {
5196 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5197 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5198 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5199 }
5200 inst->src[r].swizzle = swizzle;
5201 }
5202 }
5203
5204 switch (inst->op) {
5205 case TGSI_OPCODE_BGNLOOP:
5206 case TGSI_OPCODE_ENDLOOP:
5207 /* End of a basic block, clear the ACP entirely. */
5208 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5209 break;
5210
5211 case TGSI_OPCODE_IF:
5212 case TGSI_OPCODE_UIF:
5213 ++level;
5214 break;
5215
5216 case TGSI_OPCODE_ENDIF:
5217 case TGSI_OPCODE_ELSE:
5218 /* Clear all channels written inside the block from the ACP, but
5219 * leaving those that were not touched.
5220 */
5221 for (int r = 0; r < this->next_temp; r++) {
5222 for (int c = 0; c < 4; c++) {
5223 if (!acp[4 * r + c])
5224 continue;
5225
5226 if (acp_level[4 * r + c] >= level)
5227 acp[4 * r + c] = NULL;
5228 }
5229 }
5230 if (inst->op == TGSI_OPCODE_ENDIF)
5231 --level;
5232 break;
5233
5234 default:
5235 /* Continuing the block, clear any written channels from
5236 * the ACP.
5237 */
5238 for (int d = 0; d < 2; d++) {
5239 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5240 /* Any temporary might be written, so no copy propagation
5241 * across this instruction.
5242 */
5243 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5244 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5245 inst->dst[d].reladdr) {
5246 /* Any output might be written, so no copy propagation
5247 * from outputs across this instruction.
5248 */
5249 for (int r = 0; r < this->next_temp; r++) {
5250 for (int c = 0; c < 4; c++) {
5251 if (!acp[4 * r + c])
5252 continue;
5253
5254 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5255 acp[4 * r + c] = NULL;
5256 }
5257 }
5258 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5259 inst->dst[d].file == PROGRAM_OUTPUT) {
5260 /* Clear where it's used as dst. */
5261 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5262 for (int c = 0; c < 4; c++) {
5263 if (inst->dst[d].writemask & (1 << c))
5264 acp[4 * inst->dst[d].index + c] = NULL;
5265 }
5266 }
5267
5268 /* Clear where it's used as src. */
5269 for (int r = 0; r < this->next_temp; r++) {
5270 for (int c = 0; c < 4; c++) {
5271 if (!acp[4 * r + c])
5272 continue;
5273
5274 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5275
5276 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5277 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5278 inst->dst[d].writemask & (1 << src_chan)) {
5279 acp[4 * r + c] = NULL;
5280 }
5281 }
5282 }
5283 }
5284 }
5285 break;
5286 }
5287
5288 /* If this is a copy, add it to the ACP. */
5289 if (inst->op == TGSI_OPCODE_MOV &&
5290 inst->dst[0].file == PROGRAM_TEMPORARY &&
5291 !(inst->dst[0].file == inst->src[0].file &&
5292 inst->dst[0].index == inst->src[0].index) &&
5293 !inst->dst[0].reladdr &&
5294 !inst->dst[0].reladdr2 &&
5295 !inst->saturate &&
5296 inst->src[0].file != PROGRAM_ARRAY &&
5297 (inst->src[0].file != PROGRAM_OUTPUT ||
5298 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5299 !inst->src[0].reladdr &&
5300 !inst->src[0].reladdr2 &&
5301 !inst->src[0].negate &&
5302 !inst->src[0].abs) {
5303 for (int i = 0; i < 4; i++) {
5304 if (inst->dst[0].writemask & (1 << i)) {
5305 acp[4 * inst->dst[0].index + i] = inst;
5306 acp_level[4 * inst->dst[0].index + i] = level;
5307 }
5308 }
5309 }
5310 }
5311
5312 ralloc_free(acp_level);
5313 ralloc_free(acp);
5314 }
5315
5316 static void
5317 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5318 {
5319 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5320 /* Clear where it's used as src. */
5321 int swz = GET_SWZ(reladdr->swizzle, 0);
5322 writes[4 * reladdr->index + swz] = NULL;
5323 }
5324 }
5325
5326 /*
5327 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5328 * code elimination.
5329 *
5330 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5331 * will occur. As an example, a TXP production after copy propagation but
5332 * before this pass:
5333 *
5334 * 0: MOV TEMP[1], INPUT[4].xyyy;
5335 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5336 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5337 *
5338 * and after this pass:
5339 *
5340 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5341 */
5342 int
5343 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5344 {
5345 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5346 glsl_to_tgsi_instruction *,
5347 this->next_temp * 4);
5348 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5349 int level = 0;
5350 int removed = 0;
5351
5352 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5353 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5354 || inst->dst[0].index < this->next_temp);
5355
5356 switch (inst->op) {
5357 case TGSI_OPCODE_BGNLOOP:
5358 case TGSI_OPCODE_ENDLOOP:
5359 case TGSI_OPCODE_CONT:
5360 case TGSI_OPCODE_BRK:
5361 /* End of a basic block, clear the write array entirely.
5362 *
5363 * This keeps us from killing dead code when the writes are
5364 * on either side of a loop, even when the register isn't touched
5365 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5366 * dead code of this type, so it shouldn't make a difference as long as
5367 * the dead code elimination pass in the GLSL compiler does its job.
5368 */
5369 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5370 break;
5371
5372 case TGSI_OPCODE_ENDIF:
5373 case TGSI_OPCODE_ELSE:
5374 /* Promote the recorded level of all channels written inside the
5375 * preceding if or else block to the level above the if/else block.
5376 */
5377 for (int r = 0; r < this->next_temp; r++) {
5378 for (int c = 0; c < 4; c++) {
5379 if (!writes[4 * r + c])
5380 continue;
5381
5382 if (write_level[4 * r + c] == level)
5383 write_level[4 * r + c] = level-1;
5384 }
5385 }
5386 if (inst->op == TGSI_OPCODE_ENDIF)
5387 --level;
5388 break;
5389
5390 case TGSI_OPCODE_IF:
5391 case TGSI_OPCODE_UIF:
5392 ++level;
5393 /* fallthrough to default case to mark the condition as read */
5394 default:
5395 /* Continuing the block, clear any channels from the write array that
5396 * are read by this instruction.
5397 */
5398 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5399 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5400 /* Any temporary might be read, so no dead code elimination
5401 * across this instruction.
5402 */
5403 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5404 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5405 /* Clear where it's used as src. */
5406 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5407 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5408 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5409 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5410
5411 for (int c = 0; c < 4; c++) {
5412 if (src_chans & (1 << c))
5413 writes[4 * inst->src[i].index + c] = NULL;
5414 }
5415 }
5416 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5417 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5418 }
5419 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5420 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5421 /* Any temporary might be read, so no dead code elimination
5422 * across this instruction.
5423 */
5424 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5425 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5426 /* Clear where it's used as src. */
5427 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5428 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5429 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5430 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5431
5432 for (int c = 0; c < 4; c++) {
5433 if (src_chans & (1 << c))
5434 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5435 }
5436 }
5437 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5438 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5439 }
5440
5441 if (inst->resource.file == PROGRAM_TEMPORARY) {
5442 int src_chans;
5443
5444 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5445 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5446 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5447 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5448
5449 for (int c = 0; c < 4; c++) {
5450 if (src_chans & (1 << c))
5451 writes[4 * inst->resource.index + c] = NULL;
5452 }
5453 }
5454 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5455 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5456
5457 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5458 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5459 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5460 }
5461 break;
5462 }
5463
5464 /* If this instruction writes to a temporary, add it to the write array.
5465 * If there is already an instruction in the write array for one or more
5466 * of the channels, flag that channel write as dead.
5467 */
5468 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5469 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5470 !inst->dst[i].reladdr) {
5471 for (int c = 0; c < 4; c++) {
5472 if (inst->dst[i].writemask & (1 << c)) {
5473 if (writes[4 * inst->dst[i].index + c]) {
5474 if (write_level[4 * inst->dst[i].index + c] < level)
5475 continue;
5476 else
5477 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5478 }
5479 writes[4 * inst->dst[i].index + c] = inst;
5480 write_level[4 * inst->dst[i].index + c] = level;
5481 }
5482 }
5483 }
5484 }
5485 }
5486
5487 /* Anything still in the write array at this point is dead code. */
5488 for (int r = 0; r < this->next_temp; r++) {
5489 for (int c = 0; c < 4; c++) {
5490 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5491 if (inst)
5492 inst->dead_mask |= (1 << c);
5493 }
5494 }
5495
5496 /* Now actually remove the instructions that are completely dead and update
5497 * the writemask of other instructions with dead channels.
5498 */
5499 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5500 if (!inst->dead_mask || !inst->dst[0].writemask)
5501 continue;
5502 /* No amount of dead masks should remove memory stores */
5503 if (inst->info->is_store)
5504 continue;
5505
5506 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5507 inst->remove();
5508 delete inst;
5509 removed++;
5510 } else {
5511 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5512 if (inst->dead_mask == WRITEMASK_XY ||
5513 inst->dead_mask == WRITEMASK_ZW)
5514 inst->dst[0].writemask &= ~(inst->dead_mask);
5515 } else
5516 inst->dst[0].writemask &= ~(inst->dead_mask);
5517 }
5518 }
5519
5520 ralloc_free(write_level);
5521 ralloc_free(writes);
5522
5523 return removed;
5524 }
5525
5526 /* merge DFRACEXP instructions into one. */
5527 void
5528 glsl_to_tgsi_visitor::merge_two_dsts(void)
5529 {
5530 /* We never delete inst, but we may delete its successor. */
5531 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5532 glsl_to_tgsi_instruction *inst2;
5533 unsigned defined;
5534
5535 if (num_inst_dst_regs(inst) != 2)
5536 continue;
5537
5538 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5539 inst->dst[1].file != PROGRAM_UNDEFINED)
5540 continue;
5541
5542 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5543 inst->dst[1].file != PROGRAM_UNDEFINED);
5544
5545 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5546 defined = 1;
5547 else
5548 defined = 0;
5549
5550 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5551 while (!inst2->is_tail_sentinel()) {
5552 if (inst->op == inst2->op &&
5553 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5554 inst->src[0].file == inst2->src[0].file &&
5555 inst->src[0].index == inst2->src[0].index &&
5556 inst->src[0].type == inst2->src[0].type &&
5557 inst->src[0].swizzle == inst2->src[0].swizzle)
5558 break;
5559 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5560 }
5561
5562 if (inst2->is_tail_sentinel()) {
5563 /* Undefined destinations are not allowed, substitute with an unused
5564 * temporary register.
5565 */
5566 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5567 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5568 inst->dst[defined ^ 1].writemask = 0;
5569 continue;
5570 }
5571
5572 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5573 inst2->remove();
5574 delete inst2;
5575 }
5576 }
5577
5578 template <typename st_reg>
5579 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5580 {
5581 if (reg.file == PROGRAM_ARRAY) {
5582 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5583 has_indirect_access[reg.array_id] = true;
5584 if (reg.reladdr)
5585 test_indirect_access(*reg.reladdr, has_indirect_access);
5586 if (reg.reladdr2)
5587 test_indirect_access(*reg.reladdr2, has_indirect_access);
5588 }
5589 }
5590 }
5591
5592 template <typename st_reg>
5593 void remap_array(st_reg& reg, const int *array_remap_info,
5594 const bool *has_indirect_access)
5595 {
5596 if (reg.file == PROGRAM_ARRAY) {
5597 if (!has_indirect_access[reg.array_id]) {
5598 reg.file = PROGRAM_TEMPORARY;
5599 reg.index = reg.index + array_remap_info[reg.array_id];
5600 reg.array_id = 0;
5601 } else {
5602 reg.array_id = array_remap_info[reg.array_id];
5603 }
5604
5605 if (reg.reladdr)
5606 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5607
5608 if (reg.reladdr2)
5609 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5610 }
5611 }
5612
5613 /* One-dimensional arrays whose elements are only accessed directly are
5614 * replaced by an according set of temporary registers that then can become
5615 * subject to further optimization steps like copy propagation and
5616 * register merging.
5617 */
5618 void
5619 glsl_to_tgsi_visitor::split_arrays(void)
5620 {
5621 if (!next_array)
5622 return;
5623
5624 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5625
5626 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5627 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5628 test_indirect_access(inst->src[j], has_indirect_access);
5629
5630 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5631 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5632
5633 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5634 test_indirect_access(inst->dst[j], has_indirect_access);
5635
5636 test_indirect_access(inst->resource, has_indirect_access);
5637 }
5638
5639 unsigned array_offset = 0;
5640 unsigned n_remaining_arrays = 0;
5641
5642 /* Double use: For arrays that get split this value will contain
5643 * the base index of the temporary registers this array is replaced
5644 * with. For arrays that remain it contains the new array ID.
5645 */
5646 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5647 next_array + 1);
5648
5649 for (unsigned i = 1; i <= next_array; ++i) {
5650 if (!has_indirect_access[i]) {
5651 array_remap_info[i] = this->next_temp + array_offset;
5652 array_offset += array_sizes[i - 1];
5653 } else {
5654 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5655 array_remap_info[i] = ++n_remaining_arrays;
5656 }
5657 }
5658
5659 if (next_array != n_remaining_arrays) {
5660 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5661 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5662 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5663
5664 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5665 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5666
5667 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5668 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5669 }
5670 remap_array(inst->resource, array_remap_info, has_indirect_access);
5671 }
5672 }
5673
5674 ralloc_free(has_indirect_access);
5675 this->next_temp += array_offset;
5676 next_array = n_remaining_arrays;
5677 }
5678
5679 /* Merges temporary registers together where possible to reduce the number of
5680 * registers needed to run a program.
5681 *
5682 * Produces optimal code only after copy propagation and dead code elimination
5683 * have been run. */
5684 void
5685 glsl_to_tgsi_visitor::merge_registers(void)
5686 {
5687 class array_live_range *arr_live_ranges = NULL;
5688
5689 struct register_live_range *reg_live_ranges =
5690 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5691
5692 if (this->next_array > 0) {
5693 arr_live_ranges = new array_live_range[this->next_array];
5694 for (unsigned i = 0; i < this->next_array; ++i)
5695 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5696 }
5697
5698
5699 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5700 this->next_temp, reg_live_ranges,
5701 this->next_array, arr_live_ranges)) {
5702 struct rename_reg_pair *renames =
5703 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5704 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5705 reg_live_ranges, renames);
5706 rename_temp_registers(renames);
5707
5708 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5709 &this->instructions, arr_live_ranges);
5710 }
5711
5712 if (arr_live_ranges)
5713 delete[] arr_live_ranges;
5714
5715 ralloc_free(reg_live_ranges);
5716 }
5717
5718 /* Reassign indices to temporary registers by reusing unused indices created
5719 * by optimization passes. */
5720 void
5721 glsl_to_tgsi_visitor::renumber_registers(void)
5722 {
5723 int i = 0;
5724 int new_index = 0;
5725 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5726 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5727
5728 for (i = 0; i < this->next_temp; i++) {
5729 first_writes[i] = -1;
5730 }
5731 get_first_temp_write(first_writes);
5732
5733 for (i = 0; i < this->next_temp; i++) {
5734 if (first_writes[i] < 0) continue;
5735 if (i != new_index) {
5736 renames[i].new_reg = new_index;
5737 renames[i].valid = true;
5738 }
5739 new_index++;
5740 }
5741
5742 rename_temp_registers(renames);
5743 this->next_temp = new_index;
5744 ralloc_free(renames);
5745 ralloc_free(first_writes);
5746 }
5747
5748 #ifndef NDEBUG
5749 void glsl_to_tgsi_visitor::print_stats()
5750 {
5751 int narray_registers = 0;
5752 for (unsigned i = 0; i < this->next_array; ++i)
5753 narray_registers += this->array_sizes[i];
5754
5755 int ninstructions = 0;
5756 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5757 ++ninstructions;
5758 }
5759
5760 simple_mtx_lock(&print_stats_mutex);
5761 stats_log << next_array << ", "
5762 << next_temp << ", "
5763 << narray_registers << ", "
5764 << next_temp + narray_registers << ", "
5765 << ninstructions << "\n";
5766 simple_mtx_unlock(&print_stats_mutex);
5767 }
5768 #endif
5769 /* ------------------------- TGSI conversion stuff -------------------------- */
5770
5771 /**
5772 * Intermediate state used during shader translation.
5773 */
5774 struct st_translate {
5775 struct ureg_program *ureg;
5776
5777 unsigned temps_size;
5778 struct ureg_dst *temps;
5779
5780 struct ureg_dst *arrays;
5781 unsigned num_temp_arrays;
5782 struct ureg_src *constants;
5783 int num_constants;
5784 struct ureg_src *immediates;
5785 int num_immediates;
5786 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5787 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5788 struct ureg_dst address[3];
5789 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5790 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5791 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5792 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5793 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5794 struct ureg_src shared_memory;
5795 unsigned *array_sizes;
5796 struct inout_decl *input_decls;
5797 unsigned num_input_decls;
5798 struct inout_decl *output_decls;
5799 unsigned num_output_decls;
5800
5801 const ubyte *inputMapping;
5802 const ubyte *outputMapping;
5803
5804 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5805 bool need_uarl;
5806 bool tg4_component_in_swizzle;
5807 };
5808
5809 /**
5810 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5811 */
5812 static struct ureg_src
5813 emit_immediate(struct st_translate *t,
5814 gl_constant_value values[4],
5815 GLenum type, int size)
5816 {
5817 struct ureg_program *ureg = t->ureg;
5818
5819 switch (type) {
5820 case GL_FLOAT:
5821 return ureg_DECL_immediate(ureg, &values[0].f, size);
5822 case GL_DOUBLE:
5823 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5824 case GL_INT64_ARB:
5825 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5826 case GL_UNSIGNED_INT64_ARB:
5827 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5828 case GL_INT:
5829 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5830 case GL_UNSIGNED_INT:
5831 case GL_BOOL:
5832 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5833 default:
5834 assert(!"should not get here - type must be float, int, uint, or bool");
5835 return ureg_src_undef();
5836 }
5837 }
5838
5839 /**
5840 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5841 */
5842 static struct ureg_dst
5843 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5844 unsigned array_id)
5845 {
5846 unsigned array;
5847
5848 switch (file) {
5849 case PROGRAM_UNDEFINED:
5850 return ureg_dst_undef();
5851
5852 case PROGRAM_TEMPORARY:
5853 /* Allocate space for temporaries on demand. */
5854 if (index >= t->temps_size) {
5855 const int inc = align(index - t->temps_size + 1, 4096);
5856
5857 t->temps = (struct ureg_dst*)
5858 realloc(t->temps,
5859 (t->temps_size + inc) * sizeof(struct ureg_dst));
5860 if (!t->temps)
5861 return ureg_dst_undef();
5862
5863 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5864 t->temps_size += inc;
5865 }
5866
5867 if (ureg_dst_is_undef(t->temps[index]))
5868 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5869
5870 return t->temps[index];
5871
5872 case PROGRAM_ARRAY:
5873 assert(array_id && array_id <= t->num_temp_arrays);
5874 array = array_id - 1;
5875
5876 if (ureg_dst_is_undef(t->arrays[array]))
5877 t->arrays[array] = ureg_DECL_array_temporary(
5878 t->ureg, t->array_sizes[array], TRUE);
5879
5880 return ureg_dst_array_offset(t->arrays[array], index);
5881
5882 case PROGRAM_OUTPUT:
5883 if (!array_id) {
5884 if (t->procType == PIPE_SHADER_FRAGMENT)
5885 assert(index < 2 * FRAG_RESULT_MAX);
5886 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5887 t->procType == PIPE_SHADER_TESS_EVAL)
5888 assert(index < VARYING_SLOT_TESS_MAX);
5889 else
5890 assert(index < VARYING_SLOT_MAX);
5891
5892 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5893 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5894 return t->outputs[t->outputMapping[index]];
5895 }
5896 else {
5897 struct inout_decl *decl =
5898 find_inout_array(t->output_decls,
5899 t->num_output_decls, array_id);
5900 unsigned mesa_index = decl->mesa_index;
5901 int slot = t->outputMapping[mesa_index];
5902
5903 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5904
5905 struct ureg_dst dst = t->outputs[slot];
5906 dst.ArrayID = array_id;
5907 return ureg_dst_array_offset(dst, index - mesa_index);
5908 }
5909
5910 case PROGRAM_ADDRESS:
5911 return t->address[index];
5912
5913 default:
5914 assert(!"unknown dst register file");
5915 return ureg_dst_undef();
5916 }
5917 }
5918
5919 static struct ureg_src
5920 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5921
5922 static struct ureg_src
5923 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5924 unsigned addr_index)
5925 {
5926 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5927 return ureg_src(t->address[addr_index]);
5928
5929 return translate_src(t, reladdr);
5930 }
5931
5932 /**
5933 * Create a TGSI ureg_dst register from an st_dst_reg.
5934 */
5935 static struct ureg_dst
5936 translate_dst(struct st_translate *t,
5937 const st_dst_reg *dst_reg,
5938 bool saturate)
5939 {
5940 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5941 dst_reg->array_id);
5942
5943 if (dst.File == TGSI_FILE_NULL)
5944 return dst;
5945
5946 dst = ureg_writemask(dst, dst_reg->writemask);
5947
5948 if (saturate)
5949 dst = ureg_saturate(dst);
5950
5951 if (dst_reg->reladdr != NULL) {
5952 assert(dst_reg->file != PROGRAM_TEMPORARY);
5953 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5954 }
5955
5956 if (dst_reg->has_index2) {
5957 if (dst_reg->reladdr2)
5958 dst = ureg_dst_dimension_indirect(dst,
5959 translate_addr(t, dst_reg->reladdr2, 1),
5960 dst_reg->index2D);
5961 else
5962 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5963 }
5964
5965 return dst;
5966 }
5967
5968 /**
5969 * Create a TGSI ureg_src register from an st_src_reg.
5970 */
5971 static struct ureg_src
5972 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5973 {
5974 struct ureg_src src;
5975 int index = src_reg->index;
5976 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5977
5978 switch (src_reg->file) {
5979 case PROGRAM_UNDEFINED:
5980 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5981 break;
5982
5983 case PROGRAM_TEMPORARY:
5984 case PROGRAM_ARRAY:
5985 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5986 src_reg->array_id));
5987 break;
5988
5989 case PROGRAM_OUTPUT: {
5990 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5991 src_reg->array_id);
5992 assert(dst.WriteMask != 0);
5993 unsigned shift = ffs(dst.WriteMask) - 1;
5994 src = ureg_swizzle(ureg_src(dst),
5995 shift,
5996 MIN2(shift + 1, 3),
5997 MIN2(shift + 2, 3),
5998 MIN2(shift + 3, 3));
5999 break;
6000 }
6001
6002 case PROGRAM_UNIFORM:
6003 assert(src_reg->index >= 0);
6004 src = src_reg->index < t->num_constants ?
6005 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6006 break;
6007 case PROGRAM_STATE_VAR:
6008 case PROGRAM_CONSTANT: /* ie, immediate */
6009 if (src_reg->has_index2)
6010 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6011 else
6012 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6013 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6014 break;
6015
6016 case PROGRAM_IMMEDIATE:
6017 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6018 src = t->immediates[src_reg->index];
6019 break;
6020
6021 case PROGRAM_INPUT:
6022 /* GLSL inputs are 64-bit containers, so we have to
6023 * map back to the original index and add the offset after
6024 * mapping. */
6025 index -= double_reg2;
6026 if (!src_reg->array_id) {
6027 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6028 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6029 src = t->inputs[t->inputMapping[index] + double_reg2];
6030 }
6031 else {
6032 struct inout_decl *decl = find_inout_array(t->input_decls,
6033 t->num_input_decls,
6034 src_reg->array_id);
6035 unsigned mesa_index = decl->mesa_index;
6036 int slot = t->inputMapping[mesa_index];
6037
6038 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6039
6040 src = t->inputs[slot];
6041 src.ArrayID = src_reg->array_id;
6042 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6043 }
6044 break;
6045
6046 case PROGRAM_ADDRESS:
6047 src = ureg_src(t->address[src_reg->index]);
6048 break;
6049
6050 case PROGRAM_SYSTEM_VALUE:
6051 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6052 src = t->systemValues[src_reg->index];
6053 break;
6054
6055 case PROGRAM_HW_ATOMIC:
6056 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6057 src_reg->array_id);
6058 break;
6059
6060 default:
6061 assert(!"unknown src register file");
6062 return ureg_src_undef();
6063 }
6064
6065 if (src_reg->has_index2) {
6066 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6067 * and UBO constant buffers (buffer, position).
6068 */
6069 if (src_reg->reladdr2)
6070 src = ureg_src_dimension_indirect(src,
6071 translate_addr(t, src_reg->reladdr2, 1),
6072 src_reg->index2D);
6073 else
6074 src = ureg_src_dimension(src, src_reg->index2D);
6075 }
6076
6077 src = ureg_swizzle(src,
6078 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6079 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6080 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6081 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6082
6083 if (src_reg->abs)
6084 src = ureg_abs(src);
6085
6086 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6087 src = ureg_negate(src);
6088
6089 if (src_reg->reladdr != NULL) {
6090 assert(src_reg->file != PROGRAM_TEMPORARY);
6091 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6092 }
6093
6094 return src;
6095 }
6096
6097 static struct tgsi_texture_offset
6098 translate_tex_offset(struct st_translate *t,
6099 const st_src_reg *in_offset)
6100 {
6101 struct tgsi_texture_offset offset;
6102 struct ureg_src src = translate_src(t, in_offset);
6103
6104 offset.File = src.File;
6105 offset.Index = src.Index;
6106 offset.SwizzleX = src.SwizzleX;
6107 offset.SwizzleY = src.SwizzleY;
6108 offset.SwizzleZ = src.SwizzleZ;
6109 offset.Padding = 0;
6110
6111 assert(!src.Indirect);
6112 assert(!src.DimIndirect);
6113 assert(!src.Dimension);
6114 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6115 assert(!src.Negate);
6116
6117 return offset;
6118 }
6119
6120 static void
6121 compile_tgsi_instruction(struct st_translate *t,
6122 const glsl_to_tgsi_instruction *inst)
6123 {
6124 struct ureg_program *ureg = t->ureg;
6125 int i;
6126 struct ureg_dst dst[2];
6127 struct ureg_src src[4];
6128 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6129
6130 int num_dst;
6131 int num_src;
6132 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6133
6134 num_dst = num_inst_dst_regs(inst);
6135 num_src = num_inst_src_regs(inst);
6136
6137 for (i = 0; i < num_dst; i++)
6138 dst[i] = translate_dst(t,
6139 &inst->dst[i],
6140 inst->saturate);
6141
6142 for (i = 0; i < num_src; i++)
6143 src[i] = translate_src(t, &inst->src[i]);
6144
6145 switch (inst->op) {
6146 case TGSI_OPCODE_BGNLOOP:
6147 case TGSI_OPCODE_ELSE:
6148 case TGSI_OPCODE_ENDLOOP:
6149 case TGSI_OPCODE_IF:
6150 case TGSI_OPCODE_UIF:
6151 assert(num_dst == 0);
6152 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6153 return;
6154
6155 case TGSI_OPCODE_TEX:
6156 case TGSI_OPCODE_TEX_LZ:
6157 case TGSI_OPCODE_TXB:
6158 case TGSI_OPCODE_TXD:
6159 case TGSI_OPCODE_TXL:
6160 case TGSI_OPCODE_TXP:
6161 case TGSI_OPCODE_TXQ:
6162 case TGSI_OPCODE_TXQS:
6163 case TGSI_OPCODE_TXF:
6164 case TGSI_OPCODE_TXF_LZ:
6165 case TGSI_OPCODE_TEX2:
6166 case TGSI_OPCODE_TXB2:
6167 case TGSI_OPCODE_TXL2:
6168 case TGSI_OPCODE_TG4:
6169 case TGSI_OPCODE_LODQ:
6170 case TGSI_OPCODE_SAMP2HND:
6171 if (inst->resource.file == PROGRAM_SAMPLER) {
6172 src[num_src] = t->samplers[inst->resource.index];
6173 if (t->tg4_component_in_swizzle && inst->op == TGSI_OPCODE_TG4)
6174 src[num_src].SwizzleX = inst->gather_component;
6175 } else {
6176 /* Bindless samplers. */
6177 src[num_src] = translate_src(t, &inst->resource);
6178 }
6179 assert(src[num_src].File != TGSI_FILE_NULL);
6180 if (inst->resource.reladdr)
6181 src[num_src] =
6182 ureg_src_indirect(src[num_src],
6183 translate_addr(t, inst->resource.reladdr, 2));
6184 num_src++;
6185 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6186 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6187 }
6188 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6189
6190 ureg_tex_insn(ureg,
6191 inst->op,
6192 dst, num_dst,
6193 tex_target,
6194 st_translate_texture_type(inst->tex_type),
6195 texoffsets, inst->tex_offset_num_offset,
6196 src, num_src);
6197 return;
6198
6199 case TGSI_OPCODE_RESQ:
6200 case TGSI_OPCODE_LOAD:
6201 case TGSI_OPCODE_ATOMUADD:
6202 case TGSI_OPCODE_ATOMXCHG:
6203 case TGSI_OPCODE_ATOMCAS:
6204 case TGSI_OPCODE_ATOMAND:
6205 case TGSI_OPCODE_ATOMOR:
6206 case TGSI_OPCODE_ATOMXOR:
6207 case TGSI_OPCODE_ATOMUMIN:
6208 case TGSI_OPCODE_ATOMUMAX:
6209 case TGSI_OPCODE_ATOMIMIN:
6210 case TGSI_OPCODE_ATOMIMAX:
6211 case TGSI_OPCODE_ATOMFADD:
6212 case TGSI_OPCODE_IMG2HND:
6213 case TGSI_OPCODE_ATOMINC_WRAP:
6214 case TGSI_OPCODE_ATOMDEC_WRAP:
6215 for (i = num_src - 1; i >= 0; i--)
6216 src[i + 1] = src[i];
6217 num_src++;
6218 if (inst->resource.file == PROGRAM_MEMORY) {
6219 src[0] = t->shared_memory;
6220 } else if (inst->resource.file == PROGRAM_BUFFER) {
6221 src[0] = t->buffers[inst->resource.index];
6222 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6223 src[0] = translate_src(t, &inst->resource);
6224 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6225 assert(inst->resource.has_index2);
6226 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6227 } else {
6228 assert(inst->resource.file != PROGRAM_UNDEFINED);
6229 if (inst->resource.file == PROGRAM_IMAGE) {
6230 src[0] = t->images[inst->resource.index];
6231 } else {
6232 /* Bindless images. */
6233 src[0] = translate_src(t, &inst->resource);
6234 }
6235 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6236 }
6237 if (inst->resource.reladdr)
6238 src[0] = ureg_src_indirect(src[0],
6239 translate_addr(t, inst->resource.reladdr, 2));
6240 assert(src[0].File != TGSI_FILE_NULL);
6241 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6242 inst->buffer_access,
6243 tex_target, inst->image_format);
6244 break;
6245
6246 case TGSI_OPCODE_STORE:
6247 if (inst->resource.file == PROGRAM_MEMORY) {
6248 dst[0] = ureg_dst(t->shared_memory);
6249 } else if (inst->resource.file == PROGRAM_BUFFER) {
6250 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6251 } else {
6252 if (inst->resource.file == PROGRAM_IMAGE) {
6253 dst[0] = ureg_dst(t->images[inst->resource.index]);
6254 } else {
6255 /* Bindless images. */
6256 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6257 }
6258 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6259 }
6260 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6261 if (inst->resource.reladdr)
6262 dst[0] = ureg_dst_indirect(dst[0],
6263 translate_addr(t, inst->resource.reladdr, 2));
6264 assert(dst[0].File != TGSI_FILE_NULL);
6265 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6266 inst->buffer_access,
6267 tex_target, inst->image_format);
6268 break;
6269
6270 default:
6271 ureg_insn(ureg,
6272 inst->op,
6273 dst, num_dst,
6274 src, num_src, inst->precise);
6275 break;
6276 }
6277 }
6278
6279 /* Invert SamplePos.y when rendering to the default framebuffer. */
6280 static void
6281 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6282 {
6283 struct ureg_program *ureg = t->ureg;
6284
6285 assert(wpos_y_transform >= 0);
6286 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6287 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6288 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6289 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6290
6291 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6292 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6293
6294 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6295 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6296 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6297 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6298 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6299 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6300 samplepos_sysval);
6301
6302 /* Use the result in place of the system value. */
6303 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6304 }
6305
6306
6307 /**
6308 * Emit the TGSI instructions for inverting and adjusting WPOS.
6309 * This code is unavoidable because it also depends on whether
6310 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6311 */
6312 static void
6313 emit_wpos_adjustment(struct gl_context *ctx,
6314 struct st_translate *t,
6315 int wpos_transform_const,
6316 boolean invert,
6317 GLfloat adjX, GLfloat adjY[2])
6318 {
6319 struct ureg_program *ureg = t->ureg;
6320
6321 assert(wpos_transform_const >= 0);
6322
6323 /* Fragment program uses fragment position input.
6324 * Need to replace instances of INPUT[WPOS] with temp T
6325 * where T = INPUT[WPOS] is inverted by Y.
6326 */
6327 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6328 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6329 struct ureg_src *wpos =
6330 ctx->Const.GLSLFragCoordIsSysVal ?
6331 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6332 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6333 struct ureg_src wpos_input = *wpos;
6334
6335 /* First, apply the coordinate shift: */
6336 if (adjX || adjY[0] || adjY[1]) {
6337 if (adjY[0] != adjY[1]) {
6338 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6339 * depending on whether inversion is actually going to be applied
6340 * or not, which is determined by testing against the inversion
6341 * state variable used below, which will be either +1 or -1.
6342 */
6343 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6344
6345 ureg_CMP(ureg, adj_temp,
6346 ureg_scalar(wpostrans, invert ? 2 : 0),
6347 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6348 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6349 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6350 } else {
6351 ureg_ADD(ureg, wpos_temp, wpos_input,
6352 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6353 }
6354 wpos_input = ureg_src(wpos_temp);
6355 } else {
6356 /* MOV wpos_temp, input[wpos]
6357 */
6358 ureg_MOV(ureg, wpos_temp, wpos_input);
6359 }
6360
6361 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6362 * inversion/identity, or the other way around if we're drawing to an FBO.
6363 */
6364 if (invert) {
6365 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6366 */
6367 ureg_MAD(ureg,
6368 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6369 wpos_input,
6370 ureg_scalar(wpostrans, 0),
6371 ureg_scalar(wpostrans, 1));
6372 } else {
6373 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6374 */
6375 ureg_MAD(ureg,
6376 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6377 wpos_input,
6378 ureg_scalar(wpostrans, 2),
6379 ureg_scalar(wpostrans, 3));
6380 }
6381
6382 /* Use wpos_temp as position input from here on:
6383 */
6384 *wpos = ureg_src(wpos_temp);
6385 }
6386
6387
6388 /**
6389 * Emit fragment position/ooordinate code.
6390 */
6391 static void
6392 emit_wpos(struct st_context *st,
6393 struct st_translate *t,
6394 const struct gl_program *program,
6395 struct ureg_program *ureg,
6396 int wpos_transform_const)
6397 {
6398 struct pipe_screen *pscreen = st->pipe->screen;
6399 GLfloat adjX = 0.0f;
6400 GLfloat adjY[2] = { 0.0f, 0.0f };
6401 boolean invert = FALSE;
6402
6403 /* Query the pixel center conventions supported by the pipe driver and set
6404 * adjX, adjY to help out if it cannot handle the requested one internally.
6405 *
6406 * The bias of the y-coordinate depends on whether y-inversion takes place
6407 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6408 * drawing to an FBO (causes additional inversion), and whether the pipe
6409 * driver origin and the requested origin differ (the latter condition is
6410 * stored in the 'invert' variable).
6411 *
6412 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6413 *
6414 * center shift only:
6415 * i -> h: +0.5
6416 * h -> i: -0.5
6417 *
6418 * inversion only:
6419 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6420 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6421 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6422 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6423 *
6424 * inversion and center shift:
6425 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6426 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6427 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6428 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6429 */
6430 if (program->info.fs.origin_upper_left) {
6431 /* Fragment shader wants origin in upper-left */
6432 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6433 /* the driver supports upper-left origin */
6434 }
6435 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6436 /* the driver supports lower-left origin, need to invert Y */
6437 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6438 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6439 invert = TRUE;
6440 }
6441 else
6442 assert(0);
6443 }
6444 else {
6445 /* Fragment shader wants origin in lower-left */
6446 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6447 /* the driver supports lower-left origin */
6448 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6449 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6450 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6451 /* the driver supports upper-left origin, need to invert Y */
6452 invert = TRUE;
6453 else
6454 assert(0);
6455 }
6456
6457 if (program->info.fs.pixel_center_integer) {
6458 /* Fragment shader wants pixel center integer */
6459 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6460 /* the driver supports pixel center integer */
6461 adjY[1] = 1.0f;
6462 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6463 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6464 }
6465 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6466 /* the driver supports pixel center half integer, need to bias X,Y */
6467 adjX = -0.5f;
6468 adjY[0] = -0.5f;
6469 adjY[1] = 0.5f;
6470 }
6471 else
6472 assert(0);
6473 }
6474 else {
6475 /* Fragment shader wants pixel center half integer */
6476 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6477 /* the driver supports pixel center half integer */
6478 }
6479 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6480 /* the driver supports pixel center integer, need to bias X,Y */
6481 adjX = adjY[0] = adjY[1] = 0.5f;
6482 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6483 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6484 }
6485 else
6486 assert(0);
6487 }
6488
6489 /* we invert after adjustment so that we avoid the MOV to temporary,
6490 * and reuse the adjustment ADD instead */
6491 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6492 }
6493
6494 /**
6495 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6496 * TGSI uses +1 for front, -1 for back.
6497 * This function converts the TGSI value to the GL value. Simply clamping/
6498 * saturating the value to [0,1] does the job.
6499 */
6500 static void
6501 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6502 {
6503 struct ureg_program *ureg = t->ureg;
6504 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6505 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6506
6507 if (ctx->Const.NativeIntegers) {
6508 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6509 }
6510 else {
6511 /* MOV_SAT face_temp, input[face] */
6512 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6513 }
6514
6515 /* Use face_temp as face input from here on: */
6516 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6517 }
6518
6519 static void
6520 emit_compute_block_size(const struct gl_program *prog,
6521 struct ureg_program *ureg) {
6522 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6523 prog->info.cs.local_size[0]);
6524 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6525 prog->info.cs.local_size[1]);
6526 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6527 prog->info.cs.local_size[2]);
6528 }
6529
6530 struct sort_inout_decls {
6531 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6532 return mapping[a.mesa_index] < mapping[b.mesa_index];
6533 }
6534
6535 const ubyte *mapping;
6536 };
6537
6538 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6539 *
6540 * This is for the benefit of older drivers which are broken when the
6541 * declarations aren't sorted in this way.
6542 */
6543 static void
6544 sort_inout_decls_by_slot(struct inout_decl *decls,
6545 unsigned count,
6546 const ubyte mapping[])
6547 {
6548 sort_inout_decls sorter;
6549 sorter.mapping = mapping;
6550 std::sort(decls, decls + count, sorter);
6551 }
6552
6553 static enum tgsi_interpolate_mode
6554 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6555 {
6556 switch (glsl_qual) {
6557 case INTERP_MODE_NONE:
6558 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6559 return TGSI_INTERPOLATE_COLOR;
6560 return TGSI_INTERPOLATE_PERSPECTIVE;
6561 case INTERP_MODE_SMOOTH:
6562 return TGSI_INTERPOLATE_PERSPECTIVE;
6563 case INTERP_MODE_FLAT:
6564 return TGSI_INTERPOLATE_CONSTANT;
6565 case INTERP_MODE_NOPERSPECTIVE:
6566 return TGSI_INTERPOLATE_LINEAR;
6567 default:
6568 assert(0 && "unexpected interp mode in st_translate_interp()");
6569 return TGSI_INTERPOLATE_PERSPECTIVE;
6570 }
6571 }
6572
6573 /**
6574 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6575 * \param program the program to translate
6576 * \param numInputs number of input registers used
6577 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6578 * input indexes
6579 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6580 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6581 * each input
6582 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6583 * \param numOutputs number of output registers used
6584 * \param outputMapping maps Mesa fragment program outputs to TGSI
6585 * generic outputs
6586 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6587 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6588 * each output
6589 *
6590 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6591 */
6592 extern "C" enum pipe_error
6593 st_translate_program(
6594 struct gl_context *ctx,
6595 enum pipe_shader_type procType,
6596 struct ureg_program *ureg,
6597 glsl_to_tgsi_visitor *program,
6598 const struct gl_program *proginfo,
6599 GLuint numInputs,
6600 const ubyte inputMapping[],
6601 const ubyte inputSlotToAttr[],
6602 const ubyte inputSemanticName[],
6603 const ubyte inputSemanticIndex[],
6604 const ubyte interpMode[],
6605 GLuint numOutputs,
6606 const ubyte outputMapping[],
6607 const ubyte outputSemanticName[],
6608 const ubyte outputSemanticIndex[])
6609 {
6610 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6611 struct st_translate *t;
6612 unsigned i;
6613 struct gl_program_constants *frag_const =
6614 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6615 enum pipe_error ret = PIPE_OK;
6616
6617 assert(numInputs <= ARRAY_SIZE(t->inputs));
6618 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6619
6620 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6621 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6622 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6623 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6624 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6625 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6626 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6627 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6628 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6629 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6630
6631 t = CALLOC_STRUCT(st_translate);
6632 if (!t) {
6633 ret = PIPE_ERROR_OUT_OF_MEMORY;
6634 goto out;
6635 }
6636
6637 t->procType = procType;
6638 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6639 t->tg4_component_in_swizzle = screen->get_param(screen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
6640 t->inputMapping = inputMapping;
6641 t->outputMapping = outputMapping;
6642 t->ureg = ureg;
6643 t->num_temp_arrays = program->next_array;
6644 if (t->num_temp_arrays)
6645 t->arrays = (struct ureg_dst*)
6646 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6647
6648 /*
6649 * Declare input attributes.
6650 */
6651 switch (procType) {
6652 case PIPE_SHADER_FRAGMENT:
6653 case PIPE_SHADER_GEOMETRY:
6654 case PIPE_SHADER_TESS_EVAL:
6655 case PIPE_SHADER_TESS_CTRL:
6656 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6657
6658 for (i = 0; i < program->num_inputs; ++i) {
6659 struct inout_decl *decl = &program->inputs[i];
6660 unsigned slot = inputMapping[decl->mesa_index];
6661 struct ureg_src src;
6662 ubyte tgsi_usage_mask = decl->usage_mask;
6663
6664 if (glsl_base_type_is_64bit(decl->base_type)) {
6665 if (tgsi_usage_mask == 1)
6666 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6667 else if (tgsi_usage_mask == 2)
6668 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6669 else
6670 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6671 }
6672
6673 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6674 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6675 if (procType == PIPE_SHADER_FRAGMENT) {
6676 assert(interpMode);
6677 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6678 (enum tgsi_interpolate_mode) interpMode[slot] :
6679 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6680
6681 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6682 }
6683
6684 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6685 (enum tgsi_semantic) inputSemanticName[slot],
6686 inputSemanticIndex[slot],
6687 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6688 decl->array_id, decl->size);
6689
6690 for (unsigned j = 0; j < decl->size; ++j) {
6691 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6692 /* The ArrayID is set up in dst_register */
6693 t->inputs[slot + j] = src;
6694 t->inputs[slot + j].ArrayID = 0;
6695 t->inputs[slot + j].Index += j;
6696 }
6697 }
6698 }
6699 break;
6700 case PIPE_SHADER_VERTEX:
6701 for (i = 0; i < numInputs; i++) {
6702 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6703 }
6704 break;
6705 case PIPE_SHADER_COMPUTE:
6706 break;
6707 default:
6708 assert(0);
6709 }
6710
6711 /*
6712 * Declare output attributes.
6713 */
6714 switch (procType) {
6715 case PIPE_SHADER_FRAGMENT:
6716 case PIPE_SHADER_COMPUTE:
6717 break;
6718 case PIPE_SHADER_GEOMETRY:
6719 case PIPE_SHADER_TESS_EVAL:
6720 case PIPE_SHADER_TESS_CTRL:
6721 case PIPE_SHADER_VERTEX:
6722 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6723
6724 for (i = 0; i < program->num_outputs; ++i) {
6725 struct inout_decl *decl = &program->outputs[i];
6726 unsigned slot = outputMapping[decl->mesa_index];
6727 struct ureg_dst dst;
6728 ubyte tgsi_usage_mask = decl->usage_mask;
6729
6730 if (glsl_base_type_is_64bit(decl->base_type)) {
6731 if (tgsi_usage_mask == 1)
6732 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6733 else if (tgsi_usage_mask == 2)
6734 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6735 else
6736 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6737 }
6738
6739 dst = ureg_DECL_output_layout(ureg,
6740 (enum tgsi_semantic) outputSemanticName[slot],
6741 outputSemanticIndex[slot],
6742 decl->gs_out_streams,
6743 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6744 dst.Invariant = decl->invariant;
6745 for (unsigned j = 0; j < decl->size; ++j) {
6746 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6747 /* The ArrayID is set up in dst_register */
6748 t->outputs[slot + j] = dst;
6749 t->outputs[slot + j].ArrayID = 0;
6750 t->outputs[slot + j].Index += j;
6751 t->outputs[slot + j].Invariant = decl->invariant;
6752 }
6753 }
6754 }
6755 break;
6756 default:
6757 assert(0);
6758 }
6759
6760 if (procType == PIPE_SHADER_FRAGMENT) {
6761 if (program->shader->Program->info.fs.early_fragment_tests ||
6762 program->shader->Program->info.fs.post_depth_coverage) {
6763 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6764
6765 if (program->shader->Program->info.fs.post_depth_coverage)
6766 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6767 }
6768
6769 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6770 /* Must do this after setting up t->inputs. */
6771 emit_wpos(st_context(ctx), t, proginfo, ureg,
6772 program->wpos_transform_const);
6773 }
6774
6775 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6776 emit_face_var(ctx, t);
6777
6778 for (i = 0; i < numOutputs; i++) {
6779 switch (outputSemanticName[i]) {
6780 case TGSI_SEMANTIC_POSITION:
6781 t->outputs[i] = ureg_DECL_output(ureg,
6782 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6783 outputSemanticIndex[i]);
6784 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6785 break;
6786 case TGSI_SEMANTIC_STENCIL:
6787 t->outputs[i] = ureg_DECL_output(ureg,
6788 TGSI_SEMANTIC_STENCIL, /* Stencil */
6789 outputSemanticIndex[i]);
6790 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6791 break;
6792 case TGSI_SEMANTIC_COLOR:
6793 t->outputs[i] = ureg_DECL_output(ureg,
6794 TGSI_SEMANTIC_COLOR,
6795 outputSemanticIndex[i]);
6796 break;
6797 case TGSI_SEMANTIC_SAMPLEMASK:
6798 t->outputs[i] = ureg_DECL_output(ureg,
6799 TGSI_SEMANTIC_SAMPLEMASK,
6800 outputSemanticIndex[i]);
6801 /* TODO: If we ever support more than 32 samples, this will have
6802 * to become an array.
6803 */
6804 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6805 break;
6806 default:
6807 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6808 ret = PIPE_ERROR_BAD_INPUT;
6809 goto out;
6810 }
6811 }
6812 }
6813 else if (procType == PIPE_SHADER_VERTEX) {
6814 for (i = 0; i < numOutputs; i++) {
6815 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6816 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6817 ureg_MOV(ureg,
6818 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6819 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6820 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6821 }
6822 }
6823 }
6824
6825 if (procType == PIPE_SHADER_COMPUTE) {
6826 emit_compute_block_size(proginfo, ureg);
6827 }
6828
6829 if (program->shader->Program->info.layer_viewport_relative)
6830 ureg_property(ureg, TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE, 1);
6831
6832 /* Declare address register.
6833 */
6834 if (program->num_address_regs > 0) {
6835 assert(program->num_address_regs <= 3);
6836 for (int i = 0; i < program->num_address_regs; i++)
6837 t->address[i] = ureg_DECL_address(ureg);
6838 }
6839
6840 /* Declare misc input registers
6841 */
6842 {
6843 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6844
6845 for (i = 0; sysInputs; i++) {
6846 if (sysInputs & (1ull << i)) {
6847 enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
6848
6849 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6850
6851 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6852 semName == TGSI_SEMANTIC_VERTEXID) {
6853 /* From Gallium perspective, these system values are always
6854 * integer, and require native integer support. However, if
6855 * native integer is supported on the vertex stage but not the
6856 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6857 * assumes these system values are floats. To resolve the
6858 * inconsistency, we insert a U2F.
6859 */
6860 struct st_context *st = st_context(ctx);
6861 struct pipe_screen *pscreen = st->pipe->screen;
6862 assert(procType == PIPE_SHADER_VERTEX);
6863 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6864 (void) pscreen;
6865 if (!ctx->Const.NativeIntegers) {
6866 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6867 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6868 t->systemValues[i]);
6869 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6870 }
6871 }
6872
6873 if (procType == PIPE_SHADER_FRAGMENT &&
6874 semName == TGSI_SEMANTIC_POSITION)
6875 emit_wpos(st_context(ctx), t, proginfo, ureg,
6876 program->wpos_transform_const);
6877
6878 if (procType == PIPE_SHADER_FRAGMENT &&
6879 semName == TGSI_SEMANTIC_SAMPLEPOS)
6880 emit_samplepos_adjustment(t, program->wpos_transform_const);
6881
6882 sysInputs &= ~(1ull << i);
6883 }
6884 }
6885 }
6886
6887 t->array_sizes = program->array_sizes;
6888 t->input_decls = program->inputs;
6889 t->num_input_decls = program->num_inputs;
6890 t->output_decls = program->outputs;
6891 t->num_output_decls = program->num_outputs;
6892
6893 /* Emit constants and uniforms. TGSI uses a single index space for these,
6894 * so we put all the translated regs in t->constants.
6895 */
6896 if (proginfo->Parameters) {
6897 t->constants = (struct ureg_src *)
6898 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6899 if (t->constants == NULL) {
6900 ret = PIPE_ERROR_OUT_OF_MEMORY;
6901 goto out;
6902 }
6903 t->num_constants = proginfo->Parameters->NumParameters;
6904
6905 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6906 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6907
6908 switch (proginfo->Parameters->Parameters[i].Type) {
6909 case PROGRAM_STATE_VAR:
6910 case PROGRAM_UNIFORM:
6911 t->constants[i] = ureg_DECL_constant(ureg, i);
6912 break;
6913
6914 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6915 * addressing of the const buffer.
6916 * FIXME: Be smarter and recognize param arrays:
6917 * indirect addressing is only valid within the referenced
6918 * array.
6919 */
6920 case PROGRAM_CONSTANT:
6921 if (program->indirect_addr_consts)
6922 t->constants[i] = ureg_DECL_constant(ureg, i);
6923 else
6924 t->constants[i] = emit_immediate(t,
6925 proginfo->Parameters->ParameterValues + pvo,
6926 proginfo->Parameters->Parameters[i].DataType,
6927 4);
6928 break;
6929 default:
6930 break;
6931 }
6932 }
6933 }
6934
6935 for (i = 0; i < proginfo->info.num_ubos; i++) {
6936 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6937 unsigned num_const_vecs = (size + 15) / 16;
6938 unsigned first, last;
6939 assert(num_const_vecs > 0);
6940 first = 0;
6941 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6942 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6943 }
6944
6945 /* Emit immediate values.
6946 */
6947 t->immediates = (struct ureg_src *)
6948 calloc(program->num_immediates, sizeof(struct ureg_src));
6949 if (t->immediates == NULL) {
6950 ret = PIPE_ERROR_OUT_OF_MEMORY;
6951 goto out;
6952 }
6953 t->num_immediates = program->num_immediates;
6954
6955 i = 0;
6956 foreach_in_list(immediate_storage, imm, &program->immediates) {
6957 assert(i < program->num_immediates);
6958 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6959 }
6960 assert(i == program->num_immediates);
6961
6962 /* texture samplers */
6963 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6964 if (program->samplers_used & (1u << i)) {
6965 enum tgsi_return_type type =
6966 st_translate_texture_type(program->sampler_types[i]);
6967
6968 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6969
6970 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6971 type, type, type, type);
6972 }
6973 }
6974
6975 /* Declare atomic and shader storage buffers. */
6976 {
6977 struct gl_program *prog = program->prog;
6978
6979 if (!st_context(ctx)->has_hw_atomics) {
6980 for (i = 0; i < prog->info.num_abos; i++) {
6981 unsigned index = (prog->info.num_ssbos +
6982 prog->sh.AtomicBuffers[i]->Binding);
6983 assert(prog->sh.AtomicBuffers[i]->Binding <
6984 frag_const->MaxAtomicBuffers);
6985 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6986 }
6987 } else {
6988 for (i = 0; i < program->num_atomics; i++) {
6989 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6990 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6991 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6992 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6993 ainfo->array_id);
6994 }
6995 }
6996
6997 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6998 for (i = 0; i < prog->info.num_ssbos; i++) {
6999 t->buffers[i] = ureg_DECL_buffer(ureg, i, false);
7000 }
7001 }
7002
7003 if (program->use_shared_memory)
7004 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
7005
7006 for (i = 0; i < program->shader->Program->info.num_images; i++) {
7007 if (program->images_used & (1 << i)) {
7008 t->images[i] = ureg_DECL_image(ureg, i,
7009 program->image_targets[i],
7010 program->image_formats[i],
7011 program->image_wr[i],
7012 false);
7013 }
7014 }
7015
7016 /* Emit each instruction in turn:
7017 */
7018 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
7019 compile_tgsi_instruction(t, inst);
7020
7021 /* Set the next shader stage hint for VS and TES. */
7022 switch (procType) {
7023 case PIPE_SHADER_VERTEX:
7024 case PIPE_SHADER_TESS_EVAL:
7025 if (program->shader_program->SeparateShader)
7026 break;
7027
7028 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
7029 if (program->shader_program->_LinkedShaders[i]) {
7030 ureg_set_next_shader_processor(
7031 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
7032 break;
7033 }
7034 }
7035 break;
7036 default:
7037 ; /* nothing - silence compiler warning */
7038 }
7039
7040 out:
7041 if (t) {
7042 free(t->arrays);
7043 free(t->temps);
7044 free(t->constants);
7045 t->num_constants = 0;
7046 free(t->immediates);
7047 t->num_immediates = 0;
7048 FREE(t);
7049 }
7050
7051 return ret;
7052 }
7053 /* ----------------------------- End TGSI code ------------------------------ */
7054
7055
7056 /**
7057 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7058 * generating Mesa IR.
7059 */
7060 static struct gl_program *
7061 get_mesa_program_tgsi(struct gl_context *ctx,
7062 struct gl_shader_program *shader_program,
7063 struct gl_linked_shader *shader)
7064 {
7065 glsl_to_tgsi_visitor* v;
7066 struct gl_program *prog;
7067 struct gl_shader_compiler_options *options =
7068 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7069 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7070 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7071 unsigned skip_merge_registers;
7072
7073 validate_ir_tree(shader->ir);
7074
7075 prog = shader->Program;
7076
7077 prog->Parameters = _mesa_new_parameter_list();
7078 v = new glsl_to_tgsi_visitor();
7079 v->ctx = ctx;
7080 v->prog = prog;
7081 v->shader_program = shader_program;
7082 v->shader = shader;
7083 v->options = options;
7084 v->native_integers = ctx->Const.NativeIntegers;
7085
7086 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7087 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7088 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7089 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7090 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7091 PIPE_CAP_TGSI_TEX_TXF_LZ);
7092 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7093
7094 v->tg4_component_in_swizzle = pscreen->get_param(pscreen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
7095 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7096 _mesa_key_pointer_equal);
7097 skip_merge_registers =
7098 pscreen->get_shader_param(pscreen, ptarget,
7099 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7100
7101 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7102 prog->Parameters);
7103
7104 /* Remove reads from output registers. */
7105 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7106 lower_output_reads(shader->Stage, shader->ir);
7107
7108 /* Emit intermediate IR for main(). */
7109 visit_exec_list(shader->ir, v);
7110
7111 #if 0
7112 /* Print out some information (for debugging purposes) used by the
7113 * optimization passes. */
7114 {
7115 int i;
7116 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7117 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7118 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7119 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7120
7121 for (i = 0; i < v->next_temp; i++) {
7122 first_writes[i] = -1;
7123 first_reads[i] = -1;
7124 last_writes[i] = -1;
7125 last_reads[i] = -1;
7126 }
7127 v->get_first_temp_read(first_reads);
7128 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7129 v->get_last_temp_write(last_writes);
7130 for (i = 0; i < v->next_temp; i++)
7131 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7132 first_writes[i],
7133 last_reads[i],
7134 last_writes[i]);
7135 ralloc_free(first_writes);
7136 ralloc_free(first_reads);
7137 ralloc_free(last_writes);
7138 ralloc_free(last_reads);
7139 }
7140 #endif
7141
7142 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7143 v->simplify_cmp();
7144 v->copy_propagate();
7145
7146 while (v->eliminate_dead_code());
7147
7148 v->merge_two_dsts();
7149
7150 if (!skip_merge_registers) {
7151 v->split_arrays();
7152 v->copy_propagate();
7153 while (v->eliminate_dead_code());
7154
7155 v->merge_registers();
7156 v->copy_propagate();
7157 while (v->eliminate_dead_code());
7158 }
7159
7160 v->renumber_registers();
7161
7162 /* Write the END instruction. */
7163 v->emit_asm(NULL, TGSI_OPCODE_END);
7164
7165 if (ctx->_Shader->Flags & GLSL_DUMP) {
7166 _mesa_log("\n");
7167 _mesa_log("GLSL IR for linked %s program %d:\n",
7168 _mesa_shader_stage_to_string(shader->Stage),
7169 shader_program->Name);
7170 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7171 _mesa_log("\n\n");
7172 }
7173
7174 do_set_program_inouts(shader->ir, prog, shader->Stage);
7175
7176 _mesa_copy_linked_program_data(shader_program, shader);
7177
7178 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS)) {
7179 mark_array_io(v->inputs, v->num_inputs,
7180 &prog->info.inputs_read,
7181 prog->DualSlotInputs,
7182 &prog->info.patch_inputs_read);
7183
7184 mark_array_io(v->outputs, v->num_outputs,
7185 &prog->info.outputs_written, 0ULL,
7186 &prog->info.patch_outputs_written);
7187 } else {
7188 shrink_array_declarations(v->inputs, v->num_inputs,
7189 &prog->info.inputs_read,
7190 prog->DualSlotInputs,
7191 &prog->info.patch_inputs_read);
7192 shrink_array_declarations(v->outputs, v->num_outputs,
7193 &prog->info.outputs_written, 0ULL,
7194 &prog->info.patch_outputs_written);
7195 }
7196
7197 count_resources(v, prog);
7198
7199 /* The GLSL IR won't be needed anymore. */
7200 ralloc_free(shader->ir);
7201 shader->ir = NULL;
7202
7203 /* This must be done before the uniform storage is associated. */
7204 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7205 (prog->info.inputs_read & VARYING_BIT_POS ||
7206 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
7207 prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
7208 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7209 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7210 };
7211
7212 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7213 wposTransformState);
7214 }
7215
7216 /* Avoid reallocation of the program parameter list, because the uniform
7217 * storage is only associated with the original parameter list.
7218 * This should be enough for Bitmap and DrawPixels constants.
7219 */
7220 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7221
7222 /* This has to be done last. Any operation the can cause
7223 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7224 * program constant) has to happen before creating this linkage.
7225 */
7226 _mesa_associate_uniform_storage(ctx, shader_program, prog);
7227 if (!shader_program->data->LinkStatus) {
7228 free_glsl_to_tgsi_visitor(v);
7229 _mesa_reference_program(ctx, &shader->Program, NULL);
7230 return NULL;
7231 }
7232
7233 st_program(prog)->glsl_to_tgsi = v;
7234
7235 PRINT_STATS(v->print_stats());
7236
7237 return prog;
7238 }
7239
7240 /* See if there are unsupported control flow statements. */
7241 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7242 private:
7243 const struct gl_shader_compiler_options *options;
7244 public:
7245 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7246 : options(options),
7247 unsupported(false)
7248 {
7249 }
7250
7251 virtual ir_visitor_status visit_enter(ir_function *ir)
7252 {
7253 /* Other functions are skipped (same as glsl_to_tgsi). */
7254 if (strcmp(ir->name, "main") == 0)
7255 return visit_continue;
7256
7257 return visit_continue_with_parent;
7258 }
7259
7260 virtual ir_visitor_status visit_enter(ir_call *ir)
7261 {
7262 if (!ir->callee->is_intrinsic()) {
7263 unsupported = true; /* it's a function call */
7264 return visit_stop;
7265 }
7266 return visit_continue;
7267 }
7268
7269 virtual ir_visitor_status visit_enter(ir_return *ir)
7270 {
7271 if (options->EmitNoMainReturn) {
7272 unsupported = true;
7273 return visit_stop;
7274 }
7275 return visit_continue;
7276 }
7277
7278 bool unsupported;
7279 };
7280
7281 static bool
7282 has_unsupported_control_flow(exec_list *ir,
7283 const struct gl_shader_compiler_options *options)
7284 {
7285 ir_control_flow_info_visitor visitor(options);
7286 visit_list_elements(&visitor, ir);
7287 return visitor.unsupported;
7288 }
7289
7290 /**
7291 * Link a shader.
7292 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7293 * with code lowering and other optimizations.
7294 */
7295 GLboolean
7296 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7297 {
7298 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7299
7300 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7301 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7302 if (shader == NULL)
7303 continue;
7304
7305 exec_list *ir = shader->ir;
7306 gl_shader_stage stage = shader->Stage;
7307 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7308 const struct gl_shader_compiler_options *options =
7309 &ctx->Const.ShaderCompilerOptions[stage];
7310
7311 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7312 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7313 if (ctx->Const.GLSLOptimizeConservatively) {
7314 /* Do it once and repeat only if there's unsupported control flow. */
7315 do {
7316 do_common_optimization(ir, true, true, options,
7317 ctx->Const.NativeIntegers);
7318 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7319 options->MaxIfDepth, if_threshold);
7320 } while (has_unsupported_control_flow(ir, options));
7321 } else {
7322 /* Repeat it until it stops making changes. */
7323 bool progress;
7324 do {
7325 progress = do_common_optimization(ir, true, true, options,
7326 ctx->Const.NativeIntegers);
7327 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7328 options->MaxIfDepth, if_threshold);
7329 } while (progress);
7330 }
7331
7332 /* Do this again to lower ir_binop_vector_extract introduced
7333 * by optimization passes.
7334 */
7335 do_vec_index_to_cond_assign(ir);
7336
7337 validate_ir_tree(ir);
7338
7339 struct gl_program *linked_prog =
7340 get_mesa_program_tgsi(ctx, prog, shader);
7341 st_set_prog_affected_state_flags(linked_prog);
7342
7343 if (linked_prog) {
7344 /* This is really conservative: */
7345 linked_prog->info.writes_memory =
7346 linked_prog->info.num_ssbos ||
7347 linked_prog->info.num_images ||
7348 ctx->Extensions.ARB_bindless_texture ||
7349 (linked_prog->sh.LinkedTransformFeedback &&
7350 linked_prog->sh.LinkedTransformFeedback->NumVarying);
7351
7352 if (!ctx->Driver.ProgramStringNotify(ctx,
7353 _mesa_shader_stage_to_program(i),
7354 linked_prog)) {
7355 _mesa_reference_program(ctx, &shader->Program, NULL);
7356 return GL_FALSE;
7357 }
7358 }
7359 }
7360
7361 return GL_TRUE;
7362 }