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st/glsl: start spilling out common st glsl conversion code
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
56 #include "st_glsl_to_tgsi_temprename.h"
57
58 #include "util/hash_table.h"
59 #include <algorithm>
60
61 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
62 (1 << PROGRAM_CONSTANT) | \
63 (1 << PROGRAM_UNIFORM))
64
65 #define MAX_GLSL_TEXTURE_OFFSET 4
66
67 #ifndef NDEBUG
68 #include "util/u_atomic.h"
69 #include "util/simple_mtx.h"
70 #include <fstream>
71 #include <ios>
72
73 /* Prepare to make it possible to specify log file */
74 static std::ofstream stats_log;
75
76 /* Helper function to check whether we want to write some statistics
77 * of the shader conversion.
78 */
79
80 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
81
82 static inline bool print_stats_enabled ()
83 {
84 static int stats_enabled = 0;
85
86 if (!stats_enabled) {
87 simple_mtx_lock(&print_stats_mutex);
88 if (!stats_enabled) {
89 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
90 if (stats_filename) {
91 bool write_header = std::ifstream(stats_filename).fail();
92 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
93 stats_enabled = stats_log.good() ? 1 : -1;
94 if (write_header)
95 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
96 } else {
97 stats_enabled = -1;
98 }
99 }
100 simple_mtx_unlock(&print_stats_mutex);
101 }
102 return stats_enabled > 0;
103 }
104 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
105 #else
106 #define PRINT_STATS(X)
107 #endif
108
109
110 static unsigned is_precise(const ir_variable *ir)
111 {
112 if (!ir)
113 return 0;
114 return ir->data.precise || ir->data.invariant;
115 }
116
117 class variable_storage {
118 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
119
120 public:
121 variable_storage(ir_variable *var, gl_register_file file, int index,
122 unsigned array_id = 0)
123 : file(file), index(index), component(0), var(var), array_id(array_id)
124 {
125 assert(file != PROGRAM_ARRAY || array_id != 0);
126 }
127
128 gl_register_file file;
129 int index;
130
131 /* Explicit component location. This is given in terms of the GLSL-style
132 * swizzles where each double is a single component, i.e. for 64-bit types
133 * it can only be 0 or 1.
134 */
135 int component;
136 ir_variable *var; /* variable that maps to this, if any */
137 unsigned array_id;
138 };
139
140 class immediate_storage : public exec_node {
141 public:
142 immediate_storage(gl_constant_value *values, int size32, GLenum type)
143 {
144 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
145 this->size32 = size32;
146 this->type = type;
147 }
148
149 /* doubles are stored across 2 gl_constant_values */
150 gl_constant_value values[4];
151 int size32; /**< Number of 32-bit components (1-4) */
152 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
153 };
154
155 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
156 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
157
158 struct inout_decl {
159 unsigned mesa_index;
160 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
161 unsigned size;
162 unsigned interp_loc;
163 unsigned gs_out_streams;
164 enum glsl_interp_mode interp;
165 enum glsl_base_type base_type;
166 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
167 bool invariant;
168 };
169
170 static struct inout_decl *
171 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
172 {
173 assert(array_id != 0);
174
175 for (unsigned i = 0; i < count; i++) {
176 struct inout_decl *decl = &decls[i];
177
178 if (array_id == decl->array_id) {
179 return decl;
180 }
181 }
182
183 return NULL;
184 }
185
186 static enum glsl_base_type
187 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
188 {
189 if (!array_id)
190 return GLSL_TYPE_ERROR;
191 struct inout_decl *decl = find_inout_array(decls, count, array_id);
192 if (decl)
193 return decl->base_type;
194 return GLSL_TYPE_ERROR;
195 }
196
197 struct hwatomic_decl {
198 unsigned location;
199 unsigned binding;
200 unsigned size;
201 unsigned array_id;
202 };
203
204 struct glsl_to_tgsi_visitor : public ir_visitor {
205 public:
206 glsl_to_tgsi_visitor();
207 ~glsl_to_tgsi_visitor();
208
209 struct gl_context *ctx;
210 struct gl_program *prog;
211 struct gl_shader_program *shader_program;
212 struct gl_linked_shader *shader;
213 struct gl_shader_compiler_options *options;
214
215 int next_temp;
216
217 unsigned *array_sizes;
218 unsigned max_num_arrays;
219 unsigned next_array;
220
221 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
222 unsigned num_inputs;
223 unsigned num_input_arrays;
224 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
225 unsigned num_outputs;
226 unsigned num_output_arrays;
227
228 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
229 unsigned num_atomics;
230 unsigned num_atomic_arrays;
231 int num_address_regs;
232 uint32_t samplers_used;
233 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
234 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
235 int images_used;
236 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
237 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
238 bool image_wr[PIPE_MAX_SHADER_IMAGES];
239 bool indirect_addr_consts;
240 int wpos_transform_const;
241
242 bool native_integers;
243 bool have_sqrt;
244 bool have_fma;
245 bool use_shared_memory;
246 bool has_tex_txf_lz;
247 bool precise;
248 bool need_uarl;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_texture *);
288 virtual void visit(ir_if *);
289 virtual void visit(ir_emit_vertex *);
290 virtual void visit(ir_end_primitive *);
291 virtual void visit(ir_barrier *);
292 /*@}*/
293
294 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
295
296 void visit_atomic_counter_intrinsic(ir_call *);
297 void visit_ssbo_intrinsic(ir_call *);
298 void visit_membar_intrinsic(ir_call *);
299 void visit_shared_intrinsic(ir_call *);
300 void visit_image_intrinsic(ir_call *);
301 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
302
303 st_src_reg result;
304
305 /** List of variable_storage */
306 struct hash_table *variables;
307
308 /** List of immediate_storage */
309 exec_list immediates;
310 unsigned num_immediates;
311
312 /** List of glsl_to_tgsi_instruction */
313 exec_list instructions;
314
315 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
316 st_dst_reg dst = undef_dst,
317 st_src_reg src0 = undef_src,
318 st_src_reg src1 = undef_src,
319 st_src_reg src2 = undef_src,
320 st_src_reg src3 = undef_src);
321
322 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
323 st_dst_reg dst, st_dst_reg dst1,
324 st_src_reg src0 = undef_src,
325 st_src_reg src1 = undef_src,
326 st_src_reg src2 = undef_src,
327 st_src_reg src3 = undef_src);
328
329 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
330 st_dst_reg dst,
331 st_src_reg src0, st_src_reg src1);
332
333 /**
334 * Emit the correct dot-product instruction for the type of arguments
335 */
336 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
337 st_dst_reg dst,
338 st_src_reg src0,
339 st_src_reg src1,
340 unsigned elements);
341
342 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
343 st_dst_reg dst, st_src_reg src0);
344
345 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
346 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
347
348 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
349
350 void get_deref_offsets(ir_dereference *ir,
351 unsigned *array_size,
352 unsigned *base,
353 uint16_t *index,
354 st_src_reg *reladdr,
355 bool opaque);
356 void calc_deref_offsets(ir_dereference *tail,
357 unsigned *array_elements,
358 uint16_t *index,
359 st_src_reg *indirect,
360 unsigned *location);
361 st_src_reg canonicalize_gather_offset(st_src_reg offset);
362 bool handle_bound_deref(ir_dereference *ir);
363
364 bool try_emit_mad(ir_expression *ir,
365 int mul_operand);
366 bool try_emit_mad_for_and_not(ir_expression *ir,
367 int mul_operand);
368
369 void emit_swz(ir_expression *ir);
370
371 bool process_move_condition(ir_rvalue *ir);
372
373 void simplify_cmp(void);
374
375 void rename_temp_registers(struct rename_reg_pair *renames);
376 void get_first_temp_read(int *first_reads);
377 void get_first_temp_write(int *first_writes);
378 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
379 void get_last_temp_write(int *last_writes);
380
381 void copy_propagate(void);
382 int eliminate_dead_code(void);
383
384 void split_arrays(void);
385 void merge_two_dsts(void);
386 void merge_registers(void);
387 void renumber_registers(void);
388
389 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
390 st_dst_reg *l, st_src_reg *r,
391 st_src_reg *cond, bool cond_swap);
392
393 void print_stats();
394
395 void *mem_ctx;
396 };
397
398 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
399 GLSL_TYPE_FLOAT, 0);
400 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
401 GLSL_TYPE_FLOAT, 1);
402 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
403 GLSL_TYPE_FLOAT, 2);
404
405 static void
406 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
407 PRINTFLIKE(2, 3);
408
409 static void
410 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
411 {
412 va_list args;
413 va_start(args, fmt);
414 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
415 va_end(args);
416
417 prog->data->LinkStatus = LINKING_FAILURE;
418 }
419
420 int
421 swizzle_for_size(int size)
422 {
423 static const int size_swizzles[4] = {
424 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
428 };
429
430 assert((size >= 1) && (size <= 4));
431 return size_swizzles[size - 1];
432 }
433
434
435 glsl_to_tgsi_instruction *
436 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
437 st_dst_reg dst, st_dst_reg dst1,
438 st_src_reg src0, st_src_reg src1,
439 st_src_reg src2, st_src_reg src3)
440 {
441 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
442 int num_reladdr = 0, i, j;
443 bool dst_is_64bit[2];
444
445 op = get_opcode(op, dst, src0, src1);
446
447 /* If we have to do relative addressing, we want to load the ARL
448 * reg directly for one of the regs, and preload the other reladdr
449 * sources into temps.
450 */
451 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
452 assert(!dst1.reladdr); /* should be lowered in earlier passes */
453 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
454 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
455 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
456 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
457
458 reladdr_to_temp(ir, &src3, &num_reladdr);
459 reladdr_to_temp(ir, &src2, &num_reladdr);
460 reladdr_to_temp(ir, &src1, &num_reladdr);
461 reladdr_to_temp(ir, &src0, &num_reladdr);
462
463 if (dst.reladdr || dst.reladdr2) {
464 if (dst.reladdr)
465 emit_arl(ir, address_reg, *dst.reladdr);
466 if (dst.reladdr2)
467 emit_arl(ir, address_reg2, *dst.reladdr2);
468 num_reladdr--;
469 }
470
471 assert(num_reladdr == 0);
472
473 /* inst->op has only 8 bits. */
474 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
475
476 inst->op = op;
477 inst->precise = this->precise;
478 inst->info = tgsi_get_opcode_info(op);
479 inst->dst[0] = dst;
480 inst->dst[1] = dst1;
481 inst->src[0] = src0;
482 inst->src[1] = src1;
483 inst->src[2] = src2;
484 inst->src[3] = src3;
485 inst->is_64bit_expanded = false;
486 inst->ir = ir;
487 inst->dead_mask = 0;
488 inst->tex_offsets = NULL;
489 inst->tex_offset_num_offset = 0;
490 inst->saturate = 0;
491 inst->tex_shadow = 0;
492 /* default to float, for paths where this is not initialized
493 * (since 0==UINT which is likely wrong):
494 */
495 inst->tex_type = GLSL_TYPE_FLOAT;
496
497 /* Update indirect addressing status used by TGSI */
498 if (dst.reladdr || dst.reladdr2) {
499 switch (dst.file) {
500 case PROGRAM_STATE_VAR:
501 case PROGRAM_CONSTANT:
502 case PROGRAM_UNIFORM:
503 this->indirect_addr_consts = true;
504 break;
505 case PROGRAM_IMMEDIATE:
506 assert(!"immediates should not have indirect addressing");
507 break;
508 default:
509 break;
510 }
511 }
512 else {
513 for (i = 0; i < 4; i++) {
514 if (inst->src[i].reladdr) {
515 switch (inst->src[i].file) {
516 case PROGRAM_STATE_VAR:
517 case PROGRAM_CONSTANT:
518 case PROGRAM_UNIFORM:
519 this->indirect_addr_consts = true;
520 break;
521 case PROGRAM_IMMEDIATE:
522 assert(!"immediates should not have indirect addressing");
523 break;
524 default:
525 break;
526 }
527 }
528 }
529 }
530
531 /*
532 * This section contains the double processing.
533 * GLSL just represents doubles as single channel values,
534 * however most HW and TGSI represent doubles as pairs of register channels.
535 *
536 * so we have to fixup destination writemask/index and src swizzle/indexes.
537 * dest writemasks need to translate from single channel write mask
538 * to a dual-channel writemask, but also need to modify the index,
539 * if we are touching the Z,W fields in the pre-translated writemask.
540 *
541 * src channels have similiar index modifications along with swizzle
542 * changes to we pick the XY, ZW pairs from the correct index.
543 *
544 * GLSL [0].x -> TGSI [0].xy
545 * GLSL [0].y -> TGSI [0].zw
546 * GLSL [0].z -> TGSI [1].xy
547 * GLSL [0].w -> TGSI [1].zw
548 */
549 for (j = 0; j < 2; j++) {
550 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
551 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
552 inst->dst[j].type == GLSL_TYPE_ARRAY) {
553 enum glsl_base_type type = find_array_type(this->outputs,
554 this->num_outputs,
555 inst->dst[j].array_id);
556 if (glsl_base_type_is_64bit(type))
557 dst_is_64bit[j] = true;
558 }
559 }
560
561 if (dst_is_64bit[0] || dst_is_64bit[1] ||
562 glsl_base_type_is_64bit(inst->src[0].type)) {
563 glsl_to_tgsi_instruction *dinst = NULL;
564 int initial_src_swz[4], initial_src_idx[4];
565 int initial_dst_idx[2], initial_dst_writemask[2];
566 /* select the writemask for dst0 or dst1 */
567 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
568 ? inst->dst[0].writemask : inst->dst[1].writemask;
569
570 /* copy out the writemask, index and swizzles for all src/dsts. */
571 for (j = 0; j < 2; j++) {
572 initial_dst_writemask[j] = inst->dst[j].writemask;
573 initial_dst_idx[j] = inst->dst[j].index;
574 }
575
576 for (j = 0; j < 4; j++) {
577 initial_src_swz[j] = inst->src[j].swizzle;
578 initial_src_idx[j] = inst->src[j].index;
579 }
580
581 /*
582 * scan all the components in the dst writemask
583 * generate an instruction for each of them if required.
584 */
585 st_src_reg addr;
586 while (writemask) {
587
588 int i = u_bit_scan(&writemask);
589
590 /* before emitting the instruction, see if we have to adjust
591 * load / store address */
592 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
593 inst->op == TGSI_OPCODE_STORE) &&
594 addr.file == PROGRAM_UNDEFINED) {
595 /* We have to advance the buffer address by 16 */
596 addr = get_temp(glsl_type::uint_type);
597 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
598 inst->src[0], st_src_reg_for_int(16));
599 }
600
601 /* first time use previous instruction */
602 if (dinst == NULL) {
603 dinst = inst;
604 } else {
605 /* create a new instructions for subsequent attempts */
606 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
607 *dinst = *inst;
608 dinst->next = NULL;
609 dinst->prev = NULL;
610 }
611 this->instructions.push_tail(dinst);
612 dinst->is_64bit_expanded = true;
613
614 /* modify the destination if we are splitting */
615 for (j = 0; j < 2; j++) {
616 if (dst_is_64bit[j]) {
617 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
618 dinst->dst[j].index = initial_dst_idx[j];
619 if (i > 1) {
620 if (dinst->op == TGSI_OPCODE_LOAD ||
621 dinst->op == TGSI_OPCODE_STORE)
622 dinst->src[0] = addr;
623 if (dinst->op != TGSI_OPCODE_STORE)
624 dinst->dst[j].index++;
625 }
626 } else {
627 /* if we aren't writing to a double, just get the bit of the
628 * initial writemask for this channel
629 */
630 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
631 }
632 }
633
634 /* modify the src registers */
635 for (j = 0; j < 4; j++) {
636 int swz = GET_SWZ(initial_src_swz[j], i);
637
638 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
639 dinst->src[j].index = initial_src_idx[j];
640 if (swz > 1) {
641 dinst->src[j].double_reg2 = true;
642 dinst->src[j].index++;
643 }
644
645 if (swz & 1)
646 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
647 SWIZZLE_Z, SWIZZLE_W);
648 else
649 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
650 SWIZZLE_X, SWIZZLE_Y);
651
652 } else {
653 /* some opcodes are special case in what they use as sources
654 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
655 * integer src1
656 */
657 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
658 op == TGSI_OPCODE_I2D ||
659 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
660 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
661 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
662 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
663 }
664 }
665 }
666 }
667 inst = dinst;
668 } else {
669 this->instructions.push_tail(inst);
670 }
671
672
673 return inst;
674 }
675
676 glsl_to_tgsi_instruction *
677 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
678 st_dst_reg dst,
679 st_src_reg src0, st_src_reg src1,
680 st_src_reg src2, st_src_reg src3)
681 {
682 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
683 }
684
685 /**
686 * Determines whether to use an integer, unsigned integer, or float opcode
687 * based on the operands and input opcode, then emits the result.
688 */
689 enum tgsi_opcode
690 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
691 st_dst_reg dst,
692 st_src_reg src0, st_src_reg src1)
693 {
694 enum glsl_base_type type = GLSL_TYPE_FLOAT;
695
696 if (op == TGSI_OPCODE_MOV)
697 return op;
698
699 assert(src0.type != GLSL_TYPE_ARRAY);
700 assert(src0.type != GLSL_TYPE_STRUCT);
701 assert(src1.type != GLSL_TYPE_ARRAY);
702 assert(src1.type != GLSL_TYPE_STRUCT);
703
704 if (is_resource_instruction(op))
705 type = src1.type;
706 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
707 type = GLSL_TYPE_INT64;
708 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
709 type = GLSL_TYPE_UINT64;
710 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
711 type = GLSL_TYPE_DOUBLE;
712 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
713 type = GLSL_TYPE_FLOAT;
714 else if (native_integers)
715 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
716
717 #define case7(c, f, i, u, d, i64, ui64) \
718 case TGSI_OPCODE_##c: \
719 if (type == GLSL_TYPE_UINT64) \
720 op = TGSI_OPCODE_##ui64; \
721 else if (type == GLSL_TYPE_INT64) \
722 op = TGSI_OPCODE_##i64; \
723 else if (type == GLSL_TYPE_DOUBLE) \
724 op = TGSI_OPCODE_##d; \
725 else if (type == GLSL_TYPE_INT) \
726 op = TGSI_OPCODE_##i; \
727 else if (type == GLSL_TYPE_UINT) \
728 op = TGSI_OPCODE_##u; \
729 else \
730 op = TGSI_OPCODE_##f; \
731 break;
732
733 #define casecomp(c, f, i, u, d, i64, ui64) \
734 case TGSI_OPCODE_##c: \
735 if (type == GLSL_TYPE_INT64) \
736 op = TGSI_OPCODE_##i64; \
737 else if (type == GLSL_TYPE_UINT64) \
738 op = TGSI_OPCODE_##ui64; \
739 else if (type == GLSL_TYPE_DOUBLE) \
740 op = TGSI_OPCODE_##d; \
741 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
742 op = TGSI_OPCODE_##i; \
743 else if (type == GLSL_TYPE_UINT) \
744 op = TGSI_OPCODE_##u; \
745 else if (native_integers) \
746 op = TGSI_OPCODE_##f; \
747 else \
748 op = TGSI_OPCODE_##c; \
749 break;
750
751 switch (op) {
752 /* Some instructions are initially selected without considering the type.
753 * This fixes the type:
754 *
755 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
756 */
757 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
758 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
759 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
760 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
761 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
762 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
763 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
764 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
765 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
766 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
767 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
768 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
769 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
770 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
771 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
772 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
773
774 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
775 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
776 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
777 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
778 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
779 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
780 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
781 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
782 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
783
784 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
785 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
786 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
787 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
788
789 default:
790 break;
791 }
792
793 assert(op != TGSI_OPCODE_LAST);
794 return op;
795 }
796
797 glsl_to_tgsi_instruction *
798 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
799 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
800 unsigned elements)
801 {
802 static const enum tgsi_opcode dot_opcodes[] = {
803 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
804 };
805
806 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
807 }
808
809 /**
810 * Emits TGSI scalar opcodes to produce unique answers across channels.
811 *
812 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
813 * channel determines the result across all channels. So to do a vec4
814 * of this operation, we want to emit a scalar per source channel used
815 * to produce dest channels.
816 */
817 void
818 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
819 st_dst_reg dst,
820 st_src_reg orig_src0, st_src_reg orig_src1)
821 {
822 int i, j;
823 int done_mask = ~dst.writemask;
824
825 /* TGSI RCP is a scalar operation splatting results to all channels,
826 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
827 * dst channels.
828 */
829 for (i = 0; i < 4; i++) {
830 GLuint this_mask = (1 << i);
831 st_src_reg src0 = orig_src0;
832 st_src_reg src1 = orig_src1;
833
834 if (done_mask & this_mask)
835 continue;
836
837 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
838 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
839 for (j = i + 1; j < 4; j++) {
840 /* If there is another enabled component in the destination that is
841 * derived from the same inputs, generate its value on this pass as
842 * well.
843 */
844 if (!(done_mask & (1 << j)) &&
845 GET_SWZ(src0.swizzle, j) == src0_swiz &&
846 GET_SWZ(src1.swizzle, j) == src1_swiz) {
847 this_mask |= (1 << j);
848 }
849 }
850 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
851 src0_swiz, src0_swiz);
852 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
853 src1_swiz, src1_swiz);
854
855 dst.writemask = this_mask;
856 emit_asm(ir, op, dst, src0, src1);
857 done_mask |= this_mask;
858 }
859 }
860
861 void
862 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
863 st_dst_reg dst, st_src_reg src0)
864 {
865 st_src_reg undef = undef_src;
866
867 undef.swizzle = SWIZZLE_XXXX;
868
869 emit_scalar(ir, op, dst, src0, undef);
870 }
871
872 void
873 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
874 st_dst_reg dst, st_src_reg src0)
875 {
876 enum tgsi_opcode op = TGSI_OPCODE_ARL;
877
878 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
879 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
880 return;
881
882 op = TGSI_OPCODE_UARL;
883 }
884
885 assert(dst.file == PROGRAM_ADDRESS);
886 if (dst.index >= this->num_address_regs)
887 this->num_address_regs = dst.index + 1;
888
889 emit_asm(NULL, op, dst, src0);
890 }
891
892 int
893 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
894 gl_constant_value values[8], int size,
895 GLenum datatype,
896 uint16_t *swizzle_out)
897 {
898 if (file == PROGRAM_CONSTANT) {
899 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
900 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
901 values, size, datatype,
902 &swizzle);
903 if (swizzle_out)
904 *swizzle_out = swizzle;
905 return result;
906 }
907
908 assert(file == PROGRAM_IMMEDIATE);
909
910 int index = 0;
911 immediate_storage *entry;
912 int size32 = size * ((datatype == GL_DOUBLE ||
913 datatype == GL_INT64_ARB ||
914 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
915 int i;
916
917 /* Search immediate storage to see if we already have an identical
918 * immediate that we can use instead of adding a duplicate entry.
919 */
920 foreach_in_list(immediate_storage, entry, &this->immediates) {
921 immediate_storage *tmp = entry;
922
923 for (i = 0; i * 4 < size32; i++) {
924 int slot_size = MIN2(size32 - (i * 4), 4);
925 if (tmp->type != datatype || tmp->size32 != slot_size)
926 break;
927 if (memcmp(tmp->values, &values[i * 4],
928 slot_size * sizeof(gl_constant_value)))
929 break;
930
931 /* Everything matches, keep going until the full size is matched */
932 tmp = (immediate_storage *)tmp->next;
933 }
934
935 /* The full value matched */
936 if (i * 4 >= size32)
937 return index;
938
939 index++;
940 }
941
942 for (i = 0; i * 4 < size32; i++) {
943 int slot_size = MIN2(size32 - (i * 4), 4);
944 /* Add this immediate to the list. */
945 entry = new(mem_ctx) immediate_storage(&values[i * 4],
946 slot_size, datatype);
947 this->immediates.push_tail(entry);
948 this->num_immediates++;
949 }
950 return index;
951 }
952
953 st_src_reg
954 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
955 {
956 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
957 union gl_constant_value uval;
958
959 uval.f = val;
960 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
961
962 return src;
963 }
964
965 st_src_reg
966 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
967 {
968 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
969 union gl_constant_value uval[2];
970
971 memcpy(uval, &val, sizeof(uval));
972 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
973 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
974 return src;
975 }
976
977 st_src_reg
978 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
979 {
980 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
981 union gl_constant_value uval;
982
983 assert(native_integers);
984
985 uval.i = val;
986 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
987
988 return src;
989 }
990
991 st_src_reg
992 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
993 {
994 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
995 union gl_constant_value uval[2];
996
997 memcpy(uval, &val, sizeof(uval));
998 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
999 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1000
1001 return src;
1002 }
1003
1004 st_src_reg
1005 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1006 {
1007 if (native_integers)
1008 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1009 st_src_reg_for_int(val);
1010 else
1011 return st_src_reg_for_float(val);
1012 }
1013
1014 static int
1015 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1016 {
1017 return type->count_attribute_slots(is_vs_input);
1018 }
1019
1020 static int
1021 type_size(const struct glsl_type *type)
1022 {
1023 return type->count_attribute_slots(false);
1024 }
1025
1026 static void
1027 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1028 exec_list *instructions, ir_constant *access)
1029 {
1030 /**
1031 * emit_asm() might have actually split the op into pieces, e.g. for
1032 * double stores. We have to go back and fix up all the generated ops.
1033 */
1034 enum tgsi_opcode op = inst->op;
1035 do {
1036 inst->resource = *buf;
1037 if (access)
1038 inst->buffer_access = access->value.u[0];
1039
1040 if (inst == instructions->get_head_raw())
1041 break;
1042 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1043
1044 if (inst->op == TGSI_OPCODE_UADD) {
1045 if (inst == instructions->get_head_raw())
1046 break;
1047 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1048 }
1049 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1050 }
1051
1052 /**
1053 * If the given GLSL type is an array or matrix or a structure containing
1054 * an array/matrix member, return true. Else return false.
1055 *
1056 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1057 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1058 * we have an array that might be indexed with a variable, we need to use
1059 * the later storage type.
1060 */
1061 static bool
1062 type_has_array_or_matrix(const glsl_type *type)
1063 {
1064 if (type->is_array() || type->is_matrix())
1065 return true;
1066
1067 if (type->is_struct()) {
1068 for (unsigned i = 0; i < type->length; i++) {
1069 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1070 return true;
1071 }
1072 }
1073 }
1074
1075 return false;
1076 }
1077
1078
1079 /**
1080 * In the initial pass of codegen, we assign temporary numbers to
1081 * intermediate results. (not SSA -- variable assignments will reuse
1082 * storage).
1083 */
1084 st_src_reg
1085 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1086 {
1087 st_src_reg src;
1088
1089 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1090 src.reladdr = NULL;
1091 src.negate = 0;
1092 src.abs = 0;
1093
1094 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1095 if (next_array >= max_num_arrays) {
1096 max_num_arrays += 32;
1097 array_sizes = (unsigned*)
1098 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1099 }
1100
1101 src.file = PROGRAM_ARRAY;
1102 src.index = 0;
1103 src.array_id = next_array + 1;
1104 array_sizes[next_array] = type_size(type);
1105 ++next_array;
1106
1107 } else {
1108 src.file = PROGRAM_TEMPORARY;
1109 src.index = next_temp;
1110 next_temp += type_size(type);
1111 }
1112
1113 if (type->is_array() || type->is_struct()) {
1114 src.swizzle = SWIZZLE_NOOP;
1115 } else {
1116 src.swizzle = swizzle_for_size(type->vector_elements);
1117 }
1118
1119 return src;
1120 }
1121
1122 variable_storage *
1123 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1124 {
1125 struct hash_entry *entry;
1126
1127 entry = _mesa_hash_table_search(this->variables, var);
1128 if (!entry)
1129 return NULL;
1130
1131 return (variable_storage *)entry->data;
1132 }
1133
1134 void
1135 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1136 {
1137 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1138 unsigned int i;
1139 const ir_state_slot *const slots = ir->get_state_slots();
1140 assert(slots != NULL);
1141
1142 /* Check if this statevar's setup in the STATE file exactly
1143 * matches how we'll want to reference it as a
1144 * struct/array/whatever. If not, then we need to move it into
1145 * temporary storage and hope that it'll get copy-propagated
1146 * out.
1147 */
1148 for (i = 0; i < ir->get_num_state_slots(); i++) {
1149 if (slots[i].swizzle != SWIZZLE_XYZW) {
1150 break;
1151 }
1152 }
1153
1154 variable_storage *storage;
1155 st_dst_reg dst;
1156 if (i == ir->get_num_state_slots()) {
1157 /* We'll set the index later. */
1158 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1159
1160 _mesa_hash_table_insert(this->variables, ir, storage);
1161
1162 dst = undef_dst;
1163 } else {
1164 /* The variable_storage constructor allocates slots based on the size
1165 * of the type. However, this had better match the number of state
1166 * elements that we're going to copy into the new temporary.
1167 */
1168 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1169
1170 dst = st_dst_reg(get_temp(ir->type));
1171
1172 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1173 dst.array_id);
1174
1175 _mesa_hash_table_insert(this->variables, ir, storage);
1176 }
1177
1178
1179 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1180 int index = _mesa_add_state_reference(this->prog->Parameters,
1181 slots[i].tokens);
1182
1183 if (storage->file == PROGRAM_STATE_VAR) {
1184 if (storage->index == -1) {
1185 storage->index = index;
1186 } else {
1187 assert(index == storage->index + (int)i);
1188 }
1189 } else {
1190 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1191 * the data being moved since MOV does not care about the type of
1192 * data it is moving, and we don't want to declare registers with
1193 * array or struct types.
1194 */
1195 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1196 src.swizzle = slots[i].swizzle;
1197 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1198 /* even a float takes up a whole vec4 reg in a struct/array. */
1199 dst.index++;
1200 }
1201 }
1202
1203 if (storage->file == PROGRAM_TEMPORARY &&
1204 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1205 fail_link(this->shader_program,
1206 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1207 ir->name, dst.index - storage->index,
1208 type_size(ir->type));
1209 }
1210 }
1211 }
1212
1213 void
1214 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1215 {
1216 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1217
1218 visit_exec_list(&ir->body_instructions, this);
1219
1220 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1221 }
1222
1223 void
1224 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1225 {
1226 switch (ir->mode) {
1227 case ir_loop_jump::jump_break:
1228 emit_asm(NULL, TGSI_OPCODE_BRK);
1229 break;
1230 case ir_loop_jump::jump_continue:
1231 emit_asm(NULL, TGSI_OPCODE_CONT);
1232 break;
1233 }
1234 }
1235
1236
1237 void
1238 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1239 {
1240 assert(0);
1241 (void)ir;
1242 }
1243
1244 void
1245 glsl_to_tgsi_visitor::visit(ir_function *ir)
1246 {
1247 /* Ignore function bodies other than main() -- we shouldn't see calls to
1248 * them since they should all be inlined before we get to glsl_to_tgsi.
1249 */
1250 if (strcmp(ir->name, "main") == 0) {
1251 const ir_function_signature *sig;
1252 exec_list empty;
1253
1254 sig = ir->matching_signature(NULL, &empty, false);
1255
1256 assert(sig);
1257
1258 foreach_in_list(ir_instruction, ir, &sig->body) {
1259 ir->accept(this);
1260 }
1261 }
1262 }
1263
1264 bool
1265 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1266 {
1267 int nonmul_operand = 1 - mul_operand;
1268 st_src_reg a, b, c;
1269 st_dst_reg result_dst;
1270
1271 // there is no TGSI opcode for this
1272 if (ir->type->is_integer_64())
1273 return false;
1274
1275 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1276 if (!expr || expr->operation != ir_binop_mul)
1277 return false;
1278
1279 expr->operands[0]->accept(this);
1280 a = this->result;
1281 expr->operands[1]->accept(this);
1282 b = this->result;
1283 ir->operands[nonmul_operand]->accept(this);
1284 c = this->result;
1285
1286 this->result = get_temp(ir->type);
1287 result_dst = st_dst_reg(this->result);
1288 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1289 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1290
1291 return true;
1292 }
1293
1294 /**
1295 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1296 *
1297 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1298 * implemented using multiplication, and logical-or is implemented using
1299 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1300 * As result, the logical expression (a & !b) can be rewritten as:
1301 *
1302 * - a * !b
1303 * - a * (1 - b)
1304 * - (a * 1) - (a * b)
1305 * - a + -(a * b)
1306 * - a + (a * -b)
1307 *
1308 * This final expression can be implemented as a single MAD(a, -b, a)
1309 * instruction.
1310 */
1311 bool
1312 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1313 int try_operand)
1314 {
1315 const int other_operand = 1 - try_operand;
1316 st_src_reg a, b;
1317
1318 ir_expression *expr = ir->operands[try_operand]->as_expression();
1319 if (!expr || expr->operation != ir_unop_logic_not)
1320 return false;
1321
1322 ir->operands[other_operand]->accept(this);
1323 a = this->result;
1324 expr->operands[0]->accept(this);
1325 b = this->result;
1326
1327 b.negate = ~b.negate;
1328
1329 this->result = get_temp(ir->type);
1330 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1331
1332 return true;
1333 }
1334
1335 void
1336 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1337 st_src_reg *reg, int *num_reladdr)
1338 {
1339 if (!reg->reladdr && !reg->reladdr2)
1340 return;
1341
1342 if (reg->reladdr)
1343 emit_arl(ir, address_reg, *reg->reladdr);
1344 if (reg->reladdr2)
1345 emit_arl(ir, address_reg2, *reg->reladdr2);
1346
1347 if (*num_reladdr != 1) {
1348 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1349
1350 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1351 *reg = temp;
1352 }
1353
1354 (*num_reladdr)--;
1355 }
1356
1357 void
1358 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1359 {
1360 st_src_reg op[ARRAY_SIZE(ir->operands)];
1361
1362 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1363 */
1364 if (!this->precise && ir->operation == ir_binop_add) {
1365 if (try_emit_mad(ir, 1))
1366 return;
1367 if (try_emit_mad(ir, 0))
1368 return;
1369 }
1370
1371 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1372 */
1373 if (!native_integers && ir->operation == ir_binop_logic_and) {
1374 if (try_emit_mad_for_and_not(ir, 1))
1375 return;
1376 if (try_emit_mad_for_and_not(ir, 0))
1377 return;
1378 }
1379
1380 if (ir->operation == ir_quadop_vector)
1381 assert(!"ir_quadop_vector should have been lowered");
1382
1383 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1384 this->result.file = PROGRAM_UNDEFINED;
1385 ir->operands[operand]->accept(this);
1386 if (this->result.file == PROGRAM_UNDEFINED) {
1387 printf("Failed to get tree for expression operand:\n");
1388 ir->operands[operand]->print();
1389 printf("\n");
1390 exit(1);
1391 }
1392 op[operand] = this->result;
1393
1394 /* Matrix expression operands should have been broken down to vector
1395 * operations already.
1396 */
1397 assert(!ir->operands[operand]->type->is_matrix());
1398 }
1399
1400 visit_expression(ir, op);
1401 }
1402
1403 /* The non-recursive part of the expression visitor lives in a separate
1404 * function and should be prevented from being inlined, to avoid a stack
1405 * explosion when deeply nested expressions are visited.
1406 */
1407 void
1408 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1409 {
1410 st_src_reg result_src;
1411 st_dst_reg result_dst;
1412
1413 int vector_elements = ir->operands[0]->type->vector_elements;
1414 if (ir->operands[1] &&
1415 ir->operation != ir_binop_interpolate_at_offset &&
1416 ir->operation != ir_binop_interpolate_at_sample) {
1417 st_src_reg *swz_op = NULL;
1418 if (vector_elements > ir->operands[1]->type->vector_elements) {
1419 assert(ir->operands[1]->type->vector_elements == 1);
1420 swz_op = &op[1];
1421 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1422 assert(ir->operands[0]->type->vector_elements == 1);
1423 swz_op = &op[0];
1424 }
1425 if (swz_op) {
1426 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1427 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1428 swizzle_x, swizzle_x);
1429 }
1430 vector_elements = MAX2(vector_elements,
1431 ir->operands[1]->type->vector_elements);
1432 }
1433 if (ir->operands[2] &&
1434 ir->operands[2]->type->vector_elements != vector_elements) {
1435 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1436 assert(ir->operands[2]->type->vector_elements == 1);
1437 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1438 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1439 swizzle_x, swizzle_x);
1440 }
1441
1442 this->result.file = PROGRAM_UNDEFINED;
1443
1444 /* Storage for our result. Ideally for an assignment we'd be using
1445 * the actual storage for the result here, instead.
1446 */
1447 result_src = get_temp(ir->type);
1448 /* convenience for the emit functions below. */
1449 result_dst = st_dst_reg(result_src);
1450 /* Limit writes to the channels that will be used by result_src later.
1451 * This does limit this temp's use as a temporary for multi-instruction
1452 * sequences.
1453 */
1454 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1455
1456 switch (ir->operation) {
1457 case ir_unop_logic_not:
1458 if (result_dst.type != GLSL_TYPE_FLOAT)
1459 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1460 else {
1461 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1462 * older GPUs implement SEQ using multiple instructions (i915 uses two
1463 * SGE instructions and a MUL instruction). Since our logic values are
1464 * 0.0 and 1.0, 1-x also implements !x.
1465 */
1466 op[0].negate = ~op[0].negate;
1467 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1468 st_src_reg_for_float(1.0));
1469 }
1470 break;
1471 case ir_unop_neg:
1472 if (result_dst.type == GLSL_TYPE_INT64 ||
1473 result_dst.type == GLSL_TYPE_UINT64)
1474 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1475 else if (result_dst.type == GLSL_TYPE_INT ||
1476 result_dst.type == GLSL_TYPE_UINT)
1477 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1478 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1479 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1480 else {
1481 op[0].negate = ~op[0].negate;
1482 result_src = op[0];
1483 }
1484 break;
1485 case ir_unop_subroutine_to_int:
1486 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1487 break;
1488 case ir_unop_abs:
1489 if (result_dst.type == GLSL_TYPE_FLOAT)
1490 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1491 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1492 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1493 else if (result_dst.type == GLSL_TYPE_INT64 ||
1494 result_dst.type == GLSL_TYPE_UINT64)
1495 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1496 else
1497 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1498 break;
1499 case ir_unop_sign:
1500 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1501 break;
1502 case ir_unop_rcp:
1503 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1504 break;
1505
1506 case ir_unop_exp2:
1507 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1508 break;
1509 case ir_unop_exp:
1510 assert(!"not reached: should be handled by exp_to_exp2");
1511 break;
1512 case ir_unop_log:
1513 assert(!"not reached: should be handled by log_to_log2");
1514 break;
1515 case ir_unop_log2:
1516 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1517 break;
1518 case ir_unop_sin:
1519 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1520 break;
1521 case ir_unop_cos:
1522 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1523 break;
1524 case ir_unop_saturate: {
1525 glsl_to_tgsi_instruction *inst;
1526 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1527 inst->saturate = true;
1528 break;
1529 }
1530
1531 case ir_unop_dFdx:
1532 case ir_unop_dFdx_coarse:
1533 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1534 break;
1535 case ir_unop_dFdx_fine:
1536 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1537 break;
1538 case ir_unop_dFdy:
1539 case ir_unop_dFdy_coarse:
1540 case ir_unop_dFdy_fine:
1541 {
1542 /* The X component contains 1 or -1 depending on whether the framebuffer
1543 * is a FBO or the window system buffer, respectively.
1544 * It is then multiplied with the source operand of DDY.
1545 */
1546 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1547 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1548
1549 unsigned transform_y_index =
1550 _mesa_add_state_reference(this->prog->Parameters,
1551 transform_y_state);
1552
1553 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1554 transform_y_index,
1555 glsl_type::vec4_type);
1556 transform_y.swizzle = SWIZZLE_XXXX;
1557
1558 st_src_reg temp = get_temp(glsl_type::vec4_type);
1559
1560 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1561 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1562 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1563 break;
1564 }
1565
1566 case ir_unop_frexp_sig:
1567 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1568 break;
1569
1570 case ir_unop_frexp_exp:
1571 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1572 break;
1573
1574 case ir_unop_noise: {
1575 /* At some point, a motivated person could add a better
1576 * implementation of noise. Currently not even the nvidia
1577 * binary drivers do anything more than this. In any case, the
1578 * place to do this is in the GL state tracker, not the poor
1579 * driver.
1580 */
1581 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1582 break;
1583 }
1584
1585 case ir_binop_add:
1586 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1587 break;
1588 case ir_binop_sub:
1589 op[1].negate = ~op[1].negate;
1590 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1591 break;
1592
1593 case ir_binop_mul:
1594 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1595 break;
1596 case ir_binop_div:
1597 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1598 break;
1599 case ir_binop_mod:
1600 if (result_dst.type == GLSL_TYPE_FLOAT)
1601 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1602 else
1603 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1604 break;
1605
1606 case ir_binop_less:
1607 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1608 break;
1609 case ir_binop_gequal:
1610 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1611 break;
1612 case ir_binop_equal:
1613 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1614 break;
1615 case ir_binop_nequal:
1616 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1617 break;
1618 case ir_binop_all_equal:
1619 /* "==" operator producing a scalar boolean. */
1620 if (ir->operands[0]->type->is_vector() ||
1621 ir->operands[1]->type->is_vector()) {
1622 st_src_reg temp = get_temp(native_integers ?
1623 glsl_type::uvec4_type :
1624 glsl_type::vec4_type);
1625
1626 if (native_integers) {
1627 st_dst_reg temp_dst = st_dst_reg(temp);
1628 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1629
1630 if (ir->operands[0]->type->is_boolean() &&
1631 ir->operands[1]->as_constant() &&
1632 ir->operands[1]->as_constant()->is_one()) {
1633 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1634 } else {
1635 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1636 }
1637
1638 /* Emit 1-3 AND operations to combine the SEQ results. */
1639 switch (ir->operands[0]->type->vector_elements) {
1640 case 2:
1641 break;
1642 case 3:
1643 temp_dst.writemask = WRITEMASK_Y;
1644 temp1.swizzle = SWIZZLE_YYYY;
1645 temp2.swizzle = SWIZZLE_ZZZZ;
1646 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1647 break;
1648 case 4:
1649 temp_dst.writemask = WRITEMASK_X;
1650 temp1.swizzle = SWIZZLE_XXXX;
1651 temp2.swizzle = SWIZZLE_YYYY;
1652 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1653 temp_dst.writemask = WRITEMASK_Y;
1654 temp1.swizzle = SWIZZLE_ZZZZ;
1655 temp2.swizzle = SWIZZLE_WWWW;
1656 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1657 }
1658
1659 temp1.swizzle = SWIZZLE_XXXX;
1660 temp2.swizzle = SWIZZLE_YYYY;
1661 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1662 } else {
1663 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1664
1665 /* After the dot-product, the value will be an integer on the
1666 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1667 */
1668 emit_dp(ir, result_dst, temp, temp, vector_elements);
1669
1670 /* Negating the result of the dot-product gives values on the range
1671 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1672 * This is achieved using SGE.
1673 */
1674 st_src_reg sge_src = result_src;
1675 sge_src.negate = ~sge_src.negate;
1676 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1677 st_src_reg_for_float(0.0));
1678 }
1679 } else {
1680 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1681 }
1682 break;
1683 case ir_binop_any_nequal:
1684 /* "!=" operator producing a scalar boolean. */
1685 if (ir->operands[0]->type->is_vector() ||
1686 ir->operands[1]->type->is_vector()) {
1687 st_src_reg temp = get_temp(native_integers ?
1688 glsl_type::uvec4_type :
1689 glsl_type::vec4_type);
1690 if (ir->operands[0]->type->is_boolean() &&
1691 ir->operands[1]->as_constant() &&
1692 ir->operands[1]->as_constant()->is_zero()) {
1693 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1694 } else {
1695 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1696 }
1697
1698 if (native_integers) {
1699 st_dst_reg temp_dst = st_dst_reg(temp);
1700 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1701
1702 /* Emit 1-3 OR operations to combine the SNE results. */
1703 switch (ir->operands[0]->type->vector_elements) {
1704 case 2:
1705 break;
1706 case 3:
1707 temp_dst.writemask = WRITEMASK_Y;
1708 temp1.swizzle = SWIZZLE_YYYY;
1709 temp2.swizzle = SWIZZLE_ZZZZ;
1710 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1711 break;
1712 case 4:
1713 temp_dst.writemask = WRITEMASK_X;
1714 temp1.swizzle = SWIZZLE_XXXX;
1715 temp2.swizzle = SWIZZLE_YYYY;
1716 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1717 temp_dst.writemask = WRITEMASK_Y;
1718 temp1.swizzle = SWIZZLE_ZZZZ;
1719 temp2.swizzle = SWIZZLE_WWWW;
1720 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1721 }
1722
1723 temp1.swizzle = SWIZZLE_XXXX;
1724 temp2.swizzle = SWIZZLE_YYYY;
1725 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1726 } else {
1727 /* After the dot-product, the value will be an integer on the
1728 * range [0,4]. Zero stays zero, and positive values become 1.0.
1729 */
1730 glsl_to_tgsi_instruction *const dp =
1731 emit_dp(ir, result_dst, temp, temp, vector_elements);
1732 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1733 /* The clamping to [0,1] can be done for free in the fragment
1734 * shader with a saturate.
1735 */
1736 dp->saturate = true;
1737 } else {
1738 /* Negating the result of the dot-product gives values on the
1739 * range [-4, 0]. Zero stays zero, and negative values become
1740 * 1.0. This achieved using SLT.
1741 */
1742 st_src_reg slt_src = result_src;
1743 slt_src.negate = ~slt_src.negate;
1744 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1745 st_src_reg_for_float(0.0));
1746 }
1747 }
1748 } else {
1749 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1750 }
1751 break;
1752
1753 case ir_binop_logic_xor:
1754 if (native_integers)
1755 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1756 else
1757 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1758 break;
1759
1760 case ir_binop_logic_or: {
1761 if (native_integers) {
1762 /* If integers are used as booleans, we can use an actual "or"
1763 * instruction.
1764 */
1765 assert(native_integers);
1766 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1767 } else {
1768 /* After the addition, the value will be an integer on the
1769 * range [0,2]. Zero stays zero, and positive values become 1.0.
1770 */
1771 glsl_to_tgsi_instruction *add =
1772 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1773 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1774 /* The clamping to [0,1] can be done for free in the fragment
1775 * shader with a saturate if floats are being used as boolean
1776 * values.
1777 */
1778 add->saturate = true;
1779 } else {
1780 /* Negating the result of the addition gives values on the range
1781 * [-2, 0]. Zero stays zero, and negative values become 1.0
1782 * This is achieved using SLT.
1783 */
1784 st_src_reg slt_src = result_src;
1785 slt_src.negate = ~slt_src.negate;
1786 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1787 st_src_reg_for_float(0.0));
1788 }
1789 }
1790 break;
1791 }
1792
1793 case ir_binop_logic_and:
1794 /* If native integers are disabled, the bool args are stored as float 0.0
1795 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1796 * actual AND opcode.
1797 */
1798 if (native_integers)
1799 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1800 else
1801 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1802 break;
1803
1804 case ir_binop_dot:
1805 assert(ir->operands[0]->type->is_vector());
1806 assert(ir->operands[0]->type == ir->operands[1]->type);
1807 emit_dp(ir, result_dst, op[0], op[1],
1808 ir->operands[0]->type->vector_elements);
1809 break;
1810
1811 case ir_unop_sqrt:
1812 if (have_sqrt) {
1813 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1814 } else {
1815 /* This is the only instruction sequence that makes the game "Risen"
1816 * render correctly. ABS is not required for the game, but since GLSL
1817 * declares negative values as "undefined", allowing us to do whatever
1818 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1819 * behavior.
1820 */
1821 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1822 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1823 }
1824 break;
1825 case ir_unop_rsq:
1826 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1827 break;
1828 case ir_unop_i2f:
1829 if (native_integers) {
1830 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1831 break;
1832 }
1833 /* fallthrough to next case otherwise */
1834 case ir_unop_b2f:
1835 if (native_integers) {
1836 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1837 st_src_reg_for_float(1.0));
1838 break;
1839 }
1840 /* fallthrough to next case otherwise */
1841 case ir_unop_i2u:
1842 case ir_unop_u2i:
1843 case ir_unop_i642u64:
1844 case ir_unop_u642i64:
1845 /* Converting between signed and unsigned integers is a no-op. */
1846 result_src = op[0];
1847 result_src.type = result_dst.type;
1848 break;
1849 case ir_unop_b2i:
1850 if (native_integers) {
1851 /* Booleans are stored as integers using ~0 for true and 0 for false.
1852 * GLSL requires that int(bool) return 1 for true and 0 for false.
1853 * This conversion is done with AND, but it could be done with NEG.
1854 */
1855 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1856 st_src_reg_for_int(1));
1857 } else {
1858 /* Booleans and integers are both stored as floats when native
1859 * integers are disabled.
1860 */
1861 result_src = op[0];
1862 }
1863 break;
1864 case ir_unop_f2i:
1865 if (native_integers)
1866 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1867 else
1868 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1869 break;
1870 case ir_unop_f2u:
1871 if (native_integers)
1872 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1873 else
1874 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1875 break;
1876 case ir_unop_bitcast_f2i:
1877 case ir_unop_bitcast_f2u:
1878 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1879 if (op[0].negate || op[0].abs)
1880 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1881 else
1882 result_src = op[0];
1883 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1884 GLSL_TYPE_UINT;
1885 break;
1886 case ir_unop_bitcast_i2f:
1887 case ir_unop_bitcast_u2f:
1888 result_src = op[0];
1889 result_src.type = GLSL_TYPE_FLOAT;
1890 break;
1891 case ir_unop_f2b:
1892 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1893 st_src_reg_for_float(0.0));
1894 break;
1895 case ir_unop_d2b:
1896 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1897 st_src_reg_for_double(0.0));
1898 break;
1899 case ir_unop_i2b:
1900 if (native_integers)
1901 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1902 st_src_reg_for_int(0));
1903 else
1904 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1905 st_src_reg_for_float(0.0));
1906 break;
1907 case ir_unop_bitcast_u642d:
1908 case ir_unop_bitcast_i642d:
1909 result_src = op[0];
1910 result_src.type = GLSL_TYPE_DOUBLE;
1911 break;
1912 case ir_unop_bitcast_d2i64:
1913 result_src = op[0];
1914 result_src.type = GLSL_TYPE_INT64;
1915 break;
1916 case ir_unop_bitcast_d2u64:
1917 result_src = op[0];
1918 result_src.type = GLSL_TYPE_UINT64;
1919 break;
1920 case ir_unop_trunc:
1921 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1922 break;
1923 case ir_unop_ceil:
1924 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1925 break;
1926 case ir_unop_floor:
1927 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1928 break;
1929 case ir_unop_round_even:
1930 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1931 break;
1932 case ir_unop_fract:
1933 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1934 break;
1935
1936 case ir_binop_min:
1937 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1938 break;
1939 case ir_binop_max:
1940 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1941 break;
1942 case ir_binop_pow:
1943 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1944 break;
1945
1946 case ir_unop_bit_not:
1947 if (native_integers) {
1948 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1949 break;
1950 }
1951 case ir_unop_u2f:
1952 if (native_integers) {
1953 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1954 break;
1955 }
1956 case ir_binop_lshift:
1957 case ir_binop_rshift:
1958 if (native_integers) {
1959 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1960 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1961 st_src_reg count;
1962
1963 if (glsl_base_type_is_64bit(op[0].type)) {
1964 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1965 * 64 bits.
1966 */
1967 count = get_temp(glsl_type::u64vec(ir->operands[1]
1968 ->type->components()));
1969 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1970 } else {
1971 count = op[1];
1972 }
1973
1974 emit_asm(ir, opcode, result_dst, op[0], count);
1975 break;
1976 }
1977 case ir_binop_bit_and:
1978 if (native_integers) {
1979 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1980 break;
1981 }
1982 case ir_binop_bit_xor:
1983 if (native_integers) {
1984 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1985 break;
1986 }
1987 case ir_binop_bit_or:
1988 if (native_integers) {
1989 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1990 break;
1991 }
1992
1993 assert(!"GLSL 1.30 features unsupported");
1994 break;
1995
1996 case ir_binop_ubo_load: {
1997 if (ctx->Const.UseSTD430AsDefaultPacking) {
1998 ir_rvalue *block = ir->operands[0];
1999 ir_rvalue *offset = ir->operands[1];
2000 ir_constant *const_block = block->as_constant();
2001
2002 st_src_reg cbuf(PROGRAM_CONSTANT,
2003 (const_block ? const_block->value.u[0] + 1 : 1),
2004 ir->type->base_type);
2005
2006 cbuf.has_index2 = true;
2007
2008 if (!const_block) {
2009 block->accept(this);
2010 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2011 *cbuf.reladdr = this->result;
2012 emit_arl(ir, sampler_reladdr, this->result);
2013 }
2014
2015 /* Calculate the surface offset */
2016 offset->accept(this);
2017 st_src_reg off = this->result;
2018
2019 glsl_to_tgsi_instruction *inst =
2020 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2021
2022 if (result_dst.type == GLSL_TYPE_BOOL)
2023 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2024 st_src_reg_for_int(0));
2025
2026 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2027 NULL);
2028 } else {
2029 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2030 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2031 unsigned const_offset = const_offset_ir ?
2032 const_offset_ir->value.u[0] : 0;
2033 unsigned const_block = const_uniform_block ?
2034 const_uniform_block->value.u[0] + 1 : 1;
2035 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2036 st_src_reg cbuf;
2037
2038 cbuf.type = ir->type->base_type;
2039 cbuf.file = PROGRAM_CONSTANT;
2040 cbuf.index = 0;
2041 cbuf.reladdr = NULL;
2042 cbuf.negate = 0;
2043 cbuf.abs = 0;
2044 cbuf.index2D = const_block;
2045
2046 assert(ir->type->is_vector() || ir->type->is_scalar());
2047
2048 if (const_offset_ir) {
2049 /* Constant index into constant buffer */
2050 cbuf.reladdr = NULL;
2051 cbuf.index = const_offset / 16;
2052 } else {
2053 ir_expression *offset_expr = ir->operands[1]->as_expression();
2054 st_src_reg offset = op[1];
2055
2056 /* The OpenGL spec is written in such a way that accesses with
2057 * non-constant offset are almost always vec4-aligned. The only
2058 * exception to this are members of structs in arrays of structs:
2059 * each struct in an array of structs is at least vec4-aligned,
2060 * but single-element and [ui]vec2 members of the struct may be at
2061 * an offset that is not a multiple of 16 bytes.
2062 *
2063 * Here, we extract that offset, relying on previous passes to
2064 * always generate offset expressions of the form
2065 * (+ expr constant_offset).
2066 *
2067 * Note that the std430 layout, which allows more cases of
2068 * alignment less than vec4 in arrays, is not supported for
2069 * uniform blocks, so we do not have to deal with it here.
2070 */
2071 if (offset_expr && offset_expr->operation == ir_binop_add) {
2072 const_offset_ir = offset_expr->operands[1]->as_constant();
2073 if (const_offset_ir) {
2074 const_offset = const_offset_ir->value.u[0];
2075 cbuf.index = const_offset / 16;
2076 offset_expr->operands[0]->accept(this);
2077 offset = this->result;
2078 }
2079 }
2080
2081 /* Relative/variable index into constant buffer */
2082 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2083 st_src_reg_for_int(4));
2084 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2085 *cbuf.reladdr = index_reg;
2086 }
2087
2088 if (const_uniform_block) {
2089 /* Constant constant buffer */
2090 cbuf.reladdr2 = NULL;
2091 } else {
2092 /* Relative/variable constant buffer */
2093 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2094 *cbuf.reladdr2 = op[0];
2095 }
2096 cbuf.has_index2 = true;
2097
2098 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2099 if (glsl_base_type_is_64bit(cbuf.type))
2100 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2101 const_offset % 16 / 8,
2102 const_offset % 16 / 8,
2103 const_offset % 16 / 8);
2104 else
2105 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2106 const_offset % 16 / 4,
2107 const_offset % 16 / 4,
2108 const_offset % 16 / 4);
2109
2110 if (ir->type->is_boolean()) {
2111 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2112 st_src_reg_for_int(0));
2113 } else {
2114 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2115 }
2116 }
2117 break;
2118 }
2119 case ir_triop_lrp:
2120 /* note: we have to reorder the three args here */
2121 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2122 break;
2123 case ir_triop_csel:
2124 if (this->ctx->Const.NativeIntegers)
2125 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2126 else {
2127 op[0].negate = ~op[0].negate;
2128 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2129 }
2130 break;
2131 case ir_triop_bitfield_extract:
2132 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2133 break;
2134 case ir_quadop_bitfield_insert:
2135 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2136 break;
2137 case ir_unop_bitfield_reverse:
2138 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2139 break;
2140 case ir_unop_bit_count:
2141 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2142 break;
2143 case ir_unop_find_msb:
2144 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2145 break;
2146 case ir_unop_find_lsb:
2147 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2148 break;
2149 case ir_binop_imul_high:
2150 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2151 break;
2152 case ir_triop_fma:
2153 /* In theory, MAD is incorrect here. */
2154 if (have_fma)
2155 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2156 else
2157 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2158 break;
2159 case ir_unop_interpolate_at_centroid:
2160 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2161 break;
2162 case ir_binop_interpolate_at_offset: {
2163 /* The y coordinate needs to be flipped for the default fb */
2164 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2165 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2166
2167 unsigned transform_y_index =
2168 _mesa_add_state_reference(this->prog->Parameters,
2169 transform_y_state);
2170
2171 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2172 transform_y_index,
2173 glsl_type::vec4_type);
2174 transform_y.swizzle = SWIZZLE_XXXX;
2175
2176 st_src_reg temp = get_temp(glsl_type::vec2_type);
2177 st_dst_reg temp_dst = st_dst_reg(temp);
2178
2179 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2180 temp_dst.writemask = WRITEMASK_Y;
2181 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2182 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2183 break;
2184 }
2185 case ir_binop_interpolate_at_sample:
2186 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2187 break;
2188
2189 case ir_unop_d2f:
2190 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2191 break;
2192 case ir_unop_f2d:
2193 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2194 break;
2195 case ir_unop_d2i:
2196 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2197 break;
2198 case ir_unop_i2d:
2199 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2200 break;
2201 case ir_unop_d2u:
2202 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2203 break;
2204 case ir_unop_u2d:
2205 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2206 break;
2207 case ir_unop_unpack_double_2x32:
2208 case ir_unop_pack_double_2x32:
2209 case ir_unop_unpack_int_2x32:
2210 case ir_unop_pack_int_2x32:
2211 case ir_unop_unpack_uint_2x32:
2212 case ir_unop_pack_uint_2x32:
2213 case ir_unop_unpack_sampler_2x32:
2214 case ir_unop_pack_sampler_2x32:
2215 case ir_unop_unpack_image_2x32:
2216 case ir_unop_pack_image_2x32:
2217 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2218 break;
2219
2220 case ir_binop_ldexp:
2221 if (ir->operands[0]->type->is_double()) {
2222 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2223 } else if (ir->operands[0]->type->is_float()) {
2224 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2225 } else {
2226 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2227 }
2228 break;
2229
2230 case ir_unop_pack_half_2x16:
2231 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2232 break;
2233 case ir_unop_unpack_half_2x16:
2234 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2235 break;
2236
2237 case ir_unop_get_buffer_size: {
2238 ir_constant *const_offset = ir->operands[0]->as_constant();
2239 int buf_base = ctx->st->has_hw_atomics
2240 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
2241 st_src_reg buffer(
2242 PROGRAM_BUFFER,
2243 buf_base + (const_offset ? const_offset->value.u[0] : 0),
2244 GLSL_TYPE_UINT);
2245 if (!const_offset) {
2246 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2247 *buffer.reladdr = op[0];
2248 emit_arl(ir, sampler_reladdr, op[0]);
2249 }
2250 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2251 break;
2252 }
2253
2254 case ir_unop_u2i64:
2255 case ir_unop_u2u64:
2256 case ir_unop_b2i64: {
2257 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2258 st_dst_reg temp_dst = st_dst_reg(temp);
2259 unsigned orig_swz = op[0].swizzle;
2260 /*
2261 * To convert unsigned to 64-bit:
2262 * zero Y channel, copy X channel.
2263 */
2264 temp_dst.writemask = WRITEMASK_Y;
2265 if (vector_elements > 1)
2266 temp_dst.writemask |= WRITEMASK_W;
2267 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2268 temp_dst.writemask = WRITEMASK_X;
2269 if (vector_elements > 1)
2270 temp_dst.writemask |= WRITEMASK_Z;
2271 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2272 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2273 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2274 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2275 else
2276 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2277 result_src = temp;
2278 result_src.type = GLSL_TYPE_UINT64;
2279 if (vector_elements > 2) {
2280 /* Subtle: We rely on the fact that get_temp here returns the next
2281 * TGSI temporary register directly after the temp register used for
2282 * the first two components, so that the result gets picked up
2283 * automatically.
2284 */
2285 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2286 st_dst_reg temp_dst = st_dst_reg(temp);
2287 temp_dst.writemask = WRITEMASK_Y;
2288 if (vector_elements > 3)
2289 temp_dst.writemask |= WRITEMASK_W;
2290 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2291
2292 temp_dst.writemask = WRITEMASK_X;
2293 if (vector_elements > 3)
2294 temp_dst.writemask |= WRITEMASK_Z;
2295 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2296 GET_SWZ(orig_swz, 2),
2297 GET_SWZ(orig_swz, 3),
2298 GET_SWZ(orig_swz, 3));
2299 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2300 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2301 else
2302 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2303 st_src_reg_for_int(1));
2304 }
2305 break;
2306 }
2307 case ir_unop_i642i:
2308 case ir_unop_u642i:
2309 case ir_unop_u642u:
2310 case ir_unop_i642u: {
2311 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2312 st_dst_reg temp_dst = st_dst_reg(temp);
2313 unsigned orig_swz = op[0].swizzle;
2314 unsigned orig_idx = op[0].index;
2315 int el;
2316 temp_dst.writemask = WRITEMASK_X;
2317
2318 for (el = 0; el < vector_elements; el++) {
2319 unsigned swz = GET_SWZ(orig_swz, el);
2320 if (swz & 1)
2321 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2322 SWIZZLE_Z, SWIZZLE_Z);
2323 else
2324 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2325 SWIZZLE_X, SWIZZLE_X);
2326 if (swz > 2)
2327 op[0].index = orig_idx + 1;
2328 op[0].type = GLSL_TYPE_UINT;
2329 temp_dst.writemask = WRITEMASK_X << el;
2330 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2331 }
2332 result_src = temp;
2333 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2334 result_src.type = GLSL_TYPE_UINT;
2335 else
2336 result_src.type = GLSL_TYPE_INT;
2337 break;
2338 }
2339 case ir_unop_i642b:
2340 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2341 st_src_reg_for_int64(0));
2342 break;
2343 case ir_unop_i642f:
2344 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2345 break;
2346 case ir_unop_u642f:
2347 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2348 break;
2349 case ir_unop_i642d:
2350 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2351 break;
2352 case ir_unop_u642d:
2353 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2354 break;
2355 case ir_unop_i2i64:
2356 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2357 break;
2358 case ir_unop_f2i64:
2359 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2360 break;
2361 case ir_unop_d2i64:
2362 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2363 break;
2364 case ir_unop_i2u64:
2365 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2366 break;
2367 case ir_unop_f2u64:
2368 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2369 break;
2370 case ir_unop_d2u64:
2371 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2372 break;
2373 /* these might be needed */
2374 case ir_unop_pack_snorm_2x16:
2375 case ir_unop_pack_unorm_2x16:
2376 case ir_unop_pack_snorm_4x8:
2377 case ir_unop_pack_unorm_4x8:
2378
2379 case ir_unop_unpack_snorm_2x16:
2380 case ir_unop_unpack_unorm_2x16:
2381 case ir_unop_unpack_snorm_4x8:
2382 case ir_unop_unpack_unorm_4x8:
2383
2384 case ir_quadop_vector:
2385 case ir_binop_vector_extract:
2386 case ir_triop_vector_insert:
2387 case ir_binop_carry:
2388 case ir_binop_borrow:
2389 case ir_unop_ssbo_unsized_array_length:
2390 /* This operation is not supported, or should have already been handled.
2391 */
2392 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2393 break;
2394 }
2395
2396 this->result = result_src;
2397 }
2398
2399
2400 void
2401 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2402 {
2403 st_src_reg src;
2404 int i;
2405 int swizzle[4];
2406
2407 /* Note that this is only swizzles in expressions, not those on the left
2408 * hand side of an assignment, which do write masking. See ir_assignment
2409 * for that.
2410 */
2411
2412 ir->val->accept(this);
2413 src = this->result;
2414 assert(src.file != PROGRAM_UNDEFINED);
2415 assert(ir->type->vector_elements > 0);
2416
2417 for (i = 0; i < 4; i++) {
2418 if (i < ir->type->vector_elements) {
2419 switch (i) {
2420 case 0:
2421 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2422 break;
2423 case 1:
2424 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2425 break;
2426 case 2:
2427 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2428 break;
2429 case 3:
2430 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2431 break;
2432 }
2433 } else {
2434 /* If the type is smaller than a vec4, replicate the last
2435 * channel out.
2436 */
2437 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2438 }
2439 }
2440
2441 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2442
2443 this->result = src;
2444 }
2445
2446 /* Test if the variable is an array. Note that geometry and
2447 * tessellation shader inputs are outputs are always arrays (except
2448 * for patch inputs), so only the array element type is considered.
2449 */
2450 static bool
2451 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2452 {
2453 const glsl_type *type = var->type;
2454
2455 *remove_array = false;
2456
2457 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2458 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2459 return false;
2460
2461 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2462 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2463 stage == MESA_SHADER_TESS_CTRL) &&
2464 !var->data.patch) {
2465 if (!var->type->is_array())
2466 return false; /* a system value probably */
2467
2468 type = var->type->fields.array;
2469 *remove_array = true;
2470 }
2471
2472 return type->is_array() || type->is_matrix();
2473 }
2474
2475 static unsigned
2476 st_translate_interp_loc(ir_variable *var)
2477 {
2478 if (var->data.centroid)
2479 return TGSI_INTERPOLATE_LOC_CENTROID;
2480 else if (var->data.sample)
2481 return TGSI_INTERPOLATE_LOC_SAMPLE;
2482 else
2483 return TGSI_INTERPOLATE_LOC_CENTER;
2484 }
2485
2486 void
2487 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2488 {
2489 variable_storage *entry;
2490 ir_variable *var = ir->var;
2491 bool remove_array;
2492
2493 if (handle_bound_deref(ir->as_dereference()))
2494 return;
2495
2496 entry = find_variable_storage(ir->var);
2497
2498 if (!entry) {
2499 switch (var->data.mode) {
2500 case ir_var_uniform:
2501 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2502 var->data.param_index);
2503 _mesa_hash_table_insert(this->variables, var, entry);
2504 break;
2505 case ir_var_shader_in: {
2506 /* The linker assigns locations for varyings and attributes,
2507 * including deprecated builtins (like gl_Color), user-assign
2508 * generic attributes (glBindVertexLocation), and
2509 * user-defined varyings.
2510 */
2511 assert(var->data.location != -1);
2512
2513 const glsl_type *type_without_array = var->type->without_array();
2514 struct inout_decl *decl = &inputs[num_inputs];
2515 unsigned component = var->data.location_frac;
2516 unsigned num_components;
2517 num_inputs++;
2518
2519 if (type_without_array->is_64bit())
2520 component = component / 2;
2521 if (type_without_array->vector_elements)
2522 num_components = type_without_array->vector_elements;
2523 else
2524 num_components = 4;
2525
2526 decl->mesa_index = var->data.location;
2527 decl->interp = (glsl_interp_mode) var->data.interpolation;
2528 decl->interp_loc = st_translate_interp_loc(var);
2529 decl->base_type = type_without_array->base_type;
2530 decl->usage_mask = u_bit_consecutive(component, num_components);
2531
2532 if (is_inout_array(shader->Stage, var, &remove_array)) {
2533 decl->array_id = num_input_arrays + 1;
2534 num_input_arrays++;
2535 } else {
2536 decl->array_id = 0;
2537 }
2538
2539 if (remove_array)
2540 decl->size = type_size(var->type->fields.array);
2541 else
2542 decl->size = type_size(var->type);
2543
2544 entry = new(mem_ctx) variable_storage(var,
2545 PROGRAM_INPUT,
2546 decl->mesa_index,
2547 decl->array_id);
2548 entry->component = component;
2549
2550 _mesa_hash_table_insert(this->variables, var, entry);
2551
2552 break;
2553 }
2554 case ir_var_shader_out: {
2555 assert(var->data.location != -1);
2556
2557 const glsl_type *type_without_array = var->type->without_array();
2558 struct inout_decl *decl = &outputs[num_outputs];
2559 unsigned component = var->data.location_frac;
2560 unsigned num_components;
2561 num_outputs++;
2562
2563 decl->invariant = var->data.invariant;
2564
2565 if (type_without_array->is_64bit())
2566 component = component / 2;
2567 if (type_without_array->vector_elements)
2568 num_components = type_without_array->vector_elements;
2569 else
2570 num_components = 4;
2571
2572 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2573 decl->base_type = type_without_array->base_type;
2574 decl->usage_mask = u_bit_consecutive(component, num_components);
2575 if (var->data.stream & (1u << 31)) {
2576 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2577 } else {
2578 assert(var->data.stream < 4);
2579 decl->gs_out_streams = 0;
2580 for (unsigned i = 0; i < num_components; ++i)
2581 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2582 }
2583
2584 if (is_inout_array(shader->Stage, var, &remove_array)) {
2585 decl->array_id = num_output_arrays + 1;
2586 num_output_arrays++;
2587 } else {
2588 decl->array_id = 0;
2589 }
2590
2591 if (remove_array)
2592 decl->size = type_size(var->type->fields.array);
2593 else
2594 decl->size = type_size(var->type);
2595
2596 if (var->data.fb_fetch_output) {
2597 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2598 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2599 var->type, component, decl->array_id);
2600 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2601 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2602 dst.array_id);
2603 } else {
2604 entry = new(mem_ctx) variable_storage(var,
2605 PROGRAM_OUTPUT,
2606 decl->mesa_index,
2607 decl->array_id);
2608 }
2609 entry->component = component;
2610
2611 _mesa_hash_table_insert(this->variables, var, entry);
2612
2613 break;
2614 }
2615 case ir_var_system_value:
2616 entry = new(mem_ctx) variable_storage(var,
2617 PROGRAM_SYSTEM_VALUE,
2618 var->data.location);
2619 break;
2620 case ir_var_auto:
2621 case ir_var_temporary:
2622 st_src_reg src = get_temp(var->type);
2623
2624 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2625 src.array_id);
2626 _mesa_hash_table_insert(this->variables, var, entry);
2627
2628 break;
2629 }
2630
2631 if (!entry) {
2632 printf("Failed to make storage for %s\n", var->name);
2633 exit(1);
2634 }
2635 }
2636
2637 this->result = st_src_reg(entry->file, entry->index, var->type,
2638 entry->component, entry->array_id);
2639 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2640 var->data.mode == ir_var_shader_in &&
2641 var->type->without_array()->is_double())
2642 this->result.is_double_vertex_input = true;
2643 if (!native_integers)
2644 this->result.type = GLSL_TYPE_FLOAT;
2645 }
2646
2647 static void
2648 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2649 GLbitfield64* usage_mask,
2650 GLbitfield64 double_usage_mask,
2651 GLbitfield* patch_usage_mask)
2652 {
2653 unsigned i;
2654 int j;
2655
2656 /* Fix array declarations by removing unused array elements at both ends
2657 * of the arrays. For example, mat4[3] where only mat[1] is used.
2658 */
2659 for (i = 0; i < count; i++) {
2660 struct inout_decl *decl = &decls[i];
2661 if (!decl->array_id)
2662 continue;
2663
2664 /* Shrink the beginning. */
2665 for (j = 0; j < (int)decl->size; j++) {
2666 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2667 if (*patch_usage_mask &
2668 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2669 break;
2670 }
2671 else {
2672 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2673 break;
2674 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2675 break;
2676 }
2677
2678 decl->mesa_index++;
2679 decl->size--;
2680 j--;
2681 }
2682
2683 /* Shrink the end. */
2684 for (j = decl->size-1; j >= 0; j--) {
2685 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2686 if (*patch_usage_mask &
2687 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2688 break;
2689 }
2690 else {
2691 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2692 break;
2693 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2694 break;
2695 }
2696
2697 decl->size--;
2698 }
2699
2700 /* When not all entries of an array are accessed, we mark them as used
2701 * here anyway, to ensure that the input/output mapping logic doesn't get
2702 * confused.
2703 *
2704 * TODO This happens when an array isn't used via indirect access, which
2705 * some game ports do (at least eON-based). There is an optimization
2706 * opportunity here by replacing the array declaration with non-array
2707 * declarations of those slots that are actually used.
2708 */
2709 for (j = 1; j < (int)decl->size; ++j) {
2710 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2711 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2712 else
2713 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2714 }
2715 }
2716 }
2717
2718 void
2719 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2720 {
2721 ir_constant *index;
2722 st_src_reg src;
2723 bool is_2D = false;
2724 ir_variable *var = ir->variable_referenced();
2725
2726 if (handle_bound_deref(ir->as_dereference()))
2727 return;
2728
2729 /* We only need the logic provided by st_glsl_storage_type_size()
2730 * for arrays of structs. Indirect sampler and image indexing is handled
2731 * elsewhere.
2732 */
2733 int element_size = ir->type->without_array()->is_struct() ?
2734 st_glsl_storage_type_size(ir->type, var->data.bindless) :
2735 type_size(ir->type);
2736
2737 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2738
2739 ir->array->accept(this);
2740 src = this->result;
2741
2742 if (!src.has_index2) {
2743 switch (this->prog->Target) {
2744 case GL_TESS_CONTROL_PROGRAM_NV:
2745 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2746 !ir->variable_referenced()->data.patch;
2747 break;
2748 case GL_TESS_EVALUATION_PROGRAM_NV:
2749 is_2D = src.file == PROGRAM_INPUT &&
2750 !ir->variable_referenced()->data.patch;
2751 break;
2752 case GL_GEOMETRY_PROGRAM_NV:
2753 is_2D = src.file == PROGRAM_INPUT;
2754 break;
2755 }
2756 }
2757
2758 if (is_2D)
2759 element_size = 1;
2760
2761 if (index) {
2762
2763 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2764 src.file == PROGRAM_INPUT)
2765 element_size = attrib_type_size(ir->type, true);
2766 if (is_2D) {
2767 src.index2D = index->value.i[0];
2768 src.has_index2 = true;
2769 } else
2770 src.index += index->value.i[0] * element_size;
2771 } else {
2772 /* Variable index array dereference. It eats the "vec4" of the
2773 * base of the array and an index that offsets the TGSI register
2774 * index.
2775 */
2776 ir->array_index->accept(this);
2777
2778 st_src_reg index_reg;
2779
2780 if (element_size == 1) {
2781 index_reg = this->result;
2782 } else {
2783 index_reg = get_temp(native_integers ?
2784 glsl_type::int_type : glsl_type::float_type);
2785
2786 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2787 this->result, st_src_reg_for_type(index_reg.type, element_size));
2788 }
2789
2790 /* If there was already a relative address register involved, add the
2791 * new and the old together to get the new offset.
2792 */
2793 if (!is_2D && src.reladdr != NULL) {
2794 st_src_reg accum_reg = get_temp(native_integers ?
2795 glsl_type::int_type : glsl_type::float_type);
2796
2797 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2798 index_reg, *src.reladdr);
2799
2800 index_reg = accum_reg;
2801 }
2802
2803 if (is_2D) {
2804 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2805 *src.reladdr2 = index_reg;
2806 src.index2D = 0;
2807 src.has_index2 = true;
2808 } else {
2809 src.reladdr = ralloc(mem_ctx, st_src_reg);
2810 *src.reladdr = index_reg;
2811 }
2812 }
2813
2814 /* Change the register type to the element type of the array. */
2815 src.type = ir->type->base_type;
2816
2817 this->result = src;
2818 }
2819
2820 void
2821 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2822 {
2823 unsigned int i;
2824 const glsl_type *struct_type = ir->record->type;
2825 ir_variable *var = ir->record->variable_referenced();
2826 int offset = 0;
2827
2828 if (handle_bound_deref(ir->as_dereference()))
2829 return;
2830
2831 ir->record->accept(this);
2832
2833 assert(ir->field_idx >= 0);
2834 assert(var);
2835 for (i = 0; i < struct_type->length; i++) {
2836 if (i == (unsigned) ir->field_idx)
2837 break;
2838 const glsl_type *member_type = struct_type->fields.structure[i].type;
2839 offset += st_glsl_storage_type_size(member_type, var->data.bindless);
2840 }
2841
2842 /* If the type is smaller than a vec4, replicate the last channel out. */
2843 if (ir->type->is_scalar() || ir->type->is_vector())
2844 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2845 else
2846 this->result.swizzle = SWIZZLE_NOOP;
2847
2848 this->result.index += offset;
2849 this->result.type = ir->type->base_type;
2850 }
2851
2852 /**
2853 * We want to be careful in assignment setup to hit the actual storage
2854 * instead of potentially using a temporary like we might with the
2855 * ir_dereference handler.
2856 */
2857 static st_dst_reg
2858 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2859 {
2860 /* The LHS must be a dereference. If the LHS is a variable indexed array
2861 * access of a vector, it must be separated into a series conditional moves
2862 * before reaching this point (see ir_vec_index_to_cond_assign).
2863 */
2864 assert(ir->as_dereference());
2865 ir_dereference_array *deref_array = ir->as_dereference_array();
2866 if (deref_array) {
2867 assert(!deref_array->array->type->is_vector());
2868 }
2869
2870 /* Use the rvalue deref handler for the most part. We write swizzles using
2871 * the writemask, but we do extract the base component for enhanced layouts
2872 * from the source swizzle.
2873 */
2874 ir->accept(v);
2875 *component = GET_SWZ(v->result.swizzle, 0);
2876 return st_dst_reg(v->result);
2877 }
2878
2879 /**
2880 * Process the condition of a conditional assignment
2881 *
2882 * Examines the condition of a conditional assignment to generate the optimal
2883 * first operand of a \c CMP instruction. If the condition is a relational
2884 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2885 * used as the source for the \c CMP instruction. Otherwise the comparison
2886 * is processed to a boolean result, and the boolean result is used as the
2887 * operand to the CMP instruction.
2888 */
2889 bool
2890 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2891 {
2892 ir_rvalue *src_ir = ir;
2893 bool negate = true;
2894 bool switch_order = false;
2895
2896 ir_expression *const expr = ir->as_expression();
2897
2898 if (native_integers) {
2899 if ((expr != NULL) && (expr->num_operands == 2)) {
2900 enum glsl_base_type type = expr->operands[0]->type->base_type;
2901 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2902 type == GLSL_TYPE_BOOL) {
2903 if (expr->operation == ir_binop_equal) {
2904 if (expr->operands[0]->is_zero()) {
2905 src_ir = expr->operands[1];
2906 switch_order = true;
2907 }
2908 else if (expr->operands[1]->is_zero()) {
2909 src_ir = expr->operands[0];
2910 switch_order = true;
2911 }
2912 }
2913 else if (expr->operation == ir_binop_nequal) {
2914 if (expr->operands[0]->is_zero()) {
2915 src_ir = expr->operands[1];
2916 }
2917 else if (expr->operands[1]->is_zero()) {
2918 src_ir = expr->operands[0];
2919 }
2920 }
2921 }
2922 }
2923
2924 src_ir->accept(this);
2925 return switch_order;
2926 }
2927
2928 if ((expr != NULL) && (expr->num_operands == 2)) {
2929 bool zero_on_left = false;
2930
2931 if (expr->operands[0]->is_zero()) {
2932 src_ir = expr->operands[1];
2933 zero_on_left = true;
2934 } else if (expr->operands[1]->is_zero()) {
2935 src_ir = expr->operands[0];
2936 zero_on_left = false;
2937 }
2938
2939 /* a is - 0 + - 0 +
2940 * (a < 0) T F F ( a < 0) T F F
2941 * (0 < a) F F T (-a < 0) F F T
2942 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2943 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2944 *
2945 * Note that exchanging the order of 0 and 'a' in the comparison simply
2946 * means that the value of 'a' should be negated.
2947 */
2948 if (src_ir != ir) {
2949 switch (expr->operation) {
2950 case ir_binop_less:
2951 switch_order = false;
2952 negate = zero_on_left;
2953 break;
2954
2955 case ir_binop_gequal:
2956 switch_order = true;
2957 negate = zero_on_left;
2958 break;
2959
2960 default:
2961 /* This isn't the right kind of comparison afterall, so make sure
2962 * the whole condition is visited.
2963 */
2964 src_ir = ir;
2965 break;
2966 }
2967 }
2968 }
2969
2970 src_ir->accept(this);
2971
2972 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2973 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2974 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2975 * computing the condition.
2976 */
2977 if (negate)
2978 this->result.negate = ~this->result.negate;
2979
2980 return switch_order;
2981 }
2982
2983 void
2984 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
2985 st_dst_reg *l, st_src_reg *r,
2986 st_src_reg *cond, bool cond_swap)
2987 {
2988 if (type->is_struct()) {
2989 for (unsigned int i = 0; i < type->length; i++) {
2990 emit_block_mov(ir, type->fields.structure[i].type, l, r,
2991 cond, cond_swap);
2992 }
2993 return;
2994 }
2995
2996 if (type->is_array()) {
2997 for (unsigned int i = 0; i < type->length; i++) {
2998 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
2999 }
3000 return;
3001 }
3002
3003 if (type->is_matrix()) {
3004 const struct glsl_type *vec_type;
3005
3006 vec_type = glsl_type::get_instance(type->is_double()
3007 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3008 type->vector_elements, 1);
3009
3010 for (int i = 0; i < type->matrix_columns; i++) {
3011 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3012 }
3013 return;
3014 }
3015
3016 assert(type->is_scalar() || type->is_vector());
3017
3018 l->type = type->base_type;
3019 r->type = type->base_type;
3020 if (cond) {
3021 st_src_reg l_src = st_src_reg(*l);
3022
3023 if (l_src.file == PROGRAM_OUTPUT &&
3024 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3025 (l_src.index == FRAG_RESULT_DEPTH ||
3026 l_src.index == FRAG_RESULT_STENCIL)) {
3027 /* This is a special case because the source swizzles will be shifted
3028 * later to account for the difference between GLSL (where they're
3029 * plain floats) and TGSI (where they're Z and Y components). */
3030 l_src.swizzle = SWIZZLE_XXXX;
3031 }
3032
3033 if (native_integers) {
3034 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3035 cond_swap ? l_src : *r,
3036 cond_swap ? *r : l_src);
3037 } else {
3038 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3039 cond_swap ? l_src : *r,
3040 cond_swap ? *r : l_src);
3041 }
3042 } else {
3043 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3044 }
3045 l->index++;
3046 r->index++;
3047 if (type->is_dual_slot()) {
3048 l->index++;
3049 if (r->is_double_vertex_input == false)
3050 r->index++;
3051 }
3052 }
3053
3054 void
3055 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3056 {
3057 int dst_component;
3058 st_dst_reg l;
3059 st_src_reg r;
3060
3061 /* all generated instructions need to be flaged as precise */
3062 this->precise = is_precise(ir->lhs->variable_referenced());
3063 ir->rhs->accept(this);
3064 r = this->result;
3065
3066 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3067
3068 {
3069 int swizzles[4];
3070 int first_enabled_chan = 0;
3071 int rhs_chan = 0;
3072 ir_variable *variable = ir->lhs->variable_referenced();
3073
3074 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3075 variable->data.mode == ir_var_shader_out &&
3076 (variable->data.location == FRAG_RESULT_DEPTH ||
3077 variable->data.location == FRAG_RESULT_STENCIL)) {
3078 assert(ir->lhs->type->is_scalar());
3079 assert(ir->write_mask == WRITEMASK_X);
3080
3081 if (variable->data.location == FRAG_RESULT_DEPTH)
3082 l.writemask = WRITEMASK_Z;
3083 else {
3084 assert(variable->data.location == FRAG_RESULT_STENCIL);
3085 l.writemask = WRITEMASK_Y;
3086 }
3087 } else if (ir->write_mask == 0) {
3088 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3089
3090 unsigned num_elements =
3091 ir->lhs->type->without_array()->vector_elements;
3092
3093 if (num_elements) {
3094 l.writemask = u_bit_consecutive(0, num_elements);
3095 } else {
3096 /* The type is a struct or an array of (array of) structs. */
3097 l.writemask = WRITEMASK_XYZW;
3098 }
3099 } else {
3100 l.writemask = ir->write_mask;
3101 }
3102
3103 for (int i = 0; i < 4; i++) {
3104 if (l.writemask & (1 << i)) {
3105 first_enabled_chan = GET_SWZ(r.swizzle, i);
3106 break;
3107 }
3108 }
3109
3110 l.writemask = l.writemask << dst_component;
3111
3112 /* Swizzle a small RHS vector into the channels being written.
3113 *
3114 * glsl ir treats write_mask as dictating how many channels are
3115 * present on the RHS while TGSI treats write_mask as just
3116 * showing which channels of the vec4 RHS get written.
3117 */
3118 for (int i = 0; i < 4; i++) {
3119 if (l.writemask & (1 << i))
3120 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3121 else
3122 swizzles[i] = first_enabled_chan;
3123 }
3124 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3125 swizzles[2], swizzles[3]);
3126 }
3127
3128 assert(l.file != PROGRAM_UNDEFINED);
3129 assert(r.file != PROGRAM_UNDEFINED);
3130
3131 if (ir->condition) {
3132 const bool switch_order = this->process_move_condition(ir->condition);
3133 st_src_reg condition = this->result;
3134
3135 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3136 } else if (ir->rhs->as_expression() &&
3137 this->instructions.get_tail() &&
3138 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3139 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3140 type_size(ir->lhs->type) == 1 &&
3141 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3142 /* To avoid emitting an extra MOV when assigning an expression to a
3143 * variable, emit the last instruction of the expression again, but
3144 * replace the destination register with the target of the assignment.
3145 * Dead code elimination will remove the original instruction.
3146 */
3147 glsl_to_tgsi_instruction *inst, *new_inst;
3148 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3149 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3150 new_inst->saturate = inst->saturate;
3151 new_inst->resource = inst->resource;
3152 inst->dead_mask = inst->dst[0].writemask;
3153 } else {
3154 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3155 }
3156 this->precise = 0;
3157 }
3158
3159
3160 void
3161 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3162 {
3163 st_src_reg src;
3164 GLdouble stack_vals[4] = { 0 };
3165 gl_constant_value *values = (gl_constant_value *) stack_vals;
3166 GLenum gl_type = GL_NONE;
3167 unsigned int i, elements;
3168 static int in_array = 0;
3169 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3170
3171 /* Unfortunately, 4 floats is all we can get into
3172 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3173 * aggregate constant and move each constant value into it. If we
3174 * get lucky, copy propagation will eliminate the extra moves.
3175 */
3176 if (ir->type->is_struct()) {
3177 st_src_reg temp_base = get_temp(ir->type);
3178 st_dst_reg temp = st_dst_reg(temp_base);
3179
3180 for (i = 0; i < ir->type->length; i++) {
3181 ir_constant *const field_value = ir->get_record_field(i);
3182 int size = type_size(field_value->type);
3183
3184 assert(size > 0);
3185
3186 field_value->accept(this);
3187 src = this->result;
3188
3189 for (unsigned j = 0; j < (unsigned int)size; j++) {
3190 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3191
3192 src.index++;
3193 temp.index++;
3194 }
3195 }
3196 this->result = temp_base;
3197 return;
3198 }
3199
3200 if (ir->type->is_array()) {
3201 st_src_reg temp_base = get_temp(ir->type);
3202 st_dst_reg temp = st_dst_reg(temp_base);
3203 int size = type_size(ir->type->fields.array);
3204
3205 assert(size > 0);
3206 in_array++;
3207
3208 for (i = 0; i < ir->type->length; i++) {
3209 ir->const_elements[i]->accept(this);
3210 src = this->result;
3211 for (int j = 0; j < size; j++) {
3212 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3213
3214 src.index++;
3215 temp.index++;
3216 }
3217 }
3218 this->result = temp_base;
3219 in_array--;
3220 return;
3221 }
3222
3223 if (ir->type->is_matrix()) {
3224 st_src_reg mat = get_temp(ir->type);
3225 st_dst_reg mat_column = st_dst_reg(mat);
3226
3227 for (i = 0; i < ir->type->matrix_columns; i++) {
3228 switch (ir->type->base_type) {
3229 case GLSL_TYPE_FLOAT:
3230 values = (gl_constant_value *)
3231 &ir->value.f[i * ir->type->vector_elements];
3232
3233 src = st_src_reg(file, -1, ir->type->base_type);
3234 src.index = add_constant(file,
3235 values,
3236 ir->type->vector_elements,
3237 GL_FLOAT,
3238 &src.swizzle);
3239 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3240 break;
3241 case GLSL_TYPE_DOUBLE:
3242 values = (gl_constant_value *)
3243 &ir->value.d[i * ir->type->vector_elements];
3244 src = st_src_reg(file, -1, ir->type->base_type);
3245 src.index = add_constant(file,
3246 values,
3247 ir->type->vector_elements,
3248 GL_DOUBLE,
3249 &src.swizzle);
3250 if (ir->type->vector_elements >= 2) {
3251 mat_column.writemask = WRITEMASK_XY;
3252 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3253 SWIZZLE_X, SWIZZLE_Y);
3254 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3255 } else {
3256 mat_column.writemask = WRITEMASK_X;
3257 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3258 SWIZZLE_X, SWIZZLE_X);
3259 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3260 }
3261 src.index++;
3262 if (ir->type->vector_elements > 2) {
3263 if (ir->type->vector_elements == 4) {
3264 mat_column.writemask = WRITEMASK_ZW;
3265 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3266 SWIZZLE_X, SWIZZLE_Y);
3267 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3268 } else {
3269 mat_column.writemask = WRITEMASK_Z;
3270 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3271 SWIZZLE_Y, SWIZZLE_Y);
3272 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3273 mat_column.writemask = WRITEMASK_XYZW;
3274 src.swizzle = SWIZZLE_XYZW;
3275 }
3276 mat_column.index++;
3277 }
3278 break;
3279 default:
3280 unreachable("Illegal matrix constant type.\n");
3281 break;
3282 }
3283 mat_column.index++;
3284 }
3285 this->result = mat;
3286 return;
3287 }
3288
3289 elements = ir->type->vector_elements;
3290 switch (ir->type->base_type) {
3291 case GLSL_TYPE_FLOAT:
3292 gl_type = GL_FLOAT;
3293 for (i = 0; i < ir->type->vector_elements; i++) {
3294 values[i].f = ir->value.f[i];
3295 }
3296 break;
3297 case GLSL_TYPE_DOUBLE:
3298 gl_type = GL_DOUBLE;
3299 for (i = 0; i < ir->type->vector_elements; i++) {
3300 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3301 }
3302 break;
3303 case GLSL_TYPE_INT64:
3304 gl_type = GL_INT64_ARB;
3305 for (i = 0; i < ir->type->vector_elements; i++) {
3306 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3307 }
3308 break;
3309 case GLSL_TYPE_UINT64:
3310 gl_type = GL_UNSIGNED_INT64_ARB;
3311 for (i = 0; i < ir->type->vector_elements; i++) {
3312 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3313 }
3314 break;
3315 case GLSL_TYPE_UINT:
3316 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3317 for (i = 0; i < ir->type->vector_elements; i++) {
3318 if (native_integers)
3319 values[i].u = ir->value.u[i];
3320 else
3321 values[i].f = ir->value.u[i];
3322 }
3323 break;
3324 case GLSL_TYPE_INT:
3325 gl_type = native_integers ? GL_INT : GL_FLOAT;
3326 for (i = 0; i < ir->type->vector_elements; i++) {
3327 if (native_integers)
3328 values[i].i = ir->value.i[i];
3329 else
3330 values[i].f = ir->value.i[i];
3331 }
3332 break;
3333 case GLSL_TYPE_BOOL:
3334 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3335 for (i = 0; i < ir->type->vector_elements; i++) {
3336 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3337 }
3338 break;
3339 case GLSL_TYPE_SAMPLER:
3340 case GLSL_TYPE_IMAGE:
3341 gl_type = GL_UNSIGNED_INT;
3342 elements = 2;
3343 values[0].u = ir->value.u64[0] & 0xffffffff;
3344 values[1].u = ir->value.u64[0] >> 32;
3345 break;
3346 default:
3347 assert(!"Non-float/uint/int/bool/sampler/image constant");
3348 }
3349
3350 this->result = st_src_reg(file, -1, ir->type);
3351 this->result.index = add_constant(file,
3352 values,
3353 elements,
3354 gl_type,
3355 &this->result.swizzle);
3356 }
3357
3358 void
3359 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3360 {
3361 exec_node *param = ir->actual_parameters.get_head();
3362 ir_dereference *deref = static_cast<ir_dereference *>(param);
3363 ir_variable *location = deref->variable_referenced();
3364 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3365 /* Calculate the surface offset */
3366 st_src_reg offset;
3367 unsigned array_size = 0, base = 0;
3368 uint16_t index = 0;
3369 st_src_reg resource;
3370
3371 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3372
3373 if (has_hw_atomics) {
3374 variable_storage *entry = find_variable_storage(location);
3375 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3376 location->data.binding);
3377
3378 if (!entry) {
3379 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3380 num_atomics);
3381 _mesa_hash_table_insert(this->variables, location, entry);
3382
3383 atomic_info[num_atomics].location = location->data.location;
3384 atomic_info[num_atomics].binding = location->data.binding;
3385 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3386 if (atomic_info[num_atomics].size == 0)
3387 atomic_info[num_atomics].size = 1;
3388 atomic_info[num_atomics].array_id = 0;
3389 num_atomics++;
3390 }
3391
3392 if (offset.file != PROGRAM_UNDEFINED) {
3393 if (atomic_info[entry->index].array_id == 0) {
3394 num_atomic_arrays++;
3395 atomic_info[entry->index].array_id = num_atomic_arrays;
3396 }
3397 buffer.array_id = atomic_info[entry->index].array_id;
3398 }
3399
3400 buffer.index = index;
3401 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3402 buffer.has_index2 = true;
3403
3404 if (offset.file != PROGRAM_UNDEFINED) {
3405 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3406 *buffer.reladdr = offset;
3407 emit_arl(ir, sampler_reladdr, offset);
3408 }
3409 offset = st_src_reg_for_int(0);
3410
3411 resource = buffer;
3412 } else {
3413 st_src_reg buffer(PROGRAM_BUFFER, location->data.binding,
3414 GLSL_TYPE_ATOMIC_UINT);
3415
3416 if (offset.file != PROGRAM_UNDEFINED) {
3417 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3418 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3419 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3420 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3421 } else {
3422 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3423 }
3424 resource = buffer;
3425 }
3426
3427 ir->return_deref->accept(this);
3428 st_dst_reg dst(this->result);
3429 dst.writemask = WRITEMASK_X;
3430
3431 glsl_to_tgsi_instruction *inst;
3432
3433 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3434 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3435 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3436 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3437 st_src_reg_for_int(1));
3438 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3439 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3440 st_src_reg_for_int(-1));
3441 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3442 } else {
3443 param = param->get_next();
3444 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3445 val->accept(this);
3446
3447 st_src_reg data = this->result, data2 = undef_src;
3448 enum tgsi_opcode opcode;
3449 switch (ir->callee->intrinsic_id) {
3450 case ir_intrinsic_atomic_counter_add:
3451 opcode = TGSI_OPCODE_ATOMUADD;
3452 break;
3453 case ir_intrinsic_atomic_counter_min:
3454 opcode = TGSI_OPCODE_ATOMIMIN;
3455 break;
3456 case ir_intrinsic_atomic_counter_max:
3457 opcode = TGSI_OPCODE_ATOMIMAX;
3458 break;
3459 case ir_intrinsic_atomic_counter_and:
3460 opcode = TGSI_OPCODE_ATOMAND;
3461 break;
3462 case ir_intrinsic_atomic_counter_or:
3463 opcode = TGSI_OPCODE_ATOMOR;
3464 break;
3465 case ir_intrinsic_atomic_counter_xor:
3466 opcode = TGSI_OPCODE_ATOMXOR;
3467 break;
3468 case ir_intrinsic_atomic_counter_exchange:
3469 opcode = TGSI_OPCODE_ATOMXCHG;
3470 break;
3471 case ir_intrinsic_atomic_counter_comp_swap: {
3472 opcode = TGSI_OPCODE_ATOMCAS;
3473 param = param->get_next();
3474 val = ((ir_instruction *)param)->as_rvalue();
3475 val->accept(this);
3476 data2 = this->result;
3477 break;
3478 }
3479 default:
3480 assert(!"Unexpected intrinsic");
3481 return;
3482 }
3483
3484 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3485 }
3486
3487 inst->resource = resource;
3488 }
3489
3490 void
3491 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3492 {
3493 exec_node *param = ir->actual_parameters.get_head();
3494
3495 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3496
3497 param = param->get_next();
3498 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3499
3500 ir_constant *const_block = block->as_constant();
3501 int buf_base = st_context(ctx)->has_hw_atomics
3502 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
3503 st_src_reg buffer(
3504 PROGRAM_BUFFER,
3505 buf_base + (const_block ? const_block->value.u[0] : 0),
3506 GLSL_TYPE_UINT);
3507
3508 if (!const_block) {
3509 block->accept(this);
3510 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3511 *buffer.reladdr = this->result;
3512 emit_arl(ir, sampler_reladdr, this->result);
3513 }
3514
3515 /* Calculate the surface offset */
3516 offset->accept(this);
3517 st_src_reg off = this->result;
3518
3519 st_dst_reg dst = undef_dst;
3520 if (ir->return_deref) {
3521 ir->return_deref->accept(this);
3522 dst = st_dst_reg(this->result);
3523 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3524 }
3525
3526 glsl_to_tgsi_instruction *inst;
3527
3528 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3529 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3530 if (dst.type == GLSL_TYPE_BOOL)
3531 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3532 st_src_reg_for_int(0));
3533 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3534 param = param->get_next();
3535 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3536 val->accept(this);
3537
3538 param = param->get_next();
3539 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3540 assert(write_mask);
3541 dst.writemask = write_mask->value.u[0];
3542
3543 dst.type = this->result.type;
3544 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3545 } else {
3546 param = param->get_next();
3547 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3548 val->accept(this);
3549
3550 st_src_reg data = this->result, data2 = undef_src;
3551 enum tgsi_opcode opcode;
3552 switch (ir->callee->intrinsic_id) {
3553 case ir_intrinsic_ssbo_atomic_add:
3554 opcode = TGSI_OPCODE_ATOMUADD;
3555 break;
3556 case ir_intrinsic_ssbo_atomic_min:
3557 opcode = TGSI_OPCODE_ATOMIMIN;
3558 break;
3559 case ir_intrinsic_ssbo_atomic_max:
3560 opcode = TGSI_OPCODE_ATOMIMAX;
3561 break;
3562 case ir_intrinsic_ssbo_atomic_and:
3563 opcode = TGSI_OPCODE_ATOMAND;
3564 break;
3565 case ir_intrinsic_ssbo_atomic_or:
3566 opcode = TGSI_OPCODE_ATOMOR;
3567 break;
3568 case ir_intrinsic_ssbo_atomic_xor:
3569 opcode = TGSI_OPCODE_ATOMXOR;
3570 break;
3571 case ir_intrinsic_ssbo_atomic_exchange:
3572 opcode = TGSI_OPCODE_ATOMXCHG;
3573 break;
3574 case ir_intrinsic_ssbo_atomic_comp_swap:
3575 opcode = TGSI_OPCODE_ATOMCAS;
3576 param = param->get_next();
3577 val = ((ir_instruction *)param)->as_rvalue();
3578 val->accept(this);
3579 data2 = this->result;
3580 break;
3581 default:
3582 assert(!"Unexpected intrinsic");
3583 return;
3584 }
3585
3586 inst = emit_asm(ir, opcode, dst, off, data, data2);
3587 }
3588
3589 param = param->get_next();
3590 ir_constant *access = NULL;
3591 if (!param->is_tail_sentinel()) {
3592 access = ((ir_instruction *)param)->as_constant();
3593 assert(access);
3594 }
3595
3596 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3597 }
3598
3599 void
3600 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3601 {
3602 switch (ir->callee->intrinsic_id) {
3603 case ir_intrinsic_memory_barrier:
3604 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3605 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3606 TGSI_MEMBAR_ATOMIC_BUFFER |
3607 TGSI_MEMBAR_SHADER_IMAGE |
3608 TGSI_MEMBAR_SHARED));
3609 break;
3610 case ir_intrinsic_memory_barrier_atomic_counter:
3611 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3612 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3613 break;
3614 case ir_intrinsic_memory_barrier_buffer:
3615 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3616 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3617 break;
3618 case ir_intrinsic_memory_barrier_image:
3619 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3620 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3621 break;
3622 case ir_intrinsic_memory_barrier_shared:
3623 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3624 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3625 break;
3626 case ir_intrinsic_group_memory_barrier:
3627 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3628 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3629 TGSI_MEMBAR_ATOMIC_BUFFER |
3630 TGSI_MEMBAR_SHADER_IMAGE |
3631 TGSI_MEMBAR_SHARED |
3632 TGSI_MEMBAR_THREAD_GROUP));
3633 break;
3634 default:
3635 assert(!"Unexpected memory barrier intrinsic");
3636 }
3637 }
3638
3639 void
3640 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3641 {
3642 exec_node *param = ir->actual_parameters.get_head();
3643
3644 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3645
3646 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3647
3648 /* Calculate the surface offset */
3649 offset->accept(this);
3650 st_src_reg off = this->result;
3651
3652 st_dst_reg dst = undef_dst;
3653 if (ir->return_deref) {
3654 ir->return_deref->accept(this);
3655 dst = st_dst_reg(this->result);
3656 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3657 }
3658
3659 glsl_to_tgsi_instruction *inst;
3660
3661 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3662 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3663 inst->resource = buffer;
3664 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3665 param = param->get_next();
3666 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3667 val->accept(this);
3668
3669 param = param->get_next();
3670 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3671 assert(write_mask);
3672 dst.writemask = write_mask->value.u[0];
3673
3674 dst.type = this->result.type;
3675 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3676 inst->resource = buffer;
3677 } else {
3678 param = param->get_next();
3679 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3680 val->accept(this);
3681
3682 st_src_reg data = this->result, data2 = undef_src;
3683 enum tgsi_opcode opcode;
3684 switch (ir->callee->intrinsic_id) {
3685 case ir_intrinsic_shared_atomic_add:
3686 opcode = TGSI_OPCODE_ATOMUADD;
3687 break;
3688 case ir_intrinsic_shared_atomic_min:
3689 opcode = TGSI_OPCODE_ATOMIMIN;
3690 break;
3691 case ir_intrinsic_shared_atomic_max:
3692 opcode = TGSI_OPCODE_ATOMIMAX;
3693 break;
3694 case ir_intrinsic_shared_atomic_and:
3695 opcode = TGSI_OPCODE_ATOMAND;
3696 break;
3697 case ir_intrinsic_shared_atomic_or:
3698 opcode = TGSI_OPCODE_ATOMOR;
3699 break;
3700 case ir_intrinsic_shared_atomic_xor:
3701 opcode = TGSI_OPCODE_ATOMXOR;
3702 break;
3703 case ir_intrinsic_shared_atomic_exchange:
3704 opcode = TGSI_OPCODE_ATOMXCHG;
3705 break;
3706 case ir_intrinsic_shared_atomic_comp_swap:
3707 opcode = TGSI_OPCODE_ATOMCAS;
3708 param = param->get_next();
3709 val = ((ir_instruction *)param)->as_rvalue();
3710 val->accept(this);
3711 data2 = this->result;
3712 break;
3713 default:
3714 assert(!"Unexpected intrinsic");
3715 return;
3716 }
3717
3718 inst = emit_asm(ir, opcode, dst, off, data, data2);
3719 inst->resource = buffer;
3720 }
3721 }
3722
3723 static void
3724 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3725 bool *memory_coherent, bool *memory_volatile,
3726 bool *memory_restrict, bool *memory_read_only,
3727 unsigned *image_format)
3728 {
3729
3730 switch (ir->ir_type) {
3731 case ir_type_dereference_record: {
3732 ir_dereference_record *deref_record = ir->as_dereference_record();
3733 const glsl_type *struct_type = deref_record->record->type;
3734 int fild_idx = deref_record->field_idx;
3735
3736 *type = struct_type->fields.structure[fild_idx].type->without_array();
3737 *memory_coherent =
3738 struct_type->fields.structure[fild_idx].memory_coherent;
3739 *memory_volatile =
3740 struct_type->fields.structure[fild_idx].memory_volatile;
3741 *memory_restrict =
3742 struct_type->fields.structure[fild_idx].memory_restrict;
3743 *memory_read_only =
3744 struct_type->fields.structure[fild_idx].memory_read_only;
3745 *image_format =
3746 struct_type->fields.structure[fild_idx].image_format;
3747 break;
3748 }
3749
3750 case ir_type_dereference_array: {
3751 ir_dereference_array *deref_arr = ir->as_dereference_array();
3752 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3753 memory_coherent, memory_volatile, memory_restrict,
3754 memory_read_only, image_format);
3755 break;
3756 }
3757
3758 case ir_type_dereference_variable: {
3759 ir_variable *var = ir->variable_referenced();
3760
3761 *type = var->type->without_array();
3762 *memory_coherent = var->data.memory_coherent;
3763 *memory_volatile = var->data.memory_volatile;
3764 *memory_restrict = var->data.memory_restrict;
3765 *memory_read_only = var->data.memory_read_only;
3766 *image_format = var->data.image_format;
3767 break;
3768 }
3769
3770 default:
3771 break;
3772 }
3773 }
3774
3775 void
3776 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3777 {
3778 exec_node *param = ir->actual_parameters.get_head();
3779
3780 ir_dereference *img = (ir_dereference *)param;
3781 const ir_variable *imgvar = img->variable_referenced();
3782 unsigned sampler_array_size = 1, sampler_base = 0;
3783 bool memory_coherent = false, memory_volatile = false,
3784 memory_restrict = false, memory_read_only = false;
3785 unsigned image_format = 0;
3786 const glsl_type *type = NULL;
3787
3788 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3789 &memory_restrict, &memory_read_only, &image_format);
3790
3791 st_src_reg reladdr;
3792 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3793 uint16_t index = 0;
3794 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3795 &index, &reladdr, !imgvar->contains_bindless());
3796
3797 image.index = index;
3798 if (reladdr.file != PROGRAM_UNDEFINED) {
3799 image.reladdr = ralloc(mem_ctx, st_src_reg);
3800 *image.reladdr = reladdr;
3801 emit_arl(ir, sampler_reladdr, reladdr);
3802 }
3803
3804 st_dst_reg dst = undef_dst;
3805 if (ir->return_deref) {
3806 ir->return_deref->accept(this);
3807 dst = st_dst_reg(this->result);
3808 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3809 }
3810
3811 glsl_to_tgsi_instruction *inst;
3812
3813 st_src_reg bindless;
3814 if (imgvar->contains_bindless()) {
3815 img->accept(this);
3816 bindless = this->result;
3817 }
3818
3819 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3820 dst.writemask = WRITEMASK_XYZ;
3821 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3822 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3823 st_src_reg res = get_temp(glsl_type::ivec4_type);
3824 st_dst_reg dstres = st_dst_reg(res);
3825 dstres.writemask = WRITEMASK_W;
3826 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3827 res.swizzle = SWIZZLE_WWWW;
3828 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3829 } else {
3830 st_src_reg arg1 = undef_src, arg2 = undef_src;
3831 st_src_reg coord;
3832 st_dst_reg coord_dst;
3833 coord = get_temp(glsl_type::ivec4_type);
3834 coord_dst = st_dst_reg(coord);
3835 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3836 param = param->get_next();
3837 ((ir_dereference *)param)->accept(this);
3838 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3839 coord.swizzle = SWIZZLE_XXXX;
3840 switch (type->coordinate_components()) {
3841 case 4: assert(!"unexpected coord count");
3842 /* fallthrough */
3843 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3844 /* fallthrough */
3845 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3846 }
3847
3848 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3849 param = param->get_next();
3850 ((ir_dereference *)param)->accept(this);
3851 st_src_reg sample = this->result;
3852 sample.swizzle = SWIZZLE_XXXX;
3853 coord_dst.writemask = WRITEMASK_W;
3854 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3855 coord.swizzle |= SWIZZLE_W << 9;
3856 }
3857
3858 param = param->get_next();
3859 if (!param->is_tail_sentinel()) {
3860 ((ir_dereference *)param)->accept(this);
3861 arg1 = this->result;
3862 param = param->get_next();
3863 }
3864
3865 if (!param->is_tail_sentinel()) {
3866 ((ir_dereference *)param)->accept(this);
3867 arg2 = this->result;
3868 param = param->get_next();
3869 }
3870
3871 assert(param->is_tail_sentinel());
3872
3873 enum tgsi_opcode opcode;
3874 switch (ir->callee->intrinsic_id) {
3875 case ir_intrinsic_image_load:
3876 opcode = TGSI_OPCODE_LOAD;
3877 break;
3878 case ir_intrinsic_image_store:
3879 opcode = TGSI_OPCODE_STORE;
3880 break;
3881 case ir_intrinsic_image_atomic_add:
3882 opcode = TGSI_OPCODE_ATOMUADD;
3883 break;
3884 case ir_intrinsic_image_atomic_min:
3885 opcode = TGSI_OPCODE_ATOMIMIN;
3886 break;
3887 case ir_intrinsic_image_atomic_max:
3888 opcode = TGSI_OPCODE_ATOMIMAX;
3889 break;
3890 case ir_intrinsic_image_atomic_and:
3891 opcode = TGSI_OPCODE_ATOMAND;
3892 break;
3893 case ir_intrinsic_image_atomic_or:
3894 opcode = TGSI_OPCODE_ATOMOR;
3895 break;
3896 case ir_intrinsic_image_atomic_xor:
3897 opcode = TGSI_OPCODE_ATOMXOR;
3898 break;
3899 case ir_intrinsic_image_atomic_exchange:
3900 opcode = TGSI_OPCODE_ATOMXCHG;
3901 break;
3902 case ir_intrinsic_image_atomic_comp_swap:
3903 opcode = TGSI_OPCODE_ATOMCAS;
3904 break;
3905 default:
3906 assert(!"Unexpected intrinsic");
3907 return;
3908 }
3909
3910 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3911 if (opcode == TGSI_OPCODE_STORE)
3912 inst->dst[0].writemask = WRITEMASK_XYZW;
3913 }
3914
3915 if (imgvar->contains_bindless()) {
3916 inst->resource = bindless;
3917 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3918 SWIZZLE_X, SWIZZLE_Y);
3919 } else {
3920 inst->resource = image;
3921 inst->sampler_array_size = sampler_array_size;
3922 inst->sampler_base = sampler_base;
3923 }
3924
3925 inst->tex_target = type->sampler_index();
3926 inst->image_format = st_mesa_format_to_pipe_format(st_context(ctx),
3927 _mesa_get_shader_image_format(image_format));
3928 inst->read_only = memory_read_only;
3929
3930 if (memory_coherent)
3931 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3932 if (memory_restrict)
3933 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3934 if (memory_volatile)
3935 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3936 }
3937
3938 void
3939 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
3940 {
3941 ir->return_deref->accept(this);
3942 st_dst_reg dst = st_dst_reg(this->result);
3943
3944 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
3945
3946 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
3947 unsigned num_src = 0;
3948 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
3949 assert(num_src < ARRAY_SIZE(src));
3950
3951 this->result.file = PROGRAM_UNDEFINED;
3952 param->accept(this);
3953 assert(this->result.file != PROGRAM_UNDEFINED);
3954
3955 src[num_src] = this->result;
3956 num_src++;
3957 }
3958
3959 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
3960 }
3961
3962 void
3963 glsl_to_tgsi_visitor::visit(ir_call *ir)
3964 {
3965 ir_function_signature *sig = ir->callee;
3966
3967 /* Filter out intrinsics */
3968 switch (sig->intrinsic_id) {
3969 case ir_intrinsic_atomic_counter_read:
3970 case ir_intrinsic_atomic_counter_increment:
3971 case ir_intrinsic_atomic_counter_predecrement:
3972 case ir_intrinsic_atomic_counter_add:
3973 case ir_intrinsic_atomic_counter_min:
3974 case ir_intrinsic_atomic_counter_max:
3975 case ir_intrinsic_atomic_counter_and:
3976 case ir_intrinsic_atomic_counter_or:
3977 case ir_intrinsic_atomic_counter_xor:
3978 case ir_intrinsic_atomic_counter_exchange:
3979 case ir_intrinsic_atomic_counter_comp_swap:
3980 visit_atomic_counter_intrinsic(ir);
3981 return;
3982
3983 case ir_intrinsic_ssbo_load:
3984 case ir_intrinsic_ssbo_store:
3985 case ir_intrinsic_ssbo_atomic_add:
3986 case ir_intrinsic_ssbo_atomic_min:
3987 case ir_intrinsic_ssbo_atomic_max:
3988 case ir_intrinsic_ssbo_atomic_and:
3989 case ir_intrinsic_ssbo_atomic_or:
3990 case ir_intrinsic_ssbo_atomic_xor:
3991 case ir_intrinsic_ssbo_atomic_exchange:
3992 case ir_intrinsic_ssbo_atomic_comp_swap:
3993 visit_ssbo_intrinsic(ir);
3994 return;
3995
3996 case ir_intrinsic_memory_barrier:
3997 case ir_intrinsic_memory_barrier_atomic_counter:
3998 case ir_intrinsic_memory_barrier_buffer:
3999 case ir_intrinsic_memory_barrier_image:
4000 case ir_intrinsic_memory_barrier_shared:
4001 case ir_intrinsic_group_memory_barrier:
4002 visit_membar_intrinsic(ir);
4003 return;
4004
4005 case ir_intrinsic_shared_load:
4006 case ir_intrinsic_shared_store:
4007 case ir_intrinsic_shared_atomic_add:
4008 case ir_intrinsic_shared_atomic_min:
4009 case ir_intrinsic_shared_atomic_max:
4010 case ir_intrinsic_shared_atomic_and:
4011 case ir_intrinsic_shared_atomic_or:
4012 case ir_intrinsic_shared_atomic_xor:
4013 case ir_intrinsic_shared_atomic_exchange:
4014 case ir_intrinsic_shared_atomic_comp_swap:
4015 visit_shared_intrinsic(ir);
4016 return;
4017
4018 case ir_intrinsic_image_load:
4019 case ir_intrinsic_image_store:
4020 case ir_intrinsic_image_atomic_add:
4021 case ir_intrinsic_image_atomic_min:
4022 case ir_intrinsic_image_atomic_max:
4023 case ir_intrinsic_image_atomic_and:
4024 case ir_intrinsic_image_atomic_or:
4025 case ir_intrinsic_image_atomic_xor:
4026 case ir_intrinsic_image_atomic_exchange:
4027 case ir_intrinsic_image_atomic_comp_swap:
4028 case ir_intrinsic_image_size:
4029 case ir_intrinsic_image_samples:
4030 visit_image_intrinsic(ir);
4031 return;
4032
4033 case ir_intrinsic_shader_clock:
4034 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4035 return;
4036
4037 case ir_intrinsic_vote_all:
4038 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4039 return;
4040 case ir_intrinsic_vote_any:
4041 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4042 return;
4043 case ir_intrinsic_vote_eq:
4044 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4045 return;
4046 case ir_intrinsic_ballot:
4047 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4048 return;
4049 case ir_intrinsic_read_first_invocation:
4050 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4051 return;
4052 case ir_intrinsic_read_invocation:
4053 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4054 return;
4055
4056 case ir_intrinsic_invalid:
4057 case ir_intrinsic_generic_load:
4058 case ir_intrinsic_generic_store:
4059 case ir_intrinsic_generic_atomic_add:
4060 case ir_intrinsic_generic_atomic_and:
4061 case ir_intrinsic_generic_atomic_or:
4062 case ir_intrinsic_generic_atomic_xor:
4063 case ir_intrinsic_generic_atomic_min:
4064 case ir_intrinsic_generic_atomic_max:
4065 case ir_intrinsic_generic_atomic_exchange:
4066 case ir_intrinsic_generic_atomic_comp_swap:
4067 case ir_intrinsic_begin_invocation_interlock:
4068 case ir_intrinsic_end_invocation_interlock:
4069 unreachable("Invalid intrinsic");
4070 }
4071 }
4072
4073 void
4074 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4075 unsigned *array_elements,
4076 uint16_t *index,
4077 st_src_reg *indirect,
4078 unsigned *location)
4079 {
4080 switch (tail->ir_type) {
4081 case ir_type_dereference_record: {
4082 ir_dereference_record *deref_record = tail->as_dereference_record();
4083 const glsl_type *struct_type = deref_record->record->type;
4084 int field_index = deref_record->field_idx;
4085
4086 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4087
4088 assert(field_index >= 0);
4089 *location += struct_type->struct_location_offset(field_index);
4090 break;
4091 }
4092
4093 case ir_type_dereference_array: {
4094 ir_dereference_array *deref_arr = tail->as_dereference_array();
4095
4096 void *mem_ctx = ralloc_parent(deref_arr);
4097 ir_constant *array_index =
4098 deref_arr->array_index->constant_expression_value(mem_ctx);
4099
4100 if (!array_index) {
4101 st_src_reg temp_reg;
4102 st_dst_reg temp_dst;
4103
4104 temp_reg = get_temp(glsl_type::uint_type);
4105 temp_dst = st_dst_reg(temp_reg);
4106 temp_dst.writemask = 1;
4107
4108 deref_arr->array_index->accept(this);
4109 if (*array_elements != 1)
4110 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4111 else
4112 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4113
4114 if (indirect->file == PROGRAM_UNDEFINED)
4115 *indirect = temp_reg;
4116 else {
4117 temp_dst = st_dst_reg(*indirect);
4118 temp_dst.writemask = 1;
4119 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4120 }
4121 } else
4122 *index += array_index->value.u[0] * *array_elements;
4123
4124 *array_elements *= deref_arr->array->type->length;
4125
4126 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4127 break;
4128 }
4129 default:
4130 break;
4131 }
4132 }
4133
4134 void
4135 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4136 unsigned *array_size,
4137 unsigned *base,
4138 uint16_t *index,
4139 st_src_reg *reladdr,
4140 bool opaque)
4141 {
4142 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4143 unsigned location = 0;
4144 ir_variable *var = ir->variable_referenced();
4145
4146 reladdr->reset();
4147
4148 *base = 0;
4149 *array_size = 1;
4150
4151 assert(var);
4152 location = var->data.location;
4153 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4154
4155 /*
4156 * If we end up with no indirect then adjust the base to the index,
4157 * and set the array size to 1.
4158 */
4159 if (reladdr->file == PROGRAM_UNDEFINED) {
4160 *base = *index;
4161 *array_size = 1;
4162 }
4163
4164 if (opaque) {
4165 assert(location != 0xffffffff);
4166 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4167 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4168 }
4169 }
4170
4171 st_src_reg
4172 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4173 {
4174 if (offset.reladdr || offset.reladdr2 ||
4175 offset.has_index2 ||
4176 offset.file == PROGRAM_UNIFORM ||
4177 offset.file == PROGRAM_CONSTANT ||
4178 offset.file == PROGRAM_STATE_VAR) {
4179 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4180 st_dst_reg tmp_dst = st_dst_reg(tmp);
4181 tmp_dst.writemask = WRITEMASK_XY;
4182 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4183 return tmp;
4184 }
4185
4186 return offset;
4187 }
4188
4189 bool
4190 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4191 {
4192 ir_variable *var = ir->variable_referenced();
4193
4194 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4195 !(ir->type->is_image() || ir->type->is_sampler()))
4196 return false;
4197
4198 /* Convert from bound sampler/image to bindless handle. */
4199 bool is_image = ir->type->is_image();
4200 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4201 uint16_t index = 0;
4202 unsigned array_size = 1, base = 0;
4203 st_src_reg reladdr;
4204 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4205
4206 resource.index = index;
4207 if (reladdr.file != PROGRAM_UNDEFINED) {
4208 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4209 *resource.reladdr = reladdr;
4210 emit_arl(ir, sampler_reladdr, reladdr);
4211 }
4212
4213 this->result = get_temp(glsl_type::uvec2_type);
4214 st_dst_reg dst(this->result);
4215 dst.writemask = WRITEMASK_XY;
4216
4217 glsl_to_tgsi_instruction *inst = emit_asm(
4218 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4219
4220 inst->tex_target = ir->type->sampler_index();
4221 inst->resource = resource;
4222 inst->sampler_array_size = array_size;
4223 inst->sampler_base = base;
4224
4225 return true;
4226 }
4227
4228 void
4229 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4230 {
4231 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4232 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4233 st_src_reg levels_src, reladdr;
4234 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4235 glsl_to_tgsi_instruction *inst = NULL;
4236 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4237 const glsl_type *sampler_type = ir->sampler->type;
4238 unsigned sampler_array_size = 1, sampler_base = 0;
4239 bool is_cube_array = false, is_cube_shadow = false;
4240 ir_variable *var = ir->sampler->variable_referenced();
4241 unsigned i;
4242
4243 /* if we are a cube array sampler or a cube shadow */
4244 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4245 is_cube_array = sampler_type->sampler_array;
4246 is_cube_shadow = sampler_type->sampler_shadow;
4247 }
4248
4249 if (ir->coordinate) {
4250 ir->coordinate->accept(this);
4251
4252 /* Put our coords in a temp. We'll need to modify them for shadow,
4253 * projection, or LOD, so the only case we'd use it as-is is if
4254 * we're doing plain old texturing. The optimization passes on
4255 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4256 */
4257 coord = get_temp(glsl_type::vec4_type);
4258 coord_dst = st_dst_reg(coord);
4259 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4260 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4261 }
4262
4263 if (ir->projector) {
4264 ir->projector->accept(this);
4265 projector = this->result;
4266 }
4267
4268 /* Storage for our result. Ideally for an assignment we'd be using
4269 * the actual storage for the result here, instead.
4270 */
4271 result_src = get_temp(ir->type);
4272 result_dst = st_dst_reg(result_src);
4273 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4274
4275 switch (ir->op) {
4276 case ir_tex:
4277 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4278 if (ir->offset) {
4279 ir->offset->accept(this);
4280 offset[0] = this->result;
4281 }
4282 break;
4283 case ir_txb:
4284 if (is_cube_array || is_cube_shadow) {
4285 opcode = TGSI_OPCODE_TXB2;
4286 }
4287 else {
4288 opcode = TGSI_OPCODE_TXB;
4289 }
4290 ir->lod_info.bias->accept(this);
4291 lod_info = this->result;
4292 if (ir->offset) {
4293 ir->offset->accept(this);
4294 offset[0] = this->result;
4295 }
4296 break;
4297 case ir_txl:
4298 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4299 opcode = TGSI_OPCODE_TEX_LZ;
4300 } else {
4301 opcode = is_cube_array ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4302 ir->lod_info.lod->accept(this);
4303 lod_info = this->result;
4304 }
4305 if (ir->offset) {
4306 ir->offset->accept(this);
4307 offset[0] = this->result;
4308 }
4309 break;
4310 case ir_txd:
4311 opcode = TGSI_OPCODE_TXD;
4312 ir->lod_info.grad.dPdx->accept(this);
4313 dx = this->result;
4314 ir->lod_info.grad.dPdy->accept(this);
4315 dy = this->result;
4316 if (ir->offset) {
4317 ir->offset->accept(this);
4318 offset[0] = this->result;
4319 }
4320 break;
4321 case ir_txs:
4322 opcode = TGSI_OPCODE_TXQ;
4323 ir->lod_info.lod->accept(this);
4324 lod_info = this->result;
4325 break;
4326 case ir_query_levels:
4327 opcode = TGSI_OPCODE_TXQ;
4328 lod_info = undef_src;
4329 levels_src = get_temp(ir->type);
4330 break;
4331 case ir_txf:
4332 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4333 opcode = TGSI_OPCODE_TXF_LZ;
4334 } else {
4335 opcode = TGSI_OPCODE_TXF;
4336 ir->lod_info.lod->accept(this);
4337 lod_info = this->result;
4338 }
4339 if (ir->offset) {
4340 ir->offset->accept(this);
4341 offset[0] = this->result;
4342 }
4343 break;
4344 case ir_txf_ms:
4345 opcode = TGSI_OPCODE_TXF;
4346 ir->lod_info.sample_index->accept(this);
4347 sample_index = this->result;
4348 break;
4349 case ir_tg4:
4350 opcode = TGSI_OPCODE_TG4;
4351 ir->lod_info.component->accept(this);
4352 component = this->result;
4353 if (ir->offset) {
4354 ir->offset->accept(this);
4355 if (ir->offset->type->is_array()) {
4356 const glsl_type *elt_type = ir->offset->type->fields.array;
4357 for (i = 0; i < ir->offset->type->length; i++) {
4358 offset[i] = this->result;
4359 offset[i].index += i * type_size(elt_type);
4360 offset[i].type = elt_type->base_type;
4361 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4362 offset[i] = canonicalize_gather_offset(offset[i]);
4363 }
4364 } else {
4365 offset[0] = canonicalize_gather_offset(this->result);
4366 }
4367 }
4368 break;
4369 case ir_lod:
4370 opcode = TGSI_OPCODE_LODQ;
4371 break;
4372 case ir_texture_samples:
4373 opcode = TGSI_OPCODE_TXQS;
4374 break;
4375 case ir_samples_identical:
4376 unreachable("Unexpected ir_samples_identical opcode");
4377 }
4378
4379 if (ir->projector) {
4380 if (opcode == TGSI_OPCODE_TEX) {
4381 /* Slot the projector in as the last component of the coord. */
4382 coord_dst.writemask = WRITEMASK_W;
4383 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4384 coord_dst.writemask = WRITEMASK_XYZW;
4385 opcode = TGSI_OPCODE_TXP;
4386 } else {
4387 st_src_reg coord_w = coord;
4388 coord_w.swizzle = SWIZZLE_WWWW;
4389
4390 /* For the other TEX opcodes there's no projective version
4391 * since the last slot is taken up by LOD info. Do the
4392 * projective divide now.
4393 */
4394 coord_dst.writemask = WRITEMASK_W;
4395 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4396
4397 /* In the case where we have to project the coordinates "by hand,"
4398 * the shadow comparator value must also be projected.
4399 */
4400 st_src_reg tmp_src = coord;
4401 if (ir->shadow_comparator) {
4402 /* Slot the shadow value in as the second to last component of the
4403 * coord.
4404 */
4405 ir->shadow_comparator->accept(this);
4406
4407 tmp_src = get_temp(glsl_type::vec4_type);
4408 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4409
4410 /* Projective division not allowed for array samplers. */
4411 assert(!sampler_type->sampler_array);
4412
4413 tmp_dst.writemask = WRITEMASK_Z;
4414 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4415
4416 tmp_dst.writemask = WRITEMASK_XY;
4417 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4418 }
4419
4420 coord_dst.writemask = WRITEMASK_XYZ;
4421 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4422
4423 coord_dst.writemask = WRITEMASK_XYZW;
4424 coord.swizzle = SWIZZLE_XYZW;
4425 }
4426 }
4427
4428 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4429 * shadow comparator was put in the correct place (and projected) by the
4430 * code, above, that handles by-hand projection.
4431 */
4432 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4433 /* Slot the shadow value in as the second to last component of the
4434 * coord.
4435 */
4436 ir->shadow_comparator->accept(this);
4437
4438 if (is_cube_array) {
4439 cube_sc = get_temp(glsl_type::float_type);
4440 cube_sc_dst = st_dst_reg(cube_sc);
4441 cube_sc_dst.writemask = WRITEMASK_X;
4442 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4443 cube_sc_dst.writemask = WRITEMASK_X;
4444 }
4445 else {
4446 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4447 sampler_type->sampler_array) ||
4448 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4449 coord_dst.writemask = WRITEMASK_W;
4450 } else {
4451 coord_dst.writemask = WRITEMASK_Z;
4452 }
4453 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4454 coord_dst.writemask = WRITEMASK_XYZW;
4455 }
4456 }
4457
4458 if (ir->op == ir_txf_ms) {
4459 coord_dst.writemask = WRITEMASK_W;
4460 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4461 coord_dst.writemask = WRITEMASK_XYZW;
4462 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4463 opcode == TGSI_OPCODE_TXF) {
4464 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4465 coord_dst.writemask = WRITEMASK_W;
4466 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4467 coord_dst.writemask = WRITEMASK_XYZW;
4468 }
4469
4470 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4471
4472 uint16_t index = 0;
4473 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4474 &index, &reladdr, !var->contains_bindless());
4475
4476 sampler.index = index;
4477 if (reladdr.file != PROGRAM_UNDEFINED) {
4478 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4479 *sampler.reladdr = reladdr;
4480 emit_arl(ir, sampler_reladdr, reladdr);
4481 }
4482
4483 st_src_reg bindless;
4484 if (var->contains_bindless()) {
4485 ir->sampler->accept(this);
4486 bindless = this->result;
4487 }
4488
4489 if (opcode == TGSI_OPCODE_TXD)
4490 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4491 else if (opcode == TGSI_OPCODE_TXQ) {
4492 if (ir->op == ir_query_levels) {
4493 /* the level is stored in W */
4494 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4495 result_dst.writemask = WRITEMASK_X;
4496 levels_src.swizzle = SWIZZLE_WWWW;
4497 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4498 } else
4499 inst = emit_asm(ir, opcode, result_dst, lod_info);
4500 } else if (opcode == TGSI_OPCODE_TXQS) {
4501 inst = emit_asm(ir, opcode, result_dst);
4502 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4503 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4504 } else if (opcode == TGSI_OPCODE_TEX2) {
4505 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4506 } else if (opcode == TGSI_OPCODE_TG4) {
4507 if (is_cube_array && ir->shadow_comparator) {
4508 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4509 } else {
4510 inst = emit_asm(ir, opcode, result_dst, coord, component);
4511 }
4512 } else
4513 inst = emit_asm(ir, opcode, result_dst, coord);
4514
4515 if (ir->shadow_comparator)
4516 inst->tex_shadow = GL_TRUE;
4517
4518 if (var->contains_bindless()) {
4519 inst->resource = bindless;
4520 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4521 SWIZZLE_X, SWIZZLE_Y);
4522 } else {
4523 inst->resource = sampler;
4524 inst->sampler_array_size = sampler_array_size;
4525 inst->sampler_base = sampler_base;
4526 }
4527
4528 if (ir->offset) {
4529 if (!inst->tex_offsets)
4530 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4531 MAX_GLSL_TEXTURE_OFFSET);
4532
4533 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4534 offset[i].file != PROGRAM_UNDEFINED; i++)
4535 inst->tex_offsets[i] = offset[i];
4536 inst->tex_offset_num_offset = i;
4537 }
4538
4539 inst->tex_target = sampler_type->sampler_index();
4540 inst->tex_type = ir->type->base_type;
4541
4542 this->result = result_src;
4543 }
4544
4545 void
4546 glsl_to_tgsi_visitor::visit(ir_return *ir)
4547 {
4548 assert(!ir->get_value());
4549
4550 emit_asm(ir, TGSI_OPCODE_RET);
4551 }
4552
4553 void
4554 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4555 {
4556 if (ir->condition) {
4557 ir->condition->accept(this);
4558 st_src_reg condition = this->result;
4559
4560 /* Convert the bool condition to a float so we can negate. */
4561 if (native_integers) {
4562 st_src_reg temp = get_temp(ir->condition->type);
4563 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4564 condition, st_src_reg_for_float(1.0));
4565 condition = temp;
4566 }
4567
4568 condition.negate = ~condition.negate;
4569 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4570 } else {
4571 /* unconditional kil */
4572 emit_asm(ir, TGSI_OPCODE_KILL);
4573 }
4574 }
4575
4576 void
4577 glsl_to_tgsi_visitor::visit(ir_if *ir)
4578 {
4579 enum tgsi_opcode if_opcode;
4580 glsl_to_tgsi_instruction *if_inst;
4581
4582 ir->condition->accept(this);
4583 assert(this->result.file != PROGRAM_UNDEFINED);
4584
4585 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4586
4587 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4588
4589 this->instructions.push_tail(if_inst);
4590
4591 visit_exec_list(&ir->then_instructions, this);
4592
4593 if (!ir->else_instructions.is_empty()) {
4594 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4595 visit_exec_list(&ir->else_instructions, this);
4596 }
4597
4598 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4599 }
4600
4601
4602 void
4603 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4604 {
4605 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4606
4607 ir->stream->accept(this);
4608 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4609 }
4610
4611 void
4612 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4613 {
4614 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4615
4616 ir->stream->accept(this);
4617 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4618 }
4619
4620 void
4621 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4622 {
4623 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4624 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4625
4626 emit_asm(ir, TGSI_OPCODE_BARRIER);
4627 }
4628
4629 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4630 {
4631 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4632
4633 result.file = PROGRAM_UNDEFINED;
4634 next_temp = 1;
4635 array_sizes = NULL;
4636 max_num_arrays = 0;
4637 next_array = 0;
4638 num_inputs = 0;
4639 num_outputs = 0;
4640 num_input_arrays = 0;
4641 num_output_arrays = 0;
4642 num_atomics = 0;
4643 num_atomic_arrays = 0;
4644 num_immediates = 0;
4645 num_address_regs = 0;
4646 samplers_used = 0;
4647 images_used = 0;
4648 indirect_addr_consts = false;
4649 wpos_transform_const = -1;
4650 native_integers = false;
4651 mem_ctx = ralloc_context(NULL);
4652 ctx = NULL;
4653 prog = NULL;
4654 precise = 0;
4655 need_uarl = false;
4656 shader_program = NULL;
4657 shader = NULL;
4658 options = NULL;
4659 have_sqrt = false;
4660 have_fma = false;
4661 use_shared_memory = false;
4662 has_tex_txf_lz = false;
4663 variables = NULL;
4664 }
4665
4666 static void var_destroy(struct hash_entry *entry)
4667 {
4668 variable_storage *storage = (variable_storage *)entry->data;
4669
4670 delete storage;
4671 }
4672
4673 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4674 {
4675 _mesa_hash_table_destroy(variables, var_destroy);
4676 free(array_sizes);
4677 ralloc_free(mem_ctx);
4678 }
4679
4680 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4681 {
4682 delete v;
4683 }
4684
4685
4686 /**
4687 * Count resources used by the given gpu program (number of texture
4688 * samplers, etc).
4689 */
4690 static void
4691 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4692 {
4693 v->samplers_used = 0;
4694 v->images_used = 0;
4695 prog->info.textures_used_by_txf = 0;
4696
4697 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4698 if (inst->info->is_tex) {
4699 for (int i = 0; i < inst->sampler_array_size; i++) {
4700 unsigned idx = inst->sampler_base + i;
4701 v->samplers_used |= 1u << idx;
4702
4703 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4704 v->sampler_types[idx] = inst->tex_type;
4705 v->sampler_targets[idx] =
4706 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4707
4708 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4709 prog->info.textures_used_by_txf |= 1u << idx;
4710 }
4711 }
4712 }
4713
4714 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4715 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4716
4717 if (inst->resource.file != PROGRAM_UNDEFINED && (
4718 is_resource_instruction(inst->op) ||
4719 inst->op == TGSI_OPCODE_STORE)) {
4720 if (inst->resource.file == PROGRAM_MEMORY) {
4721 v->use_shared_memory = true;
4722 } else if (inst->resource.file == PROGRAM_IMAGE) {
4723 for (int i = 0; i < inst->sampler_array_size; i++) {
4724 unsigned idx = inst->sampler_base + i;
4725 v->images_used |= 1 << idx;
4726 v->image_targets[idx] =
4727 st_translate_texture_target(inst->tex_target, false);
4728 v->image_formats[idx] = inst->image_format;
4729 v->image_wr[idx] = !inst->read_only;
4730 }
4731 }
4732 }
4733 }
4734 prog->SamplersUsed = v->samplers_used;
4735
4736 if (v->shader_program != NULL)
4737 _mesa_update_shader_textures_used(v->shader_program, prog);
4738 }
4739
4740 /**
4741 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4742 * are read from the given src in this instruction
4743 */
4744 static int
4745 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4746 {
4747 int read_mask = 0, comp;
4748
4749 /* Now, given the src swizzle and the written channels, find which
4750 * components are actually read
4751 */
4752 for (comp = 0; comp < 4; ++comp) {
4753 const unsigned coord = GET_SWZ(src.swizzle, comp);
4754 assert(coord < 4);
4755 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4756 read_mask |= 1 << coord;
4757 }
4758
4759 return read_mask;
4760 }
4761
4762 /**
4763 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4764 * instruction is the first instruction to write to register T0. There are
4765 * several lowering passes done in GLSL IR (e.g. branches and
4766 * relative addressing) that create a large number of conditional assignments
4767 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4768 *
4769 * Here is why this conversion is safe:
4770 * CMP T0, T1 T2 T0 can be expanded to:
4771 * if (T1 < 0.0)
4772 * MOV T0, T2;
4773 * else
4774 * MOV T0, T0;
4775 *
4776 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4777 * as the original program. If (T1 < 0.0) evaluates to false, executing
4778 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4779 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4780 * because any instruction that was going to read from T0 after this was going
4781 * to read a garbage value anyway.
4782 */
4783 void
4784 glsl_to_tgsi_visitor::simplify_cmp(void)
4785 {
4786 int tempWritesSize = 0;
4787 unsigned *tempWrites = NULL;
4788 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4789
4790 memset(outputWrites, 0, sizeof(outputWrites));
4791
4792 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4793 unsigned prevWriteMask = 0;
4794
4795 /* Give up if we encounter relative addressing or flow control. */
4796 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4797 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4798 inst->info->is_branch ||
4799 inst->op == TGSI_OPCODE_CONT ||
4800 inst->op == TGSI_OPCODE_END ||
4801 inst->op == TGSI_OPCODE_RET) {
4802 break;
4803 }
4804
4805 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4806 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4807 prevWriteMask = outputWrites[inst->dst[0].index];
4808 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4809 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4810 if (inst->dst[0].index >= tempWritesSize) {
4811 const int inc = 4096;
4812
4813 tempWrites = (unsigned*)
4814 realloc(tempWrites,
4815 (tempWritesSize + inc) * sizeof(unsigned));
4816 if (!tempWrites)
4817 return;
4818
4819 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4820 tempWritesSize += inc;
4821 }
4822
4823 prevWriteMask = tempWrites[inst->dst[0].index];
4824 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4825 } else
4826 continue;
4827
4828 /* For a CMP to be considered a conditional write, the destination
4829 * register and source register two must be the same. */
4830 if (inst->op == TGSI_OPCODE_CMP
4831 && !(inst->dst[0].writemask & prevWriteMask)
4832 && inst->src[2].file == inst->dst[0].file
4833 && inst->src[2].index == inst->dst[0].index
4834 && inst->dst[0].writemask ==
4835 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4836
4837 inst->op = TGSI_OPCODE_MOV;
4838 inst->info = tgsi_get_opcode_info(inst->op);
4839 inst->src[0] = inst->src[1];
4840 }
4841 }
4842
4843 free(tempWrites);
4844 }
4845
4846 static void
4847 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4848 {
4849 if (src && src->file == PROGRAM_TEMPORARY) {
4850 int old_idx = src->index;
4851 if (renames[old_idx].valid)
4852 src->index = renames[old_idx].new_reg;
4853 }
4854 }
4855
4856 /* Replaces all references to a temporary register index with another index. */
4857 void
4858 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4859 {
4860 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4861 unsigned j;
4862 for (j = 0; j < num_inst_src_regs(inst); j++) {
4863 rename_temp_handle_src(renames, &inst->src[j]);
4864 rename_temp_handle_src(renames, inst->src[j].reladdr);
4865 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4866 }
4867
4868 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4869 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4870 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4871 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4872 }
4873
4874 rename_temp_handle_src(renames, &inst->resource);
4875 rename_temp_handle_src(renames, inst->resource.reladdr);
4876 rename_temp_handle_src(renames, inst->resource.reladdr2);
4877
4878 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4879 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4880 int old_idx = inst->dst[j].index;
4881 if (renames[old_idx].valid)
4882 inst->dst[j].index = renames[old_idx].new_reg;
4883 }
4884 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4885 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4886 }
4887 }
4888 }
4889
4890 void
4891 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4892 {
4893 int depth = 0; /* loop depth */
4894 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4895 unsigned i = 0, j;
4896
4897 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4898 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4899 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4900 if (first_writes[inst->dst[j].index] == -1)
4901 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4902 }
4903 }
4904
4905 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4906 if (depth++ == 0)
4907 loop_start = i;
4908 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4909 if (--depth == 0)
4910 loop_start = -1;
4911 }
4912 assert(depth >= 0);
4913 i++;
4914 }
4915 }
4916
4917 void
4918 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
4919 {
4920 int depth = 0; /* loop depth */
4921 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4922 unsigned i = 0, j;
4923
4924 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4925 for (j = 0; j < num_inst_src_regs(inst); j++) {
4926 if (inst->src[j].file == PROGRAM_TEMPORARY) {
4927 if (first_reads[inst->src[j].index] == -1)
4928 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
4929 }
4930 }
4931 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4932 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
4933 if (first_reads[inst->tex_offsets[j].index] == -1)
4934 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
4935 }
4936 }
4937 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4938 if (depth++ == 0)
4939 loop_start = i;
4940 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4941 if (--depth == 0)
4942 loop_start = -1;
4943 }
4944 assert(depth >= 0);
4945 i++;
4946 }
4947 }
4948
4949 void
4950 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
4951 {
4952 int depth = 0; /* loop depth */
4953 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4954 unsigned i = 0, j;
4955 int k;
4956 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4957 for (j = 0; j < num_inst_src_regs(inst); j++) {
4958 if (inst->src[j].file == PROGRAM_TEMPORARY)
4959 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
4960 }
4961 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4962 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4963 if (first_writes[inst->dst[j].index] == -1)
4964 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4965 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
4966 }
4967 }
4968 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4969 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
4970 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
4971 }
4972 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4973 if (depth++ == 0)
4974 loop_start = i;
4975 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4976 if (--depth == 0) {
4977 loop_start = -1;
4978 for (k = 0; k < this->next_temp; k++) {
4979 if (last_reads[k] == -2) {
4980 last_reads[k] = i;
4981 }
4982 }
4983 }
4984 }
4985 assert(depth >= 0);
4986 i++;
4987 }
4988 }
4989
4990 void
4991 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
4992 {
4993 int depth = 0; /* loop depth */
4994 int i = 0, k;
4995 unsigned j;
4996
4997 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4998 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4999 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5000 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5001 }
5002
5003 if (inst->op == TGSI_OPCODE_BGNLOOP)
5004 depth++;
5005 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5006 if (--depth == 0) {
5007 for (k = 0; k < this->next_temp; k++) {
5008 if (last_writes[k] == -2) {
5009 last_writes[k] = i;
5010 }
5011 }
5012 }
5013 assert(depth >= 0);
5014 i++;
5015 }
5016 }
5017
5018 /*
5019 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5020 * channels for copy propagation and updates following instructions to
5021 * use the original versions.
5022 *
5023 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5024 * will occur. As an example, a TXP production before this pass:
5025 *
5026 * 0: MOV TEMP[1], INPUT[4].xyyy;
5027 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5028 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5029 *
5030 * and after:
5031 *
5032 * 0: MOV TEMP[1], INPUT[4].xyyy;
5033 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5034 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5035 *
5036 * which allows for dead code elimination on TEMP[1]'s writes.
5037 */
5038 void
5039 glsl_to_tgsi_visitor::copy_propagate(void)
5040 {
5041 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5042 glsl_to_tgsi_instruction *,
5043 this->next_temp * 4);
5044 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5045 int level = 0;
5046
5047 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5048 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5049 || inst->dst[0].index < this->next_temp);
5050
5051 /* First, do any copy propagation possible into the src regs. */
5052 for (int r = 0; r < 3; r++) {
5053 glsl_to_tgsi_instruction *first = NULL;
5054 bool good = true;
5055 int acp_base = inst->src[r].index * 4;
5056
5057 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5058 inst->src[r].reladdr ||
5059 inst->src[r].reladdr2)
5060 continue;
5061
5062 /* See if we can find entries in the ACP consisting of MOVs
5063 * from the same src register for all the swizzled channels
5064 * of this src register reference.
5065 */
5066 for (int i = 0; i < 4; i++) {
5067 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5068 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5069
5070 if (!copy_chan) {
5071 good = false;
5072 break;
5073 }
5074
5075 assert(acp_level[acp_base + src_chan] <= level);
5076
5077 if (!first) {
5078 first = copy_chan;
5079 } else {
5080 if (first->src[0].file != copy_chan->src[0].file ||
5081 first->src[0].index != copy_chan->src[0].index ||
5082 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5083 first->src[0].index2D != copy_chan->src[0].index2D) {
5084 good = false;
5085 break;
5086 }
5087 }
5088 }
5089
5090 if (good) {
5091 /* We've now validated that we can copy-propagate to
5092 * replace this src register reference. Do it.
5093 */
5094 inst->src[r].file = first->src[0].file;
5095 inst->src[r].index = first->src[0].index;
5096 inst->src[r].index2D = first->src[0].index2D;
5097 inst->src[r].has_index2 = first->src[0].has_index2;
5098 inst->src[r].double_reg2 = first->src[0].double_reg2;
5099 inst->src[r].array_id = first->src[0].array_id;
5100
5101 int swizzle = 0;
5102 for (int i = 0; i < 4; i++) {
5103 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5104 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5105 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5106 }
5107 inst->src[r].swizzle = swizzle;
5108 }
5109 }
5110
5111 switch (inst->op) {
5112 case TGSI_OPCODE_BGNLOOP:
5113 case TGSI_OPCODE_ENDLOOP:
5114 /* End of a basic block, clear the ACP entirely. */
5115 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5116 break;
5117
5118 case TGSI_OPCODE_IF:
5119 case TGSI_OPCODE_UIF:
5120 ++level;
5121 break;
5122
5123 case TGSI_OPCODE_ENDIF:
5124 case TGSI_OPCODE_ELSE:
5125 /* Clear all channels written inside the block from the ACP, but
5126 * leaving those that were not touched.
5127 */
5128 for (int r = 0; r < this->next_temp; r++) {
5129 for (int c = 0; c < 4; c++) {
5130 if (!acp[4 * r + c])
5131 continue;
5132
5133 if (acp_level[4 * r + c] >= level)
5134 acp[4 * r + c] = NULL;
5135 }
5136 }
5137 if (inst->op == TGSI_OPCODE_ENDIF)
5138 --level;
5139 break;
5140
5141 default:
5142 /* Continuing the block, clear any written channels from
5143 * the ACP.
5144 */
5145 for (int d = 0; d < 2; d++) {
5146 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5147 /* Any temporary might be written, so no copy propagation
5148 * across this instruction.
5149 */
5150 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5151 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5152 inst->dst[d].reladdr) {
5153 /* Any output might be written, so no copy propagation
5154 * from outputs across this instruction.
5155 */
5156 for (int r = 0; r < this->next_temp; r++) {
5157 for (int c = 0; c < 4; c++) {
5158 if (!acp[4 * r + c])
5159 continue;
5160
5161 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5162 acp[4 * r + c] = NULL;
5163 }
5164 }
5165 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5166 inst->dst[d].file == PROGRAM_OUTPUT) {
5167 /* Clear where it's used as dst. */
5168 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5169 for (int c = 0; c < 4; c++) {
5170 if (inst->dst[d].writemask & (1 << c))
5171 acp[4 * inst->dst[d].index + c] = NULL;
5172 }
5173 }
5174
5175 /* Clear where it's used as src. */
5176 for (int r = 0; r < this->next_temp; r++) {
5177 for (int c = 0; c < 4; c++) {
5178 if (!acp[4 * r + c])
5179 continue;
5180
5181 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5182
5183 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5184 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5185 inst->dst[d].writemask & (1 << src_chan)) {
5186 acp[4 * r + c] = NULL;
5187 }
5188 }
5189 }
5190 }
5191 }
5192 break;
5193 }
5194
5195 /* If this is a copy, add it to the ACP. */
5196 if (inst->op == TGSI_OPCODE_MOV &&
5197 inst->dst[0].file == PROGRAM_TEMPORARY &&
5198 !(inst->dst[0].file == inst->src[0].file &&
5199 inst->dst[0].index == inst->src[0].index) &&
5200 !inst->dst[0].reladdr &&
5201 !inst->dst[0].reladdr2 &&
5202 !inst->saturate &&
5203 inst->src[0].file != PROGRAM_ARRAY &&
5204 (inst->src[0].file != PROGRAM_OUTPUT ||
5205 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5206 !inst->src[0].reladdr &&
5207 !inst->src[0].reladdr2 &&
5208 !inst->src[0].negate &&
5209 !inst->src[0].abs) {
5210 for (int i = 0; i < 4; i++) {
5211 if (inst->dst[0].writemask & (1 << i)) {
5212 acp[4 * inst->dst[0].index + i] = inst;
5213 acp_level[4 * inst->dst[0].index + i] = level;
5214 }
5215 }
5216 }
5217 }
5218
5219 ralloc_free(acp_level);
5220 ralloc_free(acp);
5221 }
5222
5223 static void
5224 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5225 {
5226 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5227 /* Clear where it's used as src. */
5228 int swz = GET_SWZ(reladdr->swizzle, 0);
5229 writes[4 * reladdr->index + swz] = NULL;
5230 }
5231 }
5232
5233 /*
5234 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5235 * code elimination.
5236 *
5237 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5238 * will occur. As an example, a TXP production after copy propagation but
5239 * before this pass:
5240 *
5241 * 0: MOV TEMP[1], INPUT[4].xyyy;
5242 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5243 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5244 *
5245 * and after this pass:
5246 *
5247 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5248 */
5249 int
5250 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5251 {
5252 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5253 glsl_to_tgsi_instruction *,
5254 this->next_temp * 4);
5255 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5256 int level = 0;
5257 int removed = 0;
5258
5259 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5260 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5261 || inst->dst[0].index < this->next_temp);
5262
5263 switch (inst->op) {
5264 case TGSI_OPCODE_BGNLOOP:
5265 case TGSI_OPCODE_ENDLOOP:
5266 case TGSI_OPCODE_CONT:
5267 case TGSI_OPCODE_BRK:
5268 /* End of a basic block, clear the write array entirely.
5269 *
5270 * This keeps us from killing dead code when the writes are
5271 * on either side of a loop, even when the register isn't touched
5272 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5273 * dead code of this type, so it shouldn't make a difference as long as
5274 * the dead code elimination pass in the GLSL compiler does its job.
5275 */
5276 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5277 break;
5278
5279 case TGSI_OPCODE_ENDIF:
5280 case TGSI_OPCODE_ELSE:
5281 /* Promote the recorded level of all channels written inside the
5282 * preceding if or else block to the level above the if/else block.
5283 */
5284 for (int r = 0; r < this->next_temp; r++) {
5285 for (int c = 0; c < 4; c++) {
5286 if (!writes[4 * r + c])
5287 continue;
5288
5289 if (write_level[4 * r + c] == level)
5290 write_level[4 * r + c] = level-1;
5291 }
5292 }
5293 if (inst->op == TGSI_OPCODE_ENDIF)
5294 --level;
5295 break;
5296
5297 case TGSI_OPCODE_IF:
5298 case TGSI_OPCODE_UIF:
5299 ++level;
5300 /* fallthrough to default case to mark the condition as read */
5301 default:
5302 /* Continuing the block, clear any channels from the write array that
5303 * are read by this instruction.
5304 */
5305 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5306 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5307 /* Any temporary might be read, so no dead code elimination
5308 * across this instruction.
5309 */
5310 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5311 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5312 /* Clear where it's used as src. */
5313 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5314 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5315 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5316 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5317
5318 for (int c = 0; c < 4; c++) {
5319 if (src_chans & (1 << c))
5320 writes[4 * inst->src[i].index + c] = NULL;
5321 }
5322 }
5323 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5324 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5325 }
5326 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5327 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5328 /* Any temporary might be read, so no dead code elimination
5329 * across this instruction.
5330 */
5331 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5332 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5333 /* Clear where it's used as src. */
5334 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5335 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5336 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5337 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5338
5339 for (int c = 0; c < 4; c++) {
5340 if (src_chans & (1 << c))
5341 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5342 }
5343 }
5344 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5345 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5346 }
5347
5348 if (inst->resource.file == PROGRAM_TEMPORARY) {
5349 int src_chans;
5350
5351 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5352 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5353 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5354 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5355
5356 for (int c = 0; c < 4; c++) {
5357 if (src_chans & (1 << c))
5358 writes[4 * inst->resource.index + c] = NULL;
5359 }
5360 }
5361 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5362 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5363
5364 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5365 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5366 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5367 }
5368 break;
5369 }
5370
5371 /* If this instruction writes to a temporary, add it to the write array.
5372 * If there is already an instruction in the write array for one or more
5373 * of the channels, flag that channel write as dead.
5374 */
5375 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5376 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5377 !inst->dst[i].reladdr) {
5378 for (int c = 0; c < 4; c++) {
5379 if (inst->dst[i].writemask & (1 << c)) {
5380 if (writes[4 * inst->dst[i].index + c]) {
5381 if (write_level[4 * inst->dst[i].index + c] < level)
5382 continue;
5383 else
5384 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5385 }
5386 writes[4 * inst->dst[i].index + c] = inst;
5387 write_level[4 * inst->dst[i].index + c] = level;
5388 }
5389 }
5390 }
5391 }
5392 }
5393
5394 /* Anything still in the write array at this point is dead code. */
5395 for (int r = 0; r < this->next_temp; r++) {
5396 for (int c = 0; c < 4; c++) {
5397 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5398 if (inst)
5399 inst->dead_mask |= (1 << c);
5400 }
5401 }
5402
5403 /* Now actually remove the instructions that are completely dead and update
5404 * the writemask of other instructions with dead channels.
5405 */
5406 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5407 if (!inst->dead_mask || !inst->dst[0].writemask)
5408 continue;
5409 /* No amount of dead masks should remove memory stores */
5410 if (inst->info->is_store)
5411 continue;
5412
5413 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5414 inst->remove();
5415 delete inst;
5416 removed++;
5417 } else {
5418 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5419 if (inst->dead_mask == WRITEMASK_XY ||
5420 inst->dead_mask == WRITEMASK_ZW)
5421 inst->dst[0].writemask &= ~(inst->dead_mask);
5422 } else
5423 inst->dst[0].writemask &= ~(inst->dead_mask);
5424 }
5425 }
5426
5427 ralloc_free(write_level);
5428 ralloc_free(writes);
5429
5430 return removed;
5431 }
5432
5433 /* merge DFRACEXP instructions into one. */
5434 void
5435 glsl_to_tgsi_visitor::merge_two_dsts(void)
5436 {
5437 /* We never delete inst, but we may delete its successor. */
5438 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5439 glsl_to_tgsi_instruction *inst2;
5440 unsigned defined;
5441
5442 if (num_inst_dst_regs(inst) != 2)
5443 continue;
5444
5445 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5446 inst->dst[1].file != PROGRAM_UNDEFINED)
5447 continue;
5448
5449 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5450 inst->dst[1].file != PROGRAM_UNDEFINED);
5451
5452 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5453 defined = 1;
5454 else
5455 defined = 0;
5456
5457 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5458 while (!inst2->is_tail_sentinel()) {
5459 if (inst->op == inst2->op &&
5460 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5461 inst->src[0].file == inst2->src[0].file &&
5462 inst->src[0].index == inst2->src[0].index &&
5463 inst->src[0].type == inst2->src[0].type &&
5464 inst->src[0].swizzle == inst2->src[0].swizzle)
5465 break;
5466 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5467 }
5468
5469 if (inst2->is_tail_sentinel()) {
5470 /* Undefined destinations are not allowed, substitute with an unused
5471 * temporary register.
5472 */
5473 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5474 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5475 inst->dst[defined ^ 1].writemask = 0;
5476 continue;
5477 }
5478
5479 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5480 inst2->remove();
5481 delete inst2;
5482 }
5483 }
5484
5485 template <typename st_reg>
5486 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5487 {
5488 if (reg.file == PROGRAM_ARRAY) {
5489 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5490 has_indirect_access[reg.array_id] = true;
5491 if (reg.reladdr)
5492 test_indirect_access(*reg.reladdr, has_indirect_access);
5493 if (reg.reladdr2)
5494 test_indirect_access(*reg.reladdr2, has_indirect_access);
5495 }
5496 }
5497 }
5498
5499 template <typename st_reg>
5500 void remap_array(st_reg& reg, const int *array_remap_info,
5501 const bool *has_indirect_access)
5502 {
5503 if (reg.file == PROGRAM_ARRAY) {
5504 if (!has_indirect_access[reg.array_id]) {
5505 reg.file = PROGRAM_TEMPORARY;
5506 reg.index = reg.index + array_remap_info[reg.array_id];
5507 reg.array_id = 0;
5508 } else {
5509 reg.array_id = array_remap_info[reg.array_id];
5510 }
5511
5512 if (reg.reladdr)
5513 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5514
5515 if (reg.reladdr2)
5516 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5517 }
5518 }
5519
5520 /* One-dimensional arrays whose elements are only accessed directly are
5521 * replaced by an according set of temporary registers that then can become
5522 * subject to further optimization steps like copy propagation and
5523 * register merging.
5524 */
5525 void
5526 glsl_to_tgsi_visitor::split_arrays(void)
5527 {
5528 if (!next_array)
5529 return;
5530
5531 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5532
5533 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5534 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5535 test_indirect_access(inst->src[j], has_indirect_access);
5536
5537 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5538 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5539
5540 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5541 test_indirect_access(inst->dst[j], has_indirect_access);
5542
5543 test_indirect_access(inst->resource, has_indirect_access);
5544 }
5545
5546 unsigned array_offset = 0;
5547 unsigned n_remaining_arrays = 0;
5548
5549 /* Double use: For arrays that get split this value will contain
5550 * the base index of the temporary registers this array is replaced
5551 * with. For arrays that remain it contains the new array ID.
5552 */
5553 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5554 next_array + 1);
5555
5556 for (unsigned i = 1; i <= next_array; ++i) {
5557 if (!has_indirect_access[i]) {
5558 array_remap_info[i] = this->next_temp + array_offset;
5559 array_offset += array_sizes[i - 1];
5560 } else {
5561 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5562 array_remap_info[i] = ++n_remaining_arrays;
5563 }
5564 }
5565
5566 if (next_array != n_remaining_arrays) {
5567 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5568 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5569 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5570
5571 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5572 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5573
5574 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5575 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5576 }
5577 remap_array(inst->resource, array_remap_info, has_indirect_access);
5578 }
5579 }
5580
5581 ralloc_free(has_indirect_access);
5582 this->next_temp += array_offset;
5583 next_array = n_remaining_arrays;
5584 }
5585
5586 /* Merges temporary registers together where possible to reduce the number of
5587 * registers needed to run a program.
5588 *
5589 * Produces optimal code only after copy propagation and dead code elimination
5590 * have been run. */
5591 void
5592 glsl_to_tgsi_visitor::merge_registers(void)
5593 {
5594 class array_live_range *arr_live_ranges = NULL;
5595
5596 struct register_live_range *reg_live_ranges =
5597 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5598
5599 if (this->next_array > 0) {
5600 arr_live_ranges = new array_live_range[this->next_array];
5601 for (unsigned i = 0; i < this->next_array; ++i)
5602 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5603 }
5604
5605
5606 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5607 this->next_temp, reg_live_ranges,
5608 this->next_array, arr_live_ranges)) {
5609 struct rename_reg_pair *renames =
5610 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5611 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5612 reg_live_ranges, renames);
5613 rename_temp_registers(renames);
5614
5615 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5616 &this->instructions, arr_live_ranges);
5617 }
5618
5619 if (arr_live_ranges)
5620 delete[] arr_live_ranges;
5621
5622 ralloc_free(reg_live_ranges);
5623 }
5624
5625 /* Reassign indices to temporary registers by reusing unused indices created
5626 * by optimization passes. */
5627 void
5628 glsl_to_tgsi_visitor::renumber_registers(void)
5629 {
5630 int i = 0;
5631 int new_index = 0;
5632 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5633 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5634
5635 for (i = 0; i < this->next_temp; i++) {
5636 first_writes[i] = -1;
5637 }
5638 get_first_temp_write(first_writes);
5639
5640 for (i = 0; i < this->next_temp; i++) {
5641 if (first_writes[i] < 0) continue;
5642 if (i != new_index) {
5643 renames[i].new_reg = new_index;
5644 renames[i].valid = true;
5645 }
5646 new_index++;
5647 }
5648
5649 rename_temp_registers(renames);
5650 this->next_temp = new_index;
5651 ralloc_free(renames);
5652 ralloc_free(first_writes);
5653 }
5654
5655 #ifndef NDEBUG
5656 void glsl_to_tgsi_visitor::print_stats()
5657 {
5658 int narray_registers = 0;
5659 for (unsigned i = 0; i < this->next_array; ++i)
5660 narray_registers += this->array_sizes[i];
5661
5662 int ninstructions = 0;
5663 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5664 ++ninstructions;
5665 }
5666
5667 simple_mtx_lock(&print_stats_mutex);
5668 stats_log << next_array << ", "
5669 << next_temp << ", "
5670 << narray_registers << ", "
5671 << next_temp + narray_registers << ", "
5672 << ninstructions << "\n";
5673 simple_mtx_unlock(&print_stats_mutex);
5674 }
5675 #endif
5676 /* ------------------------- TGSI conversion stuff -------------------------- */
5677
5678 /**
5679 * Intermediate state used during shader translation.
5680 */
5681 struct st_translate {
5682 struct ureg_program *ureg;
5683
5684 unsigned temps_size;
5685 struct ureg_dst *temps;
5686
5687 struct ureg_dst *arrays;
5688 unsigned num_temp_arrays;
5689 struct ureg_src *constants;
5690 int num_constants;
5691 struct ureg_src *immediates;
5692 int num_immediates;
5693 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5694 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5695 struct ureg_dst address[3];
5696 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5697 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5698 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5699 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5700 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5701 struct ureg_src shared_memory;
5702 unsigned *array_sizes;
5703 struct inout_decl *input_decls;
5704 unsigned num_input_decls;
5705 struct inout_decl *output_decls;
5706 unsigned num_output_decls;
5707
5708 const ubyte *inputMapping;
5709 const ubyte *outputMapping;
5710
5711 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5712 bool need_uarl;
5713 };
5714
5715 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5716 enum tgsi_semantic
5717 _mesa_sysval_to_semantic(unsigned sysval)
5718 {
5719 switch (sysval) {
5720 /* Vertex shader */
5721 case SYSTEM_VALUE_VERTEX_ID:
5722 return TGSI_SEMANTIC_VERTEXID;
5723 case SYSTEM_VALUE_INSTANCE_ID:
5724 return TGSI_SEMANTIC_INSTANCEID;
5725 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
5726 return TGSI_SEMANTIC_VERTEXID_NOBASE;
5727 case SYSTEM_VALUE_BASE_VERTEX:
5728 return TGSI_SEMANTIC_BASEVERTEX;
5729 case SYSTEM_VALUE_BASE_INSTANCE:
5730 return TGSI_SEMANTIC_BASEINSTANCE;
5731 case SYSTEM_VALUE_DRAW_ID:
5732 return TGSI_SEMANTIC_DRAWID;
5733
5734 /* Geometry shader */
5735 case SYSTEM_VALUE_INVOCATION_ID:
5736 return TGSI_SEMANTIC_INVOCATIONID;
5737
5738 /* Fragment shader */
5739 case SYSTEM_VALUE_FRAG_COORD:
5740 return TGSI_SEMANTIC_POSITION;
5741 case SYSTEM_VALUE_FRONT_FACE:
5742 return TGSI_SEMANTIC_FACE;
5743 case SYSTEM_VALUE_SAMPLE_ID:
5744 return TGSI_SEMANTIC_SAMPLEID;
5745 case SYSTEM_VALUE_SAMPLE_POS:
5746 return TGSI_SEMANTIC_SAMPLEPOS;
5747 case SYSTEM_VALUE_SAMPLE_MASK_IN:
5748 return TGSI_SEMANTIC_SAMPLEMASK;
5749 case SYSTEM_VALUE_HELPER_INVOCATION:
5750 return TGSI_SEMANTIC_HELPER_INVOCATION;
5751
5752 /* Tessellation shader */
5753 case SYSTEM_VALUE_TESS_COORD:
5754 return TGSI_SEMANTIC_TESSCOORD;
5755 case SYSTEM_VALUE_VERTICES_IN:
5756 return TGSI_SEMANTIC_VERTICESIN;
5757 case SYSTEM_VALUE_PRIMITIVE_ID:
5758 return TGSI_SEMANTIC_PRIMID;
5759 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
5760 return TGSI_SEMANTIC_TESSOUTER;
5761 case SYSTEM_VALUE_TESS_LEVEL_INNER:
5762 return TGSI_SEMANTIC_TESSINNER;
5763
5764 /* Compute shader */
5765 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
5766 return TGSI_SEMANTIC_THREAD_ID;
5767 case SYSTEM_VALUE_WORK_GROUP_ID:
5768 return TGSI_SEMANTIC_BLOCK_ID;
5769 case SYSTEM_VALUE_NUM_WORK_GROUPS:
5770 return TGSI_SEMANTIC_GRID_SIZE;
5771 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
5772 return TGSI_SEMANTIC_BLOCK_SIZE;
5773
5774 /* ARB_shader_ballot */
5775 case SYSTEM_VALUE_SUBGROUP_SIZE:
5776 return TGSI_SEMANTIC_SUBGROUP_SIZE;
5777 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
5778 return TGSI_SEMANTIC_SUBGROUP_INVOCATION;
5779 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
5780 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
5781 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
5782 return TGSI_SEMANTIC_SUBGROUP_GE_MASK;
5783 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
5784 return TGSI_SEMANTIC_SUBGROUP_GT_MASK;
5785 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
5786 return TGSI_SEMANTIC_SUBGROUP_LE_MASK;
5787 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
5788 return TGSI_SEMANTIC_SUBGROUP_LT_MASK;
5789
5790 /* Unhandled */
5791 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
5792 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
5793 case SYSTEM_VALUE_VERTEX_CNT:
5794 case SYSTEM_VALUE_VARYING_COORD:
5795 default:
5796 assert(!"Unexpected SYSTEM_VALUE_ enum");
5797 return TGSI_SEMANTIC_COUNT;
5798 }
5799 }
5800
5801 /**
5802 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5803 */
5804 static struct ureg_src
5805 emit_immediate(struct st_translate *t,
5806 gl_constant_value values[4],
5807 GLenum type, int size)
5808 {
5809 struct ureg_program *ureg = t->ureg;
5810
5811 switch (type) {
5812 case GL_FLOAT:
5813 return ureg_DECL_immediate(ureg, &values[0].f, size);
5814 case GL_DOUBLE:
5815 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5816 case GL_INT64_ARB:
5817 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5818 case GL_UNSIGNED_INT64_ARB:
5819 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5820 case GL_INT:
5821 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5822 case GL_UNSIGNED_INT:
5823 case GL_BOOL:
5824 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5825 default:
5826 assert(!"should not get here - type must be float, int, uint, or bool");
5827 return ureg_src_undef();
5828 }
5829 }
5830
5831 /**
5832 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5833 */
5834 static struct ureg_dst
5835 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5836 unsigned array_id)
5837 {
5838 unsigned array;
5839
5840 switch (file) {
5841 case PROGRAM_UNDEFINED:
5842 return ureg_dst_undef();
5843
5844 case PROGRAM_TEMPORARY:
5845 /* Allocate space for temporaries on demand. */
5846 if (index >= t->temps_size) {
5847 const int inc = align(index - t->temps_size + 1, 4096);
5848
5849 t->temps = (struct ureg_dst*)
5850 realloc(t->temps,
5851 (t->temps_size + inc) * sizeof(struct ureg_dst));
5852 if (!t->temps)
5853 return ureg_dst_undef();
5854
5855 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5856 t->temps_size += inc;
5857 }
5858
5859 if (ureg_dst_is_undef(t->temps[index]))
5860 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5861
5862 return t->temps[index];
5863
5864 case PROGRAM_ARRAY:
5865 assert(array_id && array_id <= t->num_temp_arrays);
5866 array = array_id - 1;
5867
5868 if (ureg_dst_is_undef(t->arrays[array]))
5869 t->arrays[array] = ureg_DECL_array_temporary(
5870 t->ureg, t->array_sizes[array], TRUE);
5871
5872 return ureg_dst_array_offset(t->arrays[array], index);
5873
5874 case PROGRAM_OUTPUT:
5875 if (!array_id) {
5876 if (t->procType == PIPE_SHADER_FRAGMENT)
5877 assert(index < 2 * FRAG_RESULT_MAX);
5878 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5879 t->procType == PIPE_SHADER_TESS_EVAL)
5880 assert(index < VARYING_SLOT_TESS_MAX);
5881 else
5882 assert(index < VARYING_SLOT_MAX);
5883
5884 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5885 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5886 return t->outputs[t->outputMapping[index]];
5887 }
5888 else {
5889 struct inout_decl *decl =
5890 find_inout_array(t->output_decls,
5891 t->num_output_decls, array_id);
5892 unsigned mesa_index = decl->mesa_index;
5893 int slot = t->outputMapping[mesa_index];
5894
5895 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5896
5897 struct ureg_dst dst = t->outputs[slot];
5898 dst.ArrayID = array_id;
5899 return ureg_dst_array_offset(dst, index - mesa_index);
5900 }
5901
5902 case PROGRAM_ADDRESS:
5903 return t->address[index];
5904
5905 default:
5906 assert(!"unknown dst register file");
5907 return ureg_dst_undef();
5908 }
5909 }
5910
5911 static struct ureg_src
5912 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5913
5914 static struct ureg_src
5915 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5916 unsigned addr_index)
5917 {
5918 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5919 return ureg_src(t->address[addr_index]);
5920
5921 return translate_src(t, reladdr);
5922 }
5923
5924 /**
5925 * Create a TGSI ureg_dst register from an st_dst_reg.
5926 */
5927 static struct ureg_dst
5928 translate_dst(struct st_translate *t,
5929 const st_dst_reg *dst_reg,
5930 bool saturate)
5931 {
5932 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5933 dst_reg->array_id);
5934
5935 if (dst.File == TGSI_FILE_NULL)
5936 return dst;
5937
5938 dst = ureg_writemask(dst, dst_reg->writemask);
5939
5940 if (saturate)
5941 dst = ureg_saturate(dst);
5942
5943 if (dst_reg->reladdr != NULL) {
5944 assert(dst_reg->file != PROGRAM_TEMPORARY);
5945 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5946 }
5947
5948 if (dst_reg->has_index2) {
5949 if (dst_reg->reladdr2)
5950 dst = ureg_dst_dimension_indirect(dst,
5951 translate_addr(t, dst_reg->reladdr2, 1),
5952 dst_reg->index2D);
5953 else
5954 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5955 }
5956
5957 return dst;
5958 }
5959
5960 /**
5961 * Create a TGSI ureg_src register from an st_src_reg.
5962 */
5963 static struct ureg_src
5964 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5965 {
5966 struct ureg_src src;
5967 int index = src_reg->index;
5968 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5969
5970 switch (src_reg->file) {
5971 case PROGRAM_UNDEFINED:
5972 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5973 break;
5974
5975 case PROGRAM_TEMPORARY:
5976 case PROGRAM_ARRAY:
5977 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5978 src_reg->array_id));
5979 break;
5980
5981 case PROGRAM_OUTPUT: {
5982 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5983 src_reg->array_id);
5984 assert(dst.WriteMask != 0);
5985 unsigned shift = ffs(dst.WriteMask) - 1;
5986 src = ureg_swizzle(ureg_src(dst),
5987 shift,
5988 MIN2(shift + 1, 3),
5989 MIN2(shift + 2, 3),
5990 MIN2(shift + 3, 3));
5991 break;
5992 }
5993
5994 case PROGRAM_UNIFORM:
5995 assert(src_reg->index >= 0);
5996 src = src_reg->index < t->num_constants ?
5997 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
5998 break;
5999 case PROGRAM_STATE_VAR:
6000 case PROGRAM_CONSTANT: /* ie, immediate */
6001 if (src_reg->has_index2)
6002 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6003 else
6004 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6005 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6006 break;
6007
6008 case PROGRAM_IMMEDIATE:
6009 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6010 src = t->immediates[src_reg->index];
6011 break;
6012
6013 case PROGRAM_INPUT:
6014 /* GLSL inputs are 64-bit containers, so we have to
6015 * map back to the original index and add the offset after
6016 * mapping. */
6017 index -= double_reg2;
6018 if (!src_reg->array_id) {
6019 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6020 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6021 src = t->inputs[t->inputMapping[index] + double_reg2];
6022 }
6023 else {
6024 struct inout_decl *decl = find_inout_array(t->input_decls,
6025 t->num_input_decls,
6026 src_reg->array_id);
6027 unsigned mesa_index = decl->mesa_index;
6028 int slot = t->inputMapping[mesa_index];
6029
6030 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6031
6032 src = t->inputs[slot];
6033 src.ArrayID = src_reg->array_id;
6034 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6035 }
6036 break;
6037
6038 case PROGRAM_ADDRESS:
6039 src = ureg_src(t->address[src_reg->index]);
6040 break;
6041
6042 case PROGRAM_SYSTEM_VALUE:
6043 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6044 src = t->systemValues[src_reg->index];
6045 break;
6046
6047 case PROGRAM_HW_ATOMIC:
6048 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6049 src_reg->array_id);
6050 break;
6051
6052 default:
6053 assert(!"unknown src register file");
6054 return ureg_src_undef();
6055 }
6056
6057 if (src_reg->has_index2) {
6058 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6059 * and UBO constant buffers (buffer, position).
6060 */
6061 if (src_reg->reladdr2)
6062 src = ureg_src_dimension_indirect(src,
6063 translate_addr(t, src_reg->reladdr2, 1),
6064 src_reg->index2D);
6065 else
6066 src = ureg_src_dimension(src, src_reg->index2D);
6067 }
6068
6069 src = ureg_swizzle(src,
6070 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6071 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6072 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6073 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6074
6075 if (src_reg->abs)
6076 src = ureg_abs(src);
6077
6078 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6079 src = ureg_negate(src);
6080
6081 if (src_reg->reladdr != NULL) {
6082 assert(src_reg->file != PROGRAM_TEMPORARY);
6083 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6084 }
6085
6086 return src;
6087 }
6088
6089 static struct tgsi_texture_offset
6090 translate_tex_offset(struct st_translate *t,
6091 const st_src_reg *in_offset)
6092 {
6093 struct tgsi_texture_offset offset;
6094 struct ureg_src src = translate_src(t, in_offset);
6095
6096 offset.File = src.File;
6097 offset.Index = src.Index;
6098 offset.SwizzleX = src.SwizzleX;
6099 offset.SwizzleY = src.SwizzleY;
6100 offset.SwizzleZ = src.SwizzleZ;
6101 offset.Padding = 0;
6102
6103 assert(!src.Indirect);
6104 assert(!src.DimIndirect);
6105 assert(!src.Dimension);
6106 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6107 assert(!src.Negate);
6108
6109 return offset;
6110 }
6111
6112 static void
6113 compile_tgsi_instruction(struct st_translate *t,
6114 const glsl_to_tgsi_instruction *inst)
6115 {
6116 struct ureg_program *ureg = t->ureg;
6117 int i;
6118 struct ureg_dst dst[2];
6119 struct ureg_src src[4];
6120 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6121
6122 int num_dst;
6123 int num_src;
6124 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6125
6126 num_dst = num_inst_dst_regs(inst);
6127 num_src = num_inst_src_regs(inst);
6128
6129 for (i = 0; i < num_dst; i++)
6130 dst[i] = translate_dst(t,
6131 &inst->dst[i],
6132 inst->saturate);
6133
6134 for (i = 0; i < num_src; i++)
6135 src[i] = translate_src(t, &inst->src[i]);
6136
6137 switch (inst->op) {
6138 case TGSI_OPCODE_BGNLOOP:
6139 case TGSI_OPCODE_ELSE:
6140 case TGSI_OPCODE_ENDLOOP:
6141 case TGSI_OPCODE_IF:
6142 case TGSI_OPCODE_UIF:
6143 assert(num_dst == 0);
6144 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6145 return;
6146
6147 case TGSI_OPCODE_TEX:
6148 case TGSI_OPCODE_TEX_LZ:
6149 case TGSI_OPCODE_TXB:
6150 case TGSI_OPCODE_TXD:
6151 case TGSI_OPCODE_TXL:
6152 case TGSI_OPCODE_TXP:
6153 case TGSI_OPCODE_TXQ:
6154 case TGSI_OPCODE_TXQS:
6155 case TGSI_OPCODE_TXF:
6156 case TGSI_OPCODE_TXF_LZ:
6157 case TGSI_OPCODE_TEX2:
6158 case TGSI_OPCODE_TXB2:
6159 case TGSI_OPCODE_TXL2:
6160 case TGSI_OPCODE_TG4:
6161 case TGSI_OPCODE_LODQ:
6162 case TGSI_OPCODE_SAMP2HND:
6163 if (inst->resource.file == PROGRAM_SAMPLER) {
6164 src[num_src] = t->samplers[inst->resource.index];
6165 } else {
6166 /* Bindless samplers. */
6167 src[num_src] = translate_src(t, &inst->resource);
6168 }
6169 assert(src[num_src].File != TGSI_FILE_NULL);
6170 if (inst->resource.reladdr)
6171 src[num_src] =
6172 ureg_src_indirect(src[num_src],
6173 translate_addr(t, inst->resource.reladdr, 2));
6174 num_src++;
6175 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6176 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6177 }
6178 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6179
6180 ureg_tex_insn(ureg,
6181 inst->op,
6182 dst, num_dst,
6183 tex_target,
6184 st_translate_texture_type(inst->tex_type),
6185 texoffsets, inst->tex_offset_num_offset,
6186 src, num_src);
6187 return;
6188
6189 case TGSI_OPCODE_RESQ:
6190 case TGSI_OPCODE_LOAD:
6191 case TGSI_OPCODE_ATOMUADD:
6192 case TGSI_OPCODE_ATOMXCHG:
6193 case TGSI_OPCODE_ATOMCAS:
6194 case TGSI_OPCODE_ATOMAND:
6195 case TGSI_OPCODE_ATOMOR:
6196 case TGSI_OPCODE_ATOMXOR:
6197 case TGSI_OPCODE_ATOMUMIN:
6198 case TGSI_OPCODE_ATOMUMAX:
6199 case TGSI_OPCODE_ATOMIMIN:
6200 case TGSI_OPCODE_ATOMIMAX:
6201 case TGSI_OPCODE_ATOMFADD:
6202 case TGSI_OPCODE_IMG2HND:
6203 for (i = num_src - 1; i >= 0; i--)
6204 src[i + 1] = src[i];
6205 num_src++;
6206 if (inst->resource.file == PROGRAM_MEMORY) {
6207 src[0] = t->shared_memory;
6208 } else if (inst->resource.file == PROGRAM_BUFFER) {
6209 src[0] = t->buffers[inst->resource.index];
6210 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6211 src[0] = translate_src(t, &inst->resource);
6212 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6213 assert(inst->resource.has_index2);
6214 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6215 } else {
6216 assert(inst->resource.file != PROGRAM_UNDEFINED);
6217 if (inst->resource.file == PROGRAM_IMAGE) {
6218 src[0] = t->images[inst->resource.index];
6219 } else {
6220 /* Bindless images. */
6221 src[0] = translate_src(t, &inst->resource);
6222 }
6223 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6224 }
6225 if (inst->resource.reladdr)
6226 src[0] = ureg_src_indirect(src[0],
6227 translate_addr(t, inst->resource.reladdr, 2));
6228 assert(src[0].File != TGSI_FILE_NULL);
6229 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6230 inst->buffer_access,
6231 tex_target, inst->image_format);
6232 break;
6233
6234 case TGSI_OPCODE_STORE:
6235 if (inst->resource.file == PROGRAM_MEMORY) {
6236 dst[0] = ureg_dst(t->shared_memory);
6237 } else if (inst->resource.file == PROGRAM_BUFFER) {
6238 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6239 } else {
6240 if (inst->resource.file == PROGRAM_IMAGE) {
6241 dst[0] = ureg_dst(t->images[inst->resource.index]);
6242 } else {
6243 /* Bindless images. */
6244 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6245 }
6246 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6247 }
6248 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6249 if (inst->resource.reladdr)
6250 dst[0] = ureg_dst_indirect(dst[0],
6251 translate_addr(t, inst->resource.reladdr, 2));
6252 assert(dst[0].File != TGSI_FILE_NULL);
6253 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6254 inst->buffer_access,
6255 tex_target, inst->image_format);
6256 break;
6257
6258 default:
6259 ureg_insn(ureg,
6260 inst->op,
6261 dst, num_dst,
6262 src, num_src, inst->precise);
6263 break;
6264 }
6265 }
6266
6267 /* Invert SamplePos.y when rendering to the default framebuffer. */
6268 static void
6269 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6270 {
6271 struct ureg_program *ureg = t->ureg;
6272
6273 assert(wpos_y_transform >= 0);
6274 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6275 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6276 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6277 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6278
6279 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6280 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6281
6282 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6283 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6284 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6285 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6286 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6287 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6288 samplepos_sysval);
6289
6290 /* Use the result in place of the system value. */
6291 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6292 }
6293
6294
6295 /**
6296 * Emit the TGSI instructions for inverting and adjusting WPOS.
6297 * This code is unavoidable because it also depends on whether
6298 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6299 */
6300 static void
6301 emit_wpos_adjustment(struct gl_context *ctx,
6302 struct st_translate *t,
6303 int wpos_transform_const,
6304 boolean invert,
6305 GLfloat adjX, GLfloat adjY[2])
6306 {
6307 struct ureg_program *ureg = t->ureg;
6308
6309 assert(wpos_transform_const >= 0);
6310
6311 /* Fragment program uses fragment position input.
6312 * Need to replace instances of INPUT[WPOS] with temp T
6313 * where T = INPUT[WPOS] is inverted by Y.
6314 */
6315 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6316 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6317 struct ureg_src *wpos =
6318 ctx->Const.GLSLFragCoordIsSysVal ?
6319 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6320 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6321 struct ureg_src wpos_input = *wpos;
6322
6323 /* First, apply the coordinate shift: */
6324 if (adjX || adjY[0] || adjY[1]) {
6325 if (adjY[0] != adjY[1]) {
6326 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6327 * depending on whether inversion is actually going to be applied
6328 * or not, which is determined by testing against the inversion
6329 * state variable used below, which will be either +1 or -1.
6330 */
6331 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6332
6333 ureg_CMP(ureg, adj_temp,
6334 ureg_scalar(wpostrans, invert ? 2 : 0),
6335 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6336 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6337 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6338 } else {
6339 ureg_ADD(ureg, wpos_temp, wpos_input,
6340 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6341 }
6342 wpos_input = ureg_src(wpos_temp);
6343 } else {
6344 /* MOV wpos_temp, input[wpos]
6345 */
6346 ureg_MOV(ureg, wpos_temp, wpos_input);
6347 }
6348
6349 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6350 * inversion/identity, or the other way around if we're drawing to an FBO.
6351 */
6352 if (invert) {
6353 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6354 */
6355 ureg_MAD(ureg,
6356 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6357 wpos_input,
6358 ureg_scalar(wpostrans, 0),
6359 ureg_scalar(wpostrans, 1));
6360 } else {
6361 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6362 */
6363 ureg_MAD(ureg,
6364 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6365 wpos_input,
6366 ureg_scalar(wpostrans, 2),
6367 ureg_scalar(wpostrans, 3));
6368 }
6369
6370 /* Use wpos_temp as position input from here on:
6371 */
6372 *wpos = ureg_src(wpos_temp);
6373 }
6374
6375
6376 /**
6377 * Emit fragment position/ooordinate code.
6378 */
6379 static void
6380 emit_wpos(struct st_context *st,
6381 struct st_translate *t,
6382 const struct gl_program *program,
6383 struct ureg_program *ureg,
6384 int wpos_transform_const)
6385 {
6386 struct pipe_screen *pscreen = st->pipe->screen;
6387 GLfloat adjX = 0.0f;
6388 GLfloat adjY[2] = { 0.0f, 0.0f };
6389 boolean invert = FALSE;
6390
6391 /* Query the pixel center conventions supported by the pipe driver and set
6392 * adjX, adjY to help out if it cannot handle the requested one internally.
6393 *
6394 * The bias of the y-coordinate depends on whether y-inversion takes place
6395 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6396 * drawing to an FBO (causes additional inversion), and whether the pipe
6397 * driver origin and the requested origin differ (the latter condition is
6398 * stored in the 'invert' variable).
6399 *
6400 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6401 *
6402 * center shift only:
6403 * i -> h: +0.5
6404 * h -> i: -0.5
6405 *
6406 * inversion only:
6407 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6408 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6409 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6410 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6411 *
6412 * inversion and center shift:
6413 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6414 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6415 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6416 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6417 */
6418 if (program->info.fs.origin_upper_left) {
6419 /* Fragment shader wants origin in upper-left */
6420 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6421 /* the driver supports upper-left origin */
6422 }
6423 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6424 /* the driver supports lower-left origin, need to invert Y */
6425 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6426 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6427 invert = TRUE;
6428 }
6429 else
6430 assert(0);
6431 }
6432 else {
6433 /* Fragment shader wants origin in lower-left */
6434 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6435 /* the driver supports lower-left origin */
6436 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6437 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6438 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6439 /* the driver supports upper-left origin, need to invert Y */
6440 invert = TRUE;
6441 else
6442 assert(0);
6443 }
6444
6445 if (program->info.fs.pixel_center_integer) {
6446 /* Fragment shader wants pixel center integer */
6447 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6448 /* the driver supports pixel center integer */
6449 adjY[1] = 1.0f;
6450 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6451 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6452 }
6453 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6454 /* the driver supports pixel center half integer, need to bias X,Y */
6455 adjX = -0.5f;
6456 adjY[0] = -0.5f;
6457 adjY[1] = 0.5f;
6458 }
6459 else
6460 assert(0);
6461 }
6462 else {
6463 /* Fragment shader wants pixel center half integer */
6464 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6465 /* the driver supports pixel center half integer */
6466 }
6467 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6468 /* the driver supports pixel center integer, need to bias X,Y */
6469 adjX = adjY[0] = adjY[1] = 0.5f;
6470 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6471 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6472 }
6473 else
6474 assert(0);
6475 }
6476
6477 /* we invert after adjustment so that we avoid the MOV to temporary,
6478 * and reuse the adjustment ADD instead */
6479 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6480 }
6481
6482 /**
6483 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6484 * TGSI uses +1 for front, -1 for back.
6485 * This function converts the TGSI value to the GL value. Simply clamping/
6486 * saturating the value to [0,1] does the job.
6487 */
6488 static void
6489 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6490 {
6491 struct ureg_program *ureg = t->ureg;
6492 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6493 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6494
6495 if (ctx->Const.NativeIntegers) {
6496 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6497 }
6498 else {
6499 /* MOV_SAT face_temp, input[face] */
6500 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6501 }
6502
6503 /* Use face_temp as face input from here on: */
6504 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6505 }
6506
6507 static void
6508 emit_compute_block_size(const struct gl_program *prog,
6509 struct ureg_program *ureg) {
6510 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6511 prog->info.cs.local_size[0]);
6512 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6513 prog->info.cs.local_size[1]);
6514 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6515 prog->info.cs.local_size[2]);
6516 }
6517
6518 struct sort_inout_decls {
6519 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6520 return mapping[a.mesa_index] < mapping[b.mesa_index];
6521 }
6522
6523 const ubyte *mapping;
6524 };
6525
6526 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6527 *
6528 * This is for the benefit of older drivers which are broken when the
6529 * declarations aren't sorted in this way.
6530 */
6531 static void
6532 sort_inout_decls_by_slot(struct inout_decl *decls,
6533 unsigned count,
6534 const ubyte mapping[])
6535 {
6536 sort_inout_decls sorter;
6537 sorter.mapping = mapping;
6538 std::sort(decls, decls + count, sorter);
6539 }
6540
6541 static enum tgsi_interpolate_mode
6542 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6543 {
6544 switch (glsl_qual) {
6545 case INTERP_MODE_NONE:
6546 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6547 return TGSI_INTERPOLATE_COLOR;
6548 return TGSI_INTERPOLATE_PERSPECTIVE;
6549 case INTERP_MODE_SMOOTH:
6550 return TGSI_INTERPOLATE_PERSPECTIVE;
6551 case INTERP_MODE_FLAT:
6552 return TGSI_INTERPOLATE_CONSTANT;
6553 case INTERP_MODE_NOPERSPECTIVE:
6554 return TGSI_INTERPOLATE_LINEAR;
6555 default:
6556 assert(0 && "unexpected interp mode in st_translate_interp()");
6557 return TGSI_INTERPOLATE_PERSPECTIVE;
6558 }
6559 }
6560
6561 /**
6562 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6563 * \param program the program to translate
6564 * \param numInputs number of input registers used
6565 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6566 * input indexes
6567 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6568 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6569 * each input
6570 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6571 * \param numOutputs number of output registers used
6572 * \param outputMapping maps Mesa fragment program outputs to TGSI
6573 * generic outputs
6574 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6575 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6576 * each output
6577 *
6578 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6579 */
6580 extern "C" enum pipe_error
6581 st_translate_program(
6582 struct gl_context *ctx,
6583 enum pipe_shader_type procType,
6584 struct ureg_program *ureg,
6585 glsl_to_tgsi_visitor *program,
6586 const struct gl_program *proginfo,
6587 GLuint numInputs,
6588 const ubyte inputMapping[],
6589 const ubyte inputSlotToAttr[],
6590 const ubyte inputSemanticName[],
6591 const ubyte inputSemanticIndex[],
6592 const ubyte interpMode[],
6593 GLuint numOutputs,
6594 const ubyte outputMapping[],
6595 const ubyte outputSemanticName[],
6596 const ubyte outputSemanticIndex[])
6597 {
6598 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6599 struct st_translate *t;
6600 unsigned i;
6601 struct gl_program_constants *frag_const =
6602 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6603 enum pipe_error ret = PIPE_OK;
6604
6605 assert(numInputs <= ARRAY_SIZE(t->inputs));
6606 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6607
6608 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6609 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6610 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6611 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6612 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6613 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6614 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6615 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6616 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6617 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6618
6619 t = CALLOC_STRUCT(st_translate);
6620 if (!t) {
6621 ret = PIPE_ERROR_OUT_OF_MEMORY;
6622 goto out;
6623 }
6624
6625 t->procType = procType;
6626 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6627 t->inputMapping = inputMapping;
6628 t->outputMapping = outputMapping;
6629 t->ureg = ureg;
6630 t->num_temp_arrays = program->next_array;
6631 if (t->num_temp_arrays)
6632 t->arrays = (struct ureg_dst*)
6633 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6634
6635 /*
6636 * Declare input attributes.
6637 */
6638 switch (procType) {
6639 case PIPE_SHADER_FRAGMENT:
6640 case PIPE_SHADER_GEOMETRY:
6641 case PIPE_SHADER_TESS_EVAL:
6642 case PIPE_SHADER_TESS_CTRL:
6643 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6644
6645 for (i = 0; i < program->num_inputs; ++i) {
6646 struct inout_decl *decl = &program->inputs[i];
6647 unsigned slot = inputMapping[decl->mesa_index];
6648 struct ureg_src src;
6649 ubyte tgsi_usage_mask = decl->usage_mask;
6650
6651 if (glsl_base_type_is_64bit(decl->base_type)) {
6652 if (tgsi_usage_mask == 1)
6653 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6654 else if (tgsi_usage_mask == 2)
6655 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6656 else
6657 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6658 }
6659
6660 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6661 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6662 if (procType == PIPE_SHADER_FRAGMENT) {
6663 assert(interpMode);
6664 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6665 (enum tgsi_interpolate_mode) interpMode[slot] :
6666 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6667
6668 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6669 }
6670
6671 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6672 (enum tgsi_semantic) inputSemanticName[slot],
6673 inputSemanticIndex[slot],
6674 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6675 decl->array_id, decl->size);
6676
6677 for (unsigned j = 0; j < decl->size; ++j) {
6678 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6679 /* The ArrayID is set up in dst_register */
6680 t->inputs[slot + j] = src;
6681 t->inputs[slot + j].ArrayID = 0;
6682 t->inputs[slot + j].Index += j;
6683 }
6684 }
6685 }
6686 break;
6687 case PIPE_SHADER_VERTEX:
6688 for (i = 0; i < numInputs; i++) {
6689 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6690 }
6691 break;
6692 case PIPE_SHADER_COMPUTE:
6693 break;
6694 default:
6695 assert(0);
6696 }
6697
6698 /*
6699 * Declare output attributes.
6700 */
6701 switch (procType) {
6702 case PIPE_SHADER_FRAGMENT:
6703 case PIPE_SHADER_COMPUTE:
6704 break;
6705 case PIPE_SHADER_GEOMETRY:
6706 case PIPE_SHADER_TESS_EVAL:
6707 case PIPE_SHADER_TESS_CTRL:
6708 case PIPE_SHADER_VERTEX:
6709 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6710
6711 for (i = 0; i < program->num_outputs; ++i) {
6712 struct inout_decl *decl = &program->outputs[i];
6713 unsigned slot = outputMapping[decl->mesa_index];
6714 struct ureg_dst dst;
6715 ubyte tgsi_usage_mask = decl->usage_mask;
6716
6717 if (glsl_base_type_is_64bit(decl->base_type)) {
6718 if (tgsi_usage_mask == 1)
6719 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6720 else if (tgsi_usage_mask == 2)
6721 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6722 else
6723 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6724 }
6725
6726 dst = ureg_DECL_output_layout(ureg,
6727 (enum tgsi_semantic) outputSemanticName[slot],
6728 outputSemanticIndex[slot],
6729 decl->gs_out_streams,
6730 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6731 dst.Invariant = decl->invariant;
6732 for (unsigned j = 0; j < decl->size; ++j) {
6733 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6734 /* The ArrayID is set up in dst_register */
6735 t->outputs[slot + j] = dst;
6736 t->outputs[slot + j].ArrayID = 0;
6737 t->outputs[slot + j].Index += j;
6738 t->outputs[slot + j].Invariant = decl->invariant;
6739 }
6740 }
6741 }
6742 break;
6743 default:
6744 assert(0);
6745 }
6746
6747 if (procType == PIPE_SHADER_FRAGMENT) {
6748 if (program->shader->Program->info.fs.early_fragment_tests ||
6749 program->shader->Program->info.fs.post_depth_coverage) {
6750 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6751
6752 if (program->shader->Program->info.fs.post_depth_coverage)
6753 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6754 }
6755
6756 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6757 /* Must do this after setting up t->inputs. */
6758 emit_wpos(st_context(ctx), t, proginfo, ureg,
6759 program->wpos_transform_const);
6760 }
6761
6762 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6763 emit_face_var(ctx, t);
6764
6765 for (i = 0; i < numOutputs; i++) {
6766 switch (outputSemanticName[i]) {
6767 case TGSI_SEMANTIC_POSITION:
6768 t->outputs[i] = ureg_DECL_output(ureg,
6769 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6770 outputSemanticIndex[i]);
6771 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6772 break;
6773 case TGSI_SEMANTIC_STENCIL:
6774 t->outputs[i] = ureg_DECL_output(ureg,
6775 TGSI_SEMANTIC_STENCIL, /* Stencil */
6776 outputSemanticIndex[i]);
6777 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6778 break;
6779 case TGSI_SEMANTIC_COLOR:
6780 t->outputs[i] = ureg_DECL_output(ureg,
6781 TGSI_SEMANTIC_COLOR,
6782 outputSemanticIndex[i]);
6783 break;
6784 case TGSI_SEMANTIC_SAMPLEMASK:
6785 t->outputs[i] = ureg_DECL_output(ureg,
6786 TGSI_SEMANTIC_SAMPLEMASK,
6787 outputSemanticIndex[i]);
6788 /* TODO: If we ever support more than 32 samples, this will have
6789 * to become an array.
6790 */
6791 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6792 break;
6793 default:
6794 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6795 ret = PIPE_ERROR_BAD_INPUT;
6796 goto out;
6797 }
6798 }
6799 }
6800 else if (procType == PIPE_SHADER_VERTEX) {
6801 for (i = 0; i < numOutputs; i++) {
6802 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6803 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6804 ureg_MOV(ureg,
6805 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6806 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6807 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6808 }
6809 }
6810 }
6811
6812 if (procType == PIPE_SHADER_COMPUTE) {
6813 emit_compute_block_size(proginfo, ureg);
6814 }
6815
6816 /* Declare address register.
6817 */
6818 if (program->num_address_regs > 0) {
6819 assert(program->num_address_regs <= 3);
6820 for (int i = 0; i < program->num_address_regs; i++)
6821 t->address[i] = ureg_DECL_address(ureg);
6822 }
6823
6824 /* Declare misc input registers
6825 */
6826 {
6827 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6828
6829 for (i = 0; sysInputs; i++) {
6830 if (sysInputs & (1ull << i)) {
6831 enum tgsi_semantic semName = _mesa_sysval_to_semantic(i);
6832
6833 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6834
6835 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6836 semName == TGSI_SEMANTIC_VERTEXID) {
6837 /* From Gallium perspective, these system values are always
6838 * integer, and require native integer support. However, if
6839 * native integer is supported on the vertex stage but not the
6840 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6841 * assumes these system values are floats. To resolve the
6842 * inconsistency, we insert a U2F.
6843 */
6844 struct st_context *st = st_context(ctx);
6845 struct pipe_screen *pscreen = st->pipe->screen;
6846 assert(procType == PIPE_SHADER_VERTEX);
6847 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6848 (void) pscreen;
6849 if (!ctx->Const.NativeIntegers) {
6850 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6851 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6852 t->systemValues[i]);
6853 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6854 }
6855 }
6856
6857 if (procType == PIPE_SHADER_FRAGMENT &&
6858 semName == TGSI_SEMANTIC_POSITION)
6859 emit_wpos(st_context(ctx), t, proginfo, ureg,
6860 program->wpos_transform_const);
6861
6862 if (procType == PIPE_SHADER_FRAGMENT &&
6863 semName == TGSI_SEMANTIC_SAMPLEPOS)
6864 emit_samplepos_adjustment(t, program->wpos_transform_const);
6865
6866 sysInputs &= ~(1ull << i);
6867 }
6868 }
6869 }
6870
6871 t->array_sizes = program->array_sizes;
6872 t->input_decls = program->inputs;
6873 t->num_input_decls = program->num_inputs;
6874 t->output_decls = program->outputs;
6875 t->num_output_decls = program->num_outputs;
6876
6877 /* Emit constants and uniforms. TGSI uses a single index space for these,
6878 * so we put all the translated regs in t->constants.
6879 */
6880 if (proginfo->Parameters) {
6881 t->constants = (struct ureg_src *)
6882 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6883 if (t->constants == NULL) {
6884 ret = PIPE_ERROR_OUT_OF_MEMORY;
6885 goto out;
6886 }
6887 t->num_constants = proginfo->Parameters->NumParameters;
6888
6889 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6890 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6891
6892 switch (proginfo->Parameters->Parameters[i].Type) {
6893 case PROGRAM_STATE_VAR:
6894 case PROGRAM_UNIFORM:
6895 t->constants[i] = ureg_DECL_constant(ureg, i);
6896 break;
6897
6898 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6899 * addressing of the const buffer.
6900 * FIXME: Be smarter and recognize param arrays:
6901 * indirect addressing is only valid within the referenced
6902 * array.
6903 */
6904 case PROGRAM_CONSTANT:
6905 if (program->indirect_addr_consts)
6906 t->constants[i] = ureg_DECL_constant(ureg, i);
6907 else
6908 t->constants[i] = emit_immediate(t,
6909 proginfo->Parameters->ParameterValues + pvo,
6910 proginfo->Parameters->Parameters[i].DataType,
6911 4);
6912 break;
6913 default:
6914 break;
6915 }
6916 }
6917 }
6918
6919 for (i = 0; i < proginfo->info.num_ubos; i++) {
6920 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6921 unsigned num_const_vecs = (size + 15) / 16;
6922 unsigned first, last;
6923 assert(num_const_vecs > 0);
6924 first = 0;
6925 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6926 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6927 }
6928
6929 /* Emit immediate values.
6930 */
6931 t->immediates = (struct ureg_src *)
6932 calloc(program->num_immediates, sizeof(struct ureg_src));
6933 if (t->immediates == NULL) {
6934 ret = PIPE_ERROR_OUT_OF_MEMORY;
6935 goto out;
6936 }
6937 t->num_immediates = program->num_immediates;
6938
6939 i = 0;
6940 foreach_in_list(immediate_storage, imm, &program->immediates) {
6941 assert(i < program->num_immediates);
6942 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6943 }
6944 assert(i == program->num_immediates);
6945
6946 /* texture samplers */
6947 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6948 if (program->samplers_used & (1u << i)) {
6949 enum tgsi_return_type type =
6950 st_translate_texture_type(program->sampler_types[i]);
6951
6952 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6953
6954 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6955 type, type, type, type);
6956 }
6957 }
6958
6959 /* Declare atomic and shader storage buffers. */
6960 {
6961 struct gl_program *prog = program->prog;
6962
6963 if (!st_context(ctx)->has_hw_atomics) {
6964 for (i = 0; i < prog->info.num_abos; i++) {
6965 unsigned index = prog->sh.AtomicBuffers[i]->Binding;
6966 assert(index < frag_const->MaxAtomicBuffers);
6967 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6968 }
6969 } else {
6970 for (i = 0; i < program->num_atomics; i++) {
6971 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6972 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6973 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6974 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6975 ainfo->array_id);
6976 }
6977 }
6978
6979 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6980 for (i = 0; i < prog->info.num_ssbos; i++) {
6981 unsigned index = i;
6982 if (!st_context(ctx)->has_hw_atomics)
6983 index += frag_const->MaxAtomicBuffers;
6984
6985 t->buffers[index] = ureg_DECL_buffer(ureg, index, false);
6986 }
6987 }
6988
6989 if (program->use_shared_memory)
6990 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
6991
6992 for (i = 0; i < program->shader->Program->info.num_images; i++) {
6993 if (program->images_used & (1 << i)) {
6994 t->images[i] = ureg_DECL_image(ureg, i,
6995 program->image_targets[i],
6996 program->image_formats[i],
6997 program->image_wr[i],
6998 false);
6999 }
7000 }
7001
7002 /* Emit each instruction in turn:
7003 */
7004 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
7005 compile_tgsi_instruction(t, inst);
7006
7007 /* Set the next shader stage hint for VS and TES. */
7008 switch (procType) {
7009 case PIPE_SHADER_VERTEX:
7010 case PIPE_SHADER_TESS_EVAL:
7011 if (program->shader_program->SeparateShader)
7012 break;
7013
7014 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
7015 if (program->shader_program->_LinkedShaders[i]) {
7016 ureg_set_next_shader_processor(
7017 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
7018 break;
7019 }
7020 }
7021 break;
7022 default:
7023 ; /* nothing - silence compiler warning */
7024 }
7025
7026 out:
7027 if (t) {
7028 free(t->arrays);
7029 free(t->temps);
7030 free(t->constants);
7031 t->num_constants = 0;
7032 free(t->immediates);
7033 t->num_immediates = 0;
7034 FREE(t);
7035 }
7036
7037 return ret;
7038 }
7039 /* ----------------------------- End TGSI code ------------------------------ */
7040
7041
7042 /**
7043 * Convert a shader's GLSL IR into a Mesa gl_program, although without
7044 * generating Mesa IR.
7045 */
7046 static struct gl_program *
7047 get_mesa_program_tgsi(struct gl_context *ctx,
7048 struct gl_shader_program *shader_program,
7049 struct gl_linked_shader *shader)
7050 {
7051 glsl_to_tgsi_visitor* v;
7052 struct gl_program *prog;
7053 struct gl_shader_compiler_options *options =
7054 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7055 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7056 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7057 unsigned skip_merge_registers;
7058
7059 validate_ir_tree(shader->ir);
7060
7061 prog = shader->Program;
7062
7063 prog->Parameters = _mesa_new_parameter_list();
7064 v = new glsl_to_tgsi_visitor();
7065 v->ctx = ctx;
7066 v->prog = prog;
7067 v->shader_program = shader_program;
7068 v->shader = shader;
7069 v->options = options;
7070 v->native_integers = ctx->Const.NativeIntegers;
7071
7072 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7073 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7074 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7075 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7076 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7077 PIPE_CAP_TGSI_TEX_TXF_LZ);
7078 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7079
7080 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7081 _mesa_key_pointer_equal);
7082 skip_merge_registers =
7083 pscreen->get_shader_param(pscreen, ptarget,
7084 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7085
7086 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7087 prog->Parameters);
7088
7089 /* Remove reads from output registers. */
7090 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7091 lower_output_reads(shader->Stage, shader->ir);
7092
7093 /* Emit intermediate IR for main(). */
7094 visit_exec_list(shader->ir, v);
7095
7096 #if 0
7097 /* Print out some information (for debugging purposes) used by the
7098 * optimization passes. */
7099 {
7100 int i;
7101 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7102 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7103 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7104 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7105
7106 for (i = 0; i < v->next_temp; i++) {
7107 first_writes[i] = -1;
7108 first_reads[i] = -1;
7109 last_writes[i] = -1;
7110 last_reads[i] = -1;
7111 }
7112 v->get_first_temp_read(first_reads);
7113 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7114 v->get_last_temp_write(last_writes);
7115 for (i = 0; i < v->next_temp; i++)
7116 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7117 first_writes[i],
7118 last_reads[i],
7119 last_writes[i]);
7120 ralloc_free(first_writes);
7121 ralloc_free(first_reads);
7122 ralloc_free(last_writes);
7123 ralloc_free(last_reads);
7124 }
7125 #endif
7126
7127 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7128 v->simplify_cmp();
7129 v->copy_propagate();
7130
7131 while (v->eliminate_dead_code());
7132
7133 v->merge_two_dsts();
7134
7135 if (!skip_merge_registers) {
7136 v->split_arrays();
7137 v->copy_propagate();
7138 while (v->eliminate_dead_code());
7139
7140 v->merge_registers();
7141 v->copy_propagate();
7142 while (v->eliminate_dead_code());
7143 }
7144
7145 v->renumber_registers();
7146
7147 /* Write the END instruction. */
7148 v->emit_asm(NULL, TGSI_OPCODE_END);
7149
7150 if (ctx->_Shader->Flags & GLSL_DUMP) {
7151 _mesa_log("\n");
7152 _mesa_log("GLSL IR for linked %s program %d:\n",
7153 _mesa_shader_stage_to_string(shader->Stage),
7154 shader_program->Name);
7155 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7156 _mesa_log("\n\n");
7157 }
7158
7159 do_set_program_inouts(shader->ir, prog, shader->Stage);
7160 _mesa_copy_linked_program_data(shader_program, shader);
7161 shrink_array_declarations(v->inputs, v->num_inputs,
7162 &prog->info.inputs_read,
7163 prog->DualSlotInputs,
7164 &prog->info.patch_inputs_read);
7165 shrink_array_declarations(v->outputs, v->num_outputs,
7166 &prog->info.outputs_written, 0ULL,
7167 &prog->info.patch_outputs_written);
7168 count_resources(v, prog);
7169
7170 /* The GLSL IR won't be needed anymore. */
7171 ralloc_free(shader->ir);
7172 shader->ir = NULL;
7173
7174 /* This must be done before the uniform storage is associated. */
7175 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7176 (prog->info.inputs_read & VARYING_BIT_POS ||
7177 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD) ||
7178 prog->info.system_values_read & (1ull << SYSTEM_VALUE_SAMPLE_POS))) {
7179 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7180 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7181 };
7182
7183 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7184 wposTransformState);
7185 }
7186
7187 /* Avoid reallocation of the program parameter list, because the uniform
7188 * storage is only associated with the original parameter list.
7189 * This should be enough for Bitmap and DrawPixels constants.
7190 */
7191 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7192
7193 /* This has to be done last. Any operation the can cause
7194 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7195 * program constant) has to happen before creating this linkage.
7196 */
7197 _mesa_associate_uniform_storage(ctx, shader_program, prog, true);
7198 if (!shader_program->data->LinkStatus) {
7199 free_glsl_to_tgsi_visitor(v);
7200 _mesa_reference_program(ctx, &shader->Program, NULL);
7201 return NULL;
7202 }
7203
7204 struct st_vertex_program *stvp;
7205 struct st_fragment_program *stfp;
7206 struct st_common_program *stp;
7207 struct st_compute_program *stcp;
7208
7209 switch (shader->Stage) {
7210 case MESA_SHADER_VERTEX:
7211 stvp = (struct st_vertex_program *)prog;
7212 stvp->glsl_to_tgsi = v;
7213 break;
7214 case MESA_SHADER_FRAGMENT:
7215 stfp = (struct st_fragment_program *)prog;
7216 stfp->glsl_to_tgsi = v;
7217 break;
7218 case MESA_SHADER_TESS_CTRL:
7219 case MESA_SHADER_TESS_EVAL:
7220 case MESA_SHADER_GEOMETRY:
7221 stp = st_common_program(prog);
7222 stp->glsl_to_tgsi = v;
7223 break;
7224 case MESA_SHADER_COMPUTE:
7225 stcp = (struct st_compute_program *)prog;
7226 stcp->glsl_to_tgsi = v;
7227 break;
7228 default:
7229 assert(!"should not be reached");
7230 return NULL;
7231 }
7232
7233 PRINT_STATS(v->print_stats());
7234
7235 return prog;
7236 }
7237
7238 /* See if there are unsupported control flow statements. */
7239 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7240 private:
7241 const struct gl_shader_compiler_options *options;
7242 public:
7243 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7244 : options(options),
7245 unsupported(false)
7246 {
7247 }
7248
7249 virtual ir_visitor_status visit_enter(ir_function *ir)
7250 {
7251 /* Other functions are skipped (same as glsl_to_tgsi). */
7252 if (strcmp(ir->name, "main") == 0)
7253 return visit_continue;
7254
7255 return visit_continue_with_parent;
7256 }
7257
7258 virtual ir_visitor_status visit_enter(ir_call *ir)
7259 {
7260 if (!ir->callee->is_intrinsic()) {
7261 unsupported = true; /* it's a function call */
7262 return visit_stop;
7263 }
7264 return visit_continue;
7265 }
7266
7267 virtual ir_visitor_status visit_enter(ir_return *ir)
7268 {
7269 if (options->EmitNoMainReturn) {
7270 unsupported = true;
7271 return visit_stop;
7272 }
7273 return visit_continue;
7274 }
7275
7276 bool unsupported;
7277 };
7278
7279 static bool
7280 has_unsupported_control_flow(exec_list *ir,
7281 const struct gl_shader_compiler_options *options)
7282 {
7283 ir_control_flow_info_visitor visitor(options);
7284 visit_list_elements(&visitor, ir);
7285 return visitor.unsupported;
7286 }
7287
7288 /**
7289 * Link a shader.
7290 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7291 * with code lowering and other optimizations.
7292 */
7293 GLboolean
7294 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7295 {
7296 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7297
7298 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7299 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7300 if (shader == NULL)
7301 continue;
7302
7303 exec_list *ir = shader->ir;
7304 gl_shader_stage stage = shader->Stage;
7305 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7306 const struct gl_shader_compiler_options *options =
7307 &ctx->Const.ShaderCompilerOptions[stage];
7308
7309 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7310 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7311 if (ctx->Const.GLSLOptimizeConservatively) {
7312 /* Do it once and repeat only if there's unsupported control flow. */
7313 do {
7314 do_common_optimization(ir, true, true, options,
7315 ctx->Const.NativeIntegers);
7316 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7317 options->MaxIfDepth, if_threshold);
7318 } while (has_unsupported_control_flow(ir, options));
7319 } else {
7320 /* Repeat it until it stops making changes. */
7321 bool progress;
7322 do {
7323 progress = do_common_optimization(ir, true, true, options,
7324 ctx->Const.NativeIntegers);
7325 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7326 options->MaxIfDepth, if_threshold);
7327 } while (progress);
7328 }
7329
7330 /* Do this again to lower ir_binop_vector_extract introduced
7331 * by optimization passes.
7332 */
7333 do_vec_index_to_cond_assign(ir);
7334
7335 validate_ir_tree(ir);
7336
7337 struct gl_program *linked_prog =
7338 get_mesa_program_tgsi(ctx, prog, shader);
7339 st_set_prog_affected_state_flags(linked_prog);
7340
7341 if (linked_prog) {
7342 if (!ctx->Driver.ProgramStringNotify(ctx,
7343 _mesa_shader_stage_to_program(i),
7344 linked_prog)) {
7345 _mesa_reference_program(ctx, &shader->Program, NULL);
7346 return GL_FALSE;
7347 }
7348 }
7349 }
7350
7351 return GL_TRUE;
7352 }
7353
7354 extern "C" {
7355
7356 void
7357 st_translate_stream_output_info(struct gl_transform_feedback_info *info,
7358 const ubyte outputMapping[],
7359 struct pipe_stream_output_info *so)
7360 {
7361 unsigned i;
7362
7363 if (!info) {
7364 so->num_outputs = 0;
7365 return;
7366 }
7367
7368 for (i = 0; i < info->NumOutputs; i++) {
7369 so->output[i].register_index =
7370 outputMapping[info->Outputs[i].OutputRegister];
7371 so->output[i].start_component = info->Outputs[i].ComponentOffset;
7372 so->output[i].num_components = info->Outputs[i].NumComponents;
7373 so->output[i].output_buffer = info->Outputs[i].OutputBuffer;
7374 so->output[i].dst_offset = info->Outputs[i].DstOffset;
7375 so->output[i].stream = info->Outputs[i].StreamId;
7376 }
7377
7378 for (i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
7379 so->stride[i] = info->Buffers[i].Stride;
7380 }
7381 so->num_outputs = info->NumOutputs;
7382 }
7383
7384 } /* extern "C" */