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mesa: rework ParameterList to allow packing
[mesa.git] / src / mesa / state_tracker / st_glsl_to_tgsi.cpp
1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
56 #include "st_nir.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
59
60 #include "util/hash_table.h"
61 #include <algorithm>
62
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
66
67 #define MAX_GLSL_TEXTURE_OFFSET 4
68
69 static unsigned is_precise(const ir_variable *ir)
70 {
71 if (!ir)
72 return 0;
73 return ir->data.precise || ir->data.invariant;
74 }
75
76 class variable_storage {
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
78
79 public:
80 variable_storage(ir_variable *var, gl_register_file file, int index,
81 unsigned array_id = 0)
82 : file(file), index(index), component(0), var(var), array_id(array_id)
83 {
84 assert(file != PROGRAM_ARRAY || array_id != 0);
85 }
86
87 gl_register_file file;
88 int index;
89
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
93 */
94 int component;
95 ir_variable *var; /* variable that maps to this, if any */
96 unsigned array_id;
97 };
98
99 class immediate_storage : public exec_node {
100 public:
101 immediate_storage(gl_constant_value *values, int size32, GLenum type)
102 {
103 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
104 this->size32 = size32;
105 this->type = type;
106 }
107
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values[4];
110 int size32; /**< Number of 32-bit components (1-4) */
111 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
112 };
113
114 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
115 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
116
117 struct inout_decl {
118 unsigned mesa_index;
119 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
120 unsigned size;
121 unsigned interp_loc;
122 unsigned gs_out_streams;
123 enum glsl_interp_mode interp;
124 enum glsl_base_type base_type;
125 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
126 };
127
128 static struct inout_decl *
129 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
130 {
131 assert(array_id != 0);
132
133 for (unsigned i = 0; i < count; i++) {
134 struct inout_decl *decl = &decls[i];
135
136 if (array_id == decl->array_id) {
137 return decl;
138 }
139 }
140
141 return NULL;
142 }
143
144 static enum glsl_base_type
145 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
146 {
147 if (!array_id)
148 return GLSL_TYPE_ERROR;
149 struct inout_decl *decl = find_inout_array(decls, count, array_id);
150 if (decl)
151 return decl->base_type;
152 return GLSL_TYPE_ERROR;
153 }
154
155 struct hwatomic_decl {
156 unsigned location;
157 unsigned binding;
158 unsigned size;
159 unsigned array_id;
160 };
161
162 struct glsl_to_tgsi_visitor : public ir_visitor {
163 public:
164 glsl_to_tgsi_visitor();
165 ~glsl_to_tgsi_visitor();
166
167 struct gl_context *ctx;
168 struct gl_program *prog;
169 struct gl_shader_program *shader_program;
170 struct gl_linked_shader *shader;
171 struct gl_shader_compiler_options *options;
172
173 int next_temp;
174
175 unsigned *array_sizes;
176 unsigned max_num_arrays;
177 unsigned next_array;
178
179 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
180 unsigned num_inputs;
181 unsigned num_input_arrays;
182 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
183 unsigned num_outputs;
184 unsigned num_output_arrays;
185
186 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
187 unsigned num_atomics;
188 unsigned num_atomic_arrays;
189 int num_address_regs;
190 uint32_t samplers_used;
191 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
192 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
193 int images_used;
194 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
195 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
196 bool indirect_addr_consts;
197 int wpos_transform_const;
198
199 bool native_integers;
200 bool have_sqrt;
201 bool have_fma;
202 bool use_shared_memory;
203 bool has_tex_txf_lz;
204 bool precise;
205 bool need_uarl;
206
207 variable_storage *find_variable_storage(ir_variable *var);
208
209 int add_constant(gl_register_file file, gl_constant_value values[8],
210 int size, GLenum datatype, uint16_t *swizzle_out);
211
212 st_src_reg get_temp(const glsl_type *type);
213 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
214
215 st_src_reg st_src_reg_for_double(double val);
216 st_src_reg st_src_reg_for_float(float val);
217 st_src_reg st_src_reg_for_int(int val);
218 st_src_reg st_src_reg_for_int64(int64_t val);
219 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
220
221 /**
222 * \name Visit methods
223 *
224 * As typical for the visitor pattern, there must be one \c visit method for
225 * each concrete subclass of \c ir_instruction. Virtual base classes within
226 * the hierarchy should not have \c visit methods.
227 */
228 /*@{*/
229 virtual void visit(ir_variable *);
230 virtual void visit(ir_loop *);
231 virtual void visit(ir_loop_jump *);
232 virtual void visit(ir_function_signature *);
233 virtual void visit(ir_function *);
234 virtual void visit(ir_expression *);
235 virtual void visit(ir_swizzle *);
236 virtual void visit(ir_dereference_variable *);
237 virtual void visit(ir_dereference_array *);
238 virtual void visit(ir_dereference_record *);
239 virtual void visit(ir_assignment *);
240 virtual void visit(ir_constant *);
241 virtual void visit(ir_call *);
242 virtual void visit(ir_return *);
243 virtual void visit(ir_discard *);
244 virtual void visit(ir_texture *);
245 virtual void visit(ir_if *);
246 virtual void visit(ir_emit_vertex *);
247 virtual void visit(ir_end_primitive *);
248 virtual void visit(ir_barrier *);
249 /*@}*/
250
251 void visit_expression(ir_expression *, st_src_reg *) ATTRIBUTE_NOINLINE;
252
253 void visit_atomic_counter_intrinsic(ir_call *);
254 void visit_ssbo_intrinsic(ir_call *);
255 void visit_membar_intrinsic(ir_call *);
256 void visit_shared_intrinsic(ir_call *);
257 void visit_image_intrinsic(ir_call *);
258 void visit_generic_intrinsic(ir_call *, unsigned op);
259
260 st_src_reg result;
261
262 /** List of variable_storage */
263 struct hash_table *variables;
264
265 /** List of immediate_storage */
266 exec_list immediates;
267 unsigned num_immediates;
268
269 /** List of glsl_to_tgsi_instruction */
270 exec_list instructions;
271
272 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
273 st_dst_reg dst = undef_dst,
274 st_src_reg src0 = undef_src,
275 st_src_reg src1 = undef_src,
276 st_src_reg src2 = undef_src,
277 st_src_reg src3 = undef_src);
278
279 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
280 st_dst_reg dst, st_dst_reg dst1,
281 st_src_reg src0 = undef_src,
282 st_src_reg src1 = undef_src,
283 st_src_reg src2 = undef_src,
284 st_src_reg src3 = undef_src);
285
286 unsigned get_opcode(unsigned op,
287 st_dst_reg dst,
288 st_src_reg src0, st_src_reg src1);
289
290 /**
291 * Emit the correct dot-product instruction for the type of arguments
292 */
293 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
294 st_dst_reg dst,
295 st_src_reg src0,
296 st_src_reg src1,
297 unsigned elements);
298
299 void emit_scalar(ir_instruction *ir, unsigned op,
300 st_dst_reg dst, st_src_reg src0);
301
302 void emit_scalar(ir_instruction *ir, unsigned op,
303 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
304
305 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
306
307 void get_deref_offsets(ir_dereference *ir,
308 unsigned *array_size,
309 unsigned *base,
310 uint16_t *index,
311 st_src_reg *reladdr,
312 bool opaque);
313 void calc_deref_offsets(ir_dereference *tail,
314 unsigned *array_elements,
315 uint16_t *index,
316 st_src_reg *indirect,
317 unsigned *location);
318 st_src_reg canonicalize_gather_offset(st_src_reg offset);
319
320 bool try_emit_mad(ir_expression *ir,
321 int mul_operand);
322 bool try_emit_mad_for_and_not(ir_expression *ir,
323 int mul_operand);
324
325 void emit_swz(ir_expression *ir);
326
327 bool process_move_condition(ir_rvalue *ir);
328
329 void simplify_cmp(void);
330
331 void rename_temp_registers(struct rename_reg_pair *renames);
332 void get_first_temp_read(int *first_reads);
333 void get_first_temp_write(int *first_writes);
334 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
335 void get_last_temp_write(int *last_writes);
336
337 void copy_propagate(void);
338 int eliminate_dead_code(void);
339
340 void merge_two_dsts(void);
341 void merge_registers(void);
342 void renumber_registers(void);
343
344 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
345 st_dst_reg *l, st_src_reg *r,
346 st_src_reg *cond, bool cond_swap);
347
348 void *mem_ctx;
349 };
350
351 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
352 GLSL_TYPE_FLOAT, 0);
353 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
354 GLSL_TYPE_FLOAT, 1);
355 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
356 GLSL_TYPE_FLOAT, 2);
357
358 static void
359 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
360 PRINTFLIKE(2, 3);
361
362 static void
363 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
364 {
365 va_list args;
366 va_start(args, fmt);
367 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
368 va_end(args);
369
370 prog->data->LinkStatus = LINKING_FAILURE;
371 }
372
373 int
374 swizzle_for_size(int size)
375 {
376 static const int size_swizzles[4] = {
377 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
378 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
379 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
380 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
381 };
382
383 assert((size >= 1) && (size <= 4));
384 return size_swizzles[size - 1];
385 }
386
387
388 glsl_to_tgsi_instruction *
389 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
390 st_dst_reg dst, st_dst_reg dst1,
391 st_src_reg src0, st_src_reg src1,
392 st_src_reg src2, st_src_reg src3)
393 {
394 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
395 int num_reladdr = 0, i, j;
396 bool dst_is_64bit[2];
397
398 op = get_opcode(op, dst, src0, src1);
399
400 /* If we have to do relative addressing, we want to load the ARL
401 * reg directly for one of the regs, and preload the other reladdr
402 * sources into temps.
403 */
404 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
405 assert(!dst1.reladdr); /* should be lowered in earlier passes */
406 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
407 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
408 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
409 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
410
411 reladdr_to_temp(ir, &src3, &num_reladdr);
412 reladdr_to_temp(ir, &src2, &num_reladdr);
413 reladdr_to_temp(ir, &src1, &num_reladdr);
414 reladdr_to_temp(ir, &src0, &num_reladdr);
415
416 if (dst.reladdr || dst.reladdr2) {
417 if (dst.reladdr)
418 emit_arl(ir, address_reg, *dst.reladdr);
419 if (dst.reladdr2)
420 emit_arl(ir, address_reg2, *dst.reladdr2);
421 num_reladdr--;
422 }
423
424 assert(num_reladdr == 0);
425
426 /* inst->op has only 8 bits. */
427 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
428
429 inst->op = op;
430 inst->precise = this->precise;
431 inst->info = tgsi_get_opcode_info(op);
432 inst->dst[0] = dst;
433 inst->dst[1] = dst1;
434 inst->src[0] = src0;
435 inst->src[1] = src1;
436 inst->src[2] = src2;
437 inst->src[3] = src3;
438 inst->is_64bit_expanded = false;
439 inst->ir = ir;
440 inst->dead_mask = 0;
441 inst->tex_offsets = NULL;
442 inst->tex_offset_num_offset = 0;
443 inst->saturate = 0;
444 inst->tex_shadow = 0;
445 /* default to float, for paths where this is not initialized
446 * (since 0==UINT which is likely wrong):
447 */
448 inst->tex_type = GLSL_TYPE_FLOAT;
449
450 /* Update indirect addressing status used by TGSI */
451 if (dst.reladdr || dst.reladdr2) {
452 switch (dst.file) {
453 case PROGRAM_STATE_VAR:
454 case PROGRAM_CONSTANT:
455 case PROGRAM_UNIFORM:
456 this->indirect_addr_consts = true;
457 break;
458 case PROGRAM_IMMEDIATE:
459 assert(!"immediates should not have indirect addressing");
460 break;
461 default:
462 break;
463 }
464 }
465 else {
466 for (i = 0; i < 4; i++) {
467 if (inst->src[i].reladdr) {
468 switch (inst->src[i].file) {
469 case PROGRAM_STATE_VAR:
470 case PROGRAM_CONSTANT:
471 case PROGRAM_UNIFORM:
472 this->indirect_addr_consts = true;
473 break;
474 case PROGRAM_IMMEDIATE:
475 assert(!"immediates should not have indirect addressing");
476 break;
477 default:
478 break;
479 }
480 }
481 }
482 }
483
484 /*
485 * This section contains the double processing.
486 * GLSL just represents doubles as single channel values,
487 * however most HW and TGSI represent doubles as pairs of register channels.
488 *
489 * so we have to fixup destination writemask/index and src swizzle/indexes.
490 * dest writemasks need to translate from single channel write mask
491 * to a dual-channel writemask, but also need to modify the index,
492 * if we are touching the Z,W fields in the pre-translated writemask.
493 *
494 * src channels have similiar index modifications along with swizzle
495 * changes to we pick the XY, ZW pairs from the correct index.
496 *
497 * GLSL [0].x -> TGSI [0].xy
498 * GLSL [0].y -> TGSI [0].zw
499 * GLSL [0].z -> TGSI [1].xy
500 * GLSL [0].w -> TGSI [1].zw
501 */
502 for (j = 0; j < 2; j++) {
503 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
504 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
505 inst->dst[j].type == GLSL_TYPE_ARRAY) {
506 enum glsl_base_type type = find_array_type(this->outputs,
507 this->num_outputs,
508 inst->dst[j].array_id);
509 if (glsl_base_type_is_64bit(type))
510 dst_is_64bit[j] = true;
511 }
512 }
513
514 if (dst_is_64bit[0] || dst_is_64bit[1] ||
515 glsl_base_type_is_64bit(inst->src[0].type)) {
516 glsl_to_tgsi_instruction *dinst = NULL;
517 int initial_src_swz[4], initial_src_idx[4];
518 int initial_dst_idx[2], initial_dst_writemask[2];
519 /* select the writemask for dst0 or dst1 */
520 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
521 ? inst->dst[0].writemask : inst->dst[1].writemask;
522
523 /* copy out the writemask, index and swizzles for all src/dsts. */
524 for (j = 0; j < 2; j++) {
525 initial_dst_writemask[j] = inst->dst[j].writemask;
526 initial_dst_idx[j] = inst->dst[j].index;
527 }
528
529 for (j = 0; j < 4; j++) {
530 initial_src_swz[j] = inst->src[j].swizzle;
531 initial_src_idx[j] = inst->src[j].index;
532 }
533
534 /*
535 * scan all the components in the dst writemask
536 * generate an instruction for each of them if required.
537 */
538 st_src_reg addr;
539 while (writemask) {
540
541 int i = u_bit_scan(&writemask);
542
543 /* before emitting the instruction, see if we have to adjust
544 * load / store address */
545 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
546 inst->op == TGSI_OPCODE_STORE) &&
547 addr.file == PROGRAM_UNDEFINED) {
548 /* We have to advance the buffer address by 16 */
549 addr = get_temp(glsl_type::uint_type);
550 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
551 inst->src[0], st_src_reg_for_int(16));
552 }
553
554 /* first time use previous instruction */
555 if (dinst == NULL) {
556 dinst = inst;
557 } else {
558 /* create a new instructions for subsequent attempts */
559 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
560 *dinst = *inst;
561 dinst->next = NULL;
562 dinst->prev = NULL;
563 }
564 this->instructions.push_tail(dinst);
565 dinst->is_64bit_expanded = true;
566
567 /* modify the destination if we are splitting */
568 for (j = 0; j < 2; j++) {
569 if (dst_is_64bit[j]) {
570 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
571 dinst->dst[j].index = initial_dst_idx[j];
572 if (i > 1) {
573 if (dinst->op == TGSI_OPCODE_LOAD ||
574 dinst->op == TGSI_OPCODE_STORE)
575 dinst->src[0] = addr;
576 if (dinst->op != TGSI_OPCODE_STORE)
577 dinst->dst[j].index++;
578 }
579 } else {
580 /* if we aren't writing to a double, just get the bit of the
581 * initial writemask for this channel
582 */
583 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
584 }
585 }
586
587 /* modify the src registers */
588 for (j = 0; j < 4; j++) {
589 int swz = GET_SWZ(initial_src_swz[j], i);
590
591 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
592 dinst->src[j].index = initial_src_idx[j];
593 if (swz > 1) {
594 dinst->src[j].double_reg2 = true;
595 dinst->src[j].index++;
596 }
597
598 if (swz & 1)
599 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
600 SWIZZLE_Z, SWIZZLE_W);
601 else
602 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
603 SWIZZLE_X, SWIZZLE_Y);
604
605 } else {
606 /* some opcodes are special case in what they use as sources
607 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
608 * integer src1
609 */
610 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
611 op == TGSI_OPCODE_I2D ||
612 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
613 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
614 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
615 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
616 }
617 }
618 }
619 }
620 inst = dinst;
621 } else {
622 this->instructions.push_tail(inst);
623 }
624
625
626 return inst;
627 }
628
629 glsl_to_tgsi_instruction *
630 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
631 st_dst_reg dst,
632 st_src_reg src0, st_src_reg src1,
633 st_src_reg src2, st_src_reg src3)
634 {
635 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
636 }
637
638 /**
639 * Determines whether to use an integer, unsigned integer, or float opcode
640 * based on the operands and input opcode, then emits the result.
641 */
642 unsigned
643 glsl_to_tgsi_visitor::get_opcode(unsigned op,
644 st_dst_reg dst,
645 st_src_reg src0, st_src_reg src1)
646 {
647 enum glsl_base_type type = GLSL_TYPE_FLOAT;
648
649 if (op == TGSI_OPCODE_MOV)
650 return op;
651
652 assert(src0.type != GLSL_TYPE_ARRAY);
653 assert(src0.type != GLSL_TYPE_STRUCT);
654 assert(src1.type != GLSL_TYPE_ARRAY);
655 assert(src1.type != GLSL_TYPE_STRUCT);
656
657 if (is_resource_instruction(op))
658 type = src1.type;
659 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
660 type = GLSL_TYPE_INT64;
661 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
662 type = GLSL_TYPE_UINT64;
663 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
664 type = GLSL_TYPE_DOUBLE;
665 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
666 type = GLSL_TYPE_FLOAT;
667 else if (native_integers)
668 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
669
670 #define case7(c, f, i, u, d, i64, ui64) \
671 case TGSI_OPCODE_##c: \
672 if (type == GLSL_TYPE_UINT64) \
673 op = TGSI_OPCODE_##ui64; \
674 else if (type == GLSL_TYPE_INT64) \
675 op = TGSI_OPCODE_##i64; \
676 else if (type == GLSL_TYPE_DOUBLE) \
677 op = TGSI_OPCODE_##d; \
678 else if (type == GLSL_TYPE_INT) \
679 op = TGSI_OPCODE_##i; \
680 else if (type == GLSL_TYPE_UINT) \
681 op = TGSI_OPCODE_##u; \
682 else \
683 op = TGSI_OPCODE_##f; \
684 break;
685
686 #define casecomp(c, f, i, u, d, i64, ui64) \
687 case TGSI_OPCODE_##c: \
688 if (type == GLSL_TYPE_INT64) \
689 op = TGSI_OPCODE_##i64; \
690 else if (type == GLSL_TYPE_UINT64) \
691 op = TGSI_OPCODE_##ui64; \
692 else if (type == GLSL_TYPE_DOUBLE) \
693 op = TGSI_OPCODE_##d; \
694 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
695 op = TGSI_OPCODE_##i; \
696 else if (type == GLSL_TYPE_UINT) \
697 op = TGSI_OPCODE_##u; \
698 else if (native_integers) \
699 op = TGSI_OPCODE_##f; \
700 else \
701 op = TGSI_OPCODE_##c; \
702 break;
703
704 switch (op) {
705 /* Some instructions are initially selected without considering the type.
706 * This fixes the type:
707 *
708 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
709 */
710 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
711 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
712 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
713 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
714 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
715 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
716 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
717 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
718 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
719 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
720 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
721 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
722 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
723 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
724 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
725 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
726
727 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
728 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
729 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
730 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
731 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
732 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
733 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
734 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
735
736 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
737 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
738 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
739 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
740
741 default:
742 break;
743 }
744
745 assert(op != TGSI_OPCODE_LAST);
746 return op;
747 }
748
749 glsl_to_tgsi_instruction *
750 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
751 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
752 unsigned elements)
753 {
754 static const unsigned dot_opcodes[] = {
755 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
756 };
757
758 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
759 }
760
761 /**
762 * Emits TGSI scalar opcodes to produce unique answers across channels.
763 *
764 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
765 * channel determines the result across all channels. So to do a vec4
766 * of this operation, we want to emit a scalar per source channel used
767 * to produce dest channels.
768 */
769 void
770 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, unsigned op,
771 st_dst_reg dst,
772 st_src_reg orig_src0, st_src_reg orig_src1)
773 {
774 int i, j;
775 int done_mask = ~dst.writemask;
776
777 /* TGSI RCP is a scalar operation splatting results to all channels,
778 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
779 * dst channels.
780 */
781 for (i = 0; i < 4; i++) {
782 GLuint this_mask = (1 << i);
783 st_src_reg src0 = orig_src0;
784 st_src_reg src1 = orig_src1;
785
786 if (done_mask & this_mask)
787 continue;
788
789 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
790 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
791 for (j = i + 1; j < 4; j++) {
792 /* If there is another enabled component in the destination that is
793 * derived from the same inputs, generate its value on this pass as
794 * well.
795 */
796 if (!(done_mask & (1 << j)) &&
797 GET_SWZ(src0.swizzle, j) == src0_swiz &&
798 GET_SWZ(src1.swizzle, j) == src1_swiz) {
799 this_mask |= (1 << j);
800 }
801 }
802 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
803 src0_swiz, src0_swiz);
804 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
805 src1_swiz, src1_swiz);
806
807 dst.writemask = this_mask;
808 emit_asm(ir, op, dst, src0, src1);
809 done_mask |= this_mask;
810 }
811 }
812
813 void
814 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, unsigned op,
815 st_dst_reg dst, st_src_reg src0)
816 {
817 st_src_reg undef = undef_src;
818
819 undef.swizzle = SWIZZLE_XXXX;
820
821 emit_scalar(ir, op, dst, src0, undef);
822 }
823
824 void
825 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
826 st_dst_reg dst, st_src_reg src0)
827 {
828 int op = TGSI_OPCODE_ARL;
829
830 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
831 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
832 return;
833
834 op = TGSI_OPCODE_UARL;
835 }
836
837 assert(dst.file == PROGRAM_ADDRESS);
838 if (dst.index >= this->num_address_regs)
839 this->num_address_regs = dst.index + 1;
840
841 emit_asm(NULL, op, dst, src0);
842 }
843
844 int
845 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
846 gl_constant_value values[8], int size,
847 GLenum datatype,
848 uint16_t *swizzle_out)
849 {
850 if (file == PROGRAM_CONSTANT) {
851 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
852 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
853 values, size, datatype,
854 &swizzle);
855 if (swizzle_out)
856 *swizzle_out = swizzle;
857 return result;
858 }
859
860 assert(file == PROGRAM_IMMEDIATE);
861
862 int index = 0;
863 immediate_storage *entry;
864 int size32 = size * ((datatype == GL_DOUBLE ||
865 datatype == GL_INT64_ARB ||
866 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
867 int i;
868
869 /* Search immediate storage to see if we already have an identical
870 * immediate that we can use instead of adding a duplicate entry.
871 */
872 foreach_in_list(immediate_storage, entry, &this->immediates) {
873 immediate_storage *tmp = entry;
874
875 for (i = 0; i * 4 < size32; i++) {
876 int slot_size = MIN2(size32 - (i * 4), 4);
877 if (tmp->type != datatype || tmp->size32 != slot_size)
878 break;
879 if (memcmp(tmp->values, &values[i * 4],
880 slot_size * sizeof(gl_constant_value)))
881 break;
882
883 /* Everything matches, keep going until the full size is matched */
884 tmp = (immediate_storage *)tmp->next;
885 }
886
887 /* The full value matched */
888 if (i * 4 >= size32)
889 return index;
890
891 index++;
892 }
893
894 for (i = 0; i * 4 < size32; i++) {
895 int slot_size = MIN2(size32 - (i * 4), 4);
896 /* Add this immediate to the list. */
897 entry = new(mem_ctx) immediate_storage(&values[i * 4],
898 slot_size, datatype);
899 this->immediates.push_tail(entry);
900 this->num_immediates++;
901 }
902 return index;
903 }
904
905 st_src_reg
906 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
907 {
908 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
909 union gl_constant_value uval;
910
911 uval.f = val;
912 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
913
914 return src;
915 }
916
917 st_src_reg
918 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
919 {
920 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
921 union gl_constant_value uval[2];
922
923 memcpy(uval, &val, sizeof(uval));
924 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
925 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
926 return src;
927 }
928
929 st_src_reg
930 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
931 {
932 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
933 union gl_constant_value uval;
934
935 assert(native_integers);
936
937 uval.i = val;
938 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
939
940 return src;
941 }
942
943 st_src_reg
944 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
945 {
946 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
947 union gl_constant_value uval[2];
948
949 memcpy(uval, &val, sizeof(uval));
950 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
951 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
952
953 return src;
954 }
955
956 st_src_reg
957 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
958 {
959 if (native_integers)
960 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
961 st_src_reg_for_int(val);
962 else
963 return st_src_reg_for_float(val);
964 }
965
966 static int
967 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
968 {
969 return type->count_attribute_slots(is_vs_input);
970 }
971
972 static int
973 type_size(const struct glsl_type *type)
974 {
975 return type->count_attribute_slots(false);
976 }
977
978 static void
979 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
980 exec_list *instructions, ir_constant *access)
981 {
982 /**
983 * emit_asm() might have actually split the op into pieces, e.g. for
984 * double stores. We have to go back and fix up all the generated ops.
985 */
986 unsigned op = inst->op;
987 do {
988 inst->resource = *buf;
989 if (access)
990 inst->buffer_access = access->value.u[0];
991
992 if (inst == instructions->get_head_raw())
993 break;
994 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
995
996 if (inst->op == TGSI_OPCODE_UADD) {
997 if (inst == instructions->get_head_raw())
998 break;
999 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1000 }
1001 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1002 }
1003
1004 /**
1005 * If the given GLSL type is an array or matrix or a structure containing
1006 * an array/matrix member, return true. Else return false.
1007 *
1008 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1009 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1010 * we have an array that might be indexed with a variable, we need to use
1011 * the later storage type.
1012 */
1013 static bool
1014 type_has_array_or_matrix(const glsl_type *type)
1015 {
1016 if (type->is_array() || type->is_matrix())
1017 return true;
1018
1019 if (type->is_record()) {
1020 for (unsigned i = 0; i < type->length; i++) {
1021 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1022 return true;
1023 }
1024 }
1025 }
1026
1027 return false;
1028 }
1029
1030
1031 /**
1032 * In the initial pass of codegen, we assign temporary numbers to
1033 * intermediate results. (not SSA -- variable assignments will reuse
1034 * storage).
1035 */
1036 st_src_reg
1037 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1038 {
1039 st_src_reg src;
1040
1041 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1042 src.reladdr = NULL;
1043 src.negate = 0;
1044 src.abs = 0;
1045
1046 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1047 if (next_array >= max_num_arrays) {
1048 max_num_arrays += 32;
1049 array_sizes = (unsigned*)
1050 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1051 }
1052
1053 src.file = PROGRAM_ARRAY;
1054 src.index = 0;
1055 src.array_id = next_array + 1;
1056 array_sizes[next_array] = type_size(type);
1057 ++next_array;
1058
1059 } else {
1060 src.file = PROGRAM_TEMPORARY;
1061 src.index = next_temp;
1062 next_temp += type_size(type);
1063 }
1064
1065 if (type->is_array() || type->is_record()) {
1066 src.swizzle = SWIZZLE_NOOP;
1067 } else {
1068 src.swizzle = swizzle_for_size(type->vector_elements);
1069 }
1070
1071 return src;
1072 }
1073
1074 variable_storage *
1075 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1076 {
1077 struct hash_entry *entry;
1078
1079 entry = _mesa_hash_table_search(this->variables, var);
1080 if (!entry)
1081 return NULL;
1082
1083 return (variable_storage *)entry->data;
1084 }
1085
1086 void
1087 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1088 {
1089 if (strcmp(ir->name, "gl_FragCoord") == 0) {
1090 this->prog->OriginUpperLeft = ir->data.origin_upper_left;
1091 this->prog->PixelCenterInteger = ir->data.pixel_center_integer;
1092 }
1093
1094 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1095 unsigned int i;
1096 const ir_state_slot *const slots = ir->get_state_slots();
1097 assert(slots != NULL);
1098
1099 /* Check if this statevar's setup in the STATE file exactly
1100 * matches how we'll want to reference it as a
1101 * struct/array/whatever. If not, then we need to move it into
1102 * temporary storage and hope that it'll get copy-propagated
1103 * out.
1104 */
1105 for (i = 0; i < ir->get_num_state_slots(); i++) {
1106 if (slots[i].swizzle != SWIZZLE_XYZW) {
1107 break;
1108 }
1109 }
1110
1111 variable_storage *storage;
1112 st_dst_reg dst;
1113 if (i == ir->get_num_state_slots()) {
1114 /* We'll set the index later. */
1115 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1116
1117 _mesa_hash_table_insert(this->variables, ir, storage);
1118
1119 dst = undef_dst;
1120 } else {
1121 /* The variable_storage constructor allocates slots based on the size
1122 * of the type. However, this had better match the number of state
1123 * elements that we're going to copy into the new temporary.
1124 */
1125 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1126
1127 dst = st_dst_reg(get_temp(ir->type));
1128
1129 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1130 dst.array_id);
1131
1132 _mesa_hash_table_insert(this->variables, ir, storage);
1133 }
1134
1135
1136 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1137 int index = _mesa_add_state_reference(this->prog->Parameters,
1138 slots[i].tokens);
1139
1140 if (storage->file == PROGRAM_STATE_VAR) {
1141 if (storage->index == -1) {
1142 storage->index = index;
1143 } else {
1144 assert(index == storage->index + (int)i);
1145 }
1146 } else {
1147 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1148 * the data being moved since MOV does not care about the type of
1149 * data it is moving, and we don't want to declare registers with
1150 * array or struct types.
1151 */
1152 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1153 src.swizzle = slots[i].swizzle;
1154 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1155 /* even a float takes up a whole vec4 reg in a struct/array. */
1156 dst.index++;
1157 }
1158 }
1159
1160 if (storage->file == PROGRAM_TEMPORARY &&
1161 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1162 fail_link(this->shader_program,
1163 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1164 ir->name, dst.index - storage->index,
1165 type_size(ir->type));
1166 }
1167 }
1168 }
1169
1170 void
1171 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1172 {
1173 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1174
1175 visit_exec_list(&ir->body_instructions, this);
1176
1177 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1178 }
1179
1180 void
1181 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1182 {
1183 switch (ir->mode) {
1184 case ir_loop_jump::jump_break:
1185 emit_asm(NULL, TGSI_OPCODE_BRK);
1186 break;
1187 case ir_loop_jump::jump_continue:
1188 emit_asm(NULL, TGSI_OPCODE_CONT);
1189 break;
1190 }
1191 }
1192
1193
1194 void
1195 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1196 {
1197 assert(0);
1198 (void)ir;
1199 }
1200
1201 void
1202 glsl_to_tgsi_visitor::visit(ir_function *ir)
1203 {
1204 /* Ignore function bodies other than main() -- we shouldn't see calls to
1205 * them since they should all be inlined before we get to glsl_to_tgsi.
1206 */
1207 if (strcmp(ir->name, "main") == 0) {
1208 const ir_function_signature *sig;
1209 exec_list empty;
1210
1211 sig = ir->matching_signature(NULL, &empty, false);
1212
1213 assert(sig);
1214
1215 foreach_in_list(ir_instruction, ir, &sig->body) {
1216 ir->accept(this);
1217 }
1218 }
1219 }
1220
1221 bool
1222 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1223 {
1224 int nonmul_operand = 1 - mul_operand;
1225 st_src_reg a, b, c;
1226 st_dst_reg result_dst;
1227
1228 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1229 if (!expr || expr->operation != ir_binop_mul)
1230 return false;
1231
1232 expr->operands[0]->accept(this);
1233 a = this->result;
1234 expr->operands[1]->accept(this);
1235 b = this->result;
1236 ir->operands[nonmul_operand]->accept(this);
1237 c = this->result;
1238
1239 this->result = get_temp(ir->type);
1240 result_dst = st_dst_reg(this->result);
1241 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1242 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1243
1244 return true;
1245 }
1246
1247 /**
1248 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1249 *
1250 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1251 * implemented using multiplication, and logical-or is implemented using
1252 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1253 * As result, the logical expression (a & !b) can be rewritten as:
1254 *
1255 * - a * !b
1256 * - a * (1 - b)
1257 * - (a * 1) - (a * b)
1258 * - a + -(a * b)
1259 * - a + (a * -b)
1260 *
1261 * This final expression can be implemented as a single MAD(a, -b, a)
1262 * instruction.
1263 */
1264 bool
1265 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1266 int try_operand)
1267 {
1268 const int other_operand = 1 - try_operand;
1269 st_src_reg a, b;
1270
1271 ir_expression *expr = ir->operands[try_operand]->as_expression();
1272 if (!expr || expr->operation != ir_unop_logic_not)
1273 return false;
1274
1275 ir->operands[other_operand]->accept(this);
1276 a = this->result;
1277 expr->operands[0]->accept(this);
1278 b = this->result;
1279
1280 b.negate = ~b.negate;
1281
1282 this->result = get_temp(ir->type);
1283 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1284
1285 return true;
1286 }
1287
1288 void
1289 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1290 st_src_reg *reg, int *num_reladdr)
1291 {
1292 if (!reg->reladdr && !reg->reladdr2)
1293 return;
1294
1295 if (reg->reladdr)
1296 emit_arl(ir, address_reg, *reg->reladdr);
1297 if (reg->reladdr2)
1298 emit_arl(ir, address_reg2, *reg->reladdr2);
1299
1300 if (*num_reladdr != 1) {
1301 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1302
1303 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1304 *reg = temp;
1305 }
1306
1307 (*num_reladdr)--;
1308 }
1309
1310 void
1311 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1312 {
1313 st_src_reg op[ARRAY_SIZE(ir->operands)];
1314
1315 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1316 */
1317 if (!this->precise && ir->operation == ir_binop_add) {
1318 if (try_emit_mad(ir, 1))
1319 return;
1320 if (try_emit_mad(ir, 0))
1321 return;
1322 }
1323
1324 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1325 */
1326 if (!native_integers && ir->operation == ir_binop_logic_and) {
1327 if (try_emit_mad_for_and_not(ir, 1))
1328 return;
1329 if (try_emit_mad_for_and_not(ir, 0))
1330 return;
1331 }
1332
1333 if (ir->operation == ir_quadop_vector)
1334 assert(!"ir_quadop_vector should have been lowered");
1335
1336 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1337 this->result.file = PROGRAM_UNDEFINED;
1338 ir->operands[operand]->accept(this);
1339 if (this->result.file == PROGRAM_UNDEFINED) {
1340 printf("Failed to get tree for expression operand:\n");
1341 ir->operands[operand]->print();
1342 printf("\n");
1343 exit(1);
1344 }
1345 op[operand] = this->result;
1346
1347 /* Matrix expression operands should have been broken down to vector
1348 * operations already.
1349 */
1350 assert(!ir->operands[operand]->type->is_matrix());
1351 }
1352
1353 visit_expression(ir, op);
1354 }
1355
1356 /* The non-recursive part of the expression visitor lives in a separate
1357 * function and should be prevented from being inlined, to avoid a stack
1358 * explosion when deeply nested expressions are visited.
1359 */
1360 void
1361 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1362 {
1363 st_src_reg result_src;
1364 st_dst_reg result_dst;
1365
1366 int vector_elements = ir->operands[0]->type->vector_elements;
1367 if (ir->operands[1] &&
1368 ir->operation != ir_binop_interpolate_at_offset &&
1369 ir->operation != ir_binop_interpolate_at_sample) {
1370 st_src_reg *swz_op = NULL;
1371 if (vector_elements > ir->operands[1]->type->vector_elements) {
1372 assert(ir->operands[1]->type->vector_elements == 1);
1373 swz_op = &op[1];
1374 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1375 assert(ir->operands[0]->type->vector_elements == 1);
1376 swz_op = &op[0];
1377 }
1378 if (swz_op) {
1379 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1380 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1381 swizzle_x, swizzle_x);
1382 }
1383 vector_elements = MAX2(vector_elements,
1384 ir->operands[1]->type->vector_elements);
1385 }
1386 if (ir->operands[2] &&
1387 ir->operands[2]->type->vector_elements != vector_elements) {
1388 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1389 assert(ir->operands[2]->type->vector_elements == 1);
1390 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1391 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1392 swizzle_x, swizzle_x);
1393 }
1394
1395 this->result.file = PROGRAM_UNDEFINED;
1396
1397 /* Storage for our result. Ideally for an assignment we'd be using
1398 * the actual storage for the result here, instead.
1399 */
1400 result_src = get_temp(ir->type);
1401 /* convenience for the emit functions below. */
1402 result_dst = st_dst_reg(result_src);
1403 /* Limit writes to the channels that will be used by result_src later.
1404 * This does limit this temp's use as a temporary for multi-instruction
1405 * sequences.
1406 */
1407 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1408
1409 switch (ir->operation) {
1410 case ir_unop_logic_not:
1411 if (result_dst.type != GLSL_TYPE_FLOAT)
1412 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1413 else {
1414 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1415 * older GPUs implement SEQ using multiple instructions (i915 uses two
1416 * SGE instructions and a MUL instruction). Since our logic values are
1417 * 0.0 and 1.0, 1-x also implements !x.
1418 */
1419 op[0].negate = ~op[0].negate;
1420 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1421 st_src_reg_for_float(1.0));
1422 }
1423 break;
1424 case ir_unop_neg:
1425 if (result_dst.type == GLSL_TYPE_INT64 ||
1426 result_dst.type == GLSL_TYPE_UINT64)
1427 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1428 else if (result_dst.type == GLSL_TYPE_INT ||
1429 result_dst.type == GLSL_TYPE_UINT)
1430 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1431 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1432 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1433 else {
1434 op[0].negate = ~op[0].negate;
1435 result_src = op[0];
1436 }
1437 break;
1438 case ir_unop_subroutine_to_int:
1439 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1440 break;
1441 case ir_unop_abs:
1442 if (result_dst.type == GLSL_TYPE_FLOAT)
1443 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1444 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1445 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1446 else if (result_dst.type == GLSL_TYPE_INT64 ||
1447 result_dst.type == GLSL_TYPE_UINT64)
1448 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1449 else
1450 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1451 break;
1452 case ir_unop_sign:
1453 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1454 break;
1455 case ir_unop_rcp:
1456 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1457 break;
1458
1459 case ir_unop_exp2:
1460 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1461 break;
1462 case ir_unop_exp:
1463 assert(!"not reached: should be handled by exp_to_exp2");
1464 break;
1465 case ir_unop_log:
1466 assert(!"not reached: should be handled by log_to_log2");
1467 break;
1468 case ir_unop_log2:
1469 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1470 break;
1471 case ir_unop_sin:
1472 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1473 break;
1474 case ir_unop_cos:
1475 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1476 break;
1477 case ir_unop_saturate: {
1478 glsl_to_tgsi_instruction *inst;
1479 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1480 inst->saturate = true;
1481 break;
1482 }
1483
1484 case ir_unop_dFdx:
1485 case ir_unop_dFdx_coarse:
1486 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1487 break;
1488 case ir_unop_dFdx_fine:
1489 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1490 break;
1491 case ir_unop_dFdy:
1492 case ir_unop_dFdy_coarse:
1493 case ir_unop_dFdy_fine:
1494 {
1495 /* The X component contains 1 or -1 depending on whether the framebuffer
1496 * is a FBO or the window system buffer, respectively.
1497 * It is then multiplied with the source operand of DDY.
1498 */
1499 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1500 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1501
1502 unsigned transform_y_index =
1503 _mesa_add_state_reference(this->prog->Parameters,
1504 transform_y_state);
1505
1506 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1507 transform_y_index,
1508 glsl_type::vec4_type);
1509 transform_y.swizzle = SWIZZLE_XXXX;
1510
1511 st_src_reg temp = get_temp(glsl_type::vec4_type);
1512
1513 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1514 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1515 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1516 break;
1517 }
1518
1519 case ir_unop_frexp_sig:
1520 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1521 break;
1522
1523 case ir_unop_frexp_exp:
1524 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1525 break;
1526
1527 case ir_unop_noise: {
1528 /* At some point, a motivated person could add a better
1529 * implementation of noise. Currently not even the nvidia
1530 * binary drivers do anything more than this. In any case, the
1531 * place to do this is in the GL state tracker, not the poor
1532 * driver.
1533 */
1534 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
1535 break;
1536 }
1537
1538 case ir_binop_add:
1539 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1540 break;
1541 case ir_binop_sub:
1542 op[1].negate = ~op[1].negate;
1543 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1544 break;
1545
1546 case ir_binop_mul:
1547 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1548 break;
1549 case ir_binop_div:
1550 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1551 break;
1552 case ir_binop_mod:
1553 if (result_dst.type == GLSL_TYPE_FLOAT)
1554 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1555 else
1556 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1557 break;
1558
1559 case ir_binop_less:
1560 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1561 break;
1562 case ir_binop_gequal:
1563 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1564 break;
1565 case ir_binop_equal:
1566 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1567 break;
1568 case ir_binop_nequal:
1569 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1570 break;
1571 case ir_binop_all_equal:
1572 /* "==" operator producing a scalar boolean. */
1573 if (ir->operands[0]->type->is_vector() ||
1574 ir->operands[1]->type->is_vector()) {
1575 st_src_reg temp = get_temp(native_integers ?
1576 glsl_type::uvec4_type :
1577 glsl_type::vec4_type);
1578
1579 if (native_integers) {
1580 st_dst_reg temp_dst = st_dst_reg(temp);
1581 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1582
1583 if (ir->operands[0]->type->is_boolean() &&
1584 ir->operands[1]->as_constant() &&
1585 ir->operands[1]->as_constant()->is_one()) {
1586 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1587 } else {
1588 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1589 }
1590
1591 /* Emit 1-3 AND operations to combine the SEQ results. */
1592 switch (ir->operands[0]->type->vector_elements) {
1593 case 2:
1594 break;
1595 case 3:
1596 temp_dst.writemask = WRITEMASK_Y;
1597 temp1.swizzle = SWIZZLE_YYYY;
1598 temp2.swizzle = SWIZZLE_ZZZZ;
1599 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1600 break;
1601 case 4:
1602 temp_dst.writemask = WRITEMASK_X;
1603 temp1.swizzle = SWIZZLE_XXXX;
1604 temp2.swizzle = SWIZZLE_YYYY;
1605 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1606 temp_dst.writemask = WRITEMASK_Y;
1607 temp1.swizzle = SWIZZLE_ZZZZ;
1608 temp2.swizzle = SWIZZLE_WWWW;
1609 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1610 }
1611
1612 temp1.swizzle = SWIZZLE_XXXX;
1613 temp2.swizzle = SWIZZLE_YYYY;
1614 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1615 } else {
1616 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1617
1618 /* After the dot-product, the value will be an integer on the
1619 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1620 */
1621 emit_dp(ir, result_dst, temp, temp, vector_elements);
1622
1623 /* Negating the result of the dot-product gives values on the range
1624 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1625 * This is achieved using SGE.
1626 */
1627 st_src_reg sge_src = result_src;
1628 sge_src.negate = ~sge_src.negate;
1629 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1630 st_src_reg_for_float(0.0));
1631 }
1632 } else {
1633 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1634 }
1635 break;
1636 case ir_binop_any_nequal:
1637 /* "!=" operator producing a scalar boolean. */
1638 if (ir->operands[0]->type->is_vector() ||
1639 ir->operands[1]->type->is_vector()) {
1640 st_src_reg temp = get_temp(native_integers ?
1641 glsl_type::uvec4_type :
1642 glsl_type::vec4_type);
1643 if (ir->operands[0]->type->is_boolean() &&
1644 ir->operands[1]->as_constant() &&
1645 ir->operands[1]->as_constant()->is_zero()) {
1646 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1647 } else {
1648 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1649 }
1650
1651 if (native_integers) {
1652 st_dst_reg temp_dst = st_dst_reg(temp);
1653 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1654
1655 /* Emit 1-3 OR operations to combine the SNE results. */
1656 switch (ir->operands[0]->type->vector_elements) {
1657 case 2:
1658 break;
1659 case 3:
1660 temp_dst.writemask = WRITEMASK_Y;
1661 temp1.swizzle = SWIZZLE_YYYY;
1662 temp2.swizzle = SWIZZLE_ZZZZ;
1663 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1664 break;
1665 case 4:
1666 temp_dst.writemask = WRITEMASK_X;
1667 temp1.swizzle = SWIZZLE_XXXX;
1668 temp2.swizzle = SWIZZLE_YYYY;
1669 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1670 temp_dst.writemask = WRITEMASK_Y;
1671 temp1.swizzle = SWIZZLE_ZZZZ;
1672 temp2.swizzle = SWIZZLE_WWWW;
1673 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1674 }
1675
1676 temp1.swizzle = SWIZZLE_XXXX;
1677 temp2.swizzle = SWIZZLE_YYYY;
1678 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1679 } else {
1680 /* After the dot-product, the value will be an integer on the
1681 * range [0,4]. Zero stays zero, and positive values become 1.0.
1682 */
1683 glsl_to_tgsi_instruction *const dp =
1684 emit_dp(ir, result_dst, temp, temp, vector_elements);
1685 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1686 /* The clamping to [0,1] can be done for free in the fragment
1687 * shader with a saturate.
1688 */
1689 dp->saturate = true;
1690 } else {
1691 /* Negating the result of the dot-product gives values on the
1692 * range [-4, 0]. Zero stays zero, and negative values become
1693 * 1.0. This achieved using SLT.
1694 */
1695 st_src_reg slt_src = result_src;
1696 slt_src.negate = ~slt_src.negate;
1697 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1698 st_src_reg_for_float(0.0));
1699 }
1700 }
1701 } else {
1702 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1703 }
1704 break;
1705
1706 case ir_binop_logic_xor:
1707 if (native_integers)
1708 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1709 else
1710 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1711 break;
1712
1713 case ir_binop_logic_or: {
1714 if (native_integers) {
1715 /* If integers are used as booleans, we can use an actual "or"
1716 * instruction.
1717 */
1718 assert(native_integers);
1719 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1720 } else {
1721 /* After the addition, the value will be an integer on the
1722 * range [0,2]. Zero stays zero, and positive values become 1.0.
1723 */
1724 glsl_to_tgsi_instruction *add =
1725 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1726 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1727 /* The clamping to [0,1] can be done for free in the fragment
1728 * shader with a saturate if floats are being used as boolean
1729 * values.
1730 */
1731 add->saturate = true;
1732 } else {
1733 /* Negating the result of the addition gives values on the range
1734 * [-2, 0]. Zero stays zero, and negative values become 1.0
1735 * This is achieved using SLT.
1736 */
1737 st_src_reg slt_src = result_src;
1738 slt_src.negate = ~slt_src.negate;
1739 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1740 st_src_reg_for_float(0.0));
1741 }
1742 }
1743 break;
1744 }
1745
1746 case ir_binop_logic_and:
1747 /* If native integers are disabled, the bool args are stored as float 0.0
1748 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1749 * actual AND opcode.
1750 */
1751 if (native_integers)
1752 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1753 else
1754 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1755 break;
1756
1757 case ir_binop_dot:
1758 assert(ir->operands[0]->type->is_vector());
1759 assert(ir->operands[0]->type == ir->operands[1]->type);
1760 emit_dp(ir, result_dst, op[0], op[1],
1761 ir->operands[0]->type->vector_elements);
1762 break;
1763
1764 case ir_unop_sqrt:
1765 if (have_sqrt) {
1766 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1767 } else {
1768 /* This is the only instruction sequence that makes the game "Risen"
1769 * render correctly. ABS is not required for the game, but since GLSL
1770 * declares negative values as "undefined", allowing us to do whatever
1771 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1772 * behavior.
1773 */
1774 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1775 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1776 }
1777 break;
1778 case ir_unop_rsq:
1779 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1780 break;
1781 case ir_unop_i2f:
1782 if (native_integers) {
1783 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1784 break;
1785 }
1786 /* fallthrough to next case otherwise */
1787 case ir_unop_b2f:
1788 if (native_integers) {
1789 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1790 st_src_reg_for_float(1.0));
1791 break;
1792 }
1793 /* fallthrough to next case otherwise */
1794 case ir_unop_i2u:
1795 case ir_unop_u2i:
1796 case ir_unop_i642u64:
1797 case ir_unop_u642i64:
1798 /* Converting between signed and unsigned integers is a no-op. */
1799 result_src = op[0];
1800 result_src.type = result_dst.type;
1801 break;
1802 case ir_unop_b2i:
1803 if (native_integers) {
1804 /* Booleans are stored as integers using ~0 for true and 0 for false.
1805 * GLSL requires that int(bool) return 1 for true and 0 for false.
1806 * This conversion is done with AND, but it could be done with NEG.
1807 */
1808 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1809 st_src_reg_for_int(1));
1810 } else {
1811 /* Booleans and integers are both stored as floats when native
1812 * integers are disabled.
1813 */
1814 result_src = op[0];
1815 }
1816 break;
1817 case ir_unop_f2i:
1818 if (native_integers)
1819 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1820 else
1821 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1822 break;
1823 case ir_unop_f2u:
1824 if (native_integers)
1825 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1826 else
1827 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1828 break;
1829 case ir_unop_bitcast_f2i:
1830 case ir_unop_bitcast_f2u:
1831 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1832 if (op[0].negate || op[0].abs)
1833 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1834 else
1835 result_src = op[0];
1836 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1837 GLSL_TYPE_UINT;
1838 break;
1839 case ir_unop_bitcast_i2f:
1840 case ir_unop_bitcast_u2f:
1841 result_src = op[0];
1842 result_src.type = GLSL_TYPE_FLOAT;
1843 break;
1844 case ir_unop_f2b:
1845 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1846 st_src_reg_for_float(0.0));
1847 break;
1848 case ir_unop_d2b:
1849 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1850 st_src_reg_for_double(0.0));
1851 break;
1852 case ir_unop_i2b:
1853 if (native_integers)
1854 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1855 st_src_reg_for_int(0));
1856 else
1857 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1858 st_src_reg_for_float(0.0));
1859 break;
1860 case ir_unop_bitcast_u642d:
1861 case ir_unop_bitcast_i642d:
1862 result_src = op[0];
1863 result_src.type = GLSL_TYPE_DOUBLE;
1864 break;
1865 case ir_unop_bitcast_d2i64:
1866 result_src = op[0];
1867 result_src.type = GLSL_TYPE_INT64;
1868 break;
1869 case ir_unop_bitcast_d2u64:
1870 result_src = op[0];
1871 result_src.type = GLSL_TYPE_UINT64;
1872 break;
1873 case ir_unop_trunc:
1874 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1875 break;
1876 case ir_unop_ceil:
1877 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1878 break;
1879 case ir_unop_floor:
1880 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1881 break;
1882 case ir_unop_round_even:
1883 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1884 break;
1885 case ir_unop_fract:
1886 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1887 break;
1888
1889 case ir_binop_min:
1890 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1891 break;
1892 case ir_binop_max:
1893 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1894 break;
1895 case ir_binop_pow:
1896 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1897 break;
1898
1899 case ir_unop_bit_not:
1900 if (native_integers) {
1901 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1902 break;
1903 }
1904 case ir_unop_u2f:
1905 if (native_integers) {
1906 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1907 break;
1908 }
1909 case ir_binop_lshift:
1910 case ir_binop_rshift:
1911 if (native_integers) {
1912 unsigned opcode = ir->operation == ir_binop_lshift ? TGSI_OPCODE_SHL
1913 : TGSI_OPCODE_ISHR;
1914 st_src_reg count;
1915
1916 if (glsl_base_type_is_64bit(op[0].type)) {
1917 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1918 * 64 bits.
1919 */
1920 count = get_temp(glsl_type::u64vec(ir->operands[1]
1921 ->type->components()));
1922 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1923 } else {
1924 count = op[1];
1925 }
1926
1927 emit_asm(ir, opcode, result_dst, op[0], count);
1928 break;
1929 }
1930 case ir_binop_bit_and:
1931 if (native_integers) {
1932 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1933 break;
1934 }
1935 case ir_binop_bit_xor:
1936 if (native_integers) {
1937 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1938 break;
1939 }
1940 case ir_binop_bit_or:
1941 if (native_integers) {
1942 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1943 break;
1944 }
1945
1946 assert(!"GLSL 1.30 features unsupported");
1947 break;
1948
1949 case ir_binop_ubo_load: {
1950 if (ctx->Const.UseSTD430AsDefaultPacking) {
1951 ir_rvalue *block = ir->operands[0];
1952 ir_rvalue *offset = ir->operands[1];
1953 ir_constant *const_block = block->as_constant();
1954
1955 st_src_reg cbuf(PROGRAM_CONSTANT,
1956 (const_block ? const_block->value.u[0] + 1 : 1),
1957 ir->type->base_type);
1958
1959 cbuf.has_index2 = true;
1960
1961 if (!const_block) {
1962 block->accept(this);
1963 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
1964 *cbuf.reladdr = this->result;
1965 emit_arl(ir, sampler_reladdr, this->result);
1966 }
1967
1968 /* Calculate the surface offset */
1969 offset->accept(this);
1970 st_src_reg off = this->result;
1971
1972 glsl_to_tgsi_instruction *inst =
1973 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
1974
1975 if (result_dst.type == GLSL_TYPE_BOOL)
1976 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
1977 st_src_reg_for_int(0));
1978
1979 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
1980 NULL);
1981 } else {
1982 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
1983 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
1984 unsigned const_offset = const_offset_ir ?
1985 const_offset_ir->value.u[0] : 0;
1986 unsigned const_block = const_uniform_block ?
1987 const_uniform_block->value.u[0] + 1 : 1;
1988 st_src_reg index_reg = get_temp(glsl_type::uint_type);
1989 st_src_reg cbuf;
1990
1991 cbuf.type = ir->type->base_type;
1992 cbuf.file = PROGRAM_CONSTANT;
1993 cbuf.index = 0;
1994 cbuf.reladdr = NULL;
1995 cbuf.negate = 0;
1996 cbuf.abs = 0;
1997 cbuf.index2D = const_block;
1998
1999 assert(ir->type->is_vector() || ir->type->is_scalar());
2000
2001 if (const_offset_ir) {
2002 /* Constant index into constant buffer */
2003 cbuf.reladdr = NULL;
2004 cbuf.index = const_offset / 16;
2005 } else {
2006 ir_expression *offset_expr = ir->operands[1]->as_expression();
2007 st_src_reg offset = op[1];
2008
2009 /* The OpenGL spec is written in such a way that accesses with
2010 * non-constant offset are almost always vec4-aligned. The only
2011 * exception to this are members of structs in arrays of structs:
2012 * each struct in an array of structs is at least vec4-aligned,
2013 * but single-element and [ui]vec2 members of the struct may be at
2014 * an offset that is not a multiple of 16 bytes.
2015 *
2016 * Here, we extract that offset, relying on previous passes to
2017 * always generate offset expressions of the form
2018 * (+ expr constant_offset).
2019 *
2020 * Note that the std430 layout, which allows more cases of
2021 * alignment less than vec4 in arrays, is not supported for
2022 * uniform blocks, so we do not have to deal with it here.
2023 */
2024 if (offset_expr && offset_expr->operation == ir_binop_add) {
2025 const_offset_ir = offset_expr->operands[1]->as_constant();
2026 if (const_offset_ir) {
2027 const_offset = const_offset_ir->value.u[0];
2028 cbuf.index = const_offset / 16;
2029 offset_expr->operands[0]->accept(this);
2030 offset = this->result;
2031 }
2032 }
2033
2034 /* Relative/variable index into constant buffer */
2035 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2036 st_src_reg_for_int(4));
2037 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2038 memcpy(cbuf.reladdr, &index_reg, sizeof(index_reg));
2039 }
2040
2041 if (const_uniform_block) {
2042 /* Constant constant buffer */
2043 cbuf.reladdr2 = NULL;
2044 } else {
2045 /* Relative/variable constant buffer */
2046 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2047 memcpy(cbuf.reladdr2, &op[0], sizeof(st_src_reg));
2048 }
2049 cbuf.has_index2 = true;
2050
2051 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2052 if (glsl_base_type_is_64bit(cbuf.type))
2053 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2054 const_offset % 16 / 8,
2055 const_offset % 16 / 8,
2056 const_offset % 16 / 8);
2057 else
2058 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2059 const_offset % 16 / 4,
2060 const_offset % 16 / 4,
2061 const_offset % 16 / 4);
2062
2063 if (ir->type->is_boolean()) {
2064 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2065 st_src_reg_for_int(0));
2066 } else {
2067 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2068 }
2069 }
2070 break;
2071 }
2072 case ir_triop_lrp:
2073 /* note: we have to reorder the three args here */
2074 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2075 break;
2076 case ir_triop_csel:
2077 if (this->ctx->Const.NativeIntegers)
2078 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2079 else {
2080 op[0].negate = ~op[0].negate;
2081 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2082 }
2083 break;
2084 case ir_triop_bitfield_extract:
2085 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2086 break;
2087 case ir_quadop_bitfield_insert:
2088 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2089 break;
2090 case ir_unop_bitfield_reverse:
2091 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2092 break;
2093 case ir_unop_bit_count:
2094 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2095 break;
2096 case ir_unop_find_msb:
2097 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2098 break;
2099 case ir_unop_find_lsb:
2100 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2101 break;
2102 case ir_binop_imul_high:
2103 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2104 break;
2105 case ir_triop_fma:
2106 /* In theory, MAD is incorrect here. */
2107 if (have_fma)
2108 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2109 else
2110 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2111 break;
2112 case ir_unop_interpolate_at_centroid:
2113 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2114 break;
2115 case ir_binop_interpolate_at_offset: {
2116 /* The y coordinate needs to be flipped for the default fb */
2117 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2118 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2119
2120 unsigned transform_y_index =
2121 _mesa_add_state_reference(this->prog->Parameters,
2122 transform_y_state);
2123
2124 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2125 transform_y_index,
2126 glsl_type::vec4_type);
2127 transform_y.swizzle = SWIZZLE_XXXX;
2128
2129 st_src_reg temp = get_temp(glsl_type::vec2_type);
2130 st_dst_reg temp_dst = st_dst_reg(temp);
2131
2132 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2133 temp_dst.writemask = WRITEMASK_Y;
2134 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2135 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2136 break;
2137 }
2138 case ir_binop_interpolate_at_sample:
2139 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2140 break;
2141
2142 case ir_unop_d2f:
2143 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2144 break;
2145 case ir_unop_f2d:
2146 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2147 break;
2148 case ir_unop_d2i:
2149 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2150 break;
2151 case ir_unop_i2d:
2152 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2153 break;
2154 case ir_unop_d2u:
2155 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2156 break;
2157 case ir_unop_u2d:
2158 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2159 break;
2160 case ir_unop_unpack_double_2x32:
2161 case ir_unop_pack_double_2x32:
2162 case ir_unop_unpack_int_2x32:
2163 case ir_unop_pack_int_2x32:
2164 case ir_unop_unpack_uint_2x32:
2165 case ir_unop_pack_uint_2x32:
2166 case ir_unop_unpack_sampler_2x32:
2167 case ir_unop_pack_sampler_2x32:
2168 case ir_unop_unpack_image_2x32:
2169 case ir_unop_pack_image_2x32:
2170 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2171 break;
2172
2173 case ir_binop_ldexp:
2174 if (ir->operands[0]->type->is_double()) {
2175 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2176 } else if (ir->operands[0]->type->is_float()) {
2177 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2178 } else {
2179 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2180 }
2181 break;
2182
2183 case ir_unop_pack_half_2x16:
2184 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2185 break;
2186 case ir_unop_unpack_half_2x16:
2187 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2188 break;
2189
2190 case ir_unop_get_buffer_size: {
2191 ir_constant *const_offset = ir->operands[0]->as_constant();
2192 int buf_base = ctx->st->has_hw_atomics
2193 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
2194 st_src_reg buffer(
2195 PROGRAM_BUFFER,
2196 buf_base + (const_offset ? const_offset->value.u[0] : 0),
2197 GLSL_TYPE_UINT);
2198 if (!const_offset) {
2199 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2200 *buffer.reladdr = op[0];
2201 emit_arl(ir, sampler_reladdr, op[0]);
2202 }
2203 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2204 break;
2205 }
2206
2207 case ir_unop_u2i64:
2208 case ir_unop_u2u64:
2209 case ir_unop_b2i64: {
2210 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2211 st_dst_reg temp_dst = st_dst_reg(temp);
2212 unsigned orig_swz = op[0].swizzle;
2213 /*
2214 * To convert unsigned to 64-bit:
2215 * zero Y channel, copy X channel.
2216 */
2217 temp_dst.writemask = WRITEMASK_Y;
2218 if (vector_elements > 1)
2219 temp_dst.writemask |= WRITEMASK_W;
2220 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2221 temp_dst.writemask = WRITEMASK_X;
2222 if (vector_elements > 1)
2223 temp_dst.writemask |= WRITEMASK_Z;
2224 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2225 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2226 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2227 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2228 else
2229 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2230 result_src = temp;
2231 result_src.type = GLSL_TYPE_UINT64;
2232 if (vector_elements > 2) {
2233 /* Subtle: We rely on the fact that get_temp here returns the next
2234 * TGSI temporary register directly after the temp register used for
2235 * the first two components, so that the result gets picked up
2236 * automatically.
2237 */
2238 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2239 st_dst_reg temp_dst = st_dst_reg(temp);
2240 temp_dst.writemask = WRITEMASK_Y;
2241 if (vector_elements > 3)
2242 temp_dst.writemask |= WRITEMASK_W;
2243 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2244
2245 temp_dst.writemask = WRITEMASK_X;
2246 if (vector_elements > 3)
2247 temp_dst.writemask |= WRITEMASK_Z;
2248 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2249 GET_SWZ(orig_swz, 2),
2250 GET_SWZ(orig_swz, 3),
2251 GET_SWZ(orig_swz, 3));
2252 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2253 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2254 else
2255 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2256 st_src_reg_for_int(1));
2257 }
2258 break;
2259 }
2260 case ir_unop_i642i:
2261 case ir_unop_u642i:
2262 case ir_unop_u642u:
2263 case ir_unop_i642u: {
2264 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2265 st_dst_reg temp_dst = st_dst_reg(temp);
2266 unsigned orig_swz = op[0].swizzle;
2267 unsigned orig_idx = op[0].index;
2268 int el;
2269 temp_dst.writemask = WRITEMASK_X;
2270
2271 for (el = 0; el < vector_elements; el++) {
2272 unsigned swz = GET_SWZ(orig_swz, el);
2273 if (swz & 1)
2274 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2275 SWIZZLE_Z, SWIZZLE_Z);
2276 else
2277 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2278 SWIZZLE_X, SWIZZLE_X);
2279 if (swz > 2)
2280 op[0].index = orig_idx + 1;
2281 op[0].type = GLSL_TYPE_UINT;
2282 temp_dst.writemask = WRITEMASK_X << el;
2283 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2284 }
2285 result_src = temp;
2286 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2287 result_src.type = GLSL_TYPE_UINT;
2288 else
2289 result_src.type = GLSL_TYPE_INT;
2290 break;
2291 }
2292 case ir_unop_i642b:
2293 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2294 st_src_reg_for_int64(0));
2295 break;
2296 case ir_unop_i642f:
2297 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2298 break;
2299 case ir_unop_u642f:
2300 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2301 break;
2302 case ir_unop_i642d:
2303 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2304 break;
2305 case ir_unop_u642d:
2306 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2307 break;
2308 case ir_unop_i2i64:
2309 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2310 break;
2311 case ir_unop_f2i64:
2312 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2313 break;
2314 case ir_unop_d2i64:
2315 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2316 break;
2317 case ir_unop_i2u64:
2318 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2319 break;
2320 case ir_unop_f2u64:
2321 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2322 break;
2323 case ir_unop_d2u64:
2324 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2325 break;
2326 /* these might be needed */
2327 case ir_unop_pack_snorm_2x16:
2328 case ir_unop_pack_unorm_2x16:
2329 case ir_unop_pack_snorm_4x8:
2330 case ir_unop_pack_unorm_4x8:
2331
2332 case ir_unop_unpack_snorm_2x16:
2333 case ir_unop_unpack_unorm_2x16:
2334 case ir_unop_unpack_snorm_4x8:
2335 case ir_unop_unpack_unorm_4x8:
2336
2337 case ir_quadop_vector:
2338 case ir_binop_vector_extract:
2339 case ir_triop_vector_insert:
2340 case ir_binop_carry:
2341 case ir_binop_borrow:
2342 case ir_unop_ssbo_unsized_array_length:
2343 /* This operation is not supported, or should have already been handled.
2344 */
2345 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2346 break;
2347 }
2348
2349 this->result = result_src;
2350 }
2351
2352
2353 void
2354 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2355 {
2356 st_src_reg src;
2357 int i;
2358 int swizzle[4];
2359
2360 /* Note that this is only swizzles in expressions, not those on the left
2361 * hand side of an assignment, which do write masking. See ir_assignment
2362 * for that.
2363 */
2364
2365 ir->val->accept(this);
2366 src = this->result;
2367 assert(src.file != PROGRAM_UNDEFINED);
2368 assert(ir->type->vector_elements > 0);
2369
2370 for (i = 0; i < 4; i++) {
2371 if (i < ir->type->vector_elements) {
2372 switch (i) {
2373 case 0:
2374 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2375 break;
2376 case 1:
2377 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2378 break;
2379 case 2:
2380 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2381 break;
2382 case 3:
2383 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2384 break;
2385 }
2386 } else {
2387 /* If the type is smaller than a vec4, replicate the last
2388 * channel out.
2389 */
2390 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2391 }
2392 }
2393
2394 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2395
2396 this->result = src;
2397 }
2398
2399 /* Test if the variable is an array. Note that geometry and
2400 * tessellation shader inputs are outputs are always arrays (except
2401 * for patch inputs), so only the array element type is considered.
2402 */
2403 static bool
2404 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2405 {
2406 const glsl_type *type = var->type;
2407
2408 *remove_array = false;
2409
2410 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2411 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2412 return false;
2413
2414 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2415 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2416 stage == MESA_SHADER_TESS_CTRL) &&
2417 !var->data.patch) {
2418 if (!var->type->is_array())
2419 return false; /* a system value probably */
2420
2421 type = var->type->fields.array;
2422 *remove_array = true;
2423 }
2424
2425 return type->is_array() || type->is_matrix();
2426 }
2427
2428 static unsigned
2429 st_translate_interp_loc(ir_variable *var)
2430 {
2431 if (var->data.centroid)
2432 return TGSI_INTERPOLATE_LOC_CENTROID;
2433 else if (var->data.sample)
2434 return TGSI_INTERPOLATE_LOC_SAMPLE;
2435 else
2436 return TGSI_INTERPOLATE_LOC_CENTER;
2437 }
2438
2439 void
2440 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2441 {
2442 variable_storage *entry = find_variable_storage(ir->var);
2443 ir_variable *var = ir->var;
2444 bool remove_array;
2445
2446 if (!entry) {
2447 switch (var->data.mode) {
2448 case ir_var_uniform:
2449 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2450 var->data.param_index);
2451 _mesa_hash_table_insert(this->variables, var, entry);
2452 break;
2453 case ir_var_shader_in: {
2454 /* The linker assigns locations for varyings and attributes,
2455 * including deprecated builtins (like gl_Color), user-assign
2456 * generic attributes (glBindVertexLocation), and
2457 * user-defined varyings.
2458 */
2459 assert(var->data.location != -1);
2460
2461 const glsl_type *type_without_array = var->type->without_array();
2462 struct inout_decl *decl = &inputs[num_inputs];
2463 unsigned component = var->data.location_frac;
2464 unsigned num_components;
2465 num_inputs++;
2466
2467 if (type_without_array->is_64bit())
2468 component = component / 2;
2469 if (type_without_array->vector_elements)
2470 num_components = type_without_array->vector_elements;
2471 else
2472 num_components = 4;
2473
2474 decl->mesa_index = var->data.location;
2475 decl->interp = (glsl_interp_mode) var->data.interpolation;
2476 decl->interp_loc = st_translate_interp_loc(var);
2477 decl->base_type = type_without_array->base_type;
2478 decl->usage_mask = u_bit_consecutive(component, num_components);
2479
2480 if (is_inout_array(shader->Stage, var, &remove_array)) {
2481 decl->array_id = num_input_arrays + 1;
2482 num_input_arrays++;
2483 } else {
2484 decl->array_id = 0;
2485 }
2486
2487 if (remove_array)
2488 decl->size = type_size(var->type->fields.array);
2489 else
2490 decl->size = type_size(var->type);
2491
2492 entry = new(mem_ctx) variable_storage(var,
2493 PROGRAM_INPUT,
2494 decl->mesa_index,
2495 decl->array_id);
2496 entry->component = component;
2497
2498 _mesa_hash_table_insert(this->variables, var, entry);
2499
2500 break;
2501 }
2502 case ir_var_shader_out: {
2503 assert(var->data.location != -1);
2504
2505 const glsl_type *type_without_array = var->type->without_array();
2506 struct inout_decl *decl = &outputs[num_outputs];
2507 unsigned component = var->data.location_frac;
2508 unsigned num_components;
2509 num_outputs++;
2510
2511 if (type_without_array->is_64bit())
2512 component = component / 2;
2513 if (type_without_array->vector_elements)
2514 num_components = type_without_array->vector_elements;
2515 else
2516 num_components = 4;
2517
2518 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2519 decl->base_type = type_without_array->base_type;
2520 decl->usage_mask = u_bit_consecutive(component, num_components);
2521 if (var->data.stream & (1u << 31)) {
2522 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2523 } else {
2524 assert(var->data.stream < 4);
2525 decl->gs_out_streams = 0;
2526 for (unsigned i = 0; i < num_components; ++i)
2527 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2528 }
2529
2530 if (is_inout_array(shader->Stage, var, &remove_array)) {
2531 decl->array_id = num_output_arrays + 1;
2532 num_output_arrays++;
2533 } else {
2534 decl->array_id = 0;
2535 }
2536
2537 if (remove_array)
2538 decl->size = type_size(var->type->fields.array);
2539 else
2540 decl->size = type_size(var->type);
2541
2542 if (var->data.fb_fetch_output) {
2543 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2544 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2545 var->type, component, decl->array_id);
2546 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2547 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2548 dst.array_id);
2549 } else {
2550 entry = new(mem_ctx) variable_storage(var,
2551 PROGRAM_OUTPUT,
2552 decl->mesa_index,
2553 decl->array_id);
2554 }
2555 entry->component = component;
2556
2557 _mesa_hash_table_insert(this->variables, var, entry);
2558
2559 break;
2560 }
2561 case ir_var_system_value:
2562 entry = new(mem_ctx) variable_storage(var,
2563 PROGRAM_SYSTEM_VALUE,
2564 var->data.location);
2565 break;
2566 case ir_var_auto:
2567 case ir_var_temporary:
2568 st_src_reg src = get_temp(var->type);
2569
2570 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2571 src.array_id);
2572 _mesa_hash_table_insert(this->variables, var, entry);
2573
2574 break;
2575 }
2576
2577 if (!entry) {
2578 printf("Failed to make storage for %s\n", var->name);
2579 exit(1);
2580 }
2581 }
2582
2583 this->result = st_src_reg(entry->file, entry->index, var->type,
2584 entry->component, entry->array_id);
2585 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2586 var->data.mode == ir_var_shader_in &&
2587 var->type->without_array()->is_double())
2588 this->result.is_double_vertex_input = true;
2589 if (!native_integers)
2590 this->result.type = GLSL_TYPE_FLOAT;
2591 }
2592
2593 static void
2594 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2595 GLbitfield64* usage_mask,
2596 GLbitfield64 double_usage_mask,
2597 GLbitfield* patch_usage_mask)
2598 {
2599 unsigned i;
2600 int j;
2601
2602 /* Fix array declarations by removing unused array elements at both ends
2603 * of the arrays. For example, mat4[3] where only mat[1] is used.
2604 */
2605 for (i = 0; i < count; i++) {
2606 struct inout_decl *decl = &decls[i];
2607 if (!decl->array_id)
2608 continue;
2609
2610 /* Shrink the beginning. */
2611 for (j = 0; j < (int)decl->size; j++) {
2612 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2613 if (*patch_usage_mask &
2614 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2615 break;
2616 }
2617 else {
2618 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2619 break;
2620 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2621 break;
2622 }
2623
2624 decl->mesa_index++;
2625 decl->size--;
2626 j--;
2627 }
2628
2629 /* Shrink the end. */
2630 for (j = decl->size-1; j >= 0; j--) {
2631 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2632 if (*patch_usage_mask &
2633 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2634 break;
2635 }
2636 else {
2637 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2638 break;
2639 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2640 break;
2641 }
2642
2643 decl->size--;
2644 }
2645
2646 /* When not all entries of an array are accessed, we mark them as used
2647 * here anyway, to ensure that the input/output mapping logic doesn't get
2648 * confused.
2649 *
2650 * TODO This happens when an array isn't used via indirect access, which
2651 * some game ports do (at least eON-based). There is an optimization
2652 * opportunity here by replacing the array declaration with non-array
2653 * declarations of those slots that are actually used.
2654 */
2655 for (j = 1; j < (int)decl->size; ++j) {
2656 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2657 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2658 else
2659 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2660 }
2661 }
2662 }
2663
2664 void
2665 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2666 {
2667 ir_constant *index;
2668 st_src_reg src;
2669 bool is_2D = false;
2670 ir_variable *var = ir->variable_referenced();
2671
2672 /* We only need the logic provided by st_glsl_storage_type_size()
2673 * for arrays of structs. Indirect sampler and image indexing is handled
2674 * elsewhere.
2675 */
2676 int element_size = ir->type->without_array()->is_record() ?
2677 st_glsl_storage_type_size(ir->type, var->data.bindless) :
2678 type_size(ir->type);
2679
2680 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2681
2682 ir->array->accept(this);
2683 src = this->result;
2684
2685 if (!src.has_index2) {
2686 switch (this->prog->Target) {
2687 case GL_TESS_CONTROL_PROGRAM_NV:
2688 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2689 !ir->variable_referenced()->data.patch;
2690 break;
2691 case GL_TESS_EVALUATION_PROGRAM_NV:
2692 is_2D = src.file == PROGRAM_INPUT &&
2693 !ir->variable_referenced()->data.patch;
2694 break;
2695 case GL_GEOMETRY_PROGRAM_NV:
2696 is_2D = src.file == PROGRAM_INPUT;
2697 break;
2698 }
2699 }
2700
2701 if (is_2D)
2702 element_size = 1;
2703
2704 if (index) {
2705
2706 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2707 src.file == PROGRAM_INPUT)
2708 element_size = attrib_type_size(ir->type, true);
2709 if (is_2D) {
2710 src.index2D = index->value.i[0];
2711 src.has_index2 = true;
2712 } else
2713 src.index += index->value.i[0] * element_size;
2714 } else {
2715 /* Variable index array dereference. It eats the "vec4" of the
2716 * base of the array and an index that offsets the TGSI register
2717 * index.
2718 */
2719 ir->array_index->accept(this);
2720
2721 st_src_reg index_reg;
2722
2723 if (element_size == 1) {
2724 index_reg = this->result;
2725 } else {
2726 index_reg = get_temp(native_integers ?
2727 glsl_type::int_type : glsl_type::float_type);
2728
2729 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2730 this->result, st_src_reg_for_type(index_reg.type, element_size));
2731 }
2732
2733 /* If there was already a relative address register involved, add the
2734 * new and the old together to get the new offset.
2735 */
2736 if (!is_2D && src.reladdr != NULL) {
2737 st_src_reg accum_reg = get_temp(native_integers ?
2738 glsl_type::int_type : glsl_type::float_type);
2739
2740 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2741 index_reg, *src.reladdr);
2742
2743 index_reg = accum_reg;
2744 }
2745
2746 if (is_2D) {
2747 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2748 memcpy(src.reladdr2, &index_reg, sizeof(index_reg));
2749 src.index2D = 0;
2750 src.has_index2 = true;
2751 } else {
2752 src.reladdr = ralloc(mem_ctx, st_src_reg);
2753 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
2754 }
2755 }
2756
2757 /* Change the register type to the element type of the array. */
2758 src.type = ir->type->base_type;
2759
2760 this->result = src;
2761 }
2762
2763 void
2764 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2765 {
2766 unsigned int i;
2767 const glsl_type *struct_type = ir->record->type;
2768 ir_variable *var = ir->record->variable_referenced();
2769 int offset = 0;
2770
2771 ir->record->accept(this);
2772
2773 assert(ir->field_idx >= 0);
2774 assert(var);
2775 for (i = 0; i < struct_type->length; i++) {
2776 if (i == (unsigned) ir->field_idx)
2777 break;
2778 const glsl_type *member_type = struct_type->fields.structure[i].type;
2779 offset += st_glsl_storage_type_size(member_type, var->data.bindless);
2780 }
2781
2782 /* If the type is smaller than a vec4, replicate the last channel out. */
2783 if (ir->type->is_scalar() || ir->type->is_vector())
2784 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2785 else
2786 this->result.swizzle = SWIZZLE_NOOP;
2787
2788 this->result.index += offset;
2789 this->result.type = ir->type->base_type;
2790 }
2791
2792 /**
2793 * We want to be careful in assignment setup to hit the actual storage
2794 * instead of potentially using a temporary like we might with the
2795 * ir_dereference handler.
2796 */
2797 static st_dst_reg
2798 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2799 {
2800 /* The LHS must be a dereference. If the LHS is a variable indexed array
2801 * access of a vector, it must be separated into a series conditional moves
2802 * before reaching this point (see ir_vec_index_to_cond_assign).
2803 */
2804 assert(ir->as_dereference());
2805 ir_dereference_array *deref_array = ir->as_dereference_array();
2806 if (deref_array) {
2807 assert(!deref_array->array->type->is_vector());
2808 }
2809
2810 /* Use the rvalue deref handler for the most part. We write swizzles using
2811 * the writemask, but we do extract the base component for enhanced layouts
2812 * from the source swizzle.
2813 */
2814 ir->accept(v);
2815 *component = GET_SWZ(v->result.swizzle, 0);
2816 return st_dst_reg(v->result);
2817 }
2818
2819 /**
2820 * Process the condition of a conditional assignment
2821 *
2822 * Examines the condition of a conditional assignment to generate the optimal
2823 * first operand of a \c CMP instruction. If the condition is a relational
2824 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2825 * used as the source for the \c CMP instruction. Otherwise the comparison
2826 * is processed to a boolean result, and the boolean result is used as the
2827 * operand to the CMP instruction.
2828 */
2829 bool
2830 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2831 {
2832 ir_rvalue *src_ir = ir;
2833 bool negate = true;
2834 bool switch_order = false;
2835
2836 ir_expression *const expr = ir->as_expression();
2837
2838 if (native_integers) {
2839 if ((expr != NULL) && (expr->num_operands == 2)) {
2840 enum glsl_base_type type = expr->operands[0]->type->base_type;
2841 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2842 type == GLSL_TYPE_BOOL) {
2843 if (expr->operation == ir_binop_equal) {
2844 if (expr->operands[0]->is_zero()) {
2845 src_ir = expr->operands[1];
2846 switch_order = true;
2847 }
2848 else if (expr->operands[1]->is_zero()) {
2849 src_ir = expr->operands[0];
2850 switch_order = true;
2851 }
2852 }
2853 else if (expr->operation == ir_binop_nequal) {
2854 if (expr->operands[0]->is_zero()) {
2855 src_ir = expr->operands[1];
2856 }
2857 else if (expr->operands[1]->is_zero()) {
2858 src_ir = expr->operands[0];
2859 }
2860 }
2861 }
2862 }
2863
2864 src_ir->accept(this);
2865 return switch_order;
2866 }
2867
2868 if ((expr != NULL) && (expr->num_operands == 2)) {
2869 bool zero_on_left = false;
2870
2871 if (expr->operands[0]->is_zero()) {
2872 src_ir = expr->operands[1];
2873 zero_on_left = true;
2874 } else if (expr->operands[1]->is_zero()) {
2875 src_ir = expr->operands[0];
2876 zero_on_left = false;
2877 }
2878
2879 /* a is - 0 + - 0 +
2880 * (a < 0) T F F ( a < 0) T F F
2881 * (0 < a) F F T (-a < 0) F F T
2882 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2883 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2884 *
2885 * Note that exchanging the order of 0 and 'a' in the comparison simply
2886 * means that the value of 'a' should be negated.
2887 */
2888 if (src_ir != ir) {
2889 switch (expr->operation) {
2890 case ir_binop_less:
2891 switch_order = false;
2892 negate = zero_on_left;
2893 break;
2894
2895 case ir_binop_gequal:
2896 switch_order = true;
2897 negate = zero_on_left;
2898 break;
2899
2900 default:
2901 /* This isn't the right kind of comparison afterall, so make sure
2902 * the whole condition is visited.
2903 */
2904 src_ir = ir;
2905 break;
2906 }
2907 }
2908 }
2909
2910 src_ir->accept(this);
2911
2912 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2913 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2914 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2915 * computing the condition.
2916 */
2917 if (negate)
2918 this->result.negate = ~this->result.negate;
2919
2920 return switch_order;
2921 }
2922
2923 void
2924 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
2925 st_dst_reg *l, st_src_reg *r,
2926 st_src_reg *cond, bool cond_swap)
2927 {
2928 if (type->is_record()) {
2929 for (unsigned int i = 0; i < type->length; i++) {
2930 emit_block_mov(ir, type->fields.structure[i].type, l, r,
2931 cond, cond_swap);
2932 }
2933 return;
2934 }
2935
2936 if (type->is_array()) {
2937 for (unsigned int i = 0; i < type->length; i++) {
2938 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
2939 }
2940 return;
2941 }
2942
2943 if (type->is_matrix()) {
2944 const struct glsl_type *vec_type;
2945
2946 vec_type = glsl_type::get_instance(type->is_double()
2947 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
2948 type->vector_elements, 1);
2949
2950 for (int i = 0; i < type->matrix_columns; i++) {
2951 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
2952 }
2953 return;
2954 }
2955
2956 assert(type->is_scalar() || type->is_vector());
2957
2958 l->type = type->base_type;
2959 r->type = type->base_type;
2960 if (cond) {
2961 st_src_reg l_src = st_src_reg(*l);
2962
2963 if (l_src.file == PROGRAM_OUTPUT &&
2964 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
2965 (l_src.index == FRAG_RESULT_DEPTH ||
2966 l_src.index == FRAG_RESULT_STENCIL)) {
2967 /* This is a special case because the source swizzles will be shifted
2968 * later to account for the difference between GLSL (where they're
2969 * plain floats) and TGSI (where they're Z and Y components). */
2970 l_src.swizzle = SWIZZLE_XXXX;
2971 }
2972
2973 if (native_integers) {
2974 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
2975 cond_swap ? l_src : *r,
2976 cond_swap ? *r : l_src);
2977 } else {
2978 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
2979 cond_swap ? l_src : *r,
2980 cond_swap ? *r : l_src);
2981 }
2982 } else {
2983 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
2984 }
2985 l->index++;
2986 r->index++;
2987 if (type->is_dual_slot()) {
2988 l->index++;
2989 if (r->is_double_vertex_input == false)
2990 r->index++;
2991 }
2992 }
2993
2994 void
2995 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
2996 {
2997 int dst_component;
2998 st_dst_reg l;
2999 st_src_reg r;
3000
3001 /* all generated instructions need to be flaged as precise */
3002 this->precise = is_precise(ir->lhs->variable_referenced());
3003 ir->rhs->accept(this);
3004 r = this->result;
3005
3006 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3007
3008 {
3009 int swizzles[4];
3010 int first_enabled_chan = 0;
3011 int rhs_chan = 0;
3012 ir_variable *variable = ir->lhs->variable_referenced();
3013
3014 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3015 variable->data.mode == ir_var_shader_out &&
3016 (variable->data.location == FRAG_RESULT_DEPTH ||
3017 variable->data.location == FRAG_RESULT_STENCIL)) {
3018 assert(ir->lhs->type->is_scalar());
3019 assert(ir->write_mask == WRITEMASK_X);
3020
3021 if (variable->data.location == FRAG_RESULT_DEPTH)
3022 l.writemask = WRITEMASK_Z;
3023 else {
3024 assert(variable->data.location == FRAG_RESULT_STENCIL);
3025 l.writemask = WRITEMASK_Y;
3026 }
3027 } else if (ir->write_mask == 0) {
3028 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3029
3030 unsigned num_elements =
3031 ir->lhs->type->without_array()->vector_elements;
3032
3033 if (num_elements) {
3034 l.writemask = u_bit_consecutive(0, num_elements);
3035 } else {
3036 /* The type is a struct or an array of (array of) structs. */
3037 l.writemask = WRITEMASK_XYZW;
3038 }
3039 } else {
3040 l.writemask = ir->write_mask;
3041 }
3042
3043 for (int i = 0; i < 4; i++) {
3044 if (l.writemask & (1 << i)) {
3045 first_enabled_chan = GET_SWZ(r.swizzle, i);
3046 break;
3047 }
3048 }
3049
3050 l.writemask = l.writemask << dst_component;
3051
3052 /* Swizzle a small RHS vector into the channels being written.
3053 *
3054 * glsl ir treats write_mask as dictating how many channels are
3055 * present on the RHS while TGSI treats write_mask as just
3056 * showing which channels of the vec4 RHS get written.
3057 */
3058 for (int i = 0; i < 4; i++) {
3059 if (l.writemask & (1 << i))
3060 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3061 else
3062 swizzles[i] = first_enabled_chan;
3063 }
3064 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3065 swizzles[2], swizzles[3]);
3066 }
3067
3068 assert(l.file != PROGRAM_UNDEFINED);
3069 assert(r.file != PROGRAM_UNDEFINED);
3070
3071 if (ir->condition) {
3072 const bool switch_order = this->process_move_condition(ir->condition);
3073 st_src_reg condition = this->result;
3074
3075 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3076 } else if (ir->rhs->as_expression() &&
3077 this->instructions.get_tail() &&
3078 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3079 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3080 type_size(ir->lhs->type) == 1 &&
3081 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3082 /* To avoid emitting an extra MOV when assigning an expression to a
3083 * variable, emit the last instruction of the expression again, but
3084 * replace the destination register with the target of the assignment.
3085 * Dead code elimination will remove the original instruction.
3086 */
3087 glsl_to_tgsi_instruction *inst, *new_inst;
3088 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3089 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3090 new_inst->saturate = inst->saturate;
3091 new_inst->resource = inst->resource;
3092 inst->dead_mask = inst->dst[0].writemask;
3093 } else {
3094 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3095 }
3096 this->precise = 0;
3097 }
3098
3099
3100 void
3101 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3102 {
3103 st_src_reg src;
3104 GLdouble stack_vals[4] = { 0 };
3105 gl_constant_value *values = (gl_constant_value *) stack_vals;
3106 GLenum gl_type = GL_NONE;
3107 unsigned int i;
3108 static int in_array = 0;
3109 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3110
3111 /* Unfortunately, 4 floats is all we can get into
3112 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3113 * aggregate constant and move each constant value into it. If we
3114 * get lucky, copy propagation will eliminate the extra moves.
3115 */
3116 if (ir->type->is_record()) {
3117 st_src_reg temp_base = get_temp(ir->type);
3118 st_dst_reg temp = st_dst_reg(temp_base);
3119
3120 for (i = 0; i < ir->type->length; i++) {
3121 ir_constant *const field_value = ir->get_record_field(i);
3122 int size = type_size(field_value->type);
3123
3124 assert(size > 0);
3125
3126 field_value->accept(this);
3127 src = this->result;
3128
3129 for (unsigned j = 0; j < (unsigned int)size; j++) {
3130 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3131
3132 src.index++;
3133 temp.index++;
3134 }
3135 }
3136 this->result = temp_base;
3137 return;
3138 }
3139
3140 if (ir->type->is_array()) {
3141 st_src_reg temp_base = get_temp(ir->type);
3142 st_dst_reg temp = st_dst_reg(temp_base);
3143 int size = type_size(ir->type->fields.array);
3144
3145 assert(size > 0);
3146 in_array++;
3147
3148 for (i = 0; i < ir->type->length; i++) {
3149 ir->const_elements[i]->accept(this);
3150 src = this->result;
3151 for (int j = 0; j < size; j++) {
3152 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3153
3154 src.index++;
3155 temp.index++;
3156 }
3157 }
3158 this->result = temp_base;
3159 in_array--;
3160 return;
3161 }
3162
3163 if (ir->type->is_matrix()) {
3164 st_src_reg mat = get_temp(ir->type);
3165 st_dst_reg mat_column = st_dst_reg(mat);
3166
3167 for (i = 0; i < ir->type->matrix_columns; i++) {
3168 switch (ir->type->base_type) {
3169 case GLSL_TYPE_FLOAT:
3170 values = (gl_constant_value *)
3171 &ir->value.f[i * ir->type->vector_elements];
3172
3173 src = st_src_reg(file, -1, ir->type->base_type);
3174 src.index = add_constant(file,
3175 values,
3176 ir->type->vector_elements,
3177 GL_FLOAT,
3178 &src.swizzle);
3179 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3180 break;
3181 case GLSL_TYPE_DOUBLE:
3182 values = (gl_constant_value *)
3183 &ir->value.d[i * ir->type->vector_elements];
3184 src = st_src_reg(file, -1, ir->type->base_type);
3185 src.index = add_constant(file,
3186 values,
3187 ir->type->vector_elements,
3188 GL_DOUBLE,
3189 &src.swizzle);
3190 if (ir->type->vector_elements >= 2) {
3191 mat_column.writemask = WRITEMASK_XY;
3192 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3193 SWIZZLE_X, SWIZZLE_Y);
3194 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3195 } else {
3196 mat_column.writemask = WRITEMASK_X;
3197 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3198 SWIZZLE_X, SWIZZLE_X);
3199 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3200 }
3201 src.index++;
3202 if (ir->type->vector_elements > 2) {
3203 if (ir->type->vector_elements == 4) {
3204 mat_column.writemask = WRITEMASK_ZW;
3205 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3206 SWIZZLE_X, SWIZZLE_Y);
3207 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3208 } else {
3209 mat_column.writemask = WRITEMASK_Z;
3210 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3211 SWIZZLE_Y, SWIZZLE_Y);
3212 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3213 mat_column.writemask = WRITEMASK_XYZW;
3214 src.swizzle = SWIZZLE_XYZW;
3215 }
3216 mat_column.index++;
3217 }
3218 break;
3219 default:
3220 unreachable("Illegal matrix constant type.\n");
3221 break;
3222 }
3223 mat_column.index++;
3224 }
3225 this->result = mat;
3226 return;
3227 }
3228
3229 switch (ir->type->base_type) {
3230 case GLSL_TYPE_FLOAT:
3231 gl_type = GL_FLOAT;
3232 for (i = 0; i < ir->type->vector_elements; i++) {
3233 values[i].f = ir->value.f[i];
3234 }
3235 break;
3236 case GLSL_TYPE_DOUBLE:
3237 gl_type = GL_DOUBLE;
3238 for (i = 0; i < ir->type->vector_elements; i++) {
3239 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3240 }
3241 break;
3242 case GLSL_TYPE_INT64:
3243 gl_type = GL_INT64_ARB;
3244 for (i = 0; i < ir->type->vector_elements; i++) {
3245 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3246 }
3247 break;
3248 case GLSL_TYPE_UINT64:
3249 gl_type = GL_UNSIGNED_INT64_ARB;
3250 for (i = 0; i < ir->type->vector_elements; i++) {
3251 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3252 }
3253 break;
3254 case GLSL_TYPE_UINT:
3255 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3256 for (i = 0; i < ir->type->vector_elements; i++) {
3257 if (native_integers)
3258 values[i].u = ir->value.u[i];
3259 else
3260 values[i].f = ir->value.u[i];
3261 }
3262 break;
3263 case GLSL_TYPE_INT:
3264 gl_type = native_integers ? GL_INT : GL_FLOAT;
3265 for (i = 0; i < ir->type->vector_elements; i++) {
3266 if (native_integers)
3267 values[i].i = ir->value.i[i];
3268 else
3269 values[i].f = ir->value.i[i];
3270 }
3271 break;
3272 case GLSL_TYPE_BOOL:
3273 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3274 for (i = 0; i < ir->type->vector_elements; i++) {
3275 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3276 }
3277 break;
3278 default:
3279 assert(!"Non-float/uint/int/bool constant");
3280 }
3281
3282 this->result = st_src_reg(file, -1, ir->type);
3283 this->result.index = add_constant(file,
3284 values,
3285 ir->type->vector_elements,
3286 gl_type,
3287 &this->result.swizzle);
3288 }
3289
3290 void
3291 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3292 {
3293 exec_node *param = ir->actual_parameters.get_head();
3294 ir_dereference *deref = static_cast<ir_dereference *>(param);
3295 ir_variable *location = deref->variable_referenced();
3296 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3297 /* Calculate the surface offset */
3298 st_src_reg offset;
3299 unsigned array_size = 0, base = 0;
3300 uint16_t index = 0;
3301 st_src_reg resource;
3302
3303 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3304
3305 if (has_hw_atomics) {
3306 variable_storage *entry = find_variable_storage(location);
3307 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3308 location->data.binding);
3309
3310 if (!entry) {
3311 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3312 num_atomics);
3313 _mesa_hash_table_insert(this->variables, location, entry);
3314
3315 atomic_info[num_atomics].location = location->data.location;
3316 atomic_info[num_atomics].binding = location->data.binding;
3317 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3318 if (atomic_info[num_atomics].size == 0)
3319 atomic_info[num_atomics].size = 1;
3320 atomic_info[num_atomics].array_id = 0;
3321 num_atomics++;
3322 }
3323
3324 if (offset.file != PROGRAM_UNDEFINED) {
3325 if (atomic_info[entry->index].array_id == 0) {
3326 num_atomic_arrays++;
3327 atomic_info[entry->index].array_id = num_atomic_arrays;
3328 }
3329 buffer.array_id = atomic_info[entry->index].array_id;
3330 }
3331
3332 buffer.index = index;
3333 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3334 buffer.has_index2 = true;
3335
3336 if (offset.file != PROGRAM_UNDEFINED) {
3337 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3338 *buffer.reladdr = offset;
3339 emit_arl(ir, sampler_reladdr, offset);
3340 }
3341 offset = st_src_reg_for_int(0);
3342
3343 resource = buffer;
3344 } else {
3345 st_src_reg buffer(PROGRAM_BUFFER, location->data.binding,
3346 GLSL_TYPE_ATOMIC_UINT);
3347
3348 if (offset.file != PROGRAM_UNDEFINED) {
3349 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3350 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3351 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3352 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3353 } else {
3354 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3355 }
3356 resource = buffer;
3357 }
3358
3359 ir->return_deref->accept(this);
3360 st_dst_reg dst(this->result);
3361 dst.writemask = WRITEMASK_X;
3362
3363 glsl_to_tgsi_instruction *inst;
3364
3365 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3366 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3367 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3368 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3369 st_src_reg_for_int(1));
3370 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3371 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3372 st_src_reg_for_int(-1));
3373 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3374 } else {
3375 param = param->get_next();
3376 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3377 val->accept(this);
3378
3379 st_src_reg data = this->result, data2 = undef_src;
3380 unsigned opcode;
3381 switch (ir->callee->intrinsic_id) {
3382 case ir_intrinsic_atomic_counter_add:
3383 opcode = TGSI_OPCODE_ATOMUADD;
3384 break;
3385 case ir_intrinsic_atomic_counter_min:
3386 opcode = TGSI_OPCODE_ATOMIMIN;
3387 break;
3388 case ir_intrinsic_atomic_counter_max:
3389 opcode = TGSI_OPCODE_ATOMIMAX;
3390 break;
3391 case ir_intrinsic_atomic_counter_and:
3392 opcode = TGSI_OPCODE_ATOMAND;
3393 break;
3394 case ir_intrinsic_atomic_counter_or:
3395 opcode = TGSI_OPCODE_ATOMOR;
3396 break;
3397 case ir_intrinsic_atomic_counter_xor:
3398 opcode = TGSI_OPCODE_ATOMXOR;
3399 break;
3400 case ir_intrinsic_atomic_counter_exchange:
3401 opcode = TGSI_OPCODE_ATOMXCHG;
3402 break;
3403 case ir_intrinsic_atomic_counter_comp_swap: {
3404 opcode = TGSI_OPCODE_ATOMCAS;
3405 param = param->get_next();
3406 val = ((ir_instruction *)param)->as_rvalue();
3407 val->accept(this);
3408 data2 = this->result;
3409 break;
3410 }
3411 default:
3412 assert(!"Unexpected intrinsic");
3413 return;
3414 }
3415
3416 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3417 }
3418
3419 inst->resource = resource;
3420 }
3421
3422 void
3423 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3424 {
3425 exec_node *param = ir->actual_parameters.get_head();
3426
3427 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3428
3429 param = param->get_next();
3430 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3431
3432 ir_constant *const_block = block->as_constant();
3433 int buf_base = st_context(ctx)->has_hw_atomics
3434 ? 0 : ctx->Const.Program[shader->Stage].MaxAtomicBuffers;
3435 st_src_reg buffer(
3436 PROGRAM_BUFFER,
3437 buf_base + (const_block ? const_block->value.u[0] : 0),
3438 GLSL_TYPE_UINT);
3439
3440 if (!const_block) {
3441 block->accept(this);
3442 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3443 *buffer.reladdr = this->result;
3444 emit_arl(ir, sampler_reladdr, this->result);
3445 }
3446
3447 /* Calculate the surface offset */
3448 offset->accept(this);
3449 st_src_reg off = this->result;
3450
3451 st_dst_reg dst = undef_dst;
3452 if (ir->return_deref) {
3453 ir->return_deref->accept(this);
3454 dst = st_dst_reg(this->result);
3455 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3456 }
3457
3458 glsl_to_tgsi_instruction *inst;
3459
3460 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3461 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3462 if (dst.type == GLSL_TYPE_BOOL)
3463 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3464 st_src_reg_for_int(0));
3465 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3466 param = param->get_next();
3467 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3468 val->accept(this);
3469
3470 param = param->get_next();
3471 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3472 assert(write_mask);
3473 dst.writemask = write_mask->value.u[0];
3474
3475 dst.type = this->result.type;
3476 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3477 } else {
3478 param = param->get_next();
3479 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3480 val->accept(this);
3481
3482 st_src_reg data = this->result, data2 = undef_src;
3483 unsigned opcode;
3484 switch (ir->callee->intrinsic_id) {
3485 case ir_intrinsic_ssbo_atomic_add:
3486 opcode = TGSI_OPCODE_ATOMUADD;
3487 break;
3488 case ir_intrinsic_ssbo_atomic_min:
3489 opcode = TGSI_OPCODE_ATOMIMIN;
3490 break;
3491 case ir_intrinsic_ssbo_atomic_max:
3492 opcode = TGSI_OPCODE_ATOMIMAX;
3493 break;
3494 case ir_intrinsic_ssbo_atomic_and:
3495 opcode = TGSI_OPCODE_ATOMAND;
3496 break;
3497 case ir_intrinsic_ssbo_atomic_or:
3498 opcode = TGSI_OPCODE_ATOMOR;
3499 break;
3500 case ir_intrinsic_ssbo_atomic_xor:
3501 opcode = TGSI_OPCODE_ATOMXOR;
3502 break;
3503 case ir_intrinsic_ssbo_atomic_exchange:
3504 opcode = TGSI_OPCODE_ATOMXCHG;
3505 break;
3506 case ir_intrinsic_ssbo_atomic_comp_swap:
3507 opcode = TGSI_OPCODE_ATOMCAS;
3508 param = param->get_next();
3509 val = ((ir_instruction *)param)->as_rvalue();
3510 val->accept(this);
3511 data2 = this->result;
3512 break;
3513 default:
3514 assert(!"Unexpected intrinsic");
3515 return;
3516 }
3517
3518 inst = emit_asm(ir, opcode, dst, off, data, data2);
3519 }
3520
3521 param = param->get_next();
3522 ir_constant *access = NULL;
3523 if (!param->is_tail_sentinel()) {
3524 access = ((ir_instruction *)param)->as_constant();
3525 assert(access);
3526 }
3527
3528 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3529 }
3530
3531 void
3532 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3533 {
3534 switch (ir->callee->intrinsic_id) {
3535 case ir_intrinsic_memory_barrier:
3536 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3537 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3538 TGSI_MEMBAR_ATOMIC_BUFFER |
3539 TGSI_MEMBAR_SHADER_IMAGE |
3540 TGSI_MEMBAR_SHARED));
3541 break;
3542 case ir_intrinsic_memory_barrier_atomic_counter:
3543 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3544 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3545 break;
3546 case ir_intrinsic_memory_barrier_buffer:
3547 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3548 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3549 break;
3550 case ir_intrinsic_memory_barrier_image:
3551 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3552 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3553 break;
3554 case ir_intrinsic_memory_barrier_shared:
3555 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3556 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3557 break;
3558 case ir_intrinsic_group_memory_barrier:
3559 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3560 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3561 TGSI_MEMBAR_ATOMIC_BUFFER |
3562 TGSI_MEMBAR_SHADER_IMAGE |
3563 TGSI_MEMBAR_SHARED |
3564 TGSI_MEMBAR_THREAD_GROUP));
3565 break;
3566 default:
3567 assert(!"Unexpected memory barrier intrinsic");
3568 }
3569 }
3570
3571 void
3572 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3573 {
3574 exec_node *param = ir->actual_parameters.get_head();
3575
3576 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3577
3578 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3579
3580 /* Calculate the surface offset */
3581 offset->accept(this);
3582 st_src_reg off = this->result;
3583
3584 st_dst_reg dst = undef_dst;
3585 if (ir->return_deref) {
3586 ir->return_deref->accept(this);
3587 dst = st_dst_reg(this->result);
3588 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3589 }
3590
3591 glsl_to_tgsi_instruction *inst;
3592
3593 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3594 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3595 inst->resource = buffer;
3596 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3597 param = param->get_next();
3598 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3599 val->accept(this);
3600
3601 param = param->get_next();
3602 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3603 assert(write_mask);
3604 dst.writemask = write_mask->value.u[0];
3605
3606 dst.type = this->result.type;
3607 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3608 inst->resource = buffer;
3609 } else {
3610 param = param->get_next();
3611 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3612 val->accept(this);
3613
3614 st_src_reg data = this->result, data2 = undef_src;
3615 unsigned opcode;
3616 switch (ir->callee->intrinsic_id) {
3617 case ir_intrinsic_shared_atomic_add:
3618 opcode = TGSI_OPCODE_ATOMUADD;
3619 break;
3620 case ir_intrinsic_shared_atomic_min:
3621 opcode = TGSI_OPCODE_ATOMIMIN;
3622 break;
3623 case ir_intrinsic_shared_atomic_max:
3624 opcode = TGSI_OPCODE_ATOMIMAX;
3625 break;
3626 case ir_intrinsic_shared_atomic_and:
3627 opcode = TGSI_OPCODE_ATOMAND;
3628 break;
3629 case ir_intrinsic_shared_atomic_or:
3630 opcode = TGSI_OPCODE_ATOMOR;
3631 break;
3632 case ir_intrinsic_shared_atomic_xor:
3633 opcode = TGSI_OPCODE_ATOMXOR;
3634 break;
3635 case ir_intrinsic_shared_atomic_exchange:
3636 opcode = TGSI_OPCODE_ATOMXCHG;
3637 break;
3638 case ir_intrinsic_shared_atomic_comp_swap:
3639 opcode = TGSI_OPCODE_ATOMCAS;
3640 param = param->get_next();
3641 val = ((ir_instruction *)param)->as_rvalue();
3642 val->accept(this);
3643 data2 = this->result;
3644 break;
3645 default:
3646 assert(!"Unexpected intrinsic");
3647 return;
3648 }
3649
3650 inst = emit_asm(ir, opcode, dst, off, data, data2);
3651 inst->resource = buffer;
3652 }
3653 }
3654
3655 static void
3656 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3657 bool *memory_coherent, bool *memory_volatile,
3658 bool *memory_restrict, unsigned *image_format)
3659 {
3660
3661 switch (ir->ir_type) {
3662 case ir_type_dereference_record: {
3663 ir_dereference_record *deref_record = ir->as_dereference_record();
3664 const glsl_type *struct_type = deref_record->record->type;
3665 int fild_idx = deref_record->field_idx;
3666
3667 *type = struct_type->fields.structure[fild_idx].type->without_array();
3668 *memory_coherent =
3669 struct_type->fields.structure[fild_idx].memory_coherent;
3670 *memory_volatile =
3671 struct_type->fields.structure[fild_idx].memory_volatile;
3672 *memory_restrict =
3673 struct_type->fields.structure[fild_idx].memory_restrict;
3674 *image_format =
3675 struct_type->fields.structure[fild_idx].image_format;
3676 break;
3677 }
3678
3679 case ir_type_dereference_array: {
3680 ir_dereference_array *deref_arr = ir->as_dereference_array();
3681 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3682 memory_coherent, memory_volatile, memory_restrict,
3683 image_format);
3684 break;
3685 }
3686
3687 case ir_type_dereference_variable: {
3688 ir_variable *var = ir->variable_referenced();
3689
3690 *type = var->type->without_array();
3691 *memory_coherent = var->data.memory_coherent;
3692 *memory_volatile = var->data.memory_volatile;
3693 *memory_restrict = var->data.memory_restrict;
3694 *image_format = var->data.image_format;
3695 break;
3696 }
3697
3698 default:
3699 break;
3700 }
3701 }
3702
3703 void
3704 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3705 {
3706 exec_node *param = ir->actual_parameters.get_head();
3707
3708 ir_dereference *img = (ir_dereference *)param;
3709 const ir_variable *imgvar = img->variable_referenced();
3710 unsigned sampler_array_size = 1, sampler_base = 0;
3711 bool memory_coherent = false, memory_volatile = false, memory_restrict = false;
3712 unsigned image_format = 0;
3713 const glsl_type *type = NULL;
3714
3715 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3716 &memory_restrict, &image_format);
3717
3718 st_src_reg reladdr;
3719 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3720 uint16_t index = 0;
3721 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3722 &index, &reladdr, !imgvar->contains_bindless());
3723
3724 image.index = index;
3725 if (reladdr.file != PROGRAM_UNDEFINED) {
3726 image.reladdr = ralloc(mem_ctx, st_src_reg);
3727 *image.reladdr = reladdr;
3728 emit_arl(ir, sampler_reladdr, reladdr);
3729 }
3730
3731 st_dst_reg dst = undef_dst;
3732 if (ir->return_deref) {
3733 ir->return_deref->accept(this);
3734 dst = st_dst_reg(this->result);
3735 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3736 }
3737
3738 glsl_to_tgsi_instruction *inst;
3739
3740 st_src_reg bindless;
3741 if (imgvar->contains_bindless()) {
3742 img->accept(this);
3743 bindless = this->result;
3744 }
3745
3746 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3747 dst.writemask = WRITEMASK_XYZ;
3748 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3749 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3750 st_src_reg res = get_temp(glsl_type::ivec4_type);
3751 st_dst_reg dstres = st_dst_reg(res);
3752 dstres.writemask = WRITEMASK_W;
3753 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3754 res.swizzle = SWIZZLE_WWWW;
3755 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3756 } else {
3757 st_src_reg arg1 = undef_src, arg2 = undef_src;
3758 st_src_reg coord;
3759 st_dst_reg coord_dst;
3760 coord = get_temp(glsl_type::ivec4_type);
3761 coord_dst = st_dst_reg(coord);
3762 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3763 param = param->get_next();
3764 ((ir_dereference *)param)->accept(this);
3765 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3766 coord.swizzle = SWIZZLE_XXXX;
3767 switch (type->coordinate_components()) {
3768 case 4: assert(!"unexpected coord count");
3769 /* fallthrough */
3770 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3771 /* fallthrough */
3772 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3773 }
3774
3775 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3776 param = param->get_next();
3777 ((ir_dereference *)param)->accept(this);
3778 st_src_reg sample = this->result;
3779 sample.swizzle = SWIZZLE_XXXX;
3780 coord_dst.writemask = WRITEMASK_W;
3781 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3782 coord.swizzle |= SWIZZLE_W << 9;
3783 }
3784
3785 param = param->get_next();
3786 if (!param->is_tail_sentinel()) {
3787 ((ir_dereference *)param)->accept(this);
3788 arg1 = this->result;
3789 param = param->get_next();
3790 }
3791
3792 if (!param->is_tail_sentinel()) {
3793 ((ir_dereference *)param)->accept(this);
3794 arg2 = this->result;
3795 param = param->get_next();
3796 }
3797
3798 assert(param->is_tail_sentinel());
3799
3800 unsigned opcode;
3801 switch (ir->callee->intrinsic_id) {
3802 case ir_intrinsic_image_load:
3803 opcode = TGSI_OPCODE_LOAD;
3804 break;
3805 case ir_intrinsic_image_store:
3806 opcode = TGSI_OPCODE_STORE;
3807 break;
3808 case ir_intrinsic_image_atomic_add:
3809 opcode = TGSI_OPCODE_ATOMUADD;
3810 break;
3811 case ir_intrinsic_image_atomic_min:
3812 opcode = TGSI_OPCODE_ATOMIMIN;
3813 break;
3814 case ir_intrinsic_image_atomic_max:
3815 opcode = TGSI_OPCODE_ATOMIMAX;
3816 break;
3817 case ir_intrinsic_image_atomic_and:
3818 opcode = TGSI_OPCODE_ATOMAND;
3819 break;
3820 case ir_intrinsic_image_atomic_or:
3821 opcode = TGSI_OPCODE_ATOMOR;
3822 break;
3823 case ir_intrinsic_image_atomic_xor:
3824 opcode = TGSI_OPCODE_ATOMXOR;
3825 break;
3826 case ir_intrinsic_image_atomic_exchange:
3827 opcode = TGSI_OPCODE_ATOMXCHG;
3828 break;
3829 case ir_intrinsic_image_atomic_comp_swap:
3830 opcode = TGSI_OPCODE_ATOMCAS;
3831 break;
3832 default:
3833 assert(!"Unexpected intrinsic");
3834 return;
3835 }
3836
3837 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3838 if (opcode == TGSI_OPCODE_STORE)
3839 inst->dst[0].writemask = WRITEMASK_XYZW;
3840 }
3841
3842 if (imgvar->contains_bindless()) {
3843 inst->resource = bindless;
3844 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3845 SWIZZLE_X, SWIZZLE_Y);
3846 } else {
3847 inst->resource = image;
3848 inst->sampler_array_size = sampler_array_size;
3849 inst->sampler_base = sampler_base;
3850 }
3851
3852 inst->tex_target = type->sampler_index();
3853 inst->image_format = st_mesa_format_to_pipe_format(st_context(ctx),
3854 _mesa_get_shader_image_format(image_format));
3855
3856 if (memory_coherent)
3857 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3858 if (memory_restrict)
3859 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3860 if (memory_volatile)
3861 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3862 }
3863
3864 void
3865 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, unsigned op)
3866 {
3867 ir->return_deref->accept(this);
3868 st_dst_reg dst = st_dst_reg(this->result);
3869
3870 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
3871
3872 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
3873 unsigned num_src = 0;
3874 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
3875 assert(num_src < ARRAY_SIZE(src));
3876
3877 this->result.file = PROGRAM_UNDEFINED;
3878 param->accept(this);
3879 assert(this->result.file != PROGRAM_UNDEFINED);
3880
3881 src[num_src] = this->result;
3882 num_src++;
3883 }
3884
3885 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
3886 }
3887
3888 void
3889 glsl_to_tgsi_visitor::visit(ir_call *ir)
3890 {
3891 ir_function_signature *sig = ir->callee;
3892
3893 /* Filter out intrinsics */
3894 switch (sig->intrinsic_id) {
3895 case ir_intrinsic_atomic_counter_read:
3896 case ir_intrinsic_atomic_counter_increment:
3897 case ir_intrinsic_atomic_counter_predecrement:
3898 case ir_intrinsic_atomic_counter_add:
3899 case ir_intrinsic_atomic_counter_min:
3900 case ir_intrinsic_atomic_counter_max:
3901 case ir_intrinsic_atomic_counter_and:
3902 case ir_intrinsic_atomic_counter_or:
3903 case ir_intrinsic_atomic_counter_xor:
3904 case ir_intrinsic_atomic_counter_exchange:
3905 case ir_intrinsic_atomic_counter_comp_swap:
3906 visit_atomic_counter_intrinsic(ir);
3907 return;
3908
3909 case ir_intrinsic_ssbo_load:
3910 case ir_intrinsic_ssbo_store:
3911 case ir_intrinsic_ssbo_atomic_add:
3912 case ir_intrinsic_ssbo_atomic_min:
3913 case ir_intrinsic_ssbo_atomic_max:
3914 case ir_intrinsic_ssbo_atomic_and:
3915 case ir_intrinsic_ssbo_atomic_or:
3916 case ir_intrinsic_ssbo_atomic_xor:
3917 case ir_intrinsic_ssbo_atomic_exchange:
3918 case ir_intrinsic_ssbo_atomic_comp_swap:
3919 visit_ssbo_intrinsic(ir);
3920 return;
3921
3922 case ir_intrinsic_memory_barrier:
3923 case ir_intrinsic_memory_barrier_atomic_counter:
3924 case ir_intrinsic_memory_barrier_buffer:
3925 case ir_intrinsic_memory_barrier_image:
3926 case ir_intrinsic_memory_barrier_shared:
3927 case ir_intrinsic_group_memory_barrier:
3928 visit_membar_intrinsic(ir);
3929 return;
3930
3931 case ir_intrinsic_shared_load:
3932 case ir_intrinsic_shared_store:
3933 case ir_intrinsic_shared_atomic_add:
3934 case ir_intrinsic_shared_atomic_min:
3935 case ir_intrinsic_shared_atomic_max:
3936 case ir_intrinsic_shared_atomic_and:
3937 case ir_intrinsic_shared_atomic_or:
3938 case ir_intrinsic_shared_atomic_xor:
3939 case ir_intrinsic_shared_atomic_exchange:
3940 case ir_intrinsic_shared_atomic_comp_swap:
3941 visit_shared_intrinsic(ir);
3942 return;
3943
3944 case ir_intrinsic_image_load:
3945 case ir_intrinsic_image_store:
3946 case ir_intrinsic_image_atomic_add:
3947 case ir_intrinsic_image_atomic_min:
3948 case ir_intrinsic_image_atomic_max:
3949 case ir_intrinsic_image_atomic_and:
3950 case ir_intrinsic_image_atomic_or:
3951 case ir_intrinsic_image_atomic_xor:
3952 case ir_intrinsic_image_atomic_exchange:
3953 case ir_intrinsic_image_atomic_comp_swap:
3954 case ir_intrinsic_image_size:
3955 case ir_intrinsic_image_samples:
3956 visit_image_intrinsic(ir);
3957 return;
3958
3959 case ir_intrinsic_shader_clock:
3960 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
3961 return;
3962
3963 case ir_intrinsic_vote_all:
3964 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
3965 return;
3966 case ir_intrinsic_vote_any:
3967 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
3968 return;
3969 case ir_intrinsic_vote_eq:
3970 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
3971 return;
3972 case ir_intrinsic_ballot:
3973 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
3974 return;
3975 case ir_intrinsic_read_first_invocation:
3976 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
3977 return;
3978 case ir_intrinsic_read_invocation:
3979 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
3980 return;
3981
3982 case ir_intrinsic_invalid:
3983 case ir_intrinsic_generic_load:
3984 case ir_intrinsic_generic_store:
3985 case ir_intrinsic_generic_atomic_add:
3986 case ir_intrinsic_generic_atomic_and:
3987 case ir_intrinsic_generic_atomic_or:
3988 case ir_intrinsic_generic_atomic_xor:
3989 case ir_intrinsic_generic_atomic_min:
3990 case ir_intrinsic_generic_atomic_max:
3991 case ir_intrinsic_generic_atomic_exchange:
3992 case ir_intrinsic_generic_atomic_comp_swap:
3993 unreachable("Invalid intrinsic");
3994 }
3995 }
3996
3997 void
3998 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
3999 unsigned *array_elements,
4000 uint16_t *index,
4001 st_src_reg *indirect,
4002 unsigned *location)
4003 {
4004 switch (tail->ir_type) {
4005 case ir_type_dereference_record: {
4006 ir_dereference_record *deref_record = tail->as_dereference_record();
4007 const glsl_type *struct_type = deref_record->record->type;
4008 int field_index = deref_record->field_idx;
4009
4010 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4011
4012 assert(field_index >= 0);
4013 *location += struct_type->record_location_offset(field_index);
4014 break;
4015 }
4016
4017 case ir_type_dereference_array: {
4018 ir_dereference_array *deref_arr = tail->as_dereference_array();
4019
4020 void *mem_ctx = ralloc_parent(deref_arr);
4021 ir_constant *array_index =
4022 deref_arr->array_index->constant_expression_value(mem_ctx);
4023
4024 if (!array_index) {
4025 st_src_reg temp_reg;
4026 st_dst_reg temp_dst;
4027
4028 temp_reg = get_temp(glsl_type::uint_type);
4029 temp_dst = st_dst_reg(temp_reg);
4030 temp_dst.writemask = 1;
4031
4032 deref_arr->array_index->accept(this);
4033 if (*array_elements != 1)
4034 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4035 else
4036 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4037
4038 if (indirect->file == PROGRAM_UNDEFINED)
4039 *indirect = temp_reg;
4040 else {
4041 temp_dst = st_dst_reg(*indirect);
4042 temp_dst.writemask = 1;
4043 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4044 }
4045 } else
4046 *index += array_index->value.u[0] * *array_elements;
4047
4048 *array_elements *= deref_arr->array->type->length;
4049
4050 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4051 break;
4052 }
4053 default:
4054 break;
4055 }
4056 }
4057
4058 void
4059 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4060 unsigned *array_size,
4061 unsigned *base,
4062 uint16_t *index,
4063 st_src_reg *reladdr,
4064 bool opaque)
4065 {
4066 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4067 unsigned location = 0;
4068 ir_variable *var = ir->variable_referenced();
4069
4070 memset(reladdr, 0, sizeof(*reladdr));
4071 reladdr->file = PROGRAM_UNDEFINED;
4072
4073 *base = 0;
4074 *array_size = 1;
4075
4076 assert(var);
4077 location = var->data.location;
4078 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4079
4080 /*
4081 * If we end up with no indirect then adjust the base to the index,
4082 * and set the array size to 1.
4083 */
4084 if (reladdr->file == PROGRAM_UNDEFINED) {
4085 *base = *index;
4086 *array_size = 1;
4087 }
4088
4089 if (opaque) {
4090 assert(location != 0xffffffff);
4091 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4092 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4093 }
4094 }
4095
4096 st_src_reg
4097 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4098 {
4099 if (offset.reladdr || offset.reladdr2) {
4100 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4101 st_dst_reg tmp_dst = st_dst_reg(tmp);
4102 tmp_dst.writemask = WRITEMASK_XY;
4103 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4104 return tmp;
4105 }
4106
4107 return offset;
4108 }
4109
4110 void
4111 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4112 {
4113 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4114 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4115 st_src_reg levels_src, reladdr;
4116 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4117 glsl_to_tgsi_instruction *inst = NULL;
4118 unsigned opcode = TGSI_OPCODE_NOP;
4119 const glsl_type *sampler_type = ir->sampler->type;
4120 unsigned sampler_array_size = 1, sampler_base = 0;
4121 bool is_cube_array = false, is_cube_shadow = false;
4122 ir_variable *var = ir->sampler->variable_referenced();
4123 unsigned i;
4124
4125 /* if we are a cube array sampler or a cube shadow */
4126 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4127 is_cube_array = sampler_type->sampler_array;
4128 is_cube_shadow = sampler_type->sampler_shadow;
4129 }
4130
4131 if (ir->coordinate) {
4132 ir->coordinate->accept(this);
4133
4134 /* Put our coords in a temp. We'll need to modify them for shadow,
4135 * projection, or LOD, so the only case we'd use it as-is is if
4136 * we're doing plain old texturing. The optimization passes on
4137 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4138 */
4139 coord = get_temp(glsl_type::vec4_type);
4140 coord_dst = st_dst_reg(coord);
4141 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4142 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4143 }
4144
4145 if (ir->projector) {
4146 ir->projector->accept(this);
4147 projector = this->result;
4148 }
4149
4150 /* Storage for our result. Ideally for an assignment we'd be using
4151 * the actual storage for the result here, instead.
4152 */
4153 result_src = get_temp(ir->type);
4154 result_dst = st_dst_reg(result_src);
4155 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4156
4157 switch (ir->op) {
4158 case ir_tex:
4159 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4160 if (ir->offset) {
4161 ir->offset->accept(this);
4162 offset[0] = this->result;
4163 }
4164 break;
4165 case ir_txb:
4166 if (is_cube_array || is_cube_shadow) {
4167 opcode = TGSI_OPCODE_TXB2;
4168 }
4169 else {
4170 opcode = TGSI_OPCODE_TXB;
4171 }
4172 ir->lod_info.bias->accept(this);
4173 lod_info = this->result;
4174 if (ir->offset) {
4175 ir->offset->accept(this);
4176 offset[0] = this->result;
4177 }
4178 break;
4179 case ir_txl:
4180 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4181 opcode = TGSI_OPCODE_TEX_LZ;
4182 } else {
4183 opcode = is_cube_array ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4184 ir->lod_info.lod->accept(this);
4185 lod_info = this->result;
4186 }
4187 if (ir->offset) {
4188 ir->offset->accept(this);
4189 offset[0] = this->result;
4190 }
4191 break;
4192 case ir_txd:
4193 opcode = TGSI_OPCODE_TXD;
4194 ir->lod_info.grad.dPdx->accept(this);
4195 dx = this->result;
4196 ir->lod_info.grad.dPdy->accept(this);
4197 dy = this->result;
4198 if (ir->offset) {
4199 ir->offset->accept(this);
4200 offset[0] = this->result;
4201 }
4202 break;
4203 case ir_txs:
4204 opcode = TGSI_OPCODE_TXQ;
4205 ir->lod_info.lod->accept(this);
4206 lod_info = this->result;
4207 break;
4208 case ir_query_levels:
4209 opcode = TGSI_OPCODE_TXQ;
4210 lod_info = undef_src;
4211 levels_src = get_temp(ir->type);
4212 break;
4213 case ir_txf:
4214 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4215 opcode = TGSI_OPCODE_TXF_LZ;
4216 } else {
4217 opcode = TGSI_OPCODE_TXF;
4218 ir->lod_info.lod->accept(this);
4219 lod_info = this->result;
4220 }
4221 if (ir->offset) {
4222 ir->offset->accept(this);
4223 offset[0] = this->result;
4224 }
4225 break;
4226 case ir_txf_ms:
4227 opcode = TGSI_OPCODE_TXF;
4228 ir->lod_info.sample_index->accept(this);
4229 sample_index = this->result;
4230 break;
4231 case ir_tg4:
4232 opcode = TGSI_OPCODE_TG4;
4233 ir->lod_info.component->accept(this);
4234 component = this->result;
4235 if (ir->offset) {
4236 ir->offset->accept(this);
4237 if (ir->offset->type->is_array()) {
4238 const glsl_type *elt_type = ir->offset->type->fields.array;
4239 for (i = 0; i < ir->offset->type->length; i++) {
4240 offset[i] = this->result;
4241 offset[i].index += i * type_size(elt_type);
4242 offset[i].type = elt_type->base_type;
4243 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4244 offset[i] = canonicalize_gather_offset(offset[i]);
4245 }
4246 } else {
4247 offset[0] = canonicalize_gather_offset(this->result);
4248 }
4249 }
4250 break;
4251 case ir_lod:
4252 opcode = TGSI_OPCODE_LODQ;
4253 break;
4254 case ir_texture_samples:
4255 opcode = TGSI_OPCODE_TXQS;
4256 break;
4257 case ir_samples_identical:
4258 unreachable("Unexpected ir_samples_identical opcode");
4259 }
4260
4261 if (ir->projector) {
4262 if (opcode == TGSI_OPCODE_TEX) {
4263 /* Slot the projector in as the last component of the coord. */
4264 coord_dst.writemask = WRITEMASK_W;
4265 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4266 coord_dst.writemask = WRITEMASK_XYZW;
4267 opcode = TGSI_OPCODE_TXP;
4268 } else {
4269 st_src_reg coord_w = coord;
4270 coord_w.swizzle = SWIZZLE_WWWW;
4271
4272 /* For the other TEX opcodes there's no projective version
4273 * since the last slot is taken up by LOD info. Do the
4274 * projective divide now.
4275 */
4276 coord_dst.writemask = WRITEMASK_W;
4277 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4278
4279 /* In the case where we have to project the coordinates "by hand,"
4280 * the shadow comparator value must also be projected.
4281 */
4282 st_src_reg tmp_src = coord;
4283 if (ir->shadow_comparator) {
4284 /* Slot the shadow value in as the second to last component of the
4285 * coord.
4286 */
4287 ir->shadow_comparator->accept(this);
4288
4289 tmp_src = get_temp(glsl_type::vec4_type);
4290 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4291
4292 /* Projective division not allowed for array samplers. */
4293 assert(!sampler_type->sampler_array);
4294
4295 tmp_dst.writemask = WRITEMASK_Z;
4296 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4297
4298 tmp_dst.writemask = WRITEMASK_XY;
4299 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4300 }
4301
4302 coord_dst.writemask = WRITEMASK_XYZ;
4303 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4304
4305 coord_dst.writemask = WRITEMASK_XYZW;
4306 coord.swizzle = SWIZZLE_XYZW;
4307 }
4308 }
4309
4310 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4311 * shadow comparator was put in the correct place (and projected) by the
4312 * code, above, that handles by-hand projection.
4313 */
4314 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4315 /* Slot the shadow value in as the second to last component of the
4316 * coord.
4317 */
4318 ir->shadow_comparator->accept(this);
4319
4320 if (is_cube_array) {
4321 cube_sc = get_temp(glsl_type::float_type);
4322 cube_sc_dst = st_dst_reg(cube_sc);
4323 cube_sc_dst.writemask = WRITEMASK_X;
4324 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4325 cube_sc_dst.writemask = WRITEMASK_X;
4326 }
4327 else {
4328 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4329 sampler_type->sampler_array) ||
4330 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4331 coord_dst.writemask = WRITEMASK_W;
4332 } else {
4333 coord_dst.writemask = WRITEMASK_Z;
4334 }
4335 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4336 coord_dst.writemask = WRITEMASK_XYZW;
4337 }
4338 }
4339
4340 if (ir->op == ir_txf_ms) {
4341 coord_dst.writemask = WRITEMASK_W;
4342 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4343 coord_dst.writemask = WRITEMASK_XYZW;
4344 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4345 opcode == TGSI_OPCODE_TXF) {
4346 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4347 coord_dst.writemask = WRITEMASK_W;
4348 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4349 coord_dst.writemask = WRITEMASK_XYZW;
4350 }
4351
4352 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4353
4354 uint16_t index = 0;
4355 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4356 &index, &reladdr, !var->contains_bindless());
4357
4358 sampler.index = index;
4359 if (reladdr.file != PROGRAM_UNDEFINED) {
4360 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4361 *sampler.reladdr = reladdr;
4362 emit_arl(ir, sampler_reladdr, reladdr);
4363 }
4364
4365 st_src_reg bindless;
4366 if (var->contains_bindless()) {
4367 ir->sampler->accept(this);
4368 bindless = this->result;
4369 }
4370
4371 if (opcode == TGSI_OPCODE_TXD)
4372 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4373 else if (opcode == TGSI_OPCODE_TXQ) {
4374 if (ir->op == ir_query_levels) {
4375 /* the level is stored in W */
4376 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4377 result_dst.writemask = WRITEMASK_X;
4378 levels_src.swizzle = SWIZZLE_WWWW;
4379 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4380 } else
4381 inst = emit_asm(ir, opcode, result_dst, lod_info);
4382 } else if (opcode == TGSI_OPCODE_TXQS) {
4383 inst = emit_asm(ir, opcode, result_dst);
4384 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4385 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4386 } else if (opcode == TGSI_OPCODE_TEX2) {
4387 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4388 } else if (opcode == TGSI_OPCODE_TG4) {
4389 if (is_cube_array && ir->shadow_comparator) {
4390 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4391 } else {
4392 inst = emit_asm(ir, opcode, result_dst, coord, component);
4393 }
4394 } else
4395 inst = emit_asm(ir, opcode, result_dst, coord);
4396
4397 if (ir->shadow_comparator)
4398 inst->tex_shadow = GL_TRUE;
4399
4400 if (var->contains_bindless()) {
4401 inst->resource = bindless;
4402 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4403 SWIZZLE_X, SWIZZLE_Y);
4404 } else {
4405 inst->resource = sampler;
4406 inst->sampler_array_size = sampler_array_size;
4407 inst->sampler_base = sampler_base;
4408 }
4409
4410 if (ir->offset) {
4411 if (!inst->tex_offsets)
4412 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4413 MAX_GLSL_TEXTURE_OFFSET);
4414
4415 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4416 offset[i].file != PROGRAM_UNDEFINED; i++)
4417 inst->tex_offsets[i] = offset[i];
4418 inst->tex_offset_num_offset = i;
4419 }
4420
4421 inst->tex_target = sampler_type->sampler_index();
4422 inst->tex_type = ir->type->base_type;
4423
4424 this->result = result_src;
4425 }
4426
4427 void
4428 glsl_to_tgsi_visitor::visit(ir_return *ir)
4429 {
4430 assert(!ir->get_value());
4431
4432 emit_asm(ir, TGSI_OPCODE_RET);
4433 }
4434
4435 void
4436 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4437 {
4438 if (ir->condition) {
4439 ir->condition->accept(this);
4440 st_src_reg condition = this->result;
4441
4442 /* Convert the bool condition to a float so we can negate. */
4443 if (native_integers) {
4444 st_src_reg temp = get_temp(ir->condition->type);
4445 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4446 condition, st_src_reg_for_float(1.0));
4447 condition = temp;
4448 }
4449
4450 condition.negate = ~condition.negate;
4451 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4452 } else {
4453 /* unconditional kil */
4454 emit_asm(ir, TGSI_OPCODE_KILL);
4455 }
4456 }
4457
4458 void
4459 glsl_to_tgsi_visitor::visit(ir_if *ir)
4460 {
4461 unsigned if_opcode;
4462 glsl_to_tgsi_instruction *if_inst;
4463
4464 ir->condition->accept(this);
4465 assert(this->result.file != PROGRAM_UNDEFINED);
4466
4467 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4468
4469 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4470
4471 this->instructions.push_tail(if_inst);
4472
4473 visit_exec_list(&ir->then_instructions, this);
4474
4475 if (!ir->else_instructions.is_empty()) {
4476 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4477 visit_exec_list(&ir->else_instructions, this);
4478 }
4479
4480 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4481 }
4482
4483
4484 void
4485 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4486 {
4487 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4488
4489 ir->stream->accept(this);
4490 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4491 }
4492
4493 void
4494 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4495 {
4496 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4497
4498 ir->stream->accept(this);
4499 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4500 }
4501
4502 void
4503 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4504 {
4505 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4506 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4507
4508 emit_asm(ir, TGSI_OPCODE_BARRIER);
4509 }
4510
4511 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4512 {
4513 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4514
4515 result.file = PROGRAM_UNDEFINED;
4516 next_temp = 1;
4517 array_sizes = NULL;
4518 max_num_arrays = 0;
4519 next_array = 0;
4520 num_inputs = 0;
4521 num_outputs = 0;
4522 num_input_arrays = 0;
4523 num_output_arrays = 0;
4524 num_atomics = 0;
4525 num_atomic_arrays = 0;
4526 num_immediates = 0;
4527 num_address_regs = 0;
4528 samplers_used = 0;
4529 images_used = 0;
4530 indirect_addr_consts = false;
4531 wpos_transform_const = -1;
4532 native_integers = false;
4533 mem_ctx = ralloc_context(NULL);
4534 ctx = NULL;
4535 prog = NULL;
4536 precise = 0;
4537 shader_program = NULL;
4538 shader = NULL;
4539 options = NULL;
4540 have_sqrt = false;
4541 have_fma = false;
4542 use_shared_memory = false;
4543 has_tex_txf_lz = false;
4544 variables = NULL;
4545 }
4546
4547 static void var_destroy(struct hash_entry *entry)
4548 {
4549 variable_storage *storage = (variable_storage *)entry->data;
4550
4551 delete storage;
4552 }
4553
4554 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4555 {
4556 _mesa_hash_table_destroy(variables, var_destroy);
4557 free(array_sizes);
4558 ralloc_free(mem_ctx);
4559 }
4560
4561 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4562 {
4563 delete v;
4564 }
4565
4566
4567 /**
4568 * Count resources used by the given gpu program (number of texture
4569 * samplers, etc).
4570 */
4571 static void
4572 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4573 {
4574 v->samplers_used = 0;
4575 v->images_used = 0;
4576 prog->info.textures_used_by_txf = 0;
4577
4578 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4579 if (inst->info->is_tex) {
4580 for (int i = 0; i < inst->sampler_array_size; i++) {
4581 unsigned idx = inst->sampler_base + i;
4582 v->samplers_used |= 1u << idx;
4583
4584 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4585 v->sampler_types[idx] = inst->tex_type;
4586 v->sampler_targets[idx] =
4587 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4588
4589 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4590 prog->info.textures_used_by_txf |= 1u << idx;
4591 }
4592 }
4593 }
4594
4595 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4596 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4597
4598 if (inst->resource.file != PROGRAM_UNDEFINED && (
4599 is_resource_instruction(inst->op) ||
4600 inst->op == TGSI_OPCODE_STORE)) {
4601 if (inst->resource.file == PROGRAM_MEMORY) {
4602 v->use_shared_memory = true;
4603 } else if (inst->resource.file == PROGRAM_IMAGE) {
4604 for (int i = 0; i < inst->sampler_array_size; i++) {
4605 unsigned idx = inst->sampler_base + i;
4606 v->images_used |= 1 << idx;
4607 v->image_targets[idx] =
4608 st_translate_texture_target(inst->tex_target, false);
4609 v->image_formats[idx] = inst->image_format;
4610 }
4611 }
4612 }
4613 }
4614 prog->SamplersUsed = v->samplers_used;
4615
4616 if (v->shader_program != NULL)
4617 _mesa_update_shader_textures_used(v->shader_program, prog);
4618 }
4619
4620 /**
4621 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4622 * are read from the given src in this instruction
4623 */
4624 static int
4625 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4626 {
4627 int read_mask = 0, comp;
4628
4629 /* Now, given the src swizzle and the written channels, find which
4630 * components are actually read
4631 */
4632 for (comp = 0; comp < 4; ++comp) {
4633 const unsigned coord = GET_SWZ(src.swizzle, comp);
4634 assert(coord < 4);
4635 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4636 read_mask |= 1 << coord;
4637 }
4638
4639 return read_mask;
4640 }
4641
4642 /**
4643 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4644 * instruction is the first instruction to write to register T0. There are
4645 * several lowering passes done in GLSL IR (e.g. branches and
4646 * relative addressing) that create a large number of conditional assignments
4647 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4648 *
4649 * Here is why this conversion is safe:
4650 * CMP T0, T1 T2 T0 can be expanded to:
4651 * if (T1 < 0.0)
4652 * MOV T0, T2;
4653 * else
4654 * MOV T0, T0;
4655 *
4656 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4657 * as the original program. If (T1 < 0.0) evaluates to false, executing
4658 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4659 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4660 * because any instruction that was going to read from T0 after this was going
4661 * to read a garbage value anyway.
4662 */
4663 void
4664 glsl_to_tgsi_visitor::simplify_cmp(void)
4665 {
4666 int tempWritesSize = 0;
4667 unsigned *tempWrites = NULL;
4668 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4669
4670 memset(outputWrites, 0, sizeof(outputWrites));
4671
4672 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4673 unsigned prevWriteMask = 0;
4674
4675 /* Give up if we encounter relative addressing or flow control. */
4676 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4677 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4678 inst->info->is_branch ||
4679 inst->op == TGSI_OPCODE_CONT ||
4680 inst->op == TGSI_OPCODE_END ||
4681 inst->op == TGSI_OPCODE_RET) {
4682 break;
4683 }
4684
4685 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4686 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4687 prevWriteMask = outputWrites[inst->dst[0].index];
4688 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4689 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4690 if (inst->dst[0].index >= tempWritesSize) {
4691 const int inc = 4096;
4692
4693 tempWrites = (unsigned*)
4694 realloc(tempWrites,
4695 (tempWritesSize + inc) * sizeof(unsigned));
4696 if (!tempWrites)
4697 return;
4698
4699 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4700 tempWritesSize += inc;
4701 }
4702
4703 prevWriteMask = tempWrites[inst->dst[0].index];
4704 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4705 } else
4706 continue;
4707
4708 /* For a CMP to be considered a conditional write, the destination
4709 * register and source register two must be the same. */
4710 if (inst->op == TGSI_OPCODE_CMP
4711 && !(inst->dst[0].writemask & prevWriteMask)
4712 && inst->src[2].file == inst->dst[0].file
4713 && inst->src[2].index == inst->dst[0].index
4714 && inst->dst[0].writemask ==
4715 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4716
4717 inst->op = TGSI_OPCODE_MOV;
4718 inst->info = tgsi_get_opcode_info(inst->op);
4719 inst->src[0] = inst->src[1];
4720 }
4721 }
4722
4723 free(tempWrites);
4724 }
4725
4726 static void
4727 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4728 {
4729 if (src && src->file == PROGRAM_TEMPORARY) {
4730 int old_idx = src->index;
4731 if (renames[old_idx].valid)
4732 src->index = renames[old_idx].new_reg;
4733 }
4734 }
4735
4736 /* Replaces all references to a temporary register index with another index. */
4737 void
4738 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4739 {
4740 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4741 unsigned j;
4742 for (j = 0; j < num_inst_src_regs(inst); j++) {
4743 rename_temp_handle_src(renames, &inst->src[j]);
4744 rename_temp_handle_src(renames, inst->src[j].reladdr);
4745 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4746 }
4747
4748 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4749 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4750 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4751 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4752 }
4753
4754 rename_temp_handle_src(renames, &inst->resource);
4755 rename_temp_handle_src(renames, inst->resource.reladdr);
4756 rename_temp_handle_src(renames, inst->resource.reladdr2);
4757
4758 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4759 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4760 int old_idx = inst->dst[j].index;
4761 if (renames[old_idx].valid)
4762 inst->dst[j].index = renames[old_idx].new_reg;
4763 }
4764 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4765 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4766 }
4767 }
4768 }
4769
4770 void
4771 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4772 {
4773 int depth = 0; /* loop depth */
4774 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4775 unsigned i = 0, j;
4776
4777 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4778 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4779 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4780 if (first_writes[inst->dst[j].index] == -1)
4781 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4782 }
4783 }
4784
4785 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4786 if (depth++ == 0)
4787 loop_start = i;
4788 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4789 if (--depth == 0)
4790 loop_start = -1;
4791 }
4792 assert(depth >= 0);
4793 i++;
4794 }
4795 }
4796
4797 void
4798 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
4799 {
4800 int depth = 0; /* loop depth */
4801 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4802 unsigned i = 0, j;
4803
4804 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4805 for (j = 0; j < num_inst_src_regs(inst); j++) {
4806 if (inst->src[j].file == PROGRAM_TEMPORARY) {
4807 if (first_reads[inst->src[j].index] == -1)
4808 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
4809 }
4810 }
4811 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4812 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
4813 if (first_reads[inst->tex_offsets[j].index] == -1)
4814 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
4815 }
4816 }
4817 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4818 if (depth++ == 0)
4819 loop_start = i;
4820 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4821 if (--depth == 0)
4822 loop_start = -1;
4823 }
4824 assert(depth >= 0);
4825 i++;
4826 }
4827 }
4828
4829 void
4830 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
4831 {
4832 int depth = 0; /* loop depth */
4833 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4834 unsigned i = 0, j;
4835 int k;
4836 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4837 for (j = 0; j < num_inst_src_regs(inst); j++) {
4838 if (inst->src[j].file == PROGRAM_TEMPORARY)
4839 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
4840 }
4841 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4842 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4843 if (first_writes[inst->dst[j].index] == -1)
4844 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4845 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
4846 }
4847 }
4848 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4849 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
4850 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
4851 }
4852 if (inst->op == TGSI_OPCODE_BGNLOOP) {
4853 if (depth++ == 0)
4854 loop_start = i;
4855 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
4856 if (--depth == 0) {
4857 loop_start = -1;
4858 for (k = 0; k < this->next_temp; k++) {
4859 if (last_reads[k] == -2) {
4860 last_reads[k] = i;
4861 }
4862 }
4863 }
4864 }
4865 assert(depth >= 0);
4866 i++;
4867 }
4868 }
4869
4870 void
4871 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
4872 {
4873 int depth = 0; /* loop depth */
4874 int i = 0, k;
4875 unsigned j;
4876
4877 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4878 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4879 if (inst->dst[j].file == PROGRAM_TEMPORARY)
4880 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
4881 }
4882
4883 if (inst->op == TGSI_OPCODE_BGNLOOP)
4884 depth++;
4885 else if (inst->op == TGSI_OPCODE_ENDLOOP)
4886 if (--depth == 0) {
4887 for (k = 0; k < this->next_temp; k++) {
4888 if (last_writes[k] == -2) {
4889 last_writes[k] = i;
4890 }
4891 }
4892 }
4893 assert(depth >= 0);
4894 i++;
4895 }
4896 }
4897
4898 /*
4899 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4900 * channels for copy propagation and updates following instructions to
4901 * use the original versions.
4902 *
4903 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4904 * will occur. As an example, a TXP production before this pass:
4905 *
4906 * 0: MOV TEMP[1], INPUT[4].xyyy;
4907 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4908 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4909 *
4910 * and after:
4911 *
4912 * 0: MOV TEMP[1], INPUT[4].xyyy;
4913 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4914 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4915 *
4916 * which allows for dead code elimination on TEMP[1]'s writes.
4917 */
4918 void
4919 glsl_to_tgsi_visitor::copy_propagate(void)
4920 {
4921 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
4922 glsl_to_tgsi_instruction *,
4923 this->next_temp * 4);
4924 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
4925 int level = 0;
4926
4927 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4928 assert(inst->dst[0].file != PROGRAM_TEMPORARY
4929 || inst->dst[0].index < this->next_temp);
4930
4931 /* First, do any copy propagation possible into the src regs. */
4932 for (int r = 0; r < 3; r++) {
4933 glsl_to_tgsi_instruction *first = NULL;
4934 bool good = true;
4935 int acp_base = inst->src[r].index * 4;
4936
4937 if (inst->src[r].file != PROGRAM_TEMPORARY ||
4938 inst->src[r].reladdr ||
4939 inst->src[r].reladdr2)
4940 continue;
4941
4942 /* See if we can find entries in the ACP consisting of MOVs
4943 * from the same src register for all the swizzled channels
4944 * of this src register reference.
4945 */
4946 for (int i = 0; i < 4; i++) {
4947 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
4948 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
4949
4950 if (!copy_chan) {
4951 good = false;
4952 break;
4953 }
4954
4955 assert(acp_level[acp_base + src_chan] <= level);
4956
4957 if (!first) {
4958 first = copy_chan;
4959 } else {
4960 if (first->src[0].file != copy_chan->src[0].file ||
4961 first->src[0].index != copy_chan->src[0].index ||
4962 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
4963 first->src[0].index2D != copy_chan->src[0].index2D) {
4964 good = false;
4965 break;
4966 }
4967 }
4968 }
4969
4970 if (good) {
4971 /* We've now validated that we can copy-propagate to
4972 * replace this src register reference. Do it.
4973 */
4974 inst->src[r].file = first->src[0].file;
4975 inst->src[r].index = first->src[0].index;
4976 inst->src[r].index2D = first->src[0].index2D;
4977 inst->src[r].has_index2 = first->src[0].has_index2;
4978 inst->src[r].double_reg2 = first->src[0].double_reg2;
4979 inst->src[r].array_id = first->src[0].array_id;
4980
4981 int swizzle = 0;
4982 for (int i = 0; i < 4; i++) {
4983 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
4984 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
4985 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
4986 }
4987 inst->src[r].swizzle = swizzle;
4988 }
4989 }
4990
4991 switch (inst->op) {
4992 case TGSI_OPCODE_BGNLOOP:
4993 case TGSI_OPCODE_ENDLOOP:
4994 /* End of a basic block, clear the ACP entirely. */
4995 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
4996 break;
4997
4998 case TGSI_OPCODE_IF:
4999 case TGSI_OPCODE_UIF:
5000 ++level;
5001 break;
5002
5003 case TGSI_OPCODE_ENDIF:
5004 case TGSI_OPCODE_ELSE:
5005 /* Clear all channels written inside the block from the ACP, but
5006 * leaving those that were not touched.
5007 */
5008 for (int r = 0; r < this->next_temp; r++) {
5009 for (int c = 0; c < 4; c++) {
5010 if (!acp[4 * r + c])
5011 continue;
5012
5013 if (acp_level[4 * r + c] >= level)
5014 acp[4 * r + c] = NULL;
5015 }
5016 }
5017 if (inst->op == TGSI_OPCODE_ENDIF)
5018 --level;
5019 break;
5020
5021 default:
5022 /* Continuing the block, clear any written channels from
5023 * the ACP.
5024 */
5025 for (int d = 0; d < 2; d++) {
5026 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5027 /* Any temporary might be written, so no copy propagation
5028 * across this instruction.
5029 */
5030 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5031 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5032 inst->dst[d].reladdr) {
5033 /* Any output might be written, so no copy propagation
5034 * from outputs across this instruction.
5035 */
5036 for (int r = 0; r < this->next_temp; r++) {
5037 for (int c = 0; c < 4; c++) {
5038 if (!acp[4 * r + c])
5039 continue;
5040
5041 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5042 acp[4 * r + c] = NULL;
5043 }
5044 }
5045 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5046 inst->dst[d].file == PROGRAM_OUTPUT) {
5047 /* Clear where it's used as dst. */
5048 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5049 for (int c = 0; c < 4; c++) {
5050 if (inst->dst[d].writemask & (1 << c))
5051 acp[4 * inst->dst[d].index + c] = NULL;
5052 }
5053 }
5054
5055 /* Clear where it's used as src. */
5056 for (int r = 0; r < this->next_temp; r++) {
5057 for (int c = 0; c < 4; c++) {
5058 if (!acp[4 * r + c])
5059 continue;
5060
5061 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5062
5063 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5064 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5065 inst->dst[d].writemask & (1 << src_chan)) {
5066 acp[4 * r + c] = NULL;
5067 }
5068 }
5069 }
5070 }
5071 }
5072 break;
5073 }
5074
5075 /* If this is a copy, add it to the ACP. */
5076 if (inst->op == TGSI_OPCODE_MOV &&
5077 inst->dst[0].file == PROGRAM_TEMPORARY &&
5078 !(inst->dst[0].file == inst->src[0].file &&
5079 inst->dst[0].index == inst->src[0].index) &&
5080 !inst->dst[0].reladdr &&
5081 !inst->dst[0].reladdr2 &&
5082 !inst->saturate &&
5083 inst->src[0].file != PROGRAM_ARRAY &&
5084 (inst->src[0].file != PROGRAM_OUTPUT ||
5085 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5086 !inst->src[0].reladdr &&
5087 !inst->src[0].reladdr2 &&
5088 !inst->src[0].negate &&
5089 !inst->src[0].abs) {
5090 for (int i = 0; i < 4; i++) {
5091 if (inst->dst[0].writemask & (1 << i)) {
5092 acp[4 * inst->dst[0].index + i] = inst;
5093 acp_level[4 * inst->dst[0].index + i] = level;
5094 }
5095 }
5096 }
5097 }
5098
5099 ralloc_free(acp_level);
5100 ralloc_free(acp);
5101 }
5102
5103 static void
5104 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5105 {
5106 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5107 /* Clear where it's used as src. */
5108 int swz = GET_SWZ(reladdr->swizzle, 0);
5109 writes[4 * reladdr->index + swz] = NULL;
5110 }
5111 }
5112
5113 /*
5114 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5115 * code elimination.
5116 *
5117 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5118 * will occur. As an example, a TXP production after copy propagation but
5119 * before this pass:
5120 *
5121 * 0: MOV TEMP[1], INPUT[4].xyyy;
5122 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5123 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5124 *
5125 * and after this pass:
5126 *
5127 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5128 */
5129 int
5130 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5131 {
5132 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5133 glsl_to_tgsi_instruction *,
5134 this->next_temp * 4);
5135 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5136 int level = 0;
5137 int removed = 0;
5138
5139 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5140 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5141 || inst->dst[0].index < this->next_temp);
5142
5143 switch (inst->op) {
5144 case TGSI_OPCODE_BGNLOOP:
5145 case TGSI_OPCODE_ENDLOOP:
5146 case TGSI_OPCODE_CONT:
5147 case TGSI_OPCODE_BRK:
5148 /* End of a basic block, clear the write array entirely.
5149 *
5150 * This keeps us from killing dead code when the writes are
5151 * on either side of a loop, even when the register isn't touched
5152 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5153 * dead code of this type, so it shouldn't make a difference as long as
5154 * the dead code elimination pass in the GLSL compiler does its job.
5155 */
5156 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5157 break;
5158
5159 case TGSI_OPCODE_ENDIF:
5160 case TGSI_OPCODE_ELSE:
5161 /* Promote the recorded level of all channels written inside the
5162 * preceding if or else block to the level above the if/else block.
5163 */
5164 for (int r = 0; r < this->next_temp; r++) {
5165 for (int c = 0; c < 4; c++) {
5166 if (!writes[4 * r + c])
5167 continue;
5168
5169 if (write_level[4 * r + c] == level)
5170 write_level[4 * r + c] = level-1;
5171 }
5172 }
5173 if (inst->op == TGSI_OPCODE_ENDIF)
5174 --level;
5175 break;
5176
5177 case TGSI_OPCODE_IF:
5178 case TGSI_OPCODE_UIF:
5179 ++level;
5180 /* fallthrough to default case to mark the condition as read */
5181 default:
5182 /* Continuing the block, clear any channels from the write array that
5183 * are read by this instruction.
5184 */
5185 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5186 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5187 /* Any temporary might be read, so no dead code elimination
5188 * across this instruction.
5189 */
5190 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5191 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5192 /* Clear where it's used as src. */
5193 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5194 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5195 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5196 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5197
5198 for (int c = 0; c < 4; c++) {
5199 if (src_chans & (1 << c))
5200 writes[4 * inst->src[i].index + c] = NULL;
5201 }
5202 }
5203 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5204 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5205 }
5206 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5207 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5208 /* Any temporary might be read, so no dead code elimination
5209 * across this instruction.
5210 */
5211 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5212 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5213 /* Clear where it's used as src. */
5214 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5215 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5216 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5217 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5218
5219 for (int c = 0; c < 4; c++) {
5220 if (src_chans & (1 << c))
5221 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5222 }
5223 }
5224 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5225 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5226 }
5227
5228 if (inst->resource.file == PROGRAM_TEMPORARY) {
5229 int src_chans;
5230
5231 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5232 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5233 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5234 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5235
5236 for (int c = 0; c < 4; c++) {
5237 if (src_chans & (1 << c))
5238 writes[4 * inst->resource.index + c] = NULL;
5239 }
5240 }
5241 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5242 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5243
5244 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5245 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5246 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5247 }
5248 break;
5249 }
5250
5251 /* If this instruction writes to a temporary, add it to the write array.
5252 * If there is already an instruction in the write array for one or more
5253 * of the channels, flag that channel write as dead.
5254 */
5255 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5256 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5257 !inst->dst[i].reladdr) {
5258 for (int c = 0; c < 4; c++) {
5259 if (inst->dst[i].writemask & (1 << c)) {
5260 if (writes[4 * inst->dst[i].index + c]) {
5261 if (write_level[4 * inst->dst[i].index + c] < level)
5262 continue;
5263 else
5264 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5265 }
5266 writes[4 * inst->dst[i].index + c] = inst;
5267 write_level[4 * inst->dst[i].index + c] = level;
5268 }
5269 }
5270 }
5271 }
5272 }
5273
5274 /* Anything still in the write array at this point is dead code. */
5275 for (int r = 0; r < this->next_temp; r++) {
5276 for (int c = 0; c < 4; c++) {
5277 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5278 if (inst)
5279 inst->dead_mask |= (1 << c);
5280 }
5281 }
5282
5283 /* Now actually remove the instructions that are completely dead and update
5284 * the writemask of other instructions with dead channels.
5285 */
5286 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5287 if (!inst->dead_mask || !inst->dst[0].writemask)
5288 continue;
5289 /* No amount of dead masks should remove memory stores */
5290 if (inst->info->is_store)
5291 continue;
5292
5293 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5294 inst->remove();
5295 delete inst;
5296 removed++;
5297 } else {
5298 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5299 if (inst->dead_mask == WRITEMASK_XY ||
5300 inst->dead_mask == WRITEMASK_ZW)
5301 inst->dst[0].writemask &= ~(inst->dead_mask);
5302 } else
5303 inst->dst[0].writemask &= ~(inst->dead_mask);
5304 }
5305 }
5306
5307 ralloc_free(write_level);
5308 ralloc_free(writes);
5309
5310 return removed;
5311 }
5312
5313 /* merge DFRACEXP instructions into one. */
5314 void
5315 glsl_to_tgsi_visitor::merge_two_dsts(void)
5316 {
5317 /* We never delete inst, but we may delete its successor. */
5318 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5319 glsl_to_tgsi_instruction *inst2;
5320 unsigned defined;
5321
5322 if (num_inst_dst_regs(inst) != 2)
5323 continue;
5324
5325 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5326 inst->dst[1].file != PROGRAM_UNDEFINED)
5327 continue;
5328
5329 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5330 inst->dst[1].file != PROGRAM_UNDEFINED);
5331
5332 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5333 defined = 1;
5334 else
5335 defined = 0;
5336
5337 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5338 while (!inst2->is_tail_sentinel()) {
5339 if (inst->op == inst2->op &&
5340 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5341 inst->src[0].file == inst2->src[0].file &&
5342 inst->src[0].index == inst2->src[0].index &&
5343 inst->src[0].type == inst2->src[0].type &&
5344 inst->src[0].swizzle == inst2->src[0].swizzle)
5345 break;
5346 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5347 }
5348
5349 if (inst2->is_tail_sentinel()) {
5350 /* Undefined destinations are not allowed, substitute with an unused
5351 * temporary register.
5352 */
5353 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5354 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5355 inst->dst[defined ^ 1].writemask = 0;
5356 continue;
5357 }
5358
5359 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5360 inst2->remove();
5361 delete inst2;
5362 }
5363 }
5364
5365 /* Merges temporary registers together where possible to reduce the number of
5366 * registers needed to run a program.
5367 *
5368 * Produces optimal code only after copy propagation and dead code elimination
5369 * have been run. */
5370 void
5371 glsl_to_tgsi_visitor::merge_registers(void)
5372 {
5373 struct lifetime *lifetimes =
5374 rzalloc_array(mem_ctx, struct lifetime, this->next_temp);
5375
5376 if (get_temp_registers_required_lifetimes(mem_ctx, &this->instructions,
5377 this->next_temp, lifetimes)) {
5378 struct rename_reg_pair *renames =
5379 rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5380 get_temp_registers_remapping(mem_ctx, this->next_temp, lifetimes, renames);
5381 rename_temp_registers(renames);
5382 ralloc_free(renames);
5383 }
5384
5385 ralloc_free(lifetimes);
5386 }
5387
5388 /* Reassign indices to temporary registers by reusing unused indices created
5389 * by optimization passes. */
5390 void
5391 glsl_to_tgsi_visitor::renumber_registers(void)
5392 {
5393 int i = 0;
5394 int new_index = 0;
5395 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5396 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5397
5398 for (i = 0; i < this->next_temp; i++) {
5399 first_writes[i] = -1;
5400 }
5401 get_first_temp_write(first_writes);
5402
5403 for (i = 0; i < this->next_temp; i++) {
5404 if (first_writes[i] < 0) continue;
5405 if (i != new_index) {
5406 renames[i].new_reg = new_index;
5407 renames[i].valid = true;
5408 }
5409 new_index++;
5410 }
5411
5412 rename_temp_registers(renames);
5413 this->next_temp = new_index;
5414 ralloc_free(renames);
5415 ralloc_free(first_writes);
5416 }
5417
5418 /* ------------------------- TGSI conversion stuff -------------------------- */
5419
5420 /**
5421 * Intermediate state used during shader translation.
5422 */
5423 struct st_translate {
5424 struct ureg_program *ureg;
5425
5426 unsigned temps_size;
5427 struct ureg_dst *temps;
5428
5429 struct ureg_dst *arrays;
5430 unsigned num_temp_arrays;
5431 struct ureg_src *constants;
5432 int num_constants;
5433 struct ureg_src *immediates;
5434 int num_immediates;
5435 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5436 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5437 struct ureg_dst address[3];
5438 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5439 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5440 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5441 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5442 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5443 struct ureg_src shared_memory;
5444 unsigned *array_sizes;
5445 struct inout_decl *input_decls;
5446 unsigned num_input_decls;
5447 struct inout_decl *output_decls;
5448 unsigned num_output_decls;
5449
5450 const ubyte *inputMapping;
5451 const ubyte *outputMapping;
5452
5453 unsigned procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5454 bool need_uarl;
5455 };
5456
5457 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5458 enum tgsi_semantic
5459 _mesa_sysval_to_semantic(unsigned sysval)
5460 {
5461 switch (sysval) {
5462 /* Vertex shader */
5463 case SYSTEM_VALUE_VERTEX_ID:
5464 return TGSI_SEMANTIC_VERTEXID;
5465 case SYSTEM_VALUE_INSTANCE_ID:
5466 return TGSI_SEMANTIC_INSTANCEID;
5467 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
5468 return TGSI_SEMANTIC_VERTEXID_NOBASE;
5469 case SYSTEM_VALUE_BASE_VERTEX:
5470 return TGSI_SEMANTIC_BASEVERTEX;
5471 case SYSTEM_VALUE_BASE_INSTANCE:
5472 return TGSI_SEMANTIC_BASEINSTANCE;
5473 case SYSTEM_VALUE_DRAW_ID:
5474 return TGSI_SEMANTIC_DRAWID;
5475
5476 /* Geometry shader */
5477 case SYSTEM_VALUE_INVOCATION_ID:
5478 return TGSI_SEMANTIC_INVOCATIONID;
5479
5480 /* Fragment shader */
5481 case SYSTEM_VALUE_FRAG_COORD:
5482 return TGSI_SEMANTIC_POSITION;
5483 case SYSTEM_VALUE_FRONT_FACE:
5484 return TGSI_SEMANTIC_FACE;
5485 case SYSTEM_VALUE_SAMPLE_ID:
5486 return TGSI_SEMANTIC_SAMPLEID;
5487 case SYSTEM_VALUE_SAMPLE_POS:
5488 return TGSI_SEMANTIC_SAMPLEPOS;
5489 case SYSTEM_VALUE_SAMPLE_MASK_IN:
5490 return TGSI_SEMANTIC_SAMPLEMASK;
5491 case SYSTEM_VALUE_HELPER_INVOCATION:
5492 return TGSI_SEMANTIC_HELPER_INVOCATION;
5493
5494 /* Tessellation shader */
5495 case SYSTEM_VALUE_TESS_COORD:
5496 return TGSI_SEMANTIC_TESSCOORD;
5497 case SYSTEM_VALUE_VERTICES_IN:
5498 return TGSI_SEMANTIC_VERTICESIN;
5499 case SYSTEM_VALUE_PRIMITIVE_ID:
5500 return TGSI_SEMANTIC_PRIMID;
5501 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
5502 return TGSI_SEMANTIC_TESSOUTER;
5503 case SYSTEM_VALUE_TESS_LEVEL_INNER:
5504 return TGSI_SEMANTIC_TESSINNER;
5505
5506 /* Compute shader */
5507 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
5508 return TGSI_SEMANTIC_THREAD_ID;
5509 case SYSTEM_VALUE_WORK_GROUP_ID:
5510 return TGSI_SEMANTIC_BLOCK_ID;
5511 case SYSTEM_VALUE_NUM_WORK_GROUPS:
5512 return TGSI_SEMANTIC_GRID_SIZE;
5513 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
5514 return TGSI_SEMANTIC_BLOCK_SIZE;
5515
5516 /* ARB_shader_ballot */
5517 case SYSTEM_VALUE_SUBGROUP_SIZE:
5518 return TGSI_SEMANTIC_SUBGROUP_SIZE;
5519 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
5520 return TGSI_SEMANTIC_SUBGROUP_INVOCATION;
5521 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
5522 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
5523 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
5524 return TGSI_SEMANTIC_SUBGROUP_GE_MASK;
5525 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
5526 return TGSI_SEMANTIC_SUBGROUP_GT_MASK;
5527 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
5528 return TGSI_SEMANTIC_SUBGROUP_LE_MASK;
5529 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
5530 return TGSI_SEMANTIC_SUBGROUP_LT_MASK;
5531
5532 /* Unhandled */
5533 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
5534 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
5535 case SYSTEM_VALUE_VERTEX_CNT:
5536 default:
5537 assert(!"Unexpected SYSTEM_VALUE_ enum");
5538 return TGSI_SEMANTIC_COUNT;
5539 }
5540 }
5541
5542 /**
5543 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5544 */
5545 static struct ureg_src
5546 emit_immediate(struct st_translate *t,
5547 gl_constant_value values[4],
5548 GLenum type, int size)
5549 {
5550 struct ureg_program *ureg = t->ureg;
5551
5552 switch (type) {
5553 case GL_FLOAT:
5554 return ureg_DECL_immediate(ureg, &values[0].f, size);
5555 case GL_DOUBLE:
5556 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5557 case GL_INT64_ARB:
5558 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5559 case GL_UNSIGNED_INT64_ARB:
5560 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5561 case GL_INT:
5562 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5563 case GL_UNSIGNED_INT:
5564 case GL_BOOL:
5565 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5566 default:
5567 assert(!"should not get here - type must be float, int, uint, or bool");
5568 return ureg_src_undef();
5569 }
5570 }
5571
5572 /**
5573 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5574 */
5575 static struct ureg_dst
5576 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5577 unsigned array_id)
5578 {
5579 unsigned array;
5580
5581 switch (file) {
5582 case PROGRAM_UNDEFINED:
5583 return ureg_dst_undef();
5584
5585 case PROGRAM_TEMPORARY:
5586 /* Allocate space for temporaries on demand. */
5587 if (index >= t->temps_size) {
5588 const int inc = align(index - t->temps_size + 1, 4096);
5589
5590 t->temps = (struct ureg_dst*)
5591 realloc(t->temps,
5592 (t->temps_size + inc) * sizeof(struct ureg_dst));
5593 if (!t->temps)
5594 return ureg_dst_undef();
5595
5596 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5597 t->temps_size += inc;
5598 }
5599
5600 if (ureg_dst_is_undef(t->temps[index]))
5601 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5602
5603 return t->temps[index];
5604
5605 case PROGRAM_ARRAY:
5606 assert(array_id && array_id <= t->num_temp_arrays);
5607 array = array_id - 1;
5608
5609 if (ureg_dst_is_undef(t->arrays[array]))
5610 t->arrays[array] = ureg_DECL_array_temporary(
5611 t->ureg, t->array_sizes[array], TRUE);
5612
5613 return ureg_dst_array_offset(t->arrays[array], index);
5614
5615 case PROGRAM_OUTPUT:
5616 if (!array_id) {
5617 if (t->procType == PIPE_SHADER_FRAGMENT)
5618 assert(index < 2 * FRAG_RESULT_MAX);
5619 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5620 t->procType == PIPE_SHADER_TESS_EVAL)
5621 assert(index < VARYING_SLOT_TESS_MAX);
5622 else
5623 assert(index < VARYING_SLOT_MAX);
5624
5625 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5626 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5627 return t->outputs[t->outputMapping[index]];
5628 }
5629 else {
5630 struct inout_decl *decl =
5631 find_inout_array(t->output_decls,
5632 t->num_output_decls, array_id);
5633 unsigned mesa_index = decl->mesa_index;
5634 int slot = t->outputMapping[mesa_index];
5635
5636 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5637
5638 struct ureg_dst dst = t->outputs[slot];
5639 dst.ArrayID = array_id;
5640 return ureg_dst_array_offset(dst, index - mesa_index);
5641 }
5642
5643 case PROGRAM_ADDRESS:
5644 return t->address[index];
5645
5646 default:
5647 assert(!"unknown dst register file");
5648 return ureg_dst_undef();
5649 }
5650 }
5651
5652 static struct ureg_src
5653 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5654
5655 static struct ureg_src
5656 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5657 unsigned addr_index)
5658 {
5659 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5660 return ureg_src(t->address[addr_index]);
5661
5662 return translate_src(t, reladdr);
5663 }
5664
5665 /**
5666 * Create a TGSI ureg_dst register from an st_dst_reg.
5667 */
5668 static struct ureg_dst
5669 translate_dst(struct st_translate *t,
5670 const st_dst_reg *dst_reg,
5671 bool saturate)
5672 {
5673 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5674 dst_reg->array_id);
5675
5676 if (dst.File == TGSI_FILE_NULL)
5677 return dst;
5678
5679 dst = ureg_writemask(dst, dst_reg->writemask);
5680
5681 if (saturate)
5682 dst = ureg_saturate(dst);
5683
5684 if (dst_reg->reladdr != NULL) {
5685 assert(dst_reg->file != PROGRAM_TEMPORARY);
5686 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5687 }
5688
5689 if (dst_reg->has_index2) {
5690 if (dst_reg->reladdr2)
5691 dst = ureg_dst_dimension_indirect(dst,
5692 translate_addr(t, dst_reg->reladdr2, 1),
5693 dst_reg->index2D);
5694 else
5695 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5696 }
5697
5698 return dst;
5699 }
5700
5701 /**
5702 * Create a TGSI ureg_src register from an st_src_reg.
5703 */
5704 static struct ureg_src
5705 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5706 {
5707 struct ureg_src src;
5708 int index = src_reg->index;
5709 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5710
5711 switch (src_reg->file) {
5712 case PROGRAM_UNDEFINED:
5713 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5714 break;
5715
5716 case PROGRAM_TEMPORARY:
5717 case PROGRAM_ARRAY:
5718 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5719 src_reg->array_id));
5720 break;
5721
5722 case PROGRAM_OUTPUT: {
5723 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5724 src_reg->array_id);
5725 assert(dst.WriteMask != 0);
5726 unsigned shift = ffs(dst.WriteMask) - 1;
5727 src = ureg_swizzle(ureg_src(dst),
5728 shift,
5729 MIN2(shift + 1, 3),
5730 MIN2(shift + 2, 3),
5731 MIN2(shift + 3, 3));
5732 break;
5733 }
5734
5735 case PROGRAM_UNIFORM:
5736 assert(src_reg->index >= 0);
5737 src = src_reg->index < t->num_constants ?
5738 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
5739 break;
5740 case PROGRAM_STATE_VAR:
5741 case PROGRAM_CONSTANT: /* ie, immediate */
5742 if (src_reg->has_index2)
5743 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
5744 else
5745 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
5746 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
5747 break;
5748
5749 case PROGRAM_IMMEDIATE:
5750 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
5751 src = t->immediates[src_reg->index];
5752 break;
5753
5754 case PROGRAM_INPUT:
5755 /* GLSL inputs are 64-bit containers, so we have to
5756 * map back to the original index and add the offset after
5757 * mapping. */
5758 index -= double_reg2;
5759 if (!src_reg->array_id) {
5760 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
5761 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
5762 src = t->inputs[t->inputMapping[index] + double_reg2];
5763 }
5764 else {
5765 struct inout_decl *decl = find_inout_array(t->input_decls,
5766 t->num_input_decls,
5767 src_reg->array_id);
5768 unsigned mesa_index = decl->mesa_index;
5769 int slot = t->inputMapping[mesa_index];
5770
5771 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
5772
5773 src = t->inputs[slot];
5774 src.ArrayID = src_reg->array_id;
5775 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
5776 }
5777 break;
5778
5779 case PROGRAM_ADDRESS:
5780 src = ureg_src(t->address[src_reg->index]);
5781 break;
5782
5783 case PROGRAM_SYSTEM_VALUE:
5784 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
5785 src = t->systemValues[src_reg->index];
5786 break;
5787
5788 case PROGRAM_HW_ATOMIC:
5789 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
5790 src_reg->array_id);
5791 break;
5792
5793 default:
5794 assert(!"unknown src register file");
5795 return ureg_src_undef();
5796 }
5797
5798 if (src_reg->has_index2) {
5799 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5800 * and UBO constant buffers (buffer, position).
5801 */
5802 if (src_reg->reladdr2)
5803 src = ureg_src_dimension_indirect(src,
5804 translate_addr(t, src_reg->reladdr2, 1),
5805 src_reg->index2D);
5806 else
5807 src = ureg_src_dimension(src, src_reg->index2D);
5808 }
5809
5810 src = ureg_swizzle(src,
5811 GET_SWZ(src_reg->swizzle, 0) & 0x3,
5812 GET_SWZ(src_reg->swizzle, 1) & 0x3,
5813 GET_SWZ(src_reg->swizzle, 2) & 0x3,
5814 GET_SWZ(src_reg->swizzle, 3) & 0x3);
5815
5816 if (src_reg->abs)
5817 src = ureg_abs(src);
5818
5819 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
5820 src = ureg_negate(src);
5821
5822 if (src_reg->reladdr != NULL) {
5823 assert(src_reg->file != PROGRAM_TEMPORARY);
5824 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
5825 }
5826
5827 return src;
5828 }
5829
5830 static struct tgsi_texture_offset
5831 translate_tex_offset(struct st_translate *t,
5832 const st_src_reg *in_offset)
5833 {
5834 struct tgsi_texture_offset offset;
5835 struct ureg_src src = translate_src(t, in_offset);
5836
5837 offset.File = src.File;
5838 offset.Index = src.Index;
5839 offset.SwizzleX = src.SwizzleX;
5840 offset.SwizzleY = src.SwizzleY;
5841 offset.SwizzleZ = src.SwizzleZ;
5842 offset.Padding = 0;
5843
5844 assert(!src.Indirect);
5845 assert(!src.DimIndirect);
5846 assert(!src.Dimension);
5847 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
5848 assert(!src.Negate);
5849
5850 return offset;
5851 }
5852
5853 static void
5854 compile_tgsi_instruction(struct st_translate *t,
5855 const glsl_to_tgsi_instruction *inst)
5856 {
5857 struct ureg_program *ureg = t->ureg;
5858 int i;
5859 struct ureg_dst dst[2];
5860 struct ureg_src src[4];
5861 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
5862
5863 int num_dst;
5864 int num_src;
5865 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
5866
5867 num_dst = num_inst_dst_regs(inst);
5868 num_src = num_inst_src_regs(inst);
5869
5870 for (i = 0; i < num_dst; i++)
5871 dst[i] = translate_dst(t,
5872 &inst->dst[i],
5873 inst->saturate);
5874
5875 for (i = 0; i < num_src; i++)
5876 src[i] = translate_src(t, &inst->src[i]);
5877
5878 switch (inst->op) {
5879 case TGSI_OPCODE_BGNLOOP:
5880 case TGSI_OPCODE_ELSE:
5881 case TGSI_OPCODE_ENDLOOP:
5882 case TGSI_OPCODE_IF:
5883 case TGSI_OPCODE_UIF:
5884 assert(num_dst == 0);
5885 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
5886 return;
5887
5888 case TGSI_OPCODE_TEX:
5889 case TGSI_OPCODE_TEX_LZ:
5890 case TGSI_OPCODE_TXB:
5891 case TGSI_OPCODE_TXD:
5892 case TGSI_OPCODE_TXL:
5893 case TGSI_OPCODE_TXP:
5894 case TGSI_OPCODE_TXQ:
5895 case TGSI_OPCODE_TXQS:
5896 case TGSI_OPCODE_TXF:
5897 case TGSI_OPCODE_TXF_LZ:
5898 case TGSI_OPCODE_TEX2:
5899 case TGSI_OPCODE_TXB2:
5900 case TGSI_OPCODE_TXL2:
5901 case TGSI_OPCODE_TG4:
5902 case TGSI_OPCODE_LODQ:
5903 if (inst->resource.file == PROGRAM_SAMPLER) {
5904 src[num_src] = t->samplers[inst->resource.index];
5905 } else {
5906 /* Bindless samplers. */
5907 src[num_src] = translate_src(t, &inst->resource);
5908 }
5909 assert(src[num_src].File != TGSI_FILE_NULL);
5910 if (inst->resource.reladdr)
5911 src[num_src] =
5912 ureg_src_indirect(src[num_src],
5913 translate_addr(t, inst->resource.reladdr, 2));
5914 num_src++;
5915 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
5916 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
5917 }
5918 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5919
5920 ureg_tex_insn(ureg,
5921 inst->op,
5922 dst, num_dst,
5923 tex_target,
5924 st_translate_texture_type(inst->tex_type),
5925 texoffsets, inst->tex_offset_num_offset,
5926 src, num_src);
5927 return;
5928
5929 case TGSI_OPCODE_RESQ:
5930 case TGSI_OPCODE_LOAD:
5931 case TGSI_OPCODE_ATOMUADD:
5932 case TGSI_OPCODE_ATOMXCHG:
5933 case TGSI_OPCODE_ATOMCAS:
5934 case TGSI_OPCODE_ATOMAND:
5935 case TGSI_OPCODE_ATOMOR:
5936 case TGSI_OPCODE_ATOMXOR:
5937 case TGSI_OPCODE_ATOMUMIN:
5938 case TGSI_OPCODE_ATOMUMAX:
5939 case TGSI_OPCODE_ATOMIMIN:
5940 case TGSI_OPCODE_ATOMIMAX:
5941 for (i = num_src - 1; i >= 0; i--)
5942 src[i + 1] = src[i];
5943 num_src++;
5944 if (inst->resource.file == PROGRAM_MEMORY) {
5945 src[0] = t->shared_memory;
5946 } else if (inst->resource.file == PROGRAM_BUFFER) {
5947 src[0] = t->buffers[inst->resource.index];
5948 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
5949 src[0] = translate_src(t, &inst->resource);
5950 } else if (inst->resource.file == PROGRAM_CONSTANT) {
5951 assert(inst->resource.has_index2);
5952 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
5953 } else {
5954 assert(inst->resource.file != PROGRAM_UNDEFINED);
5955 if (inst->resource.file == PROGRAM_IMAGE) {
5956 src[0] = t->images[inst->resource.index];
5957 } else {
5958 /* Bindless images. */
5959 src[0] = translate_src(t, &inst->resource);
5960 }
5961 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5962 }
5963 if (inst->resource.reladdr)
5964 src[0] = ureg_src_indirect(src[0],
5965 translate_addr(t, inst->resource.reladdr, 2));
5966 assert(src[0].File != TGSI_FILE_NULL);
5967 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
5968 inst->buffer_access,
5969 tex_target, inst->image_format);
5970 break;
5971
5972 case TGSI_OPCODE_STORE:
5973 if (inst->resource.file == PROGRAM_MEMORY) {
5974 dst[0] = ureg_dst(t->shared_memory);
5975 } else if (inst->resource.file == PROGRAM_BUFFER) {
5976 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
5977 } else {
5978 if (inst->resource.file == PROGRAM_IMAGE) {
5979 dst[0] = ureg_dst(t->images[inst->resource.index]);
5980 } else {
5981 /* Bindless images. */
5982 dst[0] = ureg_dst(translate_src(t, &inst->resource));
5983 }
5984 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
5985 }
5986 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
5987 if (inst->resource.reladdr)
5988 dst[0] = ureg_dst_indirect(dst[0],
5989 translate_addr(t, inst->resource.reladdr, 2));
5990 assert(dst[0].File != TGSI_FILE_NULL);
5991 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
5992 inst->buffer_access,
5993 tex_target, inst->image_format);
5994 break;
5995
5996 default:
5997 ureg_insn(ureg,
5998 inst->op,
5999 dst, num_dst,
6000 src, num_src, inst->precise);
6001 break;
6002 }
6003 }
6004
6005 /**
6006 * Emit the TGSI instructions for inverting and adjusting WPOS.
6007 * This code is unavoidable because it also depends on whether
6008 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6009 */
6010 static void
6011 emit_wpos_adjustment(struct gl_context *ctx,
6012 struct st_translate *t,
6013 int wpos_transform_const,
6014 boolean invert,
6015 GLfloat adjX, GLfloat adjY[2])
6016 {
6017 struct ureg_program *ureg = t->ureg;
6018
6019 assert(wpos_transform_const >= 0);
6020
6021 /* Fragment program uses fragment position input.
6022 * Need to replace instances of INPUT[WPOS] with temp T
6023 * where T = INPUT[WPOS] is inverted by Y.
6024 */
6025 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6026 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6027 struct ureg_src *wpos =
6028 ctx->Const.GLSLFragCoordIsSysVal ?
6029 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6030 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6031 struct ureg_src wpos_input = *wpos;
6032
6033 /* First, apply the coordinate shift: */
6034 if (adjX || adjY[0] || adjY[1]) {
6035 if (adjY[0] != adjY[1]) {
6036 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6037 * depending on whether inversion is actually going to be applied
6038 * or not, which is determined by testing against the inversion
6039 * state variable used below, which will be either +1 or -1.
6040 */
6041 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6042
6043 ureg_CMP(ureg, adj_temp,
6044 ureg_scalar(wpostrans, invert ? 2 : 0),
6045 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6046 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6047 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6048 } else {
6049 ureg_ADD(ureg, wpos_temp, wpos_input,
6050 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6051 }
6052 wpos_input = ureg_src(wpos_temp);
6053 } else {
6054 /* MOV wpos_temp, input[wpos]
6055 */
6056 ureg_MOV(ureg, wpos_temp, wpos_input);
6057 }
6058
6059 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6060 * inversion/identity, or the other way around if we're drawing to an FBO.
6061 */
6062 if (invert) {
6063 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6064 */
6065 ureg_MAD(ureg,
6066 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6067 wpos_input,
6068 ureg_scalar(wpostrans, 0),
6069 ureg_scalar(wpostrans, 1));
6070 } else {
6071 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6072 */
6073 ureg_MAD(ureg,
6074 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6075 wpos_input,
6076 ureg_scalar(wpostrans, 2),
6077 ureg_scalar(wpostrans, 3));
6078 }
6079
6080 /* Use wpos_temp as position input from here on:
6081 */
6082 *wpos = ureg_src(wpos_temp);
6083 }
6084
6085
6086 /**
6087 * Emit fragment position/ooordinate code.
6088 */
6089 static void
6090 emit_wpos(struct st_context *st,
6091 struct st_translate *t,
6092 const struct gl_program *program,
6093 struct ureg_program *ureg,
6094 int wpos_transform_const)
6095 {
6096 struct pipe_screen *pscreen = st->pipe->screen;
6097 GLfloat adjX = 0.0f;
6098 GLfloat adjY[2] = { 0.0f, 0.0f };
6099 boolean invert = FALSE;
6100
6101 /* Query the pixel center conventions supported by the pipe driver and set
6102 * adjX, adjY to help out if it cannot handle the requested one internally.
6103 *
6104 * The bias of the y-coordinate depends on whether y-inversion takes place
6105 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6106 * drawing to an FBO (causes additional inversion), and whether the pipe
6107 * driver origin and the requested origin differ (the latter condition is
6108 * stored in the 'invert' variable).
6109 *
6110 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6111 *
6112 * center shift only:
6113 * i -> h: +0.5
6114 * h -> i: -0.5
6115 *
6116 * inversion only:
6117 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6118 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6119 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6120 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6121 *
6122 * inversion and center shift:
6123 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6124 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6125 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6126 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6127 */
6128 if (program->OriginUpperLeft) {
6129 /* Fragment shader wants origin in upper-left */
6130 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6131 /* the driver supports upper-left origin */
6132 }
6133 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6134 /* the driver supports lower-left origin, need to invert Y */
6135 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6136 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6137 invert = TRUE;
6138 }
6139 else
6140 assert(0);
6141 }
6142 else {
6143 /* Fragment shader wants origin in lower-left */
6144 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6145 /* the driver supports lower-left origin */
6146 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6147 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6148 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6149 /* the driver supports upper-left origin, need to invert Y */
6150 invert = TRUE;
6151 else
6152 assert(0);
6153 }
6154
6155 if (program->PixelCenterInteger) {
6156 /* Fragment shader wants pixel center integer */
6157 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6158 /* the driver supports pixel center integer */
6159 adjY[1] = 1.0f;
6160 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6161 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6162 }
6163 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6164 /* the driver supports pixel center half integer, need to bias X,Y */
6165 adjX = -0.5f;
6166 adjY[0] = -0.5f;
6167 adjY[1] = 0.5f;
6168 }
6169 else
6170 assert(0);
6171 }
6172 else {
6173 /* Fragment shader wants pixel center half integer */
6174 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6175 /* the driver supports pixel center half integer */
6176 }
6177 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6178 /* the driver supports pixel center integer, need to bias X,Y */
6179 adjX = adjY[0] = adjY[1] = 0.5f;
6180 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6181 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6182 }
6183 else
6184 assert(0);
6185 }
6186
6187 /* we invert after adjustment so that we avoid the MOV to temporary,
6188 * and reuse the adjustment ADD instead */
6189 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6190 }
6191
6192 /**
6193 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6194 * TGSI uses +1 for front, -1 for back.
6195 * This function converts the TGSI value to the GL value. Simply clamping/
6196 * saturating the value to [0,1] does the job.
6197 */
6198 static void
6199 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6200 {
6201 struct ureg_program *ureg = t->ureg;
6202 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6203 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6204
6205 if (ctx->Const.NativeIntegers) {
6206 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6207 }
6208 else {
6209 /* MOV_SAT face_temp, input[face] */
6210 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6211 }
6212
6213 /* Use face_temp as face input from here on: */
6214 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6215 }
6216
6217 static void
6218 emit_compute_block_size(const struct gl_program *prog,
6219 struct ureg_program *ureg) {
6220 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
6221 prog->info.cs.local_size[0]);
6222 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
6223 prog->info.cs.local_size[1]);
6224 ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
6225 prog->info.cs.local_size[2]);
6226 }
6227
6228 struct sort_inout_decls {
6229 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6230 return mapping[a.mesa_index] < mapping[b.mesa_index];
6231 }
6232
6233 const ubyte *mapping;
6234 };
6235
6236 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6237 *
6238 * This is for the benefit of older drivers which are broken when the
6239 * declarations aren't sorted in this way.
6240 */
6241 static void
6242 sort_inout_decls_by_slot(struct inout_decl *decls,
6243 unsigned count,
6244 const ubyte mapping[])
6245 {
6246 sort_inout_decls sorter;
6247 sorter.mapping = mapping;
6248 std::sort(decls, decls + count, sorter);
6249 }
6250
6251 static enum tgsi_interpolate_mode
6252 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
6253 {
6254 switch (glsl_qual) {
6255 case INTERP_MODE_NONE:
6256 if (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1)
6257 return TGSI_INTERPOLATE_COLOR;
6258 return TGSI_INTERPOLATE_PERSPECTIVE;
6259 case INTERP_MODE_SMOOTH:
6260 return TGSI_INTERPOLATE_PERSPECTIVE;
6261 case INTERP_MODE_FLAT:
6262 return TGSI_INTERPOLATE_CONSTANT;
6263 case INTERP_MODE_NOPERSPECTIVE:
6264 return TGSI_INTERPOLATE_LINEAR;
6265 default:
6266 assert(0 && "unexpected interp mode in st_translate_interp()");
6267 return TGSI_INTERPOLATE_PERSPECTIVE;
6268 }
6269 }
6270
6271 /**
6272 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6273 * \param program the program to translate
6274 * \param numInputs number of input registers used
6275 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6276 * input indexes
6277 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6278 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6279 * each input
6280 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6281 * \param numOutputs number of output registers used
6282 * \param outputMapping maps Mesa fragment program outputs to TGSI
6283 * generic outputs
6284 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6285 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6286 * each output
6287 *
6288 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6289 */
6290 extern "C" enum pipe_error
6291 st_translate_program(
6292 struct gl_context *ctx,
6293 uint procType,
6294 struct ureg_program *ureg,
6295 glsl_to_tgsi_visitor *program,
6296 const struct gl_program *proginfo,
6297 GLuint numInputs,
6298 const ubyte inputMapping[],
6299 const ubyte inputSlotToAttr[],
6300 const ubyte inputSemanticName[],
6301 const ubyte inputSemanticIndex[],
6302 const ubyte interpMode[],
6303 GLuint numOutputs,
6304 const ubyte outputMapping[],
6305 const ubyte outputSemanticName[],
6306 const ubyte outputSemanticIndex[])
6307 {
6308 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6309 struct st_translate *t;
6310 unsigned i;
6311 struct gl_program_constants *frag_const =
6312 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6313 enum pipe_error ret = PIPE_OK;
6314
6315 assert(numInputs <= ARRAY_SIZE(t->inputs));
6316 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6317
6318 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6319 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6320 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6321 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6322 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6323 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6324 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6325 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6326 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op, TGSI_OPCODE_LAST - 1);
6327
6328 t = CALLOC_STRUCT(st_translate);
6329 if (!t) {
6330 ret = PIPE_ERROR_OUT_OF_MEMORY;
6331 goto out;
6332 }
6333
6334 t->procType = procType;
6335 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6336 t->inputMapping = inputMapping;
6337 t->outputMapping = outputMapping;
6338 t->ureg = ureg;
6339 t->num_temp_arrays = program->next_array;
6340 if (t->num_temp_arrays)
6341 t->arrays = (struct ureg_dst*)
6342 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6343
6344 /*
6345 * Declare input attributes.
6346 */
6347 switch (procType) {
6348 case PIPE_SHADER_FRAGMENT:
6349 case PIPE_SHADER_GEOMETRY:
6350 case PIPE_SHADER_TESS_EVAL:
6351 case PIPE_SHADER_TESS_CTRL:
6352 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6353
6354 for (i = 0; i < program->num_inputs; ++i) {
6355 struct inout_decl *decl = &program->inputs[i];
6356 unsigned slot = inputMapping[decl->mesa_index];
6357 struct ureg_src src;
6358 ubyte tgsi_usage_mask = decl->usage_mask;
6359
6360 if (glsl_base_type_is_64bit(decl->base_type)) {
6361 if (tgsi_usage_mask == 1)
6362 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6363 else if (tgsi_usage_mask == 2)
6364 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6365 else
6366 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6367 }
6368
6369 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6370 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6371 if (procType == PIPE_SHADER_FRAGMENT) {
6372 assert(interpMode);
6373 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6374 (enum tgsi_interpolate_mode) interpMode[slot] :
6375 st_translate_interp(decl->interp, inputSlotToAttr[slot]);
6376
6377 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6378 }
6379
6380 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6381 (enum tgsi_semantic) inputSemanticName[slot],
6382 inputSemanticIndex[slot],
6383 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6384 decl->array_id, decl->size);
6385
6386 for (unsigned j = 0; j < decl->size; ++j) {
6387 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6388 /* The ArrayID is set up in dst_register */
6389 t->inputs[slot + j] = src;
6390 t->inputs[slot + j].ArrayID = 0;
6391 t->inputs[slot + j].Index += j;
6392 }
6393 }
6394 }
6395 break;
6396 case PIPE_SHADER_VERTEX:
6397 for (i = 0; i < numInputs; i++) {
6398 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6399 }
6400 break;
6401 case PIPE_SHADER_COMPUTE:
6402 break;
6403 default:
6404 assert(0);
6405 }
6406
6407 /*
6408 * Declare output attributes.
6409 */
6410 switch (procType) {
6411 case PIPE_SHADER_FRAGMENT:
6412 case PIPE_SHADER_COMPUTE:
6413 break;
6414 case PIPE_SHADER_GEOMETRY:
6415 case PIPE_SHADER_TESS_EVAL:
6416 case PIPE_SHADER_TESS_CTRL:
6417 case PIPE_SHADER_VERTEX:
6418 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6419
6420 for (i = 0; i < program->num_outputs; ++i) {
6421 struct inout_decl *decl = &program->outputs[i];
6422 unsigned slot = outputMapping[decl->mesa_index];
6423 struct ureg_dst dst;
6424 ubyte tgsi_usage_mask = decl->usage_mask;
6425
6426 if (glsl_base_type_is_64bit(decl->base_type)) {
6427 if (tgsi_usage_mask == 1)
6428 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6429 else if (tgsi_usage_mask == 2)
6430 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6431 else
6432 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6433 }
6434
6435 dst = ureg_DECL_output_layout(ureg,
6436 (enum tgsi_semantic) outputSemanticName[slot],
6437 outputSemanticIndex[slot],
6438 decl->gs_out_streams,
6439 slot, tgsi_usage_mask, decl->array_id, decl->size);
6440
6441 for (unsigned j = 0; j < decl->size; ++j) {
6442 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6443 /* The ArrayID is set up in dst_register */
6444 t->outputs[slot + j] = dst;
6445 t->outputs[slot + j].ArrayID = 0;
6446 t->outputs[slot + j].Index += j;
6447 }
6448 }
6449 }
6450 break;
6451 default:
6452 assert(0);
6453 }
6454
6455 if (procType == PIPE_SHADER_FRAGMENT) {
6456 if (program->shader->Program->info.fs.early_fragment_tests ||
6457 program->shader->Program->info.fs.post_depth_coverage) {
6458 ureg_property(ureg, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 1);
6459
6460 if (program->shader->Program->info.fs.post_depth_coverage)
6461 ureg_property(ureg, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 1);
6462 }
6463
6464 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6465 /* Must do this after setting up t->inputs. */
6466 emit_wpos(st_context(ctx), t, proginfo, ureg,
6467 program->wpos_transform_const);
6468 }
6469
6470 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6471 emit_face_var(ctx, t);
6472
6473 for (i = 0; i < numOutputs; i++) {
6474 switch (outputSemanticName[i]) {
6475 case TGSI_SEMANTIC_POSITION:
6476 t->outputs[i] = ureg_DECL_output(ureg,
6477 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6478 outputSemanticIndex[i]);
6479 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6480 break;
6481 case TGSI_SEMANTIC_STENCIL:
6482 t->outputs[i] = ureg_DECL_output(ureg,
6483 TGSI_SEMANTIC_STENCIL, /* Stencil */
6484 outputSemanticIndex[i]);
6485 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6486 break;
6487 case TGSI_SEMANTIC_COLOR:
6488 t->outputs[i] = ureg_DECL_output(ureg,
6489 TGSI_SEMANTIC_COLOR,
6490 outputSemanticIndex[i]);
6491 break;
6492 case TGSI_SEMANTIC_SAMPLEMASK:
6493 t->outputs[i] = ureg_DECL_output(ureg,
6494 TGSI_SEMANTIC_SAMPLEMASK,
6495 outputSemanticIndex[i]);
6496 /* TODO: If we ever support more than 32 samples, this will have
6497 * to become an array.
6498 */
6499 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6500 break;
6501 default:
6502 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6503 ret = PIPE_ERROR_BAD_INPUT;
6504 goto out;
6505 }
6506 }
6507 }
6508 else if (procType == PIPE_SHADER_VERTEX) {
6509 for (i = 0; i < numOutputs; i++) {
6510 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6511 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6512 ureg_MOV(ureg,
6513 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6514 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6515 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6516 }
6517 }
6518 }
6519
6520 if (procType == PIPE_SHADER_COMPUTE) {
6521 emit_compute_block_size(proginfo, ureg);
6522 }
6523
6524 /* Declare address register.
6525 */
6526 if (program->num_address_regs > 0) {
6527 assert(program->num_address_regs <= 3);
6528 for (int i = 0; i < program->num_address_regs; i++)
6529 t->address[i] = ureg_DECL_address(ureg);
6530 }
6531
6532 /* Declare misc input registers
6533 */
6534 {
6535 GLbitfield64 sysInputs = proginfo->info.system_values_read;
6536
6537 for (i = 0; sysInputs; i++) {
6538 if (sysInputs & (1ull << i)) {
6539 enum tgsi_semantic semName = _mesa_sysval_to_semantic(i);
6540
6541 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6542
6543 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6544 semName == TGSI_SEMANTIC_VERTEXID) {
6545 /* From Gallium perspective, these system values are always
6546 * integer, and require native integer support. However, if
6547 * native integer is supported on the vertex stage but not the
6548 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6549 * assumes these system values are floats. To resolve the
6550 * inconsistency, we insert a U2F.
6551 */
6552 struct st_context *st = st_context(ctx);
6553 struct pipe_screen *pscreen = st->pipe->screen;
6554 assert(procType == PIPE_SHADER_VERTEX);
6555 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6556 (void) pscreen;
6557 if (!ctx->Const.NativeIntegers) {
6558 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6559 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6560 t->systemValues[i]);
6561 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6562 }
6563 }
6564
6565 if (procType == PIPE_SHADER_FRAGMENT &&
6566 semName == TGSI_SEMANTIC_POSITION)
6567 emit_wpos(st_context(ctx), t, proginfo, ureg,
6568 program->wpos_transform_const);
6569
6570 sysInputs &= ~(1ull << i);
6571 }
6572 }
6573 }
6574
6575 t->array_sizes = program->array_sizes;
6576 t->input_decls = program->inputs;
6577 t->num_input_decls = program->num_inputs;
6578 t->output_decls = program->outputs;
6579 t->num_output_decls = program->num_outputs;
6580
6581 /* Emit constants and uniforms. TGSI uses a single index space for these,
6582 * so we put all the translated regs in t->constants.
6583 */
6584 if (proginfo->Parameters) {
6585 t->constants = (struct ureg_src *)
6586 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6587 if (t->constants == NULL) {
6588 ret = PIPE_ERROR_OUT_OF_MEMORY;
6589 goto out;
6590 }
6591 t->num_constants = proginfo->Parameters->NumParameters;
6592
6593 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6594 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6595
6596 switch (proginfo->Parameters->Parameters[i].Type) {
6597 case PROGRAM_STATE_VAR:
6598 case PROGRAM_UNIFORM:
6599 t->constants[i] = ureg_DECL_constant(ureg, i);
6600 break;
6601
6602 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6603 * addressing of the const buffer.
6604 * FIXME: Be smarter and recognize param arrays:
6605 * indirect addressing is only valid within the referenced
6606 * array.
6607 */
6608 case PROGRAM_CONSTANT:
6609 if (program->indirect_addr_consts)
6610 t->constants[i] = ureg_DECL_constant(ureg, i);
6611 else
6612 t->constants[i] = emit_immediate(t,
6613 proginfo->Parameters->ParameterValues + pvo,
6614 proginfo->Parameters->Parameters[i].DataType,
6615 4);
6616 break;
6617 default:
6618 break;
6619 }
6620 }
6621 }
6622
6623 for (i = 0; i < proginfo->info.num_ubos; i++) {
6624 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6625 unsigned num_const_vecs = (size + 15) / 16;
6626 unsigned first, last;
6627 assert(num_const_vecs > 0);
6628 first = 0;
6629 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6630 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6631 }
6632
6633 /* Emit immediate values.
6634 */
6635 t->immediates = (struct ureg_src *)
6636 calloc(program->num_immediates, sizeof(struct ureg_src));
6637 if (t->immediates == NULL) {
6638 ret = PIPE_ERROR_OUT_OF_MEMORY;
6639 goto out;
6640 }
6641 t->num_immediates = program->num_immediates;
6642
6643 i = 0;
6644 foreach_in_list(immediate_storage, imm, &program->immediates) {
6645 assert(i < program->num_immediates);
6646 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6647 }
6648 assert(i == program->num_immediates);
6649
6650 /* texture samplers */
6651 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6652 if (program->samplers_used & (1u << i)) {
6653 enum tgsi_return_type type =
6654 st_translate_texture_type(program->sampler_types[i]);
6655
6656 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6657
6658 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6659 type, type, type, type);
6660 }
6661 }
6662
6663 /* Declare atomic and shader storage buffers. */
6664 {
6665 struct gl_program *prog = program->prog;
6666
6667 if (!st_context(ctx)->has_hw_atomics) {
6668 for (i = 0; i < prog->info.num_abos; i++) {
6669 unsigned index = prog->sh.AtomicBuffers[i]->Binding;
6670 assert(index < frag_const->MaxAtomicBuffers);
6671 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6672 }
6673 } else {
6674 for (i = 0; i < program->num_atomics; i++) {
6675 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6676 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6677 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6678 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6679 ainfo->array_id);
6680 }
6681 }
6682
6683 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6684 for (i = 0; i < prog->info.num_ssbos; i++) {
6685 unsigned index = i;
6686 if (!st_context(ctx)->has_hw_atomics)
6687 index += frag_const->MaxAtomicBuffers;
6688
6689 t->buffers[index] = ureg_DECL_buffer(ureg, index, false);
6690 }
6691 }
6692
6693 if (program->use_shared_memory)
6694 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
6695
6696 for (i = 0; i < program->shader->Program->info.num_images; i++) {
6697 if (program->images_used & (1 << i)) {
6698 t->images[i] = ureg_DECL_image(ureg, i,
6699 program->image_targets[i],
6700 program->image_formats[i],
6701 true, false);
6702 }
6703 }
6704
6705 /* Emit each instruction in turn:
6706 */
6707 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
6708 compile_tgsi_instruction(t, inst);
6709
6710 /* Set the next shader stage hint for VS and TES. */
6711 switch (procType) {
6712 case PIPE_SHADER_VERTEX:
6713 case PIPE_SHADER_TESS_EVAL:
6714 if (program->shader_program->SeparateShader)
6715 break;
6716
6717 for (i = program->shader->Stage+1; i <= MESA_SHADER_FRAGMENT; i++) {
6718 if (program->shader_program->_LinkedShaders[i]) {
6719 ureg_set_next_shader_processor(
6720 ureg, pipe_shader_type_from_mesa((gl_shader_stage)i));
6721 break;
6722 }
6723 }
6724 break;
6725 }
6726
6727 out:
6728 if (t) {
6729 free(t->arrays);
6730 free(t->temps);
6731 free(t->constants);
6732 t->num_constants = 0;
6733 free(t->immediates);
6734 t->num_immediates = 0;
6735 FREE(t);
6736 }
6737
6738 return ret;
6739 }
6740 /* ----------------------------- End TGSI code ------------------------------ */
6741
6742
6743 /**
6744 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6745 * generating Mesa IR.
6746 */
6747 static struct gl_program *
6748 get_mesa_program_tgsi(struct gl_context *ctx,
6749 struct gl_shader_program *shader_program,
6750 struct gl_linked_shader *shader)
6751 {
6752 glsl_to_tgsi_visitor* v;
6753 struct gl_program *prog;
6754 struct gl_shader_compiler_options *options =
6755 &ctx->Const.ShaderCompilerOptions[shader->Stage];
6756 struct pipe_screen *pscreen = ctx->st->pipe->screen;
6757 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
6758 unsigned skip_merge_registers;
6759
6760 validate_ir_tree(shader->ir);
6761
6762 prog = shader->Program;
6763
6764 prog->Parameters = _mesa_new_parameter_list();
6765 v = new glsl_to_tgsi_visitor();
6766 v->ctx = ctx;
6767 v->prog = prog;
6768 v->shader_program = shader_program;
6769 v->shader = shader;
6770 v->options = options;
6771 v->native_integers = ctx->Const.NativeIntegers;
6772
6773 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
6774 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
6775 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
6776 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
6777 v->has_tex_txf_lz = pscreen->get_param(pscreen,
6778 PIPE_CAP_TGSI_TEX_TXF_LZ);
6779 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6780
6781 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
6782 _mesa_key_pointer_equal);
6783 skip_merge_registers =
6784 pscreen->get_shader_param(pscreen, ptarget,
6785 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
6786
6787 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
6788 prog->Parameters);
6789
6790 /* Remove reads from output registers. */
6791 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
6792 lower_output_reads(shader->Stage, shader->ir);
6793
6794 /* Emit intermediate IR for main(). */
6795 visit_exec_list(shader->ir, v);
6796
6797 #if 0
6798 /* Print out some information (for debugging purposes) used by the
6799 * optimization passes. */
6800 {
6801 int i;
6802 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
6803 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
6804 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
6805 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
6806
6807 for (i = 0; i < v->next_temp; i++) {
6808 first_writes[i] = -1;
6809 first_reads[i] = -1;
6810 last_writes[i] = -1;
6811 last_reads[i] = -1;
6812 }
6813 v->get_first_temp_read(first_reads);
6814 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
6815 v->get_last_temp_write(last_writes);
6816 for (i = 0; i < v->next_temp; i++)
6817 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
6818 first_writes[i],
6819 last_reads[i],
6820 last_writes[i]);
6821 ralloc_free(first_writes);
6822 ralloc_free(first_reads);
6823 ralloc_free(last_writes);
6824 ralloc_free(last_reads);
6825 }
6826 #endif
6827
6828 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6829 v->simplify_cmp();
6830 v->copy_propagate();
6831
6832 while (v->eliminate_dead_code());
6833
6834 v->merge_two_dsts();
6835 if (!skip_merge_registers)
6836 v->merge_registers();
6837 v->renumber_registers();
6838
6839 /* Write the END instruction. */
6840 v->emit_asm(NULL, TGSI_OPCODE_END);
6841
6842 if (ctx->_Shader->Flags & GLSL_DUMP) {
6843 _mesa_log("\n");
6844 _mesa_log("GLSL IR for linked %s program %d:\n",
6845 _mesa_shader_stage_to_string(shader->Stage),
6846 shader_program->Name);
6847 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
6848 _mesa_log("\n\n");
6849 }
6850
6851 do_set_program_inouts(shader->ir, prog, shader->Stage);
6852 _mesa_copy_linked_program_data(shader_program, shader);
6853 shrink_array_declarations(v->inputs, v->num_inputs,
6854 &prog->info.inputs_read,
6855 prog->info.vs.double_inputs_read,
6856 &prog->info.patch_inputs_read);
6857 shrink_array_declarations(v->outputs, v->num_outputs,
6858 &prog->info.outputs_written, 0ULL,
6859 &prog->info.patch_outputs_written);
6860 count_resources(v, prog);
6861
6862 /* The GLSL IR won't be needed anymore. */
6863 ralloc_free(shader->ir);
6864 shader->ir = NULL;
6865
6866 /* This must be done before the uniform storage is associated. */
6867 if (shader->Stage == MESA_SHADER_FRAGMENT &&
6868 (prog->info.inputs_read & VARYING_BIT_POS ||
6869 prog->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD))) {
6870 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
6871 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
6872 };
6873
6874 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
6875 wposTransformState);
6876 }
6877
6878 /* Avoid reallocation of the program parameter list, because the uniform
6879 * storage is only associated with the original parameter list.
6880 * This should be enough for Bitmap and DrawPixels constants.
6881 */
6882 _mesa_reserve_parameter_storage(prog->Parameters, 8);
6883
6884 /* This has to be done last. Any operation the can cause
6885 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6886 * program constant) has to happen before creating this linkage.
6887 */
6888 _mesa_associate_uniform_storage(ctx, shader_program, prog, true);
6889 if (!shader_program->data->LinkStatus) {
6890 free_glsl_to_tgsi_visitor(v);
6891 _mesa_reference_program(ctx, &shader->Program, NULL);
6892 return NULL;
6893 }
6894
6895 struct st_vertex_program *stvp;
6896 struct st_fragment_program *stfp;
6897 struct st_common_program *stp;
6898 struct st_compute_program *stcp;
6899
6900 switch (shader->Stage) {
6901 case MESA_SHADER_VERTEX:
6902 stvp = (struct st_vertex_program *)prog;
6903 stvp->glsl_to_tgsi = v;
6904 break;
6905 case MESA_SHADER_FRAGMENT:
6906 stfp = (struct st_fragment_program *)prog;
6907 stfp->glsl_to_tgsi = v;
6908 break;
6909 case MESA_SHADER_TESS_CTRL:
6910 case MESA_SHADER_TESS_EVAL:
6911 case MESA_SHADER_GEOMETRY:
6912 stp = st_common_program(prog);
6913 stp->glsl_to_tgsi = v;
6914 break;
6915 case MESA_SHADER_COMPUTE:
6916 stcp = (struct st_compute_program *)prog;
6917 stcp->glsl_to_tgsi = v;
6918 break;
6919 default:
6920 assert(!"should not be reached");
6921 return NULL;
6922 }
6923
6924 return prog;
6925 }
6926
6927 /* See if there are unsupported control flow statements. */
6928 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
6929 private:
6930 const struct gl_shader_compiler_options *options;
6931 public:
6932 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
6933 : options(options),
6934 unsupported(false)
6935 {
6936 }
6937
6938 virtual ir_visitor_status visit_enter(ir_function *ir)
6939 {
6940 /* Other functions are skipped (same as glsl_to_tgsi). */
6941 if (strcmp(ir->name, "main") == 0)
6942 return visit_continue;
6943
6944 return visit_continue_with_parent;
6945 }
6946
6947 virtual ir_visitor_status visit_enter(ir_call *ir)
6948 {
6949 if (!ir->callee->is_intrinsic()) {
6950 unsupported = true; /* it's a function call */
6951 return visit_stop;
6952 }
6953 return visit_continue;
6954 }
6955
6956 virtual ir_visitor_status visit_enter(ir_return *ir)
6957 {
6958 if (options->EmitNoMainReturn) {
6959 unsupported = true;
6960 return visit_stop;
6961 }
6962 return visit_continue;
6963 }
6964
6965 bool unsupported;
6966 };
6967
6968 static bool
6969 has_unsupported_control_flow(exec_list *ir,
6970 const struct gl_shader_compiler_options *options)
6971 {
6972 ir_control_flow_info_visitor visitor(options);
6973 visit_list_elements(&visitor, ir);
6974 return visitor.unsupported;
6975 }
6976
6977 extern "C" {
6978
6979 /**
6980 * Link a shader.
6981 * Called via ctx->Driver.LinkShader()
6982 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6983 * with code lowering and other optimizations.
6984 */
6985 GLboolean
6986 st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
6987 {
6988 struct pipe_screen *pscreen = ctx->st->pipe->screen;
6989
6990 enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
6991 pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
6992 PIPE_SHADER_CAP_PREFERRED_IR);
6993 bool use_nir = preferred_ir == PIPE_SHADER_IR_NIR;
6994
6995 /* Return early if we are loading the shader from on-disk cache */
6996 if (st_load_ir_from_disk_cache(ctx, prog, use_nir)) {
6997 return GL_TRUE;
6998 }
6999
7000 assert(prog->data->LinkStatus);
7001
7002 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7003 if (prog->_LinkedShaders[i] == NULL)
7004 continue;
7005
7006 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7007 exec_list *ir = shader->ir;
7008 gl_shader_stage stage = shader->Stage;
7009 const struct gl_shader_compiler_options *options =
7010 &ctx->Const.ShaderCompilerOptions[stage];
7011 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7012 bool have_dround = pscreen->get_shader_param(pscreen, ptarget,
7013 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED);
7014 bool have_dfrexp = pscreen->get_shader_param(pscreen, ptarget,
7015 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED);
7016 bool have_ldexp = pscreen->get_shader_param(pscreen, ptarget,
7017 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED);
7018 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7019 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7020
7021 /* If there are forms of indirect addressing that the driver
7022 * cannot handle, perform the lowering pass.
7023 */
7024 if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput ||
7025 options->EmitNoIndirectTemp || options->EmitNoIndirectUniform) {
7026 lower_variable_index_to_cond_assign(stage, ir,
7027 options->EmitNoIndirectInput,
7028 options->EmitNoIndirectOutput,
7029 options->EmitNoIndirectTemp,
7030 options->EmitNoIndirectUniform);
7031 }
7032
7033 if (!pscreen->get_param(pscreen, PIPE_CAP_INT64_DIVMOD))
7034 lower_64bit_integer_instructions(ir, DIV64 | MOD64);
7035
7036 if (ctx->Extensions.ARB_shading_language_packing) {
7037 unsigned lower_inst = LOWER_PACK_SNORM_2x16 |
7038 LOWER_UNPACK_SNORM_2x16 |
7039 LOWER_PACK_UNORM_2x16 |
7040 LOWER_UNPACK_UNORM_2x16 |
7041 LOWER_PACK_SNORM_4x8 |
7042 LOWER_UNPACK_SNORM_4x8 |
7043 LOWER_UNPACK_UNORM_4x8 |
7044 LOWER_PACK_UNORM_4x8;
7045
7046 if (ctx->Extensions.ARB_gpu_shader5)
7047 lower_inst |= LOWER_PACK_USE_BFI |
7048 LOWER_PACK_USE_BFE;
7049 if (!ctx->st->has_half_float_packing)
7050 lower_inst |= LOWER_PACK_HALF_2x16 |
7051 LOWER_UNPACK_HALF_2x16;
7052
7053 lower_packing_builtins(ir, lower_inst);
7054 }
7055
7056 if (!pscreen->get_param(pscreen, PIPE_CAP_TEXTURE_GATHER_OFFSETS))
7057 lower_offset_arrays(ir);
7058 do_mat_op_to_vec(ir);
7059
7060 if (stage == MESA_SHADER_FRAGMENT)
7061 lower_blend_equation_advanced(
7062 shader, ctx->Extensions.KHR_blend_equation_advanced_coherent);
7063
7064 lower_instructions(ir,
7065 MOD_TO_FLOOR |
7066 FDIV_TO_MUL_RCP |
7067 EXP_TO_EXP2 |
7068 LOG_TO_LOG2 |
7069 (have_ldexp ? 0 : LDEXP_TO_ARITH) |
7070 (have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) |
7071 CARRY_TO_ARITH |
7072 BORROW_TO_ARITH |
7073 (have_dround ? 0 : DOPS_TO_DFRAC) |
7074 (options->EmitNoPow ? POW_TO_EXP2 : 0) |
7075 (!ctx->Const.NativeIntegers ? INT_DIV_TO_MUL_RCP : 0) |
7076 (options->EmitNoSat ? SAT_TO_CLAMP : 0) |
7077 (ctx->Const.ForceGLSLAbsSqrt ? SQRT_TO_ABS_SQRT : 0) |
7078 /* Assume that if ARB_gpu_shader5 is not supported
7079 * then all of the extended integer functions need
7080 * lowering. It may be necessary to add some caps
7081 * for individual instructions.
7082 */
7083 (!ctx->Extensions.ARB_gpu_shader5
7084 ? BIT_COUNT_TO_MATH |
7085 EXTRACT_TO_SHIFTS |
7086 INSERT_TO_SHIFTS |
7087 REVERSE_TO_SHIFTS |
7088 FIND_LSB_TO_FLOAT_CAST |
7089 FIND_MSB_TO_FLOAT_CAST |
7090 IMUL_HIGH_TO_MUL
7091 : 0));
7092
7093 do_vec_index_to_cond_assign(ir);
7094 lower_vector_insert(ir, true);
7095 lower_quadop_vector(ir, false);
7096 lower_noise(ir);
7097 if (options->MaxIfDepth == 0) {
7098 lower_discard(ir);
7099 }
7100
7101 if (ctx->Const.GLSLOptimizeConservatively) {
7102 /* Do it once and repeat only if there's unsupported control flow. */
7103 do {
7104 do_common_optimization(ir, true, true, options,
7105 ctx->Const.NativeIntegers);
7106 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7107 options->MaxIfDepth, if_threshold);
7108 } while (has_unsupported_control_flow(ir, options));
7109 } else {
7110 /* Repeat it until it stops making changes. */
7111 bool progress;
7112 do {
7113 progress = do_common_optimization(ir, true, true, options,
7114 ctx->Const.NativeIntegers);
7115 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7116 options->MaxIfDepth, if_threshold);
7117 } while (progress);
7118 }
7119
7120 validate_ir_tree(ir);
7121 }
7122
7123 build_program_resource_list(ctx, prog);
7124
7125 if (use_nir)
7126 return st_link_nir(ctx, prog);
7127
7128 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7129 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7130 if (shader == NULL)
7131 continue;
7132
7133 struct gl_program *linked_prog =
7134 get_mesa_program_tgsi(ctx, prog, shader);
7135 st_set_prog_affected_state_flags(linked_prog);
7136
7137 if (linked_prog) {
7138 if (!ctx->Driver.ProgramStringNotify(ctx,
7139 _mesa_shader_stage_to_program(i),
7140 linked_prog)) {
7141 _mesa_reference_program(ctx, &shader->Program, NULL);
7142 return GL_FALSE;
7143 }
7144 }
7145 }
7146
7147 return GL_TRUE;
7148 }
7149
7150 void
7151 st_translate_stream_output_info(glsl_to_tgsi_visitor *glsl_to_tgsi,
7152 const ubyte outputMapping[],
7153 struct pipe_stream_output_info *so)
7154 {
7155 if (!glsl_to_tgsi->shader_program->last_vert_prog)
7156 return;
7157
7158 struct gl_transform_feedback_info *info =
7159 glsl_to_tgsi->shader_program->last_vert_prog->sh.LinkedTransformFeedback;
7160 st_translate_stream_output_info2(info, outputMapping, so);
7161 }
7162
7163 void
7164 st_translate_stream_output_info2(struct gl_transform_feedback_info *info,
7165 const ubyte outputMapping[],
7166 struct pipe_stream_output_info *so)
7167 {
7168 unsigned i;
7169
7170 for (i = 0; i < info->NumOutputs; i++) {
7171 so->output[i].register_index =
7172 outputMapping[info->Outputs[i].OutputRegister];
7173 so->output[i].start_component = info->Outputs[i].ComponentOffset;
7174 so->output[i].num_components = info->Outputs[i].NumComponents;
7175 so->output[i].output_buffer = info->Outputs[i].OutputBuffer;
7176 so->output[i].dst_offset = info->Outputs[i].DstOffset;
7177 so->output[i].stream = info->Outputs[i].StreamId;
7178 }
7179
7180 for (i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
7181 so->stride[i] = info->Buffers[i].Stride;
7182 }
7183 so->num_outputs = info->NumOutputs;
7184 }
7185
7186 } /* extern "C" */