src/mesa/state_tracker/st_glsl_to_tgsi_private.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  * Copyright © 2011 Bryan Cain
   4  * Copyright © 2017 Gert Wollny
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #ifndef ST_GLSL_TO_TGSI_PRIVATE_H
  27 #define ST_GLSL_TO_TGSI_PRIVATE_H
  28
  29 #include "mesa/main/mtypes.h"
  30 #include "program/prog_parameter.h"
  31 #include "compiler/glsl_types.h"
  32 #include "compiler/glsl/ir.h"
  33 #include "tgsi/tgsi_info.h"
  34 #include <ostream>
  35
  36 int swizzle_for_size(int size);
  37
  38 class st_dst_reg;
  39 /**
  40  * This struct is a corresponding struct to TGSI ureg_src.
  41  */
  42 class st_src_reg {
  43 public:
  44    st_src_reg(gl_register_file file, int index, const glsl_type *type,
  45               int component = 0, unsigned array_id = 0);
  46
  47    st_src_reg(gl_register_file file, int index, enum glsl_base_type type);
  48
  49    st_src_reg(gl_register_file file, int index, enum glsl_base_type type, int index2D);
  50
  51    st_src_reg();
  52    st_src_reg(const st_src_reg &reg);
  53    void operator=(const st_src_reg &reg);
  54    void reset();
  55
  56    explicit st_src_reg(st_dst_reg reg);
  57
  58    st_src_reg get_abs();
  59
  60    int32_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
  61    int16_t index2D;
  62
  63    uint16_t swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
  64    int negate:4; /**< NEGATE_XYZW mask from mesa */
  65    unsigned abs:1;
  66    enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
  67    unsigned has_index2:1;
  68    gl_register_file file:5; /**< PROGRAM_* from Mesa */
  69    /*
  70     * Is this the second half of a double register pair?
  71     * currently used for input mapping only.
  72     */
  73    unsigned double_reg2:1;
  74    unsigned is_double_vertex_input:1;
  75    unsigned array_id:10;
  76    /** Register index should be offset by the integer in this reg. */
  77    st_src_reg *reladdr;
  78    st_src_reg *reladdr2;
  79
  80    bool is_legal_tgsi_address_operand() const
  81    {
  82       /* 2D registers can't be used as an address operand, or if the address
  83        * operand itself is a result of indirect addressing.
  84        */
  85       return (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT) &&
  86              !has_index2 && !reladdr && !reladdr2;
  87    }
  88 };
  89
  90 bool operator == (const st_src_reg& lhs, const st_src_reg& rhs);
  91
  92 std::ostream& operator << (std::ostream& os, const st_src_reg& reg);
  93
  94 class st_dst_reg {
  95 public:
  96    st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, int index);
  97
  98    st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type);
  99
 100    st_dst_reg();
 101    st_dst_reg(const st_dst_reg &reg);
 102    void operator=(const st_dst_reg &reg);
 103
 104    explicit st_dst_reg(st_src_reg reg);
 105
 106    int32_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
 107    int16_t index2D;
 108    gl_register_file file:5; /**< PROGRAM_* from Mesa */
 109    unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */
 110    enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
 111    unsigned has_index2:1;
 112    unsigned array_id:10;
 113
 114    /** Register index should be offset by the integer in this reg. */
 115    st_src_reg *reladdr;
 116    st_src_reg *reladdr2;
 117 };
 118
 119 bool operator == (const st_dst_reg& lhs, const st_dst_reg& rhs);
 120
 121 std::ostream& operator << (std::ostream& os, const st_dst_reg& reg);
 122
 123
 124 class glsl_to_tgsi_instruction : public exec_node {
 125 public:
 126    DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction)
 127
 128    st_dst_reg dst[2];
 129    st_src_reg src[4];
 130    st_src_reg resource; /**< sampler or buffer register */
 131    st_src_reg *tex_offsets;
 132
 133    /** Pointer to the ir source this tree came fe02549fdrom for debugging */
 134    ir_instruction *ir;
 135
 136    enum tgsi_opcode op:10; /**< TGSI opcode */
 137    unsigned precise:1;
 138    unsigned saturate:1;
 139    unsigned is_64bit_expanded:1;
 140    unsigned sampler_base:5;
 141    unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not array */
 142    gl_texture_index tex_target:5;
 143    glsl_base_type tex_type:6;
 144    unsigned tex_shadow:1;
 145    enum pipe_format image_format:10;
 146    unsigned tex_offset_num_offset:3;
 147    unsigned dead_mask:4; /**< Used in dead code elimination */
 148    unsigned buffer_access:3; /**< bitmask of TGSI_MEMORY_x bits */
 149    unsigned read_only:1;
 150
 151    const struct tgsi_opcode_info *info;
 152
 153    void print(std::ostream& os) const;
 154 };
 155
 156 inline std::ostream&
 157 operator << (std::ostream& os, const glsl_to_tgsi_instruction& instr)
 158 {
 159    instr.print(os);
 160    return os;
 161 }
 162
 163 struct rename_reg_pair {
 164    bool valid;
 165    int new_reg;
 166 };
 167
 168 inline static bool
 169 is_resource_instruction(unsigned opcode)
 170 {
 171    switch (opcode) {
 172    case TGSI_OPCODE_RESQ:
 173    case TGSI_OPCODE_LOAD:
 174    case TGSI_OPCODE_ATOMUADD:
 175    case TGSI_OPCODE_ATOMXCHG:
 176    case TGSI_OPCODE_ATOMCAS:
 177    case TGSI_OPCODE_ATOMAND:
 178    case TGSI_OPCODE_ATOMOR:
 179    case TGSI_OPCODE_ATOMXOR:
 180    case TGSI_OPCODE_ATOMUMIN:
 181    case TGSI_OPCODE_ATOMUMAX:
 182    case TGSI_OPCODE_ATOMIMIN:
 183    case TGSI_OPCODE_ATOMIMAX:
 184    case TGSI_OPCODE_IMG2HND:
 185       return true;
 186    default:
 187       return false;
 188    }
 189 }
 190
 191 inline static unsigned
 192 num_inst_dst_regs(const glsl_to_tgsi_instruction *op)
 193 {
 194    return op->info->num_dst;
 195 }
 196
 197 inline static unsigned
 198 num_inst_src_regs(const glsl_to_tgsi_instruction *op)
 199 {
 200    return op->info->is_tex || is_resource_instruction(op->op) ?
 201       op->info->num_src - 1 : op->info->num_src;
 202 }
 203 #endif