src/mesa/state_tracker/st_glsl_to_tgsi_private.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  * Copyright © 2011 Bryan Cain
   4  * Copyright © 2017 Gert Wollny
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #ifndef ST_GLSL_TO_TGSI_PRIVATE_H
  27 #define ST_GLSL_TO_TGSI_PRIVATE_H
  28
  29 #include <mesa/main/mtypes.h>
  30 #include <compiler/glsl_types.h>
  31 #include <compiler/glsl/ir.h>
  32 #include <tgsi/tgsi_info.h>
  33 #include <ostream>
  34
  35 int swizzle_for_size(int size);
  36
  37 class st_dst_reg;
  38 /**
  39  * This struct is a corresponding struct to TGSI ureg_src.
  40  */
  41 class st_src_reg {
  42 public:
  43    st_src_reg(gl_register_file file, int index, const glsl_type *type,
  44               int component = 0, unsigned array_id = 0);
  45
  46    st_src_reg(gl_register_file file, int index, enum glsl_base_type type);
  47
  48    st_src_reg(gl_register_file file, int index, enum glsl_base_type type, int index2D);
  49
  50    st_src_reg();
  51    st_src_reg(const st_src_reg &reg);
  52    void operator=(const st_src_reg &reg);
  53
  54    explicit st_src_reg(st_dst_reg reg);
  55
  56    st_src_reg get_abs();
  57
  58    int32_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
  59    int16_t index2D;
  60
  61    uint16_t swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
  62    int negate:4; /**< NEGATE_XYZW mask from mesa */
  63    unsigned abs:1;
  64    enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
  65    unsigned has_index2:1;
  66    gl_register_file file:5; /**< PROGRAM_* from Mesa */
  67    /*
  68     * Is this the second half of a double register pair?
  69     * currently used for input mapping only.
  70     */
  71    unsigned double_reg2:1;
  72    unsigned is_double_vertex_input:1;
  73    unsigned array_id:10;
  74    /** Register index should be offset by the integer in this reg. */
  75    st_src_reg *reladdr;
  76    st_src_reg *reladdr2;
  77
  78    bool is_legal_tgsi_address_operand() const
  79    {
  80       /* 2D registers can't be used as an address operand, or if the address
  81        * operand itself is a result of indirect addressing.
  82        */
  83       return (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT) &&
  84              !has_index2 && !reladdr && !reladdr2;
  85    }
  86 };
  87
  88 bool operator == (const st_src_reg& lhs, const st_src_reg& rhs);
  89
  90 std::ostream& operator << (std::ostream& os, const st_src_reg& reg);
  91
  92 class st_dst_reg {
  93 public:
  94    st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, int index);
  95
  96    st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type);
  97
  98    st_dst_reg();
  99    st_dst_reg(const st_dst_reg &reg);
 100    void operator=(const st_dst_reg &reg);
 101
 102    explicit st_dst_reg(st_src_reg reg);
 103
 104    int32_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
 105    int16_t index2D;
 106    gl_register_file file:5; /**< PROGRAM_* from Mesa */
 107    unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */
 108    enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
 109    unsigned has_index2:1;
 110    unsigned array_id:10;
 111
 112    /** Register index should be offset by the integer in this reg. */
 113    st_src_reg *reladdr;
 114    st_src_reg *reladdr2;
 115 };
 116
 117 bool operator == (const st_dst_reg& lhs, const st_dst_reg& rhs);
 118
 119 std::ostream& operator << (std::ostream& os, const st_dst_reg& reg);
 120
 121
 122 class glsl_to_tgsi_instruction : public exec_node {
 123 public:
 124    DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction)
 125
 126    st_dst_reg dst[2];
 127    st_src_reg src[4];
 128    st_src_reg resource; /**< sampler or buffer register */
 129    st_src_reg *tex_offsets;
 130
 131    /** Pointer to the ir source this tree came fe02549fdrom for debugging */
 132    ir_instruction *ir;
 133
 134    enum tgsi_opcode op:10; /**< TGSI opcode */
 135    unsigned precise:1;
 136    unsigned saturate:1;
 137    unsigned is_64bit_expanded:1;
 138    unsigned sampler_base:5;
 139    unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not array */
 140    gl_texture_index tex_target:5;
 141    glsl_base_type tex_type:6;
 142    unsigned tex_shadow:1;
 143    enum pipe_format image_format:10;
 144    unsigned tex_offset_num_offset:3;
 145    unsigned dead_mask:4; /**< Used in dead code elimination */
 146    unsigned buffer_access:3; /**< bitmask of TGSI_MEMORY_x bits */
 147
 148    const struct tgsi_opcode_info *info;
 149
 150    void print(std::ostream& os) const;
 151 };
 152
 153 inline std::ostream&
 154 operator << (std::ostream& os, const glsl_to_tgsi_instruction& instr)
 155 {
 156    instr.print(os);
 157    return os;
 158 }
 159
 160 struct rename_reg_pair {
 161    bool valid;
 162    int new_reg;
 163 };
 164
 165 inline static bool
 166 is_resource_instruction(unsigned opcode)
 167 {
 168    switch (opcode) {
 169    case TGSI_OPCODE_RESQ:
 170    case TGSI_OPCODE_LOAD:
 171    case TGSI_OPCODE_ATOMUADD:
 172    case TGSI_OPCODE_ATOMXCHG:
 173    case TGSI_OPCODE_ATOMCAS:
 174    case TGSI_OPCODE_ATOMAND:
 175    case TGSI_OPCODE_ATOMOR:
 176    case TGSI_OPCODE_ATOMXOR:
 177    case TGSI_OPCODE_ATOMUMIN:
 178    case TGSI_OPCODE_ATOMUMAX:
 179    case TGSI_OPCODE_ATOMIMIN:
 180    case TGSI_OPCODE_ATOMIMAX:
 181       return true;
 182    default:
 183       return false;
 184    }
 185 }
 186
 187 inline static unsigned
 188 num_inst_dst_regs(const glsl_to_tgsi_instruction *op)
 189 {
 190    return op->info->num_dst;
 191 }
 192
 193 inline static unsigned
 194 num_inst_src_regs(const glsl_to_tgsi_instruction *op)
 195 {
 196    return op->info->is_tex || is_resource_instruction(op->op) ?
 197       op->info->num_src - 1 : op->info->num_src;
 198 }
 199 #endif