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Merge branch 'glsl-to-tgsi'
[mesa.git] / src / mesa / state_tracker / st_mesa_to_tgsi.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * \author
30 * Michal Krol,
31 * Keith Whitwell
32 */
33
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47
48
49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_LOCAL_PARAM) | \
50 (1 << PROGRAM_ENV_PARAM) | \
51 (1 << PROGRAM_STATE_VAR) | \
52 (1 << PROGRAM_NAMED_PARAM) | \
53 (1 << PROGRAM_CONSTANT) | \
54 (1 << PROGRAM_UNIFORM))
55
56
57 struct label {
58 unsigned branch_target;
59 unsigned token;
60 };
61
62
63 /**
64 * Intermediate state used during shader translation.
65 */
66 struct st_translate {
67 struct ureg_program *ureg;
68
69 struct ureg_dst temps[MAX_PROGRAM_TEMPS];
70 struct ureg_src *constants;
71 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
72 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
73 struct ureg_dst address[1];
74 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
75 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
76
77 /* Extra info for handling point size clamping in vertex shader */
78 struct ureg_dst pointSizeResult; /**< Actual point size output register */
79 struct ureg_src pointSizeConst; /**< Point size range constant register */
80 GLint pointSizeOutIndex; /**< Temp point size output register */
81 GLboolean prevInstWrotePointSize;
82
83 const GLuint *inputMapping;
84 const GLuint *outputMapping;
85
86 /* For every instruction that contains a label (eg CALL), keep
87 * details so that we can go back afterwards and emit the correct
88 * tgsi instruction number for each label.
89 */
90 struct label *labels;
91 unsigned labels_size;
92 unsigned labels_count;
93
94 /* Keep a record of the tgsi instruction number that each mesa
95 * instruction starts at, will be used to fix up labels after
96 * translation.
97 */
98 unsigned *insn;
99 unsigned insn_size;
100 unsigned insn_count;
101
102 unsigned procType; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
103
104 boolean error;
105 };
106
107
108 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
109 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
110 TGSI_SEMANTIC_FACE,
111 TGSI_SEMANTIC_INSTANCEID
112 };
113
114
115 /**
116 * Make note of a branch to a label in the TGSI code.
117 * After we've emitted all instructions, we'll go over the list
118 * of labels built here and patch the TGSI code with the actual
119 * location of each label.
120 */
121 static unsigned *get_label( struct st_translate *t,
122 unsigned branch_target )
123 {
124 unsigned i;
125
126 if (t->labels_count + 1 >= t->labels_size) {
127 unsigned old_size = t->labels_size;
128 t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
129 t->labels = REALLOC( t->labels,
130 old_size * sizeof t->labels[0],
131 t->labels_size * sizeof t->labels[0] );
132 if (t->labels == NULL) {
133 static unsigned dummy;
134 t->error = TRUE;
135 return &dummy;
136 }
137 }
138
139 i = t->labels_count++;
140 t->labels[i].branch_target = branch_target;
141 return &t->labels[i].token;
142 }
143
144
145 /**
146 * Called prior to emitting the TGSI code for each Mesa instruction.
147 * Allocate additional space for instructions if needed.
148 * Update the insn[] array so the next Mesa instruction points to
149 * the next TGSI instruction.
150 */
151 static void set_insn_start( struct st_translate *t,
152 unsigned start )
153 {
154 if (t->insn_count + 1 >= t->insn_size) {
155 unsigned old_size = t->insn_size;
156 t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
157 t->insn = REALLOC( t->insn,
158 old_size * sizeof t->insn[0],
159 t->insn_size * sizeof t->insn[0] );
160 if (t->insn == NULL) {
161 t->error = TRUE;
162 return;
163 }
164 }
165
166 t->insn[t->insn_count++] = start;
167 }
168
169
170 /**
171 * Map a Mesa dst register to a TGSI ureg_dst register.
172 */
173 static struct ureg_dst
174 dst_register( struct st_translate *t,
175 gl_register_file file,
176 GLuint index )
177 {
178 switch( file ) {
179 case PROGRAM_UNDEFINED:
180 return ureg_dst_undef();
181
182 case PROGRAM_TEMPORARY:
183 if (ureg_dst_is_undef(t->temps[index]))
184 t->temps[index] = ureg_DECL_temporary( t->ureg );
185
186 return t->temps[index];
187
188 case PROGRAM_OUTPUT:
189 if (t->procType == TGSI_PROCESSOR_VERTEX && index == VERT_RESULT_PSIZ)
190 t->prevInstWrotePointSize = GL_TRUE;
191
192 if (t->procType == TGSI_PROCESSOR_VERTEX)
193 assert(index < VERT_RESULT_MAX);
194 else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
195 assert(index < FRAG_RESULT_MAX);
196 else
197 assert(index < GEOM_RESULT_MAX);
198
199 assert(t->outputMapping[index] < Elements(t->outputs));
200
201 return t->outputs[t->outputMapping[index]];
202
203 case PROGRAM_ADDRESS:
204 return t->address[index];
205
206 default:
207 debug_assert( 0 );
208 return ureg_dst_undef();
209 }
210 }
211
212
213 /**
214 * Map a Mesa src register to a TGSI ureg_src register.
215 */
216 static struct ureg_src
217 src_register( struct st_translate *t,
218 gl_register_file file,
219 GLint index )
220 {
221 switch( file ) {
222 case PROGRAM_UNDEFINED:
223 return ureg_src_undef();
224
225 case PROGRAM_TEMPORARY:
226 assert(index >= 0);
227 assert(index < Elements(t->temps));
228 if (ureg_dst_is_undef(t->temps[index]))
229 t->temps[index] = ureg_DECL_temporary( t->ureg );
230 return ureg_src(t->temps[index]);
231
232 case PROGRAM_NAMED_PARAM:
233 case PROGRAM_ENV_PARAM:
234 case PROGRAM_LOCAL_PARAM:
235 case PROGRAM_UNIFORM:
236 assert(index >= 0);
237 return t->constants[index];
238 case PROGRAM_STATE_VAR:
239 case PROGRAM_CONSTANT: /* ie, immediate */
240 if (index < 0)
241 return ureg_DECL_constant( t->ureg, 0 );
242 else
243 return t->constants[index];
244
245 case PROGRAM_INPUT:
246 assert(t->inputMapping[index] < Elements(t->inputs));
247 return t->inputs[t->inputMapping[index]];
248
249 case PROGRAM_OUTPUT:
250 assert(t->outputMapping[index] < Elements(t->outputs));
251 return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
252
253 case PROGRAM_ADDRESS:
254 return ureg_src(t->address[index]);
255
256 case PROGRAM_SYSTEM_VALUE:
257 assert(index < Elements(t->systemValues));
258 return t->systemValues[index];
259
260 default:
261 debug_assert( 0 );
262 return ureg_src_undef();
263 }
264 }
265
266
267 /**
268 * Map mesa texture target to TGSI texture target.
269 */
270 unsigned
271 translate_texture_target( GLuint textarget,
272 GLboolean shadow )
273 {
274 if (shadow) {
275 switch( textarget ) {
276 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_SHADOW1D;
277 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_SHADOW2D;
278 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
279 default: break;
280 }
281 }
282
283 switch( textarget ) {
284 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_1D;
285 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_2D;
286 case TEXTURE_3D_INDEX: return TGSI_TEXTURE_3D;
287 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
288 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
289 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_1D_ARRAY;
290 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY;
291 default:
292 debug_assert( 0 );
293 return TGSI_TEXTURE_1D;
294 }
295 }
296
297
298 /**
299 * Create a TGSI ureg_dst register from a Mesa dest register.
300 */
301 static struct ureg_dst
302 translate_dst( struct st_translate *t,
303 const struct prog_dst_register *DstReg,
304 boolean saturate )
305 {
306 struct ureg_dst dst = dst_register( t,
307 DstReg->File,
308 DstReg->Index );
309
310 dst = ureg_writemask( dst,
311 DstReg->WriteMask );
312
313 if (saturate)
314 dst = ureg_saturate( dst );
315
316 if (DstReg->RelAddr)
317 dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
318
319 return dst;
320 }
321
322
323 /**
324 * Create a TGSI ureg_src register from a Mesa src register.
325 */
326 static struct ureg_src
327 translate_src( struct st_translate *t,
328 const struct prog_src_register *SrcReg )
329 {
330 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
331
332 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
333 src = src_register( t, SrcReg->File, SrcReg->Index2 );
334 if (SrcReg->RelAddr2)
335 src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
336 SrcReg->Index);
337 else
338 src = ureg_src_dimension( src, SrcReg->Index);
339 }
340
341 src = ureg_swizzle( src,
342 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
343 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
344 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
345 GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
346
347 if (SrcReg->Negate == NEGATE_XYZW)
348 src = ureg_negate(src);
349
350 if (SrcReg->Abs)
351 src = ureg_abs(src);
352
353 if (SrcReg->RelAddr) {
354 src = ureg_src_indirect( src, ureg_src(t->address[0]));
355 if (SrcReg->File != PROGRAM_INPUT &&
356 SrcReg->File != PROGRAM_OUTPUT) {
357 /* If SrcReg->Index was negative, it was set to zero in
358 * src_register(). Reassign it now. But don't do this
359 * for input/output regs since they get remapped while
360 * const buffers don't.
361 */
362 src.Index = SrcReg->Index;
363 }
364 }
365
366 return src;
367 }
368
369
370 static struct ureg_src swizzle_4v( struct ureg_src src,
371 const unsigned *swz )
372 {
373 return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
374 }
375
376
377 /**
378 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
379 *
380 * SWZ dst, src.x-y10
381 *
382 * becomes:
383 *
384 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
385 */
386 static void emit_swz( struct st_translate *t,
387 struct ureg_dst dst,
388 const struct prog_src_register *SrcReg )
389 {
390 struct ureg_program *ureg = t->ureg;
391 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
392
393 unsigned negate_mask = SrcReg->Negate;
394
395 unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
396 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
397 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
398 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
399
400 unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
401 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
402 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
403 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
404
405 unsigned negative_one_mask = one_mask & negate_mask;
406 unsigned positive_one_mask = one_mask & ~negate_mask;
407
408 struct ureg_src imm;
409 unsigned i;
410 unsigned mul_swizzle[4] = {0,0,0,0};
411 unsigned add_swizzle[4] = {0,0,0,0};
412 unsigned src_swizzle[4] = {0,0,0,0};
413 boolean need_add = FALSE;
414 boolean need_mul = FALSE;
415
416 if (dst.WriteMask == 0)
417 return;
418
419 /* Is this just a MOV?
420 */
421 if (zero_mask == 0 &&
422 one_mask == 0 &&
423 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
424 {
425 ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
426 return;
427 }
428
429 #define IMM_ZERO 0
430 #define IMM_ONE 1
431 #define IMM_NEG_ONE 2
432
433 imm = ureg_imm3f( ureg, 0, 1, -1 );
434
435 for (i = 0; i < 4; i++) {
436 unsigned bit = 1 << i;
437
438 if (dst.WriteMask & bit) {
439 if (positive_one_mask & bit) {
440 mul_swizzle[i] = IMM_ZERO;
441 add_swizzle[i] = IMM_ONE;
442 need_add = TRUE;
443 }
444 else if (negative_one_mask & bit) {
445 mul_swizzle[i] = IMM_ZERO;
446 add_swizzle[i] = IMM_NEG_ONE;
447 need_add = TRUE;
448 }
449 else if (zero_mask & bit) {
450 mul_swizzle[i] = IMM_ZERO;
451 add_swizzle[i] = IMM_ZERO;
452 need_add = TRUE;
453 }
454 else {
455 add_swizzle[i] = IMM_ZERO;
456 src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
457 need_mul = TRUE;
458 if (negate_mask & bit) {
459 mul_swizzle[i] = IMM_NEG_ONE;
460 }
461 else {
462 mul_swizzle[i] = IMM_ONE;
463 }
464 }
465 }
466 }
467
468 if (need_mul && need_add) {
469 ureg_MAD( ureg,
470 dst,
471 swizzle_4v( src, src_swizzle ),
472 swizzle_4v( imm, mul_swizzle ),
473 swizzle_4v( imm, add_swizzle ) );
474 }
475 else if (need_mul) {
476 ureg_MUL( ureg,
477 dst,
478 swizzle_4v( src, src_swizzle ),
479 swizzle_4v( imm, mul_swizzle ) );
480 }
481 else if (need_add) {
482 ureg_MOV( ureg,
483 dst,
484 swizzle_4v( imm, add_swizzle ) );
485 }
486 else {
487 debug_assert(0);
488 }
489
490 #undef IMM_ZERO
491 #undef IMM_ONE
492 #undef IMM_NEG_ONE
493 }
494
495
496 /**
497 * Negate the value of DDY to match GL semantics where (0,0) is the
498 * lower-left corner of the window.
499 * Note that the GL_ARB_fragment_coord_conventions extension will
500 * effect this someday.
501 */
502 static void emit_ddy( struct st_translate *t,
503 struct ureg_dst dst,
504 const struct prog_src_register *SrcReg )
505 {
506 struct ureg_program *ureg = t->ureg;
507 struct ureg_src src = translate_src( t, SrcReg );
508 src = ureg_negate( src );
509 ureg_DDY( ureg, dst, src );
510 }
511
512
513
514 unsigned
515 translate_opcode( unsigned op )
516 {
517 switch( op ) {
518 case OPCODE_ARL:
519 return TGSI_OPCODE_ARL;
520 case OPCODE_ABS:
521 return TGSI_OPCODE_ABS;
522 case OPCODE_ADD:
523 return TGSI_OPCODE_ADD;
524 case OPCODE_BGNLOOP:
525 return TGSI_OPCODE_BGNLOOP;
526 case OPCODE_BGNSUB:
527 return TGSI_OPCODE_BGNSUB;
528 case OPCODE_BRA:
529 return TGSI_OPCODE_BRA;
530 case OPCODE_BRK:
531 return TGSI_OPCODE_BRK;
532 case OPCODE_CAL:
533 return TGSI_OPCODE_CAL;
534 case OPCODE_CMP:
535 return TGSI_OPCODE_CMP;
536 case OPCODE_CONT:
537 return TGSI_OPCODE_CONT;
538 case OPCODE_COS:
539 return TGSI_OPCODE_COS;
540 case OPCODE_DDX:
541 return TGSI_OPCODE_DDX;
542 case OPCODE_DDY:
543 return TGSI_OPCODE_DDY;
544 case OPCODE_DP2:
545 return TGSI_OPCODE_DP2;
546 case OPCODE_DP2A:
547 return TGSI_OPCODE_DP2A;
548 case OPCODE_DP3:
549 return TGSI_OPCODE_DP3;
550 case OPCODE_DP4:
551 return TGSI_OPCODE_DP4;
552 case OPCODE_DPH:
553 return TGSI_OPCODE_DPH;
554 case OPCODE_DST:
555 return TGSI_OPCODE_DST;
556 case OPCODE_ELSE:
557 return TGSI_OPCODE_ELSE;
558 case OPCODE_EMIT_VERTEX:
559 return TGSI_OPCODE_EMIT;
560 case OPCODE_END_PRIMITIVE:
561 return TGSI_OPCODE_ENDPRIM;
562 case OPCODE_ENDIF:
563 return TGSI_OPCODE_ENDIF;
564 case OPCODE_ENDLOOP:
565 return TGSI_OPCODE_ENDLOOP;
566 case OPCODE_ENDSUB:
567 return TGSI_OPCODE_ENDSUB;
568 case OPCODE_EX2:
569 return TGSI_OPCODE_EX2;
570 case OPCODE_EXP:
571 return TGSI_OPCODE_EXP;
572 case OPCODE_FLR:
573 return TGSI_OPCODE_FLR;
574 case OPCODE_FRC:
575 return TGSI_OPCODE_FRC;
576 case OPCODE_IF:
577 return TGSI_OPCODE_IF;
578 case OPCODE_TRUNC:
579 return TGSI_OPCODE_TRUNC;
580 case OPCODE_KIL:
581 return TGSI_OPCODE_KIL;
582 case OPCODE_KIL_NV:
583 return TGSI_OPCODE_KILP;
584 case OPCODE_LG2:
585 return TGSI_OPCODE_LG2;
586 case OPCODE_LOG:
587 return TGSI_OPCODE_LOG;
588 case OPCODE_LIT:
589 return TGSI_OPCODE_LIT;
590 case OPCODE_LRP:
591 return TGSI_OPCODE_LRP;
592 case OPCODE_MAD:
593 return TGSI_OPCODE_MAD;
594 case OPCODE_MAX:
595 return TGSI_OPCODE_MAX;
596 case OPCODE_MIN:
597 return TGSI_OPCODE_MIN;
598 case OPCODE_MOV:
599 return TGSI_OPCODE_MOV;
600 case OPCODE_MUL:
601 return TGSI_OPCODE_MUL;
602 case OPCODE_NOP:
603 return TGSI_OPCODE_NOP;
604 case OPCODE_NRM3:
605 return TGSI_OPCODE_NRM;
606 case OPCODE_NRM4:
607 return TGSI_OPCODE_NRM4;
608 case OPCODE_POW:
609 return TGSI_OPCODE_POW;
610 case OPCODE_RCP:
611 return TGSI_OPCODE_RCP;
612 case OPCODE_RET:
613 return TGSI_OPCODE_RET;
614 case OPCODE_RSQ:
615 return TGSI_OPCODE_RSQ;
616 case OPCODE_SCS:
617 return TGSI_OPCODE_SCS;
618 case OPCODE_SEQ:
619 return TGSI_OPCODE_SEQ;
620 case OPCODE_SGE:
621 return TGSI_OPCODE_SGE;
622 case OPCODE_SGT:
623 return TGSI_OPCODE_SGT;
624 case OPCODE_SIN:
625 return TGSI_OPCODE_SIN;
626 case OPCODE_SLE:
627 return TGSI_OPCODE_SLE;
628 case OPCODE_SLT:
629 return TGSI_OPCODE_SLT;
630 case OPCODE_SNE:
631 return TGSI_OPCODE_SNE;
632 case OPCODE_SSG:
633 return TGSI_OPCODE_SSG;
634 case OPCODE_SUB:
635 return TGSI_OPCODE_SUB;
636 case OPCODE_TEX:
637 return TGSI_OPCODE_TEX;
638 case OPCODE_TXB:
639 return TGSI_OPCODE_TXB;
640 case OPCODE_TXD:
641 return TGSI_OPCODE_TXD;
642 case OPCODE_TXL:
643 return TGSI_OPCODE_TXL;
644 case OPCODE_TXP:
645 return TGSI_OPCODE_TXP;
646 case OPCODE_XPD:
647 return TGSI_OPCODE_XPD;
648 case OPCODE_END:
649 return TGSI_OPCODE_END;
650 default:
651 debug_assert( 0 );
652 return TGSI_OPCODE_NOP;
653 }
654 }
655
656
657 static void
658 compile_instruction(
659 struct st_translate *t,
660 const struct prog_instruction *inst )
661 {
662 struct ureg_program *ureg = t->ureg;
663 GLuint i;
664 struct ureg_dst dst[1];
665 struct ureg_src src[4];
666 unsigned num_dst;
667 unsigned num_src;
668
669 num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
670 num_src = _mesa_num_inst_src_regs( inst->Opcode );
671
672 if (num_dst)
673 dst[0] = translate_dst( t,
674 &inst->DstReg,
675 inst->SaturateMode );
676
677 for (i = 0; i < num_src; i++)
678 src[i] = translate_src( t, &inst->SrcReg[i] );
679
680 switch( inst->Opcode ) {
681 case OPCODE_SWZ:
682 emit_swz( t, dst[0], &inst->SrcReg[0] );
683 return;
684
685 case OPCODE_BGNLOOP:
686 case OPCODE_CAL:
687 case OPCODE_ELSE:
688 case OPCODE_ENDLOOP:
689 case OPCODE_IF:
690 debug_assert(num_dst == 0);
691 ureg_label_insn( ureg,
692 translate_opcode( inst->Opcode ),
693 src, num_src,
694 get_label( t, inst->BranchTarget ));
695 return;
696
697 case OPCODE_TEX:
698 case OPCODE_TXB:
699 case OPCODE_TXD:
700 case OPCODE_TXL:
701 case OPCODE_TXP:
702 src[num_src++] = t->samplers[inst->TexSrcUnit];
703 ureg_tex_insn( ureg,
704 translate_opcode( inst->Opcode ),
705 dst, num_dst,
706 translate_texture_target( inst->TexSrcTarget,
707 inst->TexShadow ),
708 src, num_src );
709 return;
710
711 case OPCODE_SCS:
712 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
713 ureg_insn( ureg,
714 translate_opcode( inst->Opcode ),
715 dst, num_dst,
716 src, num_src );
717 break;
718
719 case OPCODE_XPD:
720 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
721 ureg_insn( ureg,
722 translate_opcode( inst->Opcode ),
723 dst, num_dst,
724 src, num_src );
725 break;
726
727 case OPCODE_NOISE1:
728 case OPCODE_NOISE2:
729 case OPCODE_NOISE3:
730 case OPCODE_NOISE4:
731 /* At some point, a motivated person could add a better
732 * implementation of noise. Currently not even the nvidia
733 * binary drivers do anything more than this. In any case, the
734 * place to do this is in the GL state tracker, not the poor
735 * driver.
736 */
737 ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
738 break;
739
740 case OPCODE_DDY:
741 emit_ddy( t, dst[0], &inst->SrcReg[0] );
742 break;
743
744 default:
745 ureg_insn( ureg,
746 translate_opcode( inst->Opcode ),
747 dst, num_dst,
748 src, num_src );
749 break;
750 }
751 }
752
753
754 /**
755 * Emit the TGSI instructions for inverting and adjusting WPOS.
756 * This code is unavoidable because it also depends on whether
757 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
758 */
759 static void
760 emit_wpos_adjustment( struct st_translate *t,
761 const struct gl_program *program,
762 boolean invert,
763 GLfloat adjX, GLfloat adjY[2])
764 {
765 struct ureg_program *ureg = t->ureg;
766
767 /* Fragment program uses fragment position input.
768 * Need to replace instances of INPUT[WPOS] with temp T
769 * where T = INPUT[WPOS] by y is inverted.
770 */
771 static const gl_state_index wposTransformState[STATE_LENGTH]
772 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
773
774 /* XXX: note we are modifying the incoming shader here! Need to
775 * do this before emitting the constant decls below, or this
776 * will be missed:
777 */
778 unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
779 wposTransformState);
780
781 struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
782 struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
783 struct ureg_src wpos_input = t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]];
784
785 /* First, apply the coordinate shift: */
786 if (adjX || adjY[0] || adjY[1]) {
787 if (adjY[0] != adjY[1]) {
788 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
789 * depending on whether inversion is actually going to be applied
790 * or not, which is determined by testing against the inversion
791 * state variable used below, which will be either +1 or -1.
792 */
793 struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
794
795 ureg_CMP(ureg, adj_temp,
796 ureg_scalar(wpostrans, invert ? 2 : 0),
797 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
798 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
799 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
800 } else {
801 ureg_ADD(ureg, wpos_temp, wpos_input,
802 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
803 }
804 wpos_input = ureg_src(wpos_temp);
805 } else {
806 /* MOV wpos_temp, input[wpos]
807 */
808 ureg_MOV( ureg, wpos_temp, wpos_input );
809 }
810
811 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
812 * inversion/identity, or the other way around if we're drawing to an FBO.
813 */
814 if (invert) {
815 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
816 */
817 ureg_MAD( ureg,
818 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
819 wpos_input,
820 ureg_scalar(wpostrans, 0),
821 ureg_scalar(wpostrans, 1));
822 } else {
823 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
824 */
825 ureg_MAD( ureg,
826 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
827 wpos_input,
828 ureg_scalar(wpostrans, 2),
829 ureg_scalar(wpostrans, 3));
830 }
831
832 /* Use wpos_temp as position input from here on:
833 */
834 t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]] = ureg_src(wpos_temp);
835 }
836
837
838 /**
839 * Emit fragment position/ooordinate code.
840 */
841 static void
842 emit_wpos(struct st_context *st,
843 struct st_translate *t,
844 const struct gl_program *program,
845 struct ureg_program *ureg)
846 {
847 const struct gl_fragment_program *fp =
848 (const struct gl_fragment_program *) program;
849 struct pipe_screen *pscreen = st->pipe->screen;
850 GLfloat adjX = 0.0f;
851 GLfloat adjY[2] = { 0.0f, 0.0f };
852 boolean invert = FALSE;
853
854 /* Query the pixel center conventions supported by the pipe driver and set
855 * adjX, adjY to help out if it cannot handle the requested one internally.
856 *
857 * The bias of the y-coordinate depends on whether y-inversion takes place
858 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
859 * drawing to an FBO (causes additional inversion), and whether the the pipe
860 * driver origin and the requested origin differ (the latter condition is
861 * stored in the 'invert' variable).
862 *
863 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
864 *
865 * center shift only:
866 * i -> h: +0.5
867 * h -> i: -0.5
868 *
869 * inversion only:
870 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
871 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
872 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
873 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
874 *
875 * inversion and center shift:
876 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
877 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
878 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
879 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
880 */
881 if (fp->OriginUpperLeft) {
882 /* Fragment shader wants origin in upper-left */
883 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
884 /* the driver supports upper-left origin */
885 }
886 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
887 /* the driver supports lower-left origin, need to invert Y */
888 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
889 invert = TRUE;
890 }
891 else
892 assert(0);
893 }
894 else {
895 /* Fragment shader wants origin in lower-left */
896 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
897 /* the driver supports lower-left origin */
898 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
899 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
900 /* the driver supports upper-left origin, need to invert Y */
901 invert = TRUE;
902 else
903 assert(0);
904 }
905
906 if (fp->PixelCenterInteger) {
907 /* Fragment shader wants pixel center integer */
908 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
909 /* the driver supports pixel center integer */
910 adjY[1] = 1.0f;
911 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
912 }
913 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
914 /* the driver supports pixel center half integer, need to bias X,Y */
915 adjX = -0.5f;
916 adjY[0] = -0.5f;
917 adjY[1] = 0.5f;
918 }
919 else
920 assert(0);
921 }
922 else {
923 /* Fragment shader wants pixel center half integer */
924 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
925 /* the driver supports pixel center half integer */
926 }
927 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
928 /* the driver supports pixel center integer, need to bias X,Y */
929 adjX = adjY[0] = adjY[1] = 0.5f;
930 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
931 }
932 else
933 assert(0);
934 }
935
936 /* we invert after adjustment so that we avoid the MOV to temporary,
937 * and reuse the adjustment ADD instead */
938 emit_wpos_adjustment(t, program, invert, adjX, adjY);
939 }
940
941
942 /**
943 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
944 * TGSI uses +1 for front, -1 for back.
945 * This function converts the TGSI value to the GL value. Simply clamping/
946 * saturating the value to [0,1] does the job.
947 */
948 static void
949 emit_face_var( struct st_translate *t,
950 const struct gl_program *program )
951 {
952 struct ureg_program *ureg = t->ureg;
953 struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
954 struct ureg_src face_input = t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]];
955
956 /* MOV_SAT face_temp, input[face]
957 */
958 face_temp = ureg_saturate( face_temp );
959 ureg_MOV( ureg, face_temp, face_input );
960
961 /* Use face_temp as face input from here on:
962 */
963 t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]] = ureg_src(face_temp);
964 }
965
966
967 static void
968 emit_edgeflags( struct st_translate *t,
969 const struct gl_program *program )
970 {
971 struct ureg_program *ureg = t->ureg;
972 struct ureg_dst edge_dst = t->outputs[t->outputMapping[VERT_RESULT_EDGE]];
973 struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
974
975 ureg_MOV( ureg, edge_dst, edge_src );
976 }
977
978
979 /**
980 * Translate Mesa program to TGSI format.
981 * \param program the program to translate
982 * \param numInputs number of input registers used
983 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
984 * input indexes
985 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
986 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
987 * each input
988 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
989 * \param numOutputs number of output registers used
990 * \param outputMapping maps Mesa fragment program outputs to TGSI
991 * generic outputs
992 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
993 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
994 * each output
995 *
996 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
997 */
998 enum pipe_error
999 st_translate_mesa_program(
1000 struct gl_context *ctx,
1001 uint procType,
1002 struct ureg_program *ureg,
1003 const struct gl_program *program,
1004 GLuint numInputs,
1005 const GLuint inputMapping[],
1006 const ubyte inputSemanticName[],
1007 const ubyte inputSemanticIndex[],
1008 const GLuint interpMode[],
1009 GLuint numOutputs,
1010 const GLuint outputMapping[],
1011 const ubyte outputSemanticName[],
1012 const ubyte outputSemanticIndex[],
1013 boolean passthrough_edgeflags )
1014 {
1015 struct st_translate translate, *t;
1016 unsigned i;
1017 enum pipe_error ret = PIPE_OK;
1018
1019 assert(numInputs <= Elements(t->inputs));
1020 assert(numOutputs <= Elements(t->outputs));
1021
1022 t = &translate;
1023 memset(t, 0, sizeof *t);
1024
1025 t->procType = procType;
1026 t->inputMapping = inputMapping;
1027 t->outputMapping = outputMapping;
1028 t->ureg = ureg;
1029 t->pointSizeOutIndex = -1;
1030 t->prevInstWrotePointSize = GL_FALSE;
1031
1032 /*_mesa_print_program(program);*/
1033
1034 /*
1035 * Declare input attributes.
1036 */
1037 if (procType == TGSI_PROCESSOR_FRAGMENT) {
1038 for (i = 0; i < numInputs; i++) {
1039 if (program->InputFlags[0] & PROG_PARAM_BIT_CYL_WRAP) {
1040 t->inputs[i] = ureg_DECL_fs_input_cyl(ureg,
1041 inputSemanticName[i],
1042 inputSemanticIndex[i],
1043 interpMode[i],
1044 TGSI_CYLINDRICAL_WRAP_X);
1045 }
1046 else {
1047 t->inputs[i] = ureg_DECL_fs_input(ureg,
1048 inputSemanticName[i],
1049 inputSemanticIndex[i],
1050 interpMode[i]);
1051 }
1052 }
1053
1054 if (program->InputsRead & FRAG_BIT_WPOS) {
1055 /* Must do this after setting up t->inputs, and before
1056 * emitting constant references, below:
1057 */
1058 emit_wpos(st_context(ctx), t, program, ureg);
1059 }
1060
1061 if (program->InputsRead & FRAG_BIT_FACE) {
1062 emit_face_var( t, program );
1063 }
1064
1065 /*
1066 * Declare output attributes.
1067 */
1068 for (i = 0; i < numOutputs; i++) {
1069 switch (outputSemanticName[i]) {
1070 case TGSI_SEMANTIC_POSITION:
1071 t->outputs[i] = ureg_DECL_output( ureg,
1072 TGSI_SEMANTIC_POSITION, /* Z / Depth */
1073 outputSemanticIndex[i] );
1074
1075 t->outputs[i] = ureg_writemask( t->outputs[i],
1076 TGSI_WRITEMASK_Z );
1077 break;
1078 case TGSI_SEMANTIC_STENCIL:
1079 t->outputs[i] = ureg_DECL_output( ureg,
1080 TGSI_SEMANTIC_STENCIL, /* Stencil */
1081 outputSemanticIndex[i] );
1082 t->outputs[i] = ureg_writemask( t->outputs[i],
1083 TGSI_WRITEMASK_Y );
1084 break;
1085 case TGSI_SEMANTIC_COLOR:
1086 t->outputs[i] = ureg_DECL_output( ureg,
1087 TGSI_SEMANTIC_COLOR,
1088 outputSemanticIndex[i] );
1089 break;
1090 default:
1091 debug_assert(0);
1092 return 0;
1093 }
1094 }
1095 }
1096 else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1097 for (i = 0; i < numInputs; i++) {
1098 t->inputs[i] = ureg_DECL_gs_input(ureg,
1099 i,
1100 inputSemanticName[i],
1101 inputSemanticIndex[i]);
1102 }
1103
1104 for (i = 0; i < numOutputs; i++) {
1105 t->outputs[i] = ureg_DECL_output( ureg,
1106 outputSemanticName[i],
1107 outputSemanticIndex[i] );
1108 }
1109 }
1110 else {
1111 assert(procType == TGSI_PROCESSOR_VERTEX);
1112
1113 for (i = 0; i < numInputs; i++) {
1114 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1115 }
1116
1117 for (i = 0; i < numOutputs; i++) {
1118 t->outputs[i] = ureg_DECL_output( ureg,
1119 outputSemanticName[i],
1120 outputSemanticIndex[i] );
1121 if ((outputSemanticName[i] == TGSI_SEMANTIC_PSIZE) && program->Id) {
1122 /* Writing to the point size result register requires special
1123 * handling to implement clamping.
1124 */
1125 static const gl_state_index pointSizeClampState[STATE_LENGTH]
1126 = { STATE_INTERNAL, STATE_POINT_SIZE_IMPL_CLAMP, 0, 0, 0 };
1127 /* XXX: note we are modifying the incoming shader here! Need to
1128 * do this before emitting the constant decls below, or this
1129 * will be missed:
1130 */
1131 unsigned pointSizeClampConst =
1132 _mesa_add_state_reference(program->Parameters,
1133 pointSizeClampState);
1134 struct ureg_dst psizregtemp = ureg_DECL_temporary( ureg );
1135 t->pointSizeConst = ureg_DECL_constant( ureg, pointSizeClampConst );
1136 t->pointSizeResult = t->outputs[i];
1137 t->pointSizeOutIndex = i;
1138 t->outputs[i] = psizregtemp;
1139 }
1140 }
1141 if (passthrough_edgeflags)
1142 emit_edgeflags( t, program );
1143 }
1144
1145 /* Declare address register.
1146 */
1147 if (program->NumAddressRegs > 0) {
1148 debug_assert( program->NumAddressRegs == 1 );
1149 t->address[0] = ureg_DECL_address( ureg );
1150 }
1151
1152 /* Declare misc input registers
1153 */
1154 {
1155 GLbitfield sysInputs = program->SystemValuesRead;
1156 unsigned numSys = 0;
1157 for (i = 0; sysInputs; i++) {
1158 if (sysInputs & (1 << i)) {
1159 unsigned semName = mesa_sysval_to_semantic[i];
1160 t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1161 numSys++;
1162 sysInputs &= ~(1 << i);
1163 }
1164 }
1165 }
1166
1167 if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1168 /* If temps are accessed with indirect addressing, declare temporaries
1169 * in sequential order. Else, we declare them on demand elsewhere.
1170 */
1171 for (i = 0; i < program->NumTemporaries; i++) {
1172 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1173 t->temps[i] = ureg_DECL_temporary( t->ureg );
1174 }
1175 }
1176
1177 /* Emit constants and immediates. Mesa uses a single index space
1178 * for these, so we put all the translated regs in t->constants.
1179 */
1180 if (program->Parameters) {
1181 t->constants = CALLOC( program->Parameters->NumParameters,
1182 sizeof t->constants[0] );
1183 if (t->constants == NULL) {
1184 ret = PIPE_ERROR_OUT_OF_MEMORY;
1185 goto out;
1186 }
1187
1188 for (i = 0; i < program->Parameters->NumParameters; i++) {
1189 switch (program->Parameters->Parameters[i].Type) {
1190 case PROGRAM_ENV_PARAM:
1191 case PROGRAM_LOCAL_PARAM:
1192 case PROGRAM_STATE_VAR:
1193 case PROGRAM_NAMED_PARAM:
1194 case PROGRAM_UNIFORM:
1195 t->constants[i] = ureg_DECL_constant( ureg, i );
1196 break;
1197
1198 /* Emit immediates only when there's no indirect addressing of
1199 * the const buffer.
1200 * FIXME: Be smarter and recognize param arrays:
1201 * indirect addressing is only valid within the referenced
1202 * array.
1203 */
1204 case PROGRAM_CONSTANT:
1205 if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1206 t->constants[i] = ureg_DECL_constant( ureg, i );
1207 else
1208 t->constants[i] =
1209 ureg_DECL_immediate( ureg,
1210 (const float*) program->Parameters->ParameterValues[i],
1211 4 );
1212 break;
1213 default:
1214 break;
1215 }
1216 }
1217 }
1218
1219 /* texture samplers */
1220 for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
1221 if (program->SamplersUsed & (1 << i)) {
1222 t->samplers[i] = ureg_DECL_sampler( ureg, i );
1223 }
1224 }
1225
1226 /* Emit each instruction in turn:
1227 */
1228 for (i = 0; i < program->NumInstructions; i++) {
1229 set_insn_start( t, ureg_get_instruction_number( ureg ));
1230 compile_instruction( t, &program->Instructions[i] );
1231
1232 if (t->prevInstWrotePointSize && program->Id) {
1233 /* The previous instruction wrote to the (fake) vertex point size
1234 * result register. Now we need to clamp that value to the min/max
1235 * point size range, putting the result into the real point size
1236 * register.
1237 * Note that we can't do this easily at the end of program due to
1238 * possible early return.
1239 */
1240 set_insn_start( t, ureg_get_instruction_number( ureg ));
1241 ureg_MAX( t->ureg,
1242 ureg_writemask(t->outputs[t->pointSizeOutIndex], WRITEMASK_X),
1243 ureg_src(t->outputs[t->pointSizeOutIndex]),
1244 ureg_swizzle(t->pointSizeConst, 1,1,1,1));
1245 ureg_MIN( t->ureg, ureg_writemask(t->pointSizeResult, WRITEMASK_X),
1246 ureg_src(t->outputs[t->pointSizeOutIndex]),
1247 ureg_swizzle(t->pointSizeConst, 2,2,2,2));
1248 }
1249 t->prevInstWrotePointSize = GL_FALSE;
1250 }
1251
1252 /* Fix up all emitted labels:
1253 */
1254 for (i = 0; i < t->labels_count; i++) {
1255 ureg_fixup_label( ureg,
1256 t->labels[i].token,
1257 t->insn[t->labels[i].branch_target] );
1258 }
1259
1260 out:
1261 FREE(t->insn);
1262 FREE(t->labels);
1263 FREE(t->constants);
1264
1265 if (t->error) {
1266 debug_printf("%s: translate error flag set\n", __FUNCTION__);
1267 }
1268
1269 return ret;
1270 }
1271
1272
1273 /**
1274 * Tokens cannot be free with free otherwise the builtin gallium
1275 * malloc debugging will get confused.
1276 */
1277 void
1278 st_free_tokens(const struct tgsi_token *tokens)
1279 {
1280 FREE((void *)tokens);
1281 }