projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
s/Tungsten Graphics/VMware/
[mesa.git] / src / mesa / state_tracker / st_mesa_to_tgsi.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * \author
30 * Michal Krol,
31 * Keith Whitwell
32 */
33
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47
48
49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
50 (1 << PROGRAM_CONSTANT) | \
51 (1 << PROGRAM_UNIFORM))
52
53
54 struct label {
55 unsigned branch_target;
56 unsigned token;
57 };
58
59
60 /**
61 * Intermediate state used during shader translation.
62 */
63 struct st_translate {
64 struct ureg_program *ureg;
65
66 struct ureg_dst temps[MAX_PROGRAM_TEMPS];
67 struct ureg_src *constants;
68 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
69 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
70 struct ureg_dst address[1];
71 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
72 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
73
74 const GLuint *inputMapping;
75 const GLuint *outputMapping;
76
77 /* For every instruction that contains a label (eg CALL), keep
78 * details so that we can go back afterwards and emit the correct
79 * tgsi instruction number for each label.
80 */
81 struct label *labels;
82 unsigned labels_size;
83 unsigned labels_count;
84
85 /* Keep a record of the tgsi instruction number that each mesa
86 * instruction starts at, will be used to fix up labels after
87 * translation.
88 */
89 unsigned *insn;
90 unsigned insn_size;
91 unsigned insn_count;
92
93 unsigned procType; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
94
95 boolean error;
96 };
97
98
99 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
100 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
101 TGSI_SEMANTIC_FACE,
102 TGSI_SEMANTIC_VERTEXID,
103 TGSI_SEMANTIC_INSTANCEID
104 };
105
106
107 /**
108 * Make note of a branch to a label in the TGSI code.
109 * After we've emitted all instructions, we'll go over the list
110 * of labels built here and patch the TGSI code with the actual
111 * location of each label.
112 */
113 static unsigned *get_label( struct st_translate *t,
114 unsigned branch_target )
115 {
116 unsigned i;
117
118 if (t->labels_count + 1 >= t->labels_size) {
119 t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
120 t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
121 if (t->labels == NULL) {
122 static unsigned dummy;
123 t->error = TRUE;
124 return &dummy;
125 }
126 }
127
128 i = t->labels_count++;
129 t->labels[i].branch_target = branch_target;
130 return &t->labels[i].token;
131 }
132
133
134 /**
135 * Called prior to emitting the TGSI code for each Mesa instruction.
136 * Allocate additional space for instructions if needed.
137 * Update the insn[] array so the next Mesa instruction points to
138 * the next TGSI instruction.
139 */
140 static void set_insn_start( struct st_translate *t,
141 unsigned start )
142 {
143 if (t->insn_count + 1 >= t->insn_size) {
144 t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
145 t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
146 if (t->insn == NULL) {
147 t->error = TRUE;
148 return;
149 }
150 }
151
152 t->insn[t->insn_count++] = start;
153 }
154
155
156 /**
157 * Map a Mesa dst register to a TGSI ureg_dst register.
158 */
159 static struct ureg_dst
160 dst_register( struct st_translate *t,
161 gl_register_file file,
162 GLuint index )
163 {
164 switch( file ) {
165 case PROGRAM_UNDEFINED:
166 return ureg_dst_undef();
167
168 case PROGRAM_TEMPORARY:
169 if (ureg_dst_is_undef(t->temps[index]))
170 t->temps[index] = ureg_DECL_temporary( t->ureg );
171
172 return t->temps[index];
173
174 case PROGRAM_OUTPUT:
175 if (t->procType == TGSI_PROCESSOR_VERTEX)
176 assert(index < VARYING_SLOT_MAX);
177 else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
178 assert(index < FRAG_RESULT_MAX);
179 else
180 assert(index < VARYING_SLOT_MAX);
181
182 assert(t->outputMapping[index] < Elements(t->outputs));
183
184 return t->outputs[t->outputMapping[index]];
185
186 case PROGRAM_ADDRESS:
187 return t->address[index];
188
189 default:
190 debug_assert( 0 );
191 return ureg_dst_undef();
192 }
193 }
194
195
196 /**
197 * Map a Mesa src register to a TGSI ureg_src register.
198 */
199 static struct ureg_src
200 src_register( struct st_translate *t,
201 gl_register_file file,
202 GLint index )
203 {
204 switch( file ) {
205 case PROGRAM_UNDEFINED:
206 return ureg_src_undef();
207
208 case PROGRAM_TEMPORARY:
209 assert(index >= 0);
210 assert(index < Elements(t->temps));
211 if (ureg_dst_is_undef(t->temps[index]))
212 t->temps[index] = ureg_DECL_temporary( t->ureg );
213 return ureg_src(t->temps[index]);
214
215 case PROGRAM_UNIFORM:
216 assert(index >= 0);
217 return t->constants[index];
218 case PROGRAM_STATE_VAR:
219 case PROGRAM_CONSTANT: /* ie, immediate */
220 if (index < 0)
221 return ureg_DECL_constant( t->ureg, 0 );
222 else
223 return t->constants[index];
224
225 case PROGRAM_INPUT:
226 assert(t->inputMapping[index] < Elements(t->inputs));
227 return t->inputs[t->inputMapping[index]];
228
229 case PROGRAM_OUTPUT:
230 assert(t->outputMapping[index] < Elements(t->outputs));
231 return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
232
233 case PROGRAM_ADDRESS:
234 return ureg_src(t->address[index]);
235
236 case PROGRAM_SYSTEM_VALUE:
237 assert(index < Elements(t->systemValues));
238 return t->systemValues[index];
239
240 default:
241 debug_assert( 0 );
242 return ureg_src_undef();
243 }
244 }
245
246
247 /**
248 * Map mesa texture target to TGSI texture target.
249 */
250 unsigned
251 st_translate_texture_target( GLuint textarget,
252 GLboolean shadow )
253 {
254 if (shadow) {
255 switch( textarget ) {
256 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_SHADOW1D;
257 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_SHADOW2D;
258 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
259 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
260 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
261 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
262 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
263 default: break;
264 }
265 }
266
267 switch( textarget ) {
268 case TEXTURE_2D_MULTISAMPLE_INDEX: return TGSI_TEXTURE_2D_MSAA;
269 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY_MSAA;
270 case TEXTURE_BUFFER_INDEX: return TGSI_TEXTURE_BUFFER;
271 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_1D;
272 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_2D;
273 case TEXTURE_3D_INDEX: return TGSI_TEXTURE_3D;
274 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
275 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
276 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
277 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_1D_ARRAY;
278 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY;
279 case TEXTURE_EXTERNAL_INDEX: return TGSI_TEXTURE_2D;
280 default:
281 debug_assert( 0 );
282 return TGSI_TEXTURE_1D;
283 }
284 }
285
286
287 /**
288 * Create a TGSI ureg_dst register from a Mesa dest register.
289 */
290 static struct ureg_dst
291 translate_dst( struct st_translate *t,
292 const struct prog_dst_register *DstReg,
293 boolean saturate,
294 boolean clamp_color)
295 {
296 struct ureg_dst dst = dst_register( t,
297 DstReg->File,
298 DstReg->Index );
299
300 dst = ureg_writemask( dst,
301 DstReg->WriteMask );
302
303 if (saturate)
304 dst = ureg_saturate( dst );
305 else if (clamp_color && DstReg->File == PROGRAM_OUTPUT) {
306 /* Clamp colors for ARB_color_buffer_float. */
307 switch (t->procType) {
308 case TGSI_PROCESSOR_VERTEX:
309 /* XXX if the geometry shader is present, this must be done there
310 * instead of here. */
311 if (DstReg->Index == VARYING_SLOT_COL0 ||
312 DstReg->Index == VARYING_SLOT_COL1 ||
313 DstReg->Index == VARYING_SLOT_BFC0 ||
314 DstReg->Index == VARYING_SLOT_BFC1) {
315 dst = ureg_saturate(dst);
316 }
317 break;
318
319 case TGSI_PROCESSOR_FRAGMENT:
320 if (DstReg->Index >= FRAG_RESULT_COLOR) {
321 dst = ureg_saturate(dst);
322 }
323 break;
324 }
325 }
326
327 if (DstReg->RelAddr)
328 dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
329
330 return dst;
331 }
332
333
334 /**
335 * Create a TGSI ureg_src register from a Mesa src register.
336 */
337 static struct ureg_src
338 translate_src( struct st_translate *t,
339 const struct prog_src_register *SrcReg )
340 {
341 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
342
343 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
344 src = src_register( t, SrcReg->File, SrcReg->Index2 );
345 if (SrcReg->RelAddr2)
346 src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
347 SrcReg->Index);
348 else
349 src = ureg_src_dimension( src, SrcReg->Index);
350 }
351
352 src = ureg_swizzle( src,
353 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
354 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
355 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
356 GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
357
358 if (SrcReg->Negate == NEGATE_XYZW)
359 src = ureg_negate(src);
360
361 if (SrcReg->Abs)
362 src = ureg_abs(src);
363
364 if (SrcReg->RelAddr) {
365 src = ureg_src_indirect( src, ureg_src(t->address[0]));
366 if (SrcReg->File != PROGRAM_INPUT &&
367 SrcReg->File != PROGRAM_OUTPUT) {
368 /* If SrcReg->Index was negative, it was set to zero in
369 * src_register(). Reassign it now. But don't do this
370 * for input/output regs since they get remapped while
371 * const buffers don't.
372 */
373 src.Index = SrcReg->Index;
374 }
375 }
376
377 return src;
378 }
379
380
381 static struct ureg_src swizzle_4v( struct ureg_src src,
382 const unsigned *swz )
383 {
384 return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
385 }
386
387
388 /**
389 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
390 *
391 * SWZ dst, src.x-y10
392 *
393 * becomes:
394 *
395 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
396 */
397 static void emit_swz( struct st_translate *t,
398 struct ureg_dst dst,
399 const struct prog_src_register *SrcReg )
400 {
401 struct ureg_program *ureg = t->ureg;
402 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
403
404 unsigned negate_mask = SrcReg->Negate;
405
406 unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
407 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
408 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
409 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
410
411 unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
412 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
413 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
414 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
415
416 unsigned negative_one_mask = one_mask & negate_mask;
417 unsigned positive_one_mask = one_mask & ~negate_mask;
418
419 struct ureg_src imm;
420 unsigned i;
421 unsigned mul_swizzle[4] = {0,0,0,0};
422 unsigned add_swizzle[4] = {0,0,0,0};
423 unsigned src_swizzle[4] = {0,0,0,0};
424 boolean need_add = FALSE;
425 boolean need_mul = FALSE;
426
427 if (dst.WriteMask == 0)
428 return;
429
430 /* Is this just a MOV?
431 */
432 if (zero_mask == 0 &&
433 one_mask == 0 &&
434 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
435 {
436 ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
437 return;
438 }
439
440 #define IMM_ZERO 0
441 #define IMM_ONE 1
442 #define IMM_NEG_ONE 2
443
444 imm = ureg_imm3f( ureg, 0, 1, -1 );
445
446 for (i = 0; i < 4; i++) {
447 unsigned bit = 1 << i;
448
449 if (dst.WriteMask & bit) {
450 if (positive_one_mask & bit) {
451 mul_swizzle[i] = IMM_ZERO;
452 add_swizzle[i] = IMM_ONE;
453 need_add = TRUE;
454 }
455 else if (negative_one_mask & bit) {
456 mul_swizzle[i] = IMM_ZERO;
457 add_swizzle[i] = IMM_NEG_ONE;
458 need_add = TRUE;
459 }
460 else if (zero_mask & bit) {
461 mul_swizzle[i] = IMM_ZERO;
462 add_swizzle[i] = IMM_ZERO;
463 need_add = TRUE;
464 }
465 else {
466 add_swizzle[i] = IMM_ZERO;
467 src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
468 need_mul = TRUE;
469 if (negate_mask & bit) {
470 mul_swizzle[i] = IMM_NEG_ONE;
471 }
472 else {
473 mul_swizzle[i] = IMM_ONE;
474 }
475 }
476 }
477 }
478
479 if (need_mul && need_add) {
480 ureg_MAD( ureg,
481 dst,
482 swizzle_4v( src, src_swizzle ),
483 swizzle_4v( imm, mul_swizzle ),
484 swizzle_4v( imm, add_swizzle ) );
485 }
486 else if (need_mul) {
487 ureg_MUL( ureg,
488 dst,
489 swizzle_4v( src, src_swizzle ),
490 swizzle_4v( imm, mul_swizzle ) );
491 }
492 else if (need_add) {
493 ureg_MOV( ureg,
494 dst,
495 swizzle_4v( imm, add_swizzle ) );
496 }
497 else {
498 debug_assert(0);
499 }
500
501 #undef IMM_ZERO
502 #undef IMM_ONE
503 #undef IMM_NEG_ONE
504 }
505
506
507 /**
508 * Negate the value of DDY to match GL semantics where (0,0) is the
509 * lower-left corner of the window.
510 * Note that the GL_ARB_fragment_coord_conventions extension will
511 * effect this someday.
512 */
513 static void emit_ddy( struct st_translate *t,
514 struct ureg_dst dst,
515 const struct prog_src_register *SrcReg )
516 {
517 struct ureg_program *ureg = t->ureg;
518 struct ureg_src src = translate_src( t, SrcReg );
519 src = ureg_negate( src );
520 ureg_DDY( ureg, dst, src );
521 }
522
523
524
525 static unsigned
526 translate_opcode( unsigned op )
527 {
528 switch( op ) {
529 case OPCODE_ARL:
530 return TGSI_OPCODE_ARL;
531 case OPCODE_ABS:
532 return TGSI_OPCODE_ABS;
533 case OPCODE_ADD:
534 return TGSI_OPCODE_ADD;
535 case OPCODE_BGNLOOP:
536 return TGSI_OPCODE_BGNLOOP;
537 case OPCODE_BGNSUB:
538 return TGSI_OPCODE_BGNSUB;
539 case OPCODE_BRK:
540 return TGSI_OPCODE_BRK;
541 case OPCODE_CAL:
542 return TGSI_OPCODE_CAL;
543 case OPCODE_CMP:
544 return TGSI_OPCODE_CMP;
545 case OPCODE_CONT:
546 return TGSI_OPCODE_CONT;
547 case OPCODE_COS:
548 return TGSI_OPCODE_COS;
549 case OPCODE_DDX:
550 return TGSI_OPCODE_DDX;
551 case OPCODE_DDY:
552 return TGSI_OPCODE_DDY;
553 case OPCODE_DP2:
554 return TGSI_OPCODE_DP2;
555 case OPCODE_DP3:
556 return TGSI_OPCODE_DP3;
557 case OPCODE_DP4:
558 return TGSI_OPCODE_DP4;
559 case OPCODE_DPH:
560 return TGSI_OPCODE_DPH;
561 case OPCODE_DST:
562 return TGSI_OPCODE_DST;
563 case OPCODE_ELSE:
564 return TGSI_OPCODE_ELSE;
565 case OPCODE_ENDIF:
566 return TGSI_OPCODE_ENDIF;
567 case OPCODE_ENDLOOP:
568 return TGSI_OPCODE_ENDLOOP;
569 case OPCODE_ENDSUB:
570 return TGSI_OPCODE_ENDSUB;
571 case OPCODE_EX2:
572 return TGSI_OPCODE_EX2;
573 case OPCODE_EXP:
574 return TGSI_OPCODE_EXP;
575 case OPCODE_FLR:
576 return TGSI_OPCODE_FLR;
577 case OPCODE_FRC:
578 return TGSI_OPCODE_FRC;
579 case OPCODE_IF:
580 return TGSI_OPCODE_IF;
581 case OPCODE_TRUNC:
582 return TGSI_OPCODE_TRUNC;
583 case OPCODE_KIL:
584 return TGSI_OPCODE_KILL_IF;
585 case OPCODE_KIL_NV:
586 /* XXX we don't support condition codes in TGSI */
587 return TGSI_OPCODE_KILL;
588 case OPCODE_LG2:
589 return TGSI_OPCODE_LG2;
590 case OPCODE_LOG:
591 return TGSI_OPCODE_LOG;
592 case OPCODE_LIT:
593 return TGSI_OPCODE_LIT;
594 case OPCODE_LRP:
595 return TGSI_OPCODE_LRP;
596 case OPCODE_MAD:
597 return TGSI_OPCODE_MAD;
598 case OPCODE_MAX:
599 return TGSI_OPCODE_MAX;
600 case OPCODE_MIN:
601 return TGSI_OPCODE_MIN;
602 case OPCODE_MOV:
603 return TGSI_OPCODE_MOV;
604 case OPCODE_MUL:
605 return TGSI_OPCODE_MUL;
606 case OPCODE_NOP:
607 return TGSI_OPCODE_NOP;
608 case OPCODE_POW:
609 return TGSI_OPCODE_POW;
610 case OPCODE_RCP:
611 return TGSI_OPCODE_RCP;
612 case OPCODE_RET:
613 return TGSI_OPCODE_RET;
614 case OPCODE_SCS:
615 return TGSI_OPCODE_SCS;
616 case OPCODE_SEQ:
617 return TGSI_OPCODE_SEQ;
618 case OPCODE_SGE:
619 return TGSI_OPCODE_SGE;
620 case OPCODE_SGT:
621 return TGSI_OPCODE_SGT;
622 case OPCODE_SIN:
623 return TGSI_OPCODE_SIN;
624 case OPCODE_SLE:
625 return TGSI_OPCODE_SLE;
626 case OPCODE_SLT:
627 return TGSI_OPCODE_SLT;
628 case OPCODE_SNE:
629 return TGSI_OPCODE_SNE;
630 case OPCODE_SSG:
631 return TGSI_OPCODE_SSG;
632 case OPCODE_SUB:
633 return TGSI_OPCODE_SUB;
634 case OPCODE_TEX:
635 return TGSI_OPCODE_TEX;
636 case OPCODE_TXB:
637 return TGSI_OPCODE_TXB;
638 case OPCODE_TXD:
639 return TGSI_OPCODE_TXD;
640 case OPCODE_TXL:
641 return TGSI_OPCODE_TXL;
642 case OPCODE_TXP:
643 return TGSI_OPCODE_TXP;
644 case OPCODE_XPD:
645 return TGSI_OPCODE_XPD;
646 case OPCODE_END:
647 return TGSI_OPCODE_END;
648 default:
649 debug_assert( 0 );
650 return TGSI_OPCODE_NOP;
651 }
652 }
653
654
655 static void
656 compile_instruction(
657 struct gl_context *ctx,
658 struct st_translate *t,
659 const struct prog_instruction *inst,
660 boolean clamp_dst_color_output)
661 {
662 struct ureg_program *ureg = t->ureg;
663 GLuint i;
664 struct ureg_dst dst[1] = { { 0 } };
665 struct ureg_src src[4];
666 unsigned num_dst;
667 unsigned num_src;
668
669 num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
670 num_src = _mesa_num_inst_src_regs( inst->Opcode );
671
672 if (num_dst)
673 dst[0] = translate_dst( t,
674 &inst->DstReg,
675 inst->SaturateMode,
676 clamp_dst_color_output);
677
678 for (i = 0; i < num_src; i++)
679 src[i] = translate_src( t, &inst->SrcReg[i] );
680
681 switch( inst->Opcode ) {
682 case OPCODE_SWZ:
683 emit_swz( t, dst[0], &inst->SrcReg[0] );
684 return;
685
686 case OPCODE_BGNLOOP:
687 case OPCODE_CAL:
688 case OPCODE_ELSE:
689 case OPCODE_ENDLOOP:
690 debug_assert(num_dst == 0);
691 ureg_label_insn( ureg,
692 translate_opcode( inst->Opcode ),
693 src, num_src,
694 get_label( t, inst->BranchTarget ));
695 return;
696
697 case OPCODE_IF:
698 debug_assert(num_dst == 0);
699 ureg_label_insn( ureg,
700 ctx->Const.NativeIntegers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF,
701 src, num_src,
702 get_label( t, inst->BranchTarget ));
703 return;
704
705 case OPCODE_TEX:
706 case OPCODE_TXB:
707 case OPCODE_TXD:
708 case OPCODE_TXL:
709 case OPCODE_TXP:
710 src[num_src++] = t->samplers[inst->TexSrcUnit];
711 ureg_tex_insn( ureg,
712 translate_opcode( inst->Opcode ),
713 dst, num_dst,
714 st_translate_texture_target( inst->TexSrcTarget,
715 inst->TexShadow ),
716 NULL, 0,
717 src, num_src );
718 return;
719
720 case OPCODE_SCS:
721 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
722 ureg_insn( ureg,
723 translate_opcode( inst->Opcode ),
724 dst, num_dst,
725 src, num_src );
726 break;
727
728 case OPCODE_XPD:
729 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
730 ureg_insn( ureg,
731 translate_opcode( inst->Opcode ),
732 dst, num_dst,
733 src, num_src );
734 break;
735
736 case OPCODE_NOISE1:
737 case OPCODE_NOISE2:
738 case OPCODE_NOISE3:
739 case OPCODE_NOISE4:
740 /* At some point, a motivated person could add a better
741 * implementation of noise. Currently not even the nvidia
742 * binary drivers do anything more than this. In any case, the
743 * place to do this is in the GL state tracker, not the poor
744 * driver.
745 */
746 ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
747 break;
748
749 case OPCODE_DDY:
750 emit_ddy( t, dst[0], &inst->SrcReg[0] );
751 break;
752
753 case OPCODE_RSQ:
754 ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
755 break;
756
757 default:
758 ureg_insn( ureg,
759 translate_opcode( inst->Opcode ),
760 dst, num_dst,
761 src, num_src );
762 break;
763 }
764 }
765
766
767 /**
768 * Emit the TGSI instructions for inverting and adjusting WPOS.
769 * This code is unavoidable because it also depends on whether
770 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
771 */
772 static void
773 emit_wpos_adjustment( struct st_translate *t,
774 const struct gl_program *program,
775 boolean invert,
776 GLfloat adjX, GLfloat adjY[2])
777 {
778 struct ureg_program *ureg = t->ureg;
779
780 /* Fragment program uses fragment position input.
781 * Need to replace instances of INPUT[WPOS] with temp T
782 * where T = INPUT[WPOS] by y is inverted.
783 */
784 static const gl_state_index wposTransformState[STATE_LENGTH]
785 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
786
787 /* XXX: note we are modifying the incoming shader here! Need to
788 * do this before emitting the constant decls below, or this
789 * will be missed:
790 */
791 unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
792 wposTransformState);
793
794 struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
795 struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
796 struct ureg_src wpos_input = t->inputs[t->inputMapping[VARYING_SLOT_POS]];
797
798 /* First, apply the coordinate shift: */
799 if (adjX || adjY[0] || adjY[1]) {
800 if (adjY[0] != adjY[1]) {
801 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
802 * depending on whether inversion is actually going to be applied
803 * or not, which is determined by testing against the inversion
804 * state variable used below, which will be either +1 or -1.
805 */
806 struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
807
808 ureg_CMP(ureg, adj_temp,
809 ureg_scalar(wpostrans, invert ? 2 : 0),
810 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
811 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
812 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
813 } else {
814 ureg_ADD(ureg, wpos_temp, wpos_input,
815 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
816 }
817 wpos_input = ureg_src(wpos_temp);
818 } else {
819 /* MOV wpos_temp, input[wpos]
820 */
821 ureg_MOV( ureg, wpos_temp, wpos_input );
822 }
823
824 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
825 * inversion/identity, or the other way around if we're drawing to an FBO.
826 */
827 if (invert) {
828 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
829 */
830 ureg_MAD( ureg,
831 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
832 wpos_input,
833 ureg_scalar(wpostrans, 0),
834 ureg_scalar(wpostrans, 1));
835 } else {
836 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
837 */
838 ureg_MAD( ureg,
839 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
840 wpos_input,
841 ureg_scalar(wpostrans, 2),
842 ureg_scalar(wpostrans, 3));
843 }
844
845 /* Use wpos_temp as position input from here on:
846 */
847 t->inputs[t->inputMapping[VARYING_SLOT_POS]] = ureg_src(wpos_temp);
848 }
849
850
851 /**
852 * Emit fragment position/coordinate code.
853 */
854 static void
855 emit_wpos(struct st_context *st,
856 struct st_translate *t,
857 const struct gl_program *program,
858 struct ureg_program *ureg)
859 {
860 const struct gl_fragment_program *fp =
861 (const struct gl_fragment_program *) program;
862 struct pipe_screen *pscreen = st->pipe->screen;
863 GLfloat adjX = 0.0f;
864 GLfloat adjY[2] = { 0.0f, 0.0f };
865 boolean invert = FALSE;
866
867 /* Query the pixel center conventions supported by the pipe driver and set
868 * adjX, adjY to help out if it cannot handle the requested one internally.
869 *
870 * The bias of the y-coordinate depends on whether y-inversion takes place
871 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
872 * drawing to an FBO (causes additional inversion), and whether the the pipe
873 * driver origin and the requested origin differ (the latter condition is
874 * stored in the 'invert' variable).
875 *
876 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
877 *
878 * center shift only:
879 * i -> h: +0.5
880 * h -> i: -0.5
881 *
882 * inversion only:
883 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
884 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
885 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
886 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
887 *
888 * inversion and center shift:
889 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
890 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
891 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
892 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
893 */
894 if (fp->OriginUpperLeft) {
895 /* Fragment shader wants origin in upper-left */
896 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
897 /* the driver supports upper-left origin */
898 }
899 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
900 /* the driver supports lower-left origin, need to invert Y */
901 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
902 invert = TRUE;
903 }
904 else
905 assert(0);
906 }
907 else {
908 /* Fragment shader wants origin in lower-left */
909 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
910 /* the driver supports lower-left origin */
911 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
912 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
913 /* the driver supports upper-left origin, need to invert Y */
914 invert = TRUE;
915 else
916 assert(0);
917 }
918
919 if (fp->PixelCenterInteger) {
920 /* Fragment shader wants pixel center integer */
921 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
922 /* the driver supports pixel center integer */
923 adjY[1] = 1.0f;
924 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
925 }
926 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
927 /* the driver supports pixel center half integer, need to bias X,Y */
928 adjX = -0.5f;
929 adjY[0] = -0.5f;
930 adjY[1] = 0.5f;
931 }
932 else
933 assert(0);
934 }
935 else {
936 /* Fragment shader wants pixel center half integer */
937 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
938 /* the driver supports pixel center half integer */
939 }
940 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
941 /* the driver supports pixel center integer, need to bias X,Y */
942 adjX = adjY[0] = adjY[1] = 0.5f;
943 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
944 }
945 else
946 assert(0);
947 }
948
949 /* we invert after adjustment so that we avoid the MOV to temporary,
950 * and reuse the adjustment ADD instead */
951 emit_wpos_adjustment(t, program, invert, adjX, adjY);
952 }
953
954
955 /**
956 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
957 * TGSI uses +1 for front, -1 for back.
958 * This function converts the TGSI value to the GL value. Simply clamping/
959 * saturating the value to [0,1] does the job.
960 */
961 static void
962 emit_face_var( struct st_translate *t,
963 const struct gl_program *program )
964 {
965 struct ureg_program *ureg = t->ureg;
966 struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
967 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
968
969 /* MOV_SAT face_temp, input[face]
970 */
971 face_temp = ureg_saturate( face_temp );
972 ureg_MOV( ureg, face_temp, face_input );
973
974 /* Use face_temp as face input from here on:
975 */
976 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
977 }
978
979
980 static void
981 emit_edgeflags( struct st_translate *t,
982 const struct gl_program *program )
983 {
984 struct ureg_program *ureg = t->ureg;
985 struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]];
986 struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
987
988 ureg_MOV( ureg, edge_dst, edge_src );
989 }
990
991
992 /**
993 * Translate Mesa program to TGSI format.
994 * \param program the program to translate
995 * \param numInputs number of input registers used
996 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
997 * input indexes
998 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
999 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
1000 * each input
1001 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
1002 * \param numOutputs number of output registers used
1003 * \param outputMapping maps Mesa fragment program outputs to TGSI
1004 * generic outputs
1005 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
1006 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
1007 * each output
1008 *
1009 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
1010 */
1011 enum pipe_error
1012 st_translate_mesa_program(
1013 struct gl_context *ctx,
1014 uint procType,
1015 struct ureg_program *ureg,
1016 const struct gl_program *program,
1017 GLuint numInputs,
1018 const GLuint inputMapping[],
1019 const ubyte inputSemanticName[],
1020 const ubyte inputSemanticIndex[],
1021 const GLuint interpMode[],
1022 GLuint numOutputs,
1023 const GLuint outputMapping[],
1024 const ubyte outputSemanticName[],
1025 const ubyte outputSemanticIndex[],
1026 boolean passthrough_edgeflags,
1027 boolean clamp_color)
1028 {
1029 struct st_translate translate, *t;
1030 unsigned i;
1031 enum pipe_error ret = PIPE_OK;
1032
1033 assert(numInputs <= Elements(t->inputs));
1034 assert(numOutputs <= Elements(t->outputs));
1035
1036 t = &translate;
1037 memset(t, 0, sizeof *t);
1038
1039 t->procType = procType;
1040 t->inputMapping = inputMapping;
1041 t->outputMapping = outputMapping;
1042 t->ureg = ureg;
1043
1044 /*_mesa_print_program(program);*/
1045
1046 /*
1047 * Declare input attributes.
1048 */
1049 if (procType == TGSI_PROCESSOR_FRAGMENT) {
1050 for (i = 0; i < numInputs; i++) {
1051 t->inputs[i] = ureg_DECL_fs_input(ureg,
1052 inputSemanticName[i],
1053 inputSemanticIndex[i],
1054 interpMode[i]);
1055 }
1056
1057 if (program->InputsRead & VARYING_BIT_POS) {
1058 /* Must do this after setting up t->inputs, and before
1059 * emitting constant references, below:
1060 */
1061 emit_wpos(st_context(ctx), t, program, ureg);
1062 }
1063
1064 if (program->InputsRead & VARYING_BIT_FACE) {
1065 emit_face_var( t, program );
1066 }
1067
1068 /*
1069 * Declare output attributes.
1070 */
1071 for (i = 0; i < numOutputs; i++) {
1072 switch (outputSemanticName[i]) {
1073 case TGSI_SEMANTIC_POSITION:
1074 t->outputs[i] = ureg_DECL_output( ureg,
1075 TGSI_SEMANTIC_POSITION, /* Z / Depth */
1076 outputSemanticIndex[i] );
1077
1078 t->outputs[i] = ureg_writemask( t->outputs[i],
1079 TGSI_WRITEMASK_Z );
1080 break;
1081 case TGSI_SEMANTIC_STENCIL:
1082 t->outputs[i] = ureg_DECL_output( ureg,
1083 TGSI_SEMANTIC_STENCIL, /* Stencil */
1084 outputSemanticIndex[i] );
1085 t->outputs[i] = ureg_writemask( t->outputs[i],
1086 TGSI_WRITEMASK_Y );
1087 break;
1088 case TGSI_SEMANTIC_COLOR:
1089 t->outputs[i] = ureg_DECL_output( ureg,
1090 TGSI_SEMANTIC_COLOR,
1091 outputSemanticIndex[i] );
1092 break;
1093 default:
1094 debug_assert(0);
1095 return 0;
1096 }
1097 }
1098 }
1099 else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1100 for (i = 0; i < numInputs; i++) {
1101 t->inputs[i] = ureg_DECL_gs_input(ureg,
1102 i,
1103 inputSemanticName[i],
1104 inputSemanticIndex[i]);
1105 }
1106
1107 for (i = 0; i < numOutputs; i++) {
1108 t->outputs[i] = ureg_DECL_output( ureg,
1109 outputSemanticName[i],
1110 outputSemanticIndex[i] );
1111 }
1112 }
1113 else {
1114 assert(procType == TGSI_PROCESSOR_VERTEX);
1115
1116 for (i = 0; i < numInputs; i++) {
1117 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1118 }
1119
1120 for (i = 0; i < numOutputs; i++) {
1121 t->outputs[i] = ureg_DECL_output( ureg,
1122 outputSemanticName[i],
1123 outputSemanticIndex[i] );
1124 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
1125 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
1126 ureg_MOV(ureg,
1127 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
1128 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
1129 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
1130 }
1131 }
1132 if (passthrough_edgeflags)
1133 emit_edgeflags( t, program );
1134 }
1135
1136 /* Declare address register.
1137 */
1138 if (program->NumAddressRegs > 0) {
1139 debug_assert( program->NumAddressRegs == 1 );
1140 t->address[0] = ureg_DECL_address( ureg );
1141 }
1142
1143 /* Declare misc input registers
1144 */
1145 {
1146 GLbitfield sysInputs = program->SystemValuesRead;
1147 unsigned numSys = 0;
1148 for (i = 0; sysInputs; i++) {
1149 if (sysInputs & (1 << i)) {
1150 unsigned semName = mesa_sysval_to_semantic[i];
1151 t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1152 if (semName == TGSI_SEMANTIC_INSTANCEID ||
1153 semName == TGSI_SEMANTIC_VERTEXID) {
1154 /* From Gallium perspective, these system values are always
1155 * integer, and require native integer support. However, if
1156 * native integer is supported on the vertex stage but not the
1157 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1158 * assumes these system values are floats. To resolve the
1159 * inconsistency, we insert a U2F.
1160 */
1161 struct st_context *st = st_context(ctx);
1162 struct pipe_screen *pscreen = st->pipe->screen;
1163 assert(procType == TGSI_PROCESSOR_VERTEX);
1164 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
1165 (void) pscreen; /* silence non-debug build warnings */
1166 if (!ctx->Const.NativeIntegers) {
1167 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
1168 ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
1169 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
1170 }
1171 }
1172 numSys++;
1173 sysInputs &= ~(1 << i);
1174 }
1175 }
1176 }
1177
1178 if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1179 /* If temps are accessed with indirect addressing, declare temporaries
1180 * in sequential order. Else, we declare them on demand elsewhere.
1181 */
1182 for (i = 0; i < program->NumTemporaries; i++) {
1183 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1184 t->temps[i] = ureg_DECL_temporary( t->ureg );
1185 }
1186 }
1187
1188 /* Emit constants and immediates. Mesa uses a single index space
1189 * for these, so we put all the translated regs in t->constants.
1190 */
1191 if (program->Parameters) {
1192 t->constants = calloc( program->Parameters->NumParameters,
1193 sizeof t->constants[0] );
1194 if (t->constants == NULL) {
1195 ret = PIPE_ERROR_OUT_OF_MEMORY;
1196 goto out;
1197 }
1198
1199 for (i = 0; i < program->Parameters->NumParameters; i++) {
1200 switch (program->Parameters->Parameters[i].Type) {
1201 case PROGRAM_STATE_VAR:
1202 case PROGRAM_UNIFORM:
1203 t->constants[i] = ureg_DECL_constant( ureg, i );
1204 break;
1205
1206 /* Emit immediates only when there's no indirect addressing of
1207 * the const buffer.
1208 * FIXME: Be smarter and recognize param arrays:
1209 * indirect addressing is only valid within the referenced
1210 * array.
1211 */
1212 case PROGRAM_CONSTANT:
1213 if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1214 t->constants[i] = ureg_DECL_constant( ureg, i );
1215 else
1216 t->constants[i] =
1217 ureg_DECL_immediate( ureg,
1218 (const float*) program->Parameters->ParameterValues[i],
1219 4 );
1220 break;
1221 default:
1222 break;
1223 }
1224 }
1225 }
1226
1227 /* texture samplers */
1228 for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1229 if (program->SamplersUsed & (1 << i)) {
1230 t->samplers[i] = ureg_DECL_sampler( ureg, i );
1231 }
1232 }
1233
1234 /* Emit each instruction in turn:
1235 */
1236 for (i = 0; i < program->NumInstructions; i++) {
1237 set_insn_start( t, ureg_get_instruction_number( ureg ));
1238 compile_instruction( ctx, t, &program->Instructions[i], clamp_color );
1239 }
1240
1241 /* Fix up all emitted labels:
1242 */
1243 for (i = 0; i < t->labels_count; i++) {
1244 ureg_fixup_label( ureg,
1245 t->labels[i].token,
1246 t->insn[t->labels[i].branch_target] );
1247 }
1248
1249 out:
1250 free(t->insn);
1251 free(t->labels);
1252 free(t->constants);
1253
1254 if (t->error) {
1255 debug_printf("%s: translate error flag set\n", __FUNCTION__);
1256 }
1257
1258 return ret;
1259 }
1260
1261
1262 /**
1263 * Tokens cannot be free with free otherwise the builtin gallium
1264 * malloc debugging will get confused.
1265 */
1266 void
1267 st_free_tokens(const struct tgsi_token *tokens)
1268 {
1269 ureg_free_tokens(tokens);
1270 }