projects / mesa.git / blob
? search:


6fe8f851757a34f12095bf8099a912bdc90fed5b
[mesa.git] / src / mesa / state_tracker / st_mesa_to_tgsi.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * \author
30 * Michal Krol,
31 * Keith Whitwell
32 */
33
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "tgsi/tgsi_from_mesa.h"
41 #include "st_mesa_to_tgsi.h"
42 #include "st_context.h"
43 #include "program/prog_instruction.h"
44 #include "program/prog_parameter.h"
45 #include "util/u_debug.h"
46 #include "util/u_math.h"
47 #include "util/u_memory.h"
48 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
49
50
51 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
52 (1 << PROGRAM_CONSTANT) | \
53 (1 << PROGRAM_UNIFORM))
54
55 /**
56 * Intermediate state used during shader translation.
57 */
58 struct st_translate {
59 struct ureg_program *ureg;
60
61 struct ureg_dst temps[MAX_PROGRAM_TEMPS];
62 struct ureg_src *constants;
63 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
64 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
65 struct ureg_dst address[1];
66 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
67 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
68
69 const ubyte *inputMapping;
70 const ubyte *outputMapping;
71
72 unsigned procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
73 };
74
75
76 /**
77 * Map a Mesa dst register to a TGSI ureg_dst register.
78 */
79 static struct ureg_dst
80 dst_register(struct st_translate *t, gl_register_file file, GLuint index)
81 {
82 switch(file) {
83 case PROGRAM_UNDEFINED:
84 return ureg_dst_undef();
85
86 case PROGRAM_TEMPORARY:
87 if (ureg_dst_is_undef(t->temps[index]))
88 t->temps[index] = ureg_DECL_temporary(t->ureg);
89
90 return t->temps[index];
91
92 case PROGRAM_OUTPUT:
93 if (t->procType == PIPE_SHADER_VERTEX)
94 assert(index < VARYING_SLOT_MAX);
95 else if (t->procType == PIPE_SHADER_FRAGMENT)
96 assert(index < FRAG_RESULT_MAX);
97 else
98 assert(index < VARYING_SLOT_MAX);
99
100 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
101
102 return t->outputs[t->outputMapping[index]];
103
104 case PROGRAM_ADDRESS:
105 return t->address[index];
106
107 default:
108 debug_assert(0);
109 return ureg_dst_undef();
110 }
111 }
112
113
114 /**
115 * Map a Mesa src register to a TGSI ureg_src register.
116 */
117 static struct ureg_src
118 src_register(struct st_translate *t,
119 gl_register_file file,
120 GLint index)
121 {
122 switch(file) {
123 case PROGRAM_UNDEFINED:
124 return ureg_src_undef();
125
126 case PROGRAM_TEMPORARY:
127 assert(index >= 0);
128 assert(index < ARRAY_SIZE(t->temps));
129 if (ureg_dst_is_undef(t->temps[index]))
130 t->temps[index] = ureg_DECL_temporary(t->ureg);
131 return ureg_src(t->temps[index]);
132
133 case PROGRAM_UNIFORM:
134 assert(index >= 0);
135 return t->constants[index];
136 case PROGRAM_STATE_VAR:
137 case PROGRAM_CONSTANT: /* ie, immediate */
138 if (index < 0)
139 return ureg_DECL_constant(t->ureg, 0);
140 else
141 return t->constants[index];
142
143 case PROGRAM_INPUT:
144 if (t->inputMapping[index] < ARRAY_SIZE(t->inputs))
145 return t->inputs[t->inputMapping[index]];
146 else {
147 assert(t->procType == PIPE_SHADER_VERTEX);
148 return ureg_DECL_constant(t->ureg, 0);
149 }
150
151 case PROGRAM_OUTPUT:
152 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
153 return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
154
155 case PROGRAM_ADDRESS:
156 return ureg_src(t->address[index]);
157
158 case PROGRAM_SYSTEM_VALUE:
159 assert(index < ARRAY_SIZE(t->systemValues));
160 return t->systemValues[index];
161
162 default:
163 debug_assert(0);
164 return ureg_src_undef();
165 }
166 }
167
168
169 /**
170 * Map mesa texture target to TGSI texture target.
171 */
172 enum tgsi_texture_type
173 st_translate_texture_target(gl_texture_index textarget, GLboolean shadow)
174 {
175 if (shadow) {
176 switch (textarget) {
177 case TEXTURE_1D_INDEX:
178 return TGSI_TEXTURE_SHADOW1D;
179 case TEXTURE_2D_INDEX:
180 return TGSI_TEXTURE_SHADOW2D;
181 case TEXTURE_RECT_INDEX:
182 return TGSI_TEXTURE_SHADOWRECT;
183 case TEXTURE_1D_ARRAY_INDEX:
184 return TGSI_TEXTURE_SHADOW1D_ARRAY;
185 case TEXTURE_2D_ARRAY_INDEX:
186 return TGSI_TEXTURE_SHADOW2D_ARRAY;
187 case TEXTURE_CUBE_INDEX:
188 return TGSI_TEXTURE_SHADOWCUBE;
189 case TEXTURE_CUBE_ARRAY_INDEX:
190 return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
191 default:
192 break;
193 }
194 }
195
196 switch (textarget) {
197 case TEXTURE_2D_MULTISAMPLE_INDEX:
198 return TGSI_TEXTURE_2D_MSAA;
199 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX:
200 return TGSI_TEXTURE_2D_ARRAY_MSAA;
201 case TEXTURE_BUFFER_INDEX:
202 return TGSI_TEXTURE_BUFFER;
203 case TEXTURE_1D_INDEX:
204 return TGSI_TEXTURE_1D;
205 case TEXTURE_2D_INDEX:
206 return TGSI_TEXTURE_2D;
207 case TEXTURE_3D_INDEX:
208 return TGSI_TEXTURE_3D;
209 case TEXTURE_CUBE_INDEX:
210 return TGSI_TEXTURE_CUBE;
211 case TEXTURE_CUBE_ARRAY_INDEX:
212 return TGSI_TEXTURE_CUBE_ARRAY;
213 case TEXTURE_RECT_INDEX:
214 return TGSI_TEXTURE_RECT;
215 case TEXTURE_1D_ARRAY_INDEX:
216 return TGSI_TEXTURE_1D_ARRAY;
217 case TEXTURE_2D_ARRAY_INDEX:
218 return TGSI_TEXTURE_2D_ARRAY;
219 case TEXTURE_EXTERNAL_INDEX:
220 return TGSI_TEXTURE_2D;
221 default:
222 debug_assert(!"unexpected texture target index");
223 return TGSI_TEXTURE_1D;
224 }
225 }
226
227
228 /**
229 * Map GLSL base type to TGSI return type.
230 */
231 enum tgsi_return_type
232 st_translate_texture_type(enum glsl_base_type type)
233 {
234 switch (type) {
235 case GLSL_TYPE_INT:
236 return TGSI_RETURN_TYPE_SINT;
237 case GLSL_TYPE_UINT:
238 return TGSI_RETURN_TYPE_UINT;
239 case GLSL_TYPE_FLOAT:
240 return TGSI_RETURN_TYPE_FLOAT;
241 default:
242 assert(!"unexpected texture type");
243 return TGSI_RETURN_TYPE_UNKNOWN;
244 }
245 }
246
247
248 /**
249 * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
250 */
251 static unsigned
252 translate_texture_index(GLbitfield texBit, bool shadow)
253 {
254 int index = ffs(texBit);
255 assert(index > 0);
256 assert(index - 1 < NUM_TEXTURE_TARGETS);
257 return st_translate_texture_target(index - 1, shadow);
258 }
259
260
261 /**
262 * Create a TGSI ureg_dst register from a Mesa dest register.
263 */
264 static struct ureg_dst
265 translate_dst(struct st_translate *t,
266 const struct prog_dst_register *DstReg,
267 boolean saturate)
268 {
269 struct ureg_dst dst = dst_register(t, DstReg->File, DstReg->Index);
270
271 dst = ureg_writemask(dst, DstReg->WriteMask);
272
273 if (saturate)
274 dst = ureg_saturate(dst);
275
276 if (DstReg->RelAddr)
277 dst = ureg_dst_indirect(dst, ureg_src(t->address[0]));
278
279 return dst;
280 }
281
282
283 /**
284 * Create a TGSI ureg_src register from a Mesa src register.
285 */
286 static struct ureg_src
287 translate_src(struct st_translate *t,
288 const struct prog_src_register *SrcReg)
289 {
290 struct ureg_src src = src_register(t, SrcReg->File, SrcReg->Index);
291
292 src = ureg_swizzle(src,
293 GET_SWZ(SrcReg->Swizzle, 0) & 0x3,
294 GET_SWZ(SrcReg->Swizzle, 1) & 0x3,
295 GET_SWZ(SrcReg->Swizzle, 2) & 0x3,
296 GET_SWZ(SrcReg->Swizzle, 3) & 0x3);
297
298 if (SrcReg->Negate == NEGATE_XYZW)
299 src = ureg_negate(src);
300
301 if (SrcReg->RelAddr) {
302 src = ureg_src_indirect(src, ureg_src(t->address[0]));
303 if (SrcReg->File != PROGRAM_INPUT &&
304 SrcReg->File != PROGRAM_OUTPUT) {
305 /* If SrcReg->Index was negative, it was set to zero in
306 * src_register(). Reassign it now. But don't do this
307 * for input/output regs since they get remapped while
308 * const buffers don't.
309 */
310 src.Index = SrcReg->Index;
311 }
312 }
313
314 return src;
315 }
316
317
318 static struct ureg_src
319 swizzle_4v(struct ureg_src src, const unsigned *swz)
320 {
321 return ureg_swizzle(src, swz[0], swz[1], swz[2], swz[3]);
322 }
323
324
325 /**
326 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
327 *
328 * SWZ dst, src.x-y10
329 *
330 * becomes:
331 *
332 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
333 */
334 static void
335 emit_swz(struct st_translate *t,
336 struct ureg_dst dst,
337 const struct prog_src_register *SrcReg)
338 {
339 struct ureg_program *ureg = t->ureg;
340 struct ureg_src src = src_register(t, SrcReg->File, SrcReg->Index);
341
342 unsigned negate_mask = SrcReg->Negate;
343
344 unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
345 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
346 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
347 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
348
349 unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
350 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
351 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
352 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
353
354 unsigned negative_one_mask = one_mask & negate_mask;
355 unsigned positive_one_mask = one_mask & ~negate_mask;
356
357 struct ureg_src imm;
358 unsigned i;
359 unsigned mul_swizzle[4] = {0,0,0,0};
360 unsigned add_swizzle[4] = {0,0,0,0};
361 unsigned src_swizzle[4] = {0,0,0,0};
362 boolean need_add = FALSE;
363 boolean need_mul = FALSE;
364
365 if (dst.WriteMask == 0)
366 return;
367
368 /* Is this just a MOV?
369 */
370 if (zero_mask == 0 &&
371 one_mask == 0 &&
372 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW)) {
373 ureg_MOV(ureg, dst, translate_src(t, SrcReg));
374 return;
375 }
376
377 #define IMM_ZERO 0
378 #define IMM_ONE 1
379 #define IMM_NEG_ONE 2
380
381 imm = ureg_imm3f(ureg, 0, 1, -1);
382
383 for (i = 0; i < 4; i++) {
384 unsigned bit = 1 << i;
385
386 if (dst.WriteMask & bit) {
387 if (positive_one_mask & bit) {
388 mul_swizzle[i] = IMM_ZERO;
389 add_swizzle[i] = IMM_ONE;
390 need_add = TRUE;
391 }
392 else if (negative_one_mask & bit) {
393 mul_swizzle[i] = IMM_ZERO;
394 add_swizzle[i] = IMM_NEG_ONE;
395 need_add = TRUE;
396 }
397 else if (zero_mask & bit) {
398 mul_swizzle[i] = IMM_ZERO;
399 add_swizzle[i] = IMM_ZERO;
400 need_add = TRUE;
401 }
402 else {
403 add_swizzle[i] = IMM_ZERO;
404 src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
405 need_mul = TRUE;
406 if (negate_mask & bit) {
407 mul_swizzle[i] = IMM_NEG_ONE;
408 }
409 else {
410 mul_swizzle[i] = IMM_ONE;
411 }
412 }
413 }
414 }
415
416 if (need_mul && need_add) {
417 ureg_MAD(ureg,
418 dst,
419 swizzle_4v(src, src_swizzle),
420 swizzle_4v(imm, mul_swizzle),
421 swizzle_4v(imm, add_swizzle));
422 }
423 else if (need_mul) {
424 ureg_MUL(ureg,
425 dst,
426 swizzle_4v(src, src_swizzle),
427 swizzle_4v(imm, mul_swizzle));
428 }
429 else if (need_add) {
430 ureg_MOV(ureg,
431 dst,
432 swizzle_4v(imm, add_swizzle));
433 }
434 else {
435 debug_assert(0);
436 }
437
438 #undef IMM_ZERO
439 #undef IMM_ONE
440 #undef IMM_NEG_ONE
441 }
442
443
444 static unsigned
445 translate_opcode(unsigned op)
446 {
447 switch(op) {
448 case OPCODE_ARL:
449 return TGSI_OPCODE_ARL;
450 case OPCODE_ADD:
451 return TGSI_OPCODE_ADD;
452 case OPCODE_CMP:
453 return TGSI_OPCODE_CMP;
454 case OPCODE_COS:
455 return TGSI_OPCODE_COS;
456 case OPCODE_DP3:
457 return TGSI_OPCODE_DP3;
458 case OPCODE_DP4:
459 return TGSI_OPCODE_DP4;
460 case OPCODE_DST:
461 return TGSI_OPCODE_DST;
462 case OPCODE_EX2:
463 return TGSI_OPCODE_EX2;
464 case OPCODE_EXP:
465 return TGSI_OPCODE_EXP;
466 case OPCODE_FLR:
467 return TGSI_OPCODE_FLR;
468 case OPCODE_FRC:
469 return TGSI_OPCODE_FRC;
470 case OPCODE_KIL:
471 return TGSI_OPCODE_KILL_IF;
472 case OPCODE_LG2:
473 return TGSI_OPCODE_LG2;
474 case OPCODE_LOG:
475 return TGSI_OPCODE_LOG;
476 case OPCODE_LIT:
477 return TGSI_OPCODE_LIT;
478 case OPCODE_LRP:
479 return TGSI_OPCODE_LRP;
480 case OPCODE_MAD:
481 return TGSI_OPCODE_MAD;
482 case OPCODE_MAX:
483 return TGSI_OPCODE_MAX;
484 case OPCODE_MIN:
485 return TGSI_OPCODE_MIN;
486 case OPCODE_MOV:
487 return TGSI_OPCODE_MOV;
488 case OPCODE_MUL:
489 return TGSI_OPCODE_MUL;
490 case OPCODE_POW:
491 return TGSI_OPCODE_POW;
492 case OPCODE_RCP:
493 return TGSI_OPCODE_RCP;
494 case OPCODE_SGE:
495 return TGSI_OPCODE_SGE;
496 case OPCODE_SIN:
497 return TGSI_OPCODE_SIN;
498 case OPCODE_SLT:
499 return TGSI_OPCODE_SLT;
500 case OPCODE_TEX:
501 return TGSI_OPCODE_TEX;
502 case OPCODE_TXB:
503 return TGSI_OPCODE_TXB;
504 case OPCODE_TXP:
505 return TGSI_OPCODE_TXP;
506 case OPCODE_END:
507 return TGSI_OPCODE_END;
508 default:
509 debug_assert(0);
510 return TGSI_OPCODE_NOP;
511 }
512 }
513
514
515 static void
516 compile_instruction(struct gl_context *ctx,
517 struct st_translate *t,
518 const struct prog_instruction *inst)
519 {
520 struct ureg_program *ureg = t->ureg;
521 GLuint i;
522 struct ureg_dst dst[1] = { { 0 } };
523 struct ureg_src src[4];
524 unsigned num_dst;
525 unsigned num_src;
526
527 num_dst = _mesa_num_inst_dst_regs(inst->Opcode);
528 num_src = _mesa_num_inst_src_regs(inst->Opcode);
529
530 if (num_dst)
531 dst[0] = translate_dst(t, &inst->DstReg, inst->Saturate);
532
533 for (i = 0; i < num_src; i++)
534 src[i] = translate_src(t, &inst->SrcReg[i]);
535
536 switch(inst->Opcode) {
537 case OPCODE_SWZ:
538 emit_swz(t, dst[0], &inst->SrcReg[0]);
539 return;
540
541 case OPCODE_TEX:
542 case OPCODE_TXB:
543 case OPCODE_TXP:
544 src[num_src++] = t->samplers[inst->TexSrcUnit];
545 ureg_tex_insn(ureg,
546 translate_opcode(inst->Opcode),
547 dst, num_dst,
548 st_translate_texture_target(inst->TexSrcTarget,
549 inst->TexShadow),
550 TGSI_RETURN_TYPE_FLOAT,
551 NULL, 0,
552 src, num_src);
553 return;
554
555 case OPCODE_SCS:
556 ureg_COS(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_X),
557 ureg_scalar(src[0], TGSI_SWIZZLE_X));
558 ureg_SIN(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_Y),
559 ureg_scalar(src[0], TGSI_SWIZZLE_X));
560 break;
561
562 case OPCODE_XPD: {
563 struct ureg_dst tmp = ureg_DECL_temporary(ureg);
564
565 ureg_MUL(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_XYZ),
566 ureg_swizzle(src[0], TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z,
567 TGSI_SWIZZLE_X, 0),
568 ureg_swizzle(src[1], TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X,
569 TGSI_SWIZZLE_Y, 0));
570 ureg_MAD(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ),
571 ureg_swizzle(src[0], TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X,
572 TGSI_SWIZZLE_Y, 0),
573 ureg_negate(ureg_swizzle(src[1], TGSI_SWIZZLE_Y,
574 TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X, 0)),
575 ureg_src(tmp));
576 break;
577 }
578
579 case OPCODE_RSQ:
580 ureg_RSQ(ureg, dst[0], ureg_abs(src[0]));
581 break;
582
583 case OPCODE_ABS:
584 ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
585 break;
586
587 case OPCODE_SUB:
588 ureg_ADD(ureg, dst[0], src[0], ureg_negate(src[1]));
589 break;
590
591 case OPCODE_DPH: {
592 struct ureg_dst temp = ureg_DECL_temporary(ureg);
593
594 /* DPH = DP4(src0, src1) where src0.w = 1. */
595 ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_XYZ), src[0]);
596 ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_W),
597 ureg_imm1f(ureg, 1));
598 ureg_DP4(ureg, dst[0], ureg_src(temp), src[1]);
599 break;
600 }
601
602 default:
603 ureg_insn(ureg,
604 translate_opcode(inst->Opcode),
605 dst, num_dst,
606 src, num_src, 0);
607 break;
608 }
609 }
610
611
612 /**
613 * Emit the TGSI instructions for inverting and adjusting WPOS.
614 * This code is unavoidable because it also depends on whether
615 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
616 */
617 static void
618 emit_wpos_adjustment(struct gl_context *ctx,
619 struct st_translate *t,
620 const struct gl_program *program,
621 boolean invert,
622 GLfloat adjX, GLfloat adjY[2])
623 {
624 struct ureg_program *ureg = t->ureg;
625
626 /* Fragment program uses fragment position input.
627 * Need to replace instances of INPUT[WPOS] with temp T
628 * where T = INPUT[WPOS] by y is inverted.
629 */
630 static const gl_state_index16 wposTransformState[STATE_LENGTH]
631 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
632
633 /* XXX: note we are modifying the incoming shader here! Need to
634 * do this before emitting the constant decls below, or this
635 * will be missed:
636 */
637 unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
638 wposTransformState);
639
640 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wposTransConst);
641 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
642 struct ureg_src *wpos =
643 ctx->Const.GLSLFragCoordIsSysVal ?
644 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
645 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
646 struct ureg_src wpos_input = *wpos;
647
648 /* First, apply the coordinate shift: */
649 if (adjX || adjY[0] || adjY[1]) {
650 if (adjY[0] != adjY[1]) {
651 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
652 * depending on whether inversion is actually going to be applied
653 * or not, which is determined by testing against the inversion
654 * state variable used below, which will be either +1 or -1.
655 */
656 struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
657
658 ureg_CMP(ureg, adj_temp,
659 ureg_scalar(wpostrans, invert ? 2 : 0),
660 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
661 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
662 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
663 } else {
664 ureg_ADD(ureg, wpos_temp, wpos_input,
665 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
666 }
667 wpos_input = ureg_src(wpos_temp);
668 } else {
669 /* MOV wpos_temp, input[wpos]
670 */
671 ureg_MOV(ureg, wpos_temp, wpos_input);
672 }
673
674 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
675 * inversion/identity, or the other way around if we're drawing to an FBO.
676 */
677 if (invert) {
678 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
679 */
680 ureg_MAD(ureg,
681 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
682 wpos_input,
683 ureg_scalar(wpostrans, 0),
684 ureg_scalar(wpostrans, 1));
685 } else {
686 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
687 */
688 ureg_MAD(ureg,
689 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
690 wpos_input,
691 ureg_scalar(wpostrans, 2),
692 ureg_scalar(wpostrans, 3));
693 }
694
695 /* Use wpos_temp as position input from here on:
696 */
697 *wpos = ureg_src(wpos_temp);
698 }
699
700
701 /**
702 * Emit fragment position/coordinate code.
703 */
704 static void
705 emit_wpos(struct st_context *st,
706 struct st_translate *t,
707 const struct gl_program *program,
708 struct ureg_program *ureg)
709 {
710 struct pipe_screen *pscreen = st->pipe->screen;
711 GLfloat adjX = 0.0f;
712 GLfloat adjY[2] = { 0.0f, 0.0f };
713 boolean invert = FALSE;
714
715 /* Query the pixel center conventions supported by the pipe driver and set
716 * adjX, adjY to help out if it cannot handle the requested one internally.
717 *
718 * The bias of the y-coordinate depends on whether y-inversion takes place
719 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
720 * drawing to an FBO (causes additional inversion), and whether the pipe
721 * driver origin and the requested origin differ (the latter condition is
722 * stored in the 'invert' variable).
723 *
724 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
725 *
726 * center shift only:
727 * i -> h: +0.5
728 * h -> i: -0.5
729 *
730 * inversion only:
731 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
732 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
733 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
734 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
735 *
736 * inversion and center shift:
737 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
738 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
739 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
740 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
741 */
742 if (program->info.fs.origin_upper_left) {
743 /* Fragment shader wants origin in upper-left */
744 if (pscreen->get_param(pscreen,
745 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
746 /* the driver supports upper-left origin */
747 }
748 else if (pscreen->get_param(pscreen,
749 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
750 /* the driver supports lower-left origin, need to invert Y */
751 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
752 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
753 invert = TRUE;
754 }
755 else
756 assert(0);
757 }
758 else {
759 /* Fragment shader wants origin in lower-left */
760 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
761 /* the driver supports lower-left origin */
762 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
763 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
764 else if (pscreen->get_param(pscreen,
765 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
766 /* the driver supports upper-left origin, need to invert Y */
767 invert = TRUE;
768 else
769 assert(0);
770 }
771
772 if (program->info.fs.pixel_center_integer) {
773 /* Fragment shader wants pixel center integer */
774 if (pscreen->get_param(pscreen,
775 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
776 /* the driver supports pixel center integer */
777 adjY[1] = 1.0f;
778 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
779 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
780 }
781 else if (pscreen->get_param(pscreen,
782 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
783 /* the driver supports pixel center half integer, need to bias X,Y */
784 adjX = -0.5f;
785 adjY[0] = -0.5f;
786 adjY[1] = 0.5f;
787 }
788 else
789 assert(0);
790 }
791 else {
792 /* Fragment shader wants pixel center half integer */
793 if (pscreen->get_param(pscreen,
794 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
795 /* the driver supports pixel center half integer */
796 }
797 else if (pscreen->get_param(pscreen,
798 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
799 /* the driver supports pixel center integer, need to bias X,Y */
800 adjX = adjY[0] = adjY[1] = 0.5f;
801 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
802 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
803 }
804 else
805 assert(0);
806 }
807
808 /* we invert after adjustment so that we avoid the MOV to temporary,
809 * and reuse the adjustment ADD instead */
810 emit_wpos_adjustment(st->ctx, t, program, invert, adjX, adjY);
811 }
812
813
814 /**
815 * Translate Mesa program to TGSI format.
816 * \param program the program to translate
817 * \param numInputs number of input registers used
818 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
819 * input indexes
820 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
821 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
822 * each input
823 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
824 * \param numOutputs number of output registers used
825 * \param outputMapping maps Mesa fragment program outputs to TGSI
826 * generic outputs
827 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
828 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
829 * each output
830 *
831 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
832 */
833 enum pipe_error
834 st_translate_mesa_program(struct gl_context *ctx,
835 uint procType,
836 struct ureg_program *ureg,
837 const struct gl_program *program,
838 GLuint numInputs,
839 const ubyte inputMapping[],
840 const ubyte inputSemanticName[],
841 const ubyte inputSemanticIndex[],
842 const ubyte interpMode[],
843 GLuint numOutputs,
844 const ubyte outputMapping[],
845 const ubyte outputSemanticName[],
846 const ubyte outputSemanticIndex[])
847 {
848 struct st_translate translate, *t;
849 unsigned i;
850 enum pipe_error ret = PIPE_OK;
851
852 assert(numInputs <= ARRAY_SIZE(t->inputs));
853 assert(numOutputs <= ARRAY_SIZE(t->outputs));
854
855 t = &translate;
856 memset(t, 0, sizeof *t);
857
858 t->procType = procType;
859 t->inputMapping = inputMapping;
860 t->outputMapping = outputMapping;
861 t->ureg = ureg;
862
863 /*_mesa_print_program(program);*/
864
865 /*
866 * Declare input attributes.
867 */
868 if (procType == PIPE_SHADER_FRAGMENT) {
869 for (i = 0; i < numInputs; i++) {
870 t->inputs[i] = ureg_DECL_fs_input(ureg,
871 inputSemanticName[i],
872 inputSemanticIndex[i],
873 interpMode[i]);
874 }
875
876 if (program->info.inputs_read & VARYING_BIT_POS) {
877 /* Must do this after setting up t->inputs, and before
878 * emitting constant references, below:
879 */
880 emit_wpos(st_context(ctx), t, program, ureg);
881 }
882
883 /*
884 * Declare output attributes.
885 */
886 for (i = 0; i < numOutputs; i++) {
887 switch (outputSemanticName[i]) {
888 case TGSI_SEMANTIC_POSITION:
889 t->outputs[i] = ureg_DECL_output(ureg,
890 TGSI_SEMANTIC_POSITION, /* Z / Depth */
891 outputSemanticIndex[i]);
892
893 t->outputs[i] = ureg_writemask(t->outputs[i],
894 TGSI_WRITEMASK_Z);
895 break;
896 case TGSI_SEMANTIC_STENCIL:
897 t->outputs[i] = ureg_DECL_output(ureg,
898 TGSI_SEMANTIC_STENCIL, /* Stencil */
899 outputSemanticIndex[i]);
900 t->outputs[i] = ureg_writemask(t->outputs[i],
901 TGSI_WRITEMASK_Y);
902 break;
903 case TGSI_SEMANTIC_COLOR:
904 t->outputs[i] = ureg_DECL_output(ureg,
905 TGSI_SEMANTIC_COLOR,
906 outputSemanticIndex[i]);
907 break;
908 default:
909 debug_assert(0);
910 return 0;
911 }
912 }
913 }
914 else if (procType == PIPE_SHADER_GEOMETRY) {
915 for (i = 0; i < numInputs; i++) {
916 t->inputs[i] = ureg_DECL_input(ureg,
917 inputSemanticName[i],
918 inputSemanticIndex[i], 0, 1);
919 }
920
921 for (i = 0; i < numOutputs; i++) {
922 t->outputs[i] = ureg_DECL_output(ureg,
923 outputSemanticName[i],
924 outputSemanticIndex[i]);
925 }
926 }
927 else {
928 assert(procType == PIPE_SHADER_VERTEX);
929
930 for (i = 0; i < numInputs; i++) {
931 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
932 }
933
934 for (i = 0; i < numOutputs; i++) {
935 t->outputs[i] = ureg_DECL_output(ureg,
936 outputSemanticName[i],
937 outputSemanticIndex[i]);
938 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
939 /* force register to contain a fog coordinate in the
940 * form (F, 0, 0, 1).
941 */
942 ureg_MOV(ureg,
943 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
944 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
945 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
946 }
947 }
948 }
949
950 /* Declare address register.
951 */
952 if (program->arb.NumAddressRegs > 0) {
953 debug_assert(program->arb.NumAddressRegs == 1);
954 t->address[0] = ureg_DECL_address(ureg);
955 }
956
957 /* Declare misc input registers
958 */
959 GLbitfield64 sysInputs = program->info.system_values_read;
960 for (i = 0; sysInputs; i++) {
961 if (sysInputs & (1ull << i)) {
962 unsigned semName = tgsi_get_sysval_semantic(i);
963
964 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
965
966 if (semName == TGSI_SEMANTIC_INSTANCEID ||
967 semName == TGSI_SEMANTIC_VERTEXID) {
968 /* From Gallium perspective, these system values are always
969 * integer, and require native integer support. However, if
970 * native integer is supported on the vertex stage but not the
971 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
972 * assumes these system values are floats. To resolve the
973 * inconsistency, we insert a U2F.
974 */
975 struct st_context *st = st_context(ctx);
976 struct pipe_screen *pscreen = st->pipe->screen;
977 assert(procType == PIPE_SHADER_VERTEX);
978 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
979 PIPE_SHADER_CAP_INTEGERS));
980 (void) pscreen; /* silence non-debug build warnings */
981 if (!ctx->Const.NativeIntegers) {
982 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
983 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
984 t->systemValues[i]);
985 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
986 }
987 }
988
989 if (procType == PIPE_SHADER_FRAGMENT &&
990 semName == TGSI_SEMANTIC_POSITION)
991 emit_wpos(st_context(ctx), t, program, ureg);
992
993 sysInputs &= ~(1ull << i);
994 }
995 }
996
997 if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
998 /* If temps are accessed with indirect addressing, declare temporaries
999 * in sequential order. Else, we declare them on demand elsewhere.
1000 */
1001 for (i = 0; i < program->arb.NumTemporaries; i++) {
1002 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1003 t->temps[i] = ureg_DECL_temporary(t->ureg);
1004 }
1005 }
1006
1007 /* Emit constants and immediates. Mesa uses a single index space
1008 * for these, so we put all the translated regs in t->constants.
1009 */
1010 if (program->Parameters) {
1011 t->constants = calloc(program->Parameters->NumParameters,
1012 sizeof t->constants[0]);
1013 if (t->constants == NULL) {
1014 ret = PIPE_ERROR_OUT_OF_MEMORY;
1015 goto out;
1016 }
1017
1018 for (i = 0; i < program->Parameters->NumParameters; i++) {
1019 unsigned pvo = program->Parameters->ParameterValueOffset[i];
1020
1021 switch (program->Parameters->Parameters[i].Type) {
1022 case PROGRAM_STATE_VAR:
1023 case PROGRAM_UNIFORM:
1024 t->constants[i] = ureg_DECL_constant(ureg, i);
1025 break;
1026
1027 /* Emit immediates only when there's no indirect addressing of
1028 * the const buffer.
1029 * FIXME: Be smarter and recognize param arrays:
1030 * indirect addressing is only valid within the referenced
1031 * array.
1032 */
1033 case PROGRAM_CONSTANT:
1034 if (program->arb.IndirectRegisterFiles & PROGRAM_ANY_CONST)
1035 t->constants[i] = ureg_DECL_constant( ureg, i );
1036 else
1037 t->constants[i] =
1038 ureg_DECL_immediate(ureg,
1039 (const float *)
1040 program->Parameters->ParameterValues + pvo,
1041 4);
1042 break;
1043 default:
1044 break;
1045 }
1046 }
1047 }
1048
1049 /* texture samplers */
1050 for (i = 0;
1051 i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1052 if (program->SamplersUsed & (1u << i)) {
1053 unsigned target =
1054 translate_texture_index(program->TexturesUsed[i],
1055 !!(program->ShadowSamplers & (1 << i)));
1056 t->samplers[i] = ureg_DECL_sampler(ureg, i);
1057 ureg_DECL_sampler_view(ureg, i, target,
1058 TGSI_RETURN_TYPE_FLOAT,
1059 TGSI_RETURN_TYPE_FLOAT,
1060 TGSI_RETURN_TYPE_FLOAT,
1061 TGSI_RETURN_TYPE_FLOAT);
1062
1063 }
1064 }
1065
1066 /* Emit each instruction in turn:
1067 */
1068 for (i = 0; i < program->arb.NumInstructions; i++)
1069 compile_instruction(ctx, t, &program->arb.Instructions[i]);
1070
1071 out:
1072 free(t->constants);
1073 return ret;
1074 }