src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_shader_tokens.h"
  36 #include "pipe/p_state.h"
  37 #include "pipe/p_context.h"
  38 #include "tgsi/tgsi_ureg.h"
  39 #include "st_mesa_to_tgsi.h"
  40 #include "st_context.h"
  41 #include "program/prog_instruction.h"
  42 #include "program/prog_parameter.h"
  43 #include "util/u_debug.h"
  44 #include "util/u_math.h"
  45 #include "util/u_memory.h"
  46
  47 struct label {
  48    unsigned branch_target;
  49    unsigned token;
  50 };
  51
  52
  53 /**
  54  * Intermediate state used during shader translation.
  55  */
  56 struct st_translate {
  57    struct ureg_program *ureg;
  58
  59    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  60    struct ureg_src *constants;
  61    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  62    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  63    struct ureg_dst address[1];
  64    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  65
  66    /* Extra info for handling point size clamping in vertex shader */
  67    struct ureg_dst pointSizeResult; /**< Actual point size output register */
  68    struct ureg_src pointSizeConst;  /**< Point size range constant register */
  69    GLint pointSizeOutIndex;         /**< Temp point size output register */
  70    GLboolean prevInstWrotePointSize;
  71
  72    const GLuint *inputMapping;
  73    const GLuint *outputMapping;
  74
  75    /* For every instruction that contains a label (eg CALL), keep
  76     * details so that we can go back afterwards and emit the correct
  77     * tgsi instruction number for each label.
  78     */
  79    struct label *labels;
  80    unsigned labels_size;
  81    unsigned labels_count;
  82
  83    /* Keep a record of the tgsi instruction number that each mesa
  84     * instruction starts at, will be used to fix up labels after
  85     * translation.
  86     */
  87    unsigned *insn;
  88    unsigned insn_size;
  89    unsigned insn_count;
  90
  91    unsigned procType;  /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
  92
  93    boolean error;
  94 };
  95
  96
  97 /**
  98  * Make note of a branch to a label in the TGSI code.
  99  * After we've emitted all instructions, we'll go over the list
 100  * of labels built here and patch the TGSI code with the actual
 101  * location of each label.
 102  */
 103 static unsigned *get_label( struct st_translate *t,
 104                             unsigned branch_target )
 105 {
 106    unsigned i;
 107
 108    if (t->labels_count + 1 >= t->labels_size) {
 109       unsigned old_size = t->labels_size;
 110       t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
 111       t->labels = REALLOC( t->labels,
 112                            old_size * sizeof t->labels[0],
 113                            t->labels_size * sizeof t->labels[0] );
 114       if (t->labels == NULL) {
 115          static unsigned dummy;
 116          t->error = TRUE;
 117          return &dummy;
 118       }
 119    }
 120
 121    i = t->labels_count++;
 122    t->labels[i].branch_target = branch_target;
 123    return &t->labels[i].token;
 124 }
 125
 126
 127 /**
 128  * Called prior to emitting the TGSI code for each Mesa instruction.
 129  * Allocate additional space for instructions if needed.
 130  * Update the insn[] array so the next Mesa instruction points to
 131  * the next TGSI instruction.
 132  */
 133 static void set_insn_start( struct st_translate *t,
 134                             unsigned start )
 135 {
 136    if (t->insn_count + 1 >= t->insn_size) {
 137       unsigned old_size = t->insn_size;
 138       t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
 139       t->insn = REALLOC( t->insn,
 140                          old_size * sizeof t->insn[0],
 141                          t->insn_size * sizeof t->insn[0] );
 142       if (t->insn == NULL) {
 143          t->error = TRUE;
 144          return;
 145       }
 146    }
 147
 148    t->insn[t->insn_count++] = start;
 149 }
 150
 151
 152 /**
 153  * Map a Mesa dst register to a TGSI ureg_dst register.
 154  */
 155 static struct ureg_dst
 156 dst_register( struct st_translate *t,
 157               gl_register_file file,
 158               GLuint index )
 159 {
 160    switch( file ) {
 161    case PROGRAM_UNDEFINED:
 162       return ureg_dst_undef();
 163
 164    case PROGRAM_TEMPORARY:
 165       if (ureg_dst_is_undef(t->temps[index]))
 166          t->temps[index] = ureg_DECL_temporary( t->ureg );
 167
 168       return t->temps[index];
 169
 170    case PROGRAM_OUTPUT:
 171       if (t->procType == TGSI_PROCESSOR_VERTEX && index == VERT_RESULT_PSIZ)
 172          t->prevInstWrotePointSize = GL_TRUE;
 173
 174       if (t->procType == TGSI_PROCESSOR_VERTEX)
 175          assert(index < VERT_RESULT_MAX);
 176       else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
 177          assert(index < FRAG_RESULT_MAX);
 178       else
 179          assert(0 && "geom shaders not handled in dst_register() yet");
 180
 181       assert(t->outputMapping[index] < Elements(t->outputs));
 182
 183       return t->outputs[t->outputMapping[index]];
 184
 185    case PROGRAM_ADDRESS:
 186       return t->address[index];
 187
 188    default:
 189       debug_assert( 0 );
 190       return ureg_dst_undef();
 191    }
 192 }
 193
 194
 195 /**
 196  * Map a Mesa src register to a TGSI ureg_src register.
 197  */
 198 static struct ureg_src
 199 src_register( struct st_translate *t,
 200               gl_register_file file,
 201               GLint index )
 202 {
 203    switch( file ) {
 204    case PROGRAM_UNDEFINED:
 205       return ureg_src_undef();
 206
 207    case PROGRAM_TEMPORARY:
 208       ASSERT(index >= 0);
 209       if (ureg_dst_is_undef(t->temps[index]))
 210          t->temps[index] = ureg_DECL_temporary( t->ureg );
 211       assert(index < Elements(t->temps));
 212       return ureg_src(t->temps[index]);
 213
 214    case PROGRAM_NAMED_PARAM:
 215    case PROGRAM_ENV_PARAM:
 216    case PROGRAM_LOCAL_PARAM:
 217    case PROGRAM_UNIFORM:
 218       ASSERT(index >= 0);
 219       return t->constants[index];
 220    case PROGRAM_STATE_VAR:
 221    case PROGRAM_CONSTANT:       /* ie, immediate */
 222       if (index < 0)
 223          return ureg_DECL_constant( t->ureg, 0 );
 224       else
 225          return t->constants[index];
 226
 227    case PROGRAM_INPUT:
 228       assert(t->inputMapping[index] < Elements(t->inputs));
 229       return t->inputs[t->inputMapping[index]];
 230
 231    case PROGRAM_OUTPUT:
 232       assert(t->outputMapping[index] < Elements(t->outputs));
 233       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 234
 235    case PROGRAM_ADDRESS:
 236       return ureg_src(t->address[index]);
 237
 238    default:
 239       debug_assert( 0 );
 240       return ureg_src_undef();
 241    }
 242 }
 243
 244
 245 /**
 246  * Map mesa texture target to TGSI texture target.
 247  */
 248 static unsigned
 249 translate_texture_target( GLuint textarget,
 250                           GLboolean shadow )
 251 {
 252    if (shadow) {
 253       switch( textarget ) {
 254       case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_SHADOW1D;
 255       case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_SHADOW2D;
 256       case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
 257       default: break;
 258       }
 259    }
 260
 261    switch( textarget ) {
 262    case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_1D;
 263    case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_2D;
 264    case TEXTURE_3D_INDEX:   return TGSI_TEXTURE_3D;
 265    case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
 266    case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
 267    default:
 268       debug_assert( 0 );
 269       return TGSI_TEXTURE_1D;
 270    }
 271 }
 272
 273
 274 /**
 275  * Create a TGSI ureg_dst register from a Mesa dest register.
 276  */
 277 static struct ureg_dst
 278 translate_dst( struct st_translate *t,
 279                const struct prog_dst_register *DstReg,
 280                boolean saturate )
 281 {
 282    struct ureg_dst dst = dst_register( t,
 283                                        DstReg->File,
 284                                        DstReg->Index );
 285
 286    dst = ureg_writemask( dst,
 287                          DstReg->WriteMask );
 288
 289    if (saturate)
 290       dst = ureg_saturate( dst );
 291
 292    if (DstReg->RelAddr)
 293       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 294
 295    return dst;
 296 }
 297
 298
 299 /**
 300  * Create a TGSI ureg_src register from a Mesa src register.
 301  */
 302 static struct ureg_src
 303 translate_src( struct st_translate *t,
 304                const struct prog_src_register *SrcReg )
 305 {
 306    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 307
 308    src = ureg_swizzle( src,
 309                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 310                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 311                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 312                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 313
 314    if (SrcReg->Negate == NEGATE_XYZW)
 315       src = ureg_negate(src);
 316
 317    if (SrcReg->Abs)
 318       src = ureg_abs(src);
 319
 320    if (SrcReg->RelAddr) {
 321       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 322       if (SrcReg->File != PROGRAM_INPUT &&
 323           SrcReg->File != PROGRAM_OUTPUT) {
 324          /* If SrcReg->Index was negative, it was set to zero in
 325           * src_register().  Reassign it now.  But don't do this
 326           * for input/output regs since they get remapped while
 327           * const buffers don't.
 328           */
 329          src.Index = SrcReg->Index;
 330       }
 331    }
 332
 333    if (SrcReg->HasIndex2D) {
 334       if (SrcReg->RelAddr2D)
 335          src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
 336                                             SrcReg->Index2D);
 337       else
 338          src = ureg_src_dimension( src, SrcReg->Index2D);
 339    }
 340
 341    return src;
 342 }
 343
 344
 345 static struct ureg_src swizzle_4v( struct ureg_src src,
 346                                    const unsigned *swz )
 347 {
 348    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 349 }
 350
 351
 352 /**
 353  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 354  *
 355  *   SWZ dst, src.x-y10
 356  *
 357  * becomes:
 358  *
 359  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 360  */
 361 static void emit_swz( struct st_translate *t,
 362                       struct ureg_dst dst,
 363                       const struct prog_src_register *SrcReg )
 364 {
 365    struct ureg_program *ureg = t->ureg;
 366    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 367
 368    unsigned negate_mask =  SrcReg->Negate;
 369
 370    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 371                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 372                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 373                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 374
 375    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 376                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 377                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 378                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 379
 380    unsigned negative_one_mask = one_mask & negate_mask;
 381    unsigned positive_one_mask = one_mask & ~negate_mask;
 382
 383    struct ureg_src imm;
 384    unsigned i;
 385    unsigned mul_swizzle[4] = {0,0,0,0};
 386    unsigned add_swizzle[4] = {0,0,0,0};
 387    unsigned src_swizzle[4] = {0,0,0,0};
 388    boolean need_add = FALSE;
 389    boolean need_mul = FALSE;
 390
 391    if (dst.WriteMask == 0)
 392       return;
 393
 394    /* Is this just a MOV?
 395     */
 396    if (zero_mask == 0 &&
 397        one_mask == 0 &&
 398        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 399    {
 400       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 401       return;
 402    }
 403
 404 #define IMM_ZERO    0
 405 #define IMM_ONE     1
 406 #define IMM_NEG_ONE 2
 407
 408    imm = ureg_imm3f( ureg, 0, 1, -1 );
 409
 410    for (i = 0; i < 4; i++) {
 411       unsigned bit = 1 << i;
 412
 413       if (dst.WriteMask & bit) {
 414          if (positive_one_mask & bit) {
 415             mul_swizzle[i] = IMM_ZERO;
 416             add_swizzle[i] = IMM_ONE;
 417             need_add = TRUE;
 418          }
 419          else if (negative_one_mask & bit) {
 420             mul_swizzle[i] = IMM_ZERO;
 421             add_swizzle[i] = IMM_NEG_ONE;
 422             need_add = TRUE;
 423          }
 424          else if (zero_mask & bit) {
 425             mul_swizzle[i] = IMM_ZERO;
 426             add_swizzle[i] = IMM_ZERO;
 427             need_add = TRUE;
 428          }
 429          else {
 430             add_swizzle[i] = IMM_ZERO;
 431             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 432             need_mul = TRUE;
 433             if (negate_mask & bit) {
 434                mul_swizzle[i] = IMM_NEG_ONE;
 435             }
 436             else {
 437                mul_swizzle[i] = IMM_ONE;
 438             }
 439          }
 440       }
 441    }
 442
 443    if (need_mul && need_add) {
 444       ureg_MAD( ureg,
 445                 dst,
 446                 swizzle_4v( src, src_swizzle ),
 447                 swizzle_4v( imm, mul_swizzle ),
 448                 swizzle_4v( imm, add_swizzle ) );
 449    }
 450    else if (need_mul) {
 451       ureg_MUL( ureg,
 452                 dst,
 453                 swizzle_4v( src, src_swizzle ),
 454                 swizzle_4v( imm, mul_swizzle ) );
 455    }
 456    else if (need_add) {
 457       ureg_MOV( ureg,
 458                 dst,
 459                 swizzle_4v( imm, add_swizzle ) );
 460    }
 461    else {
 462       debug_assert(0);
 463    }
 464
 465 #undef IMM_ZERO
 466 #undef IMM_ONE
 467 #undef IMM_NEG_ONE
 468 }
 469
 470
 471 /**
 472  * Negate the value of DDY to match GL semantics where (0,0) is the
 473  * lower-left corner of the window.
 474  * Note that the GL_ARB_fragment_coord_conventions extension will
 475  * effect this someday.
 476  */
 477 static void emit_ddy( struct st_translate *t,
 478                       struct ureg_dst dst,
 479                       const struct prog_src_register *SrcReg )
 480 {
 481    struct ureg_program *ureg = t->ureg;
 482    struct ureg_src src = translate_src( t, SrcReg );
 483    src = ureg_negate( src );
 484    ureg_DDY( ureg, dst, src );
 485 }
 486
 487
 488
 489 static unsigned
 490 translate_opcode( unsigned op )
 491 {
 492    switch( op ) {
 493    case OPCODE_ARL:
 494       return TGSI_OPCODE_ARL;
 495    case OPCODE_ABS:
 496       return TGSI_OPCODE_ABS;
 497    case OPCODE_ADD:
 498       return TGSI_OPCODE_ADD;
 499    case OPCODE_BGNLOOP:
 500       return TGSI_OPCODE_BGNLOOP;
 501    case OPCODE_BGNSUB:
 502       return TGSI_OPCODE_BGNSUB;
 503    case OPCODE_BRA:
 504       return TGSI_OPCODE_BRA;
 505    case OPCODE_BRK:
 506       return TGSI_OPCODE_BRK;
 507    case OPCODE_CAL:
 508       return TGSI_OPCODE_CAL;
 509    case OPCODE_CMP:
 510       return TGSI_OPCODE_CMP;
 511    case OPCODE_CONT:
 512       return TGSI_OPCODE_CONT;
 513    case OPCODE_COS:
 514       return TGSI_OPCODE_COS;
 515    case OPCODE_DDX:
 516       return TGSI_OPCODE_DDX;
 517    case OPCODE_DDY:
 518       return TGSI_OPCODE_DDY;
 519    case OPCODE_DP2:
 520       return TGSI_OPCODE_DP2;
 521    case OPCODE_DP2A:
 522       return TGSI_OPCODE_DP2A;
 523    case OPCODE_DP3:
 524       return TGSI_OPCODE_DP3;
 525    case OPCODE_DP4:
 526       return TGSI_OPCODE_DP4;
 527    case OPCODE_DPH:
 528       return TGSI_OPCODE_DPH;
 529    case OPCODE_DST:
 530       return TGSI_OPCODE_DST;
 531    case OPCODE_ELSE:
 532       return TGSI_OPCODE_ELSE;
 533    case OPCODE_EMIT_VERTEX:
 534       return TGSI_OPCODE_EMIT;
 535    case OPCODE_END_PRIMITIVE:
 536       return TGSI_OPCODE_ENDPRIM;
 537    case OPCODE_ENDIF:
 538       return TGSI_OPCODE_ENDIF;
 539    case OPCODE_ENDLOOP:
 540       return TGSI_OPCODE_ENDLOOP;
 541    case OPCODE_ENDSUB:
 542       return TGSI_OPCODE_ENDSUB;
 543    case OPCODE_EX2:
 544       return TGSI_OPCODE_EX2;
 545    case OPCODE_EXP:
 546       return TGSI_OPCODE_EXP;
 547    case OPCODE_FLR:
 548       return TGSI_OPCODE_FLR;
 549    case OPCODE_FRC:
 550       return TGSI_OPCODE_FRC;
 551    case OPCODE_IF:
 552       return TGSI_OPCODE_IF;
 553    case OPCODE_TRUNC:
 554       return TGSI_OPCODE_TRUNC;
 555    case OPCODE_KIL:
 556       return TGSI_OPCODE_KIL;
 557    case OPCODE_KIL_NV:
 558       return TGSI_OPCODE_KILP;
 559    case OPCODE_LG2:
 560       return TGSI_OPCODE_LG2;
 561    case OPCODE_LOG:
 562       return TGSI_OPCODE_LOG;
 563    case OPCODE_LIT:
 564       return TGSI_OPCODE_LIT;
 565    case OPCODE_LRP:
 566       return TGSI_OPCODE_LRP;
 567    case OPCODE_MAD:
 568       return TGSI_OPCODE_MAD;
 569    case OPCODE_MAX:
 570       return TGSI_OPCODE_MAX;
 571    case OPCODE_MIN:
 572       return TGSI_OPCODE_MIN;
 573    case OPCODE_MOV:
 574       return TGSI_OPCODE_MOV;
 575    case OPCODE_MUL:
 576       return TGSI_OPCODE_MUL;
 577    case OPCODE_NOP:
 578       return TGSI_OPCODE_NOP;
 579    case OPCODE_NRM3:
 580       return TGSI_OPCODE_NRM;
 581    case OPCODE_NRM4:
 582       return TGSI_OPCODE_NRM4;
 583    case OPCODE_POW:
 584       return TGSI_OPCODE_POW;
 585    case OPCODE_RCP:
 586       return TGSI_OPCODE_RCP;
 587    case OPCODE_RET:
 588       return TGSI_OPCODE_RET;
 589    case OPCODE_RSQ:
 590       return TGSI_OPCODE_RSQ;
 591    case OPCODE_SCS:
 592       return TGSI_OPCODE_SCS;
 593    case OPCODE_SEQ:
 594       return TGSI_OPCODE_SEQ;
 595    case OPCODE_SGE:
 596       return TGSI_OPCODE_SGE;
 597    case OPCODE_SGT:
 598       return TGSI_OPCODE_SGT;
 599    case OPCODE_SIN:
 600       return TGSI_OPCODE_SIN;
 601    case OPCODE_SLE:
 602       return TGSI_OPCODE_SLE;
 603    case OPCODE_SLT:
 604       return TGSI_OPCODE_SLT;
 605    case OPCODE_SNE:
 606       return TGSI_OPCODE_SNE;
 607    case OPCODE_SSG:
 608       return TGSI_OPCODE_SSG;
 609    case OPCODE_SUB:
 610       return TGSI_OPCODE_SUB;
 611    case OPCODE_TEX:
 612       return TGSI_OPCODE_TEX;
 613    case OPCODE_TXB:
 614       return TGSI_OPCODE_TXB;
 615    case OPCODE_TXD:
 616       return TGSI_OPCODE_TXD;
 617    case OPCODE_TXL:
 618       return TGSI_OPCODE_TXL;
 619    case OPCODE_TXP:
 620       return TGSI_OPCODE_TXP;
 621    case OPCODE_XPD:
 622       return TGSI_OPCODE_XPD;
 623    case OPCODE_END:
 624       return TGSI_OPCODE_END;
 625    default:
 626       debug_assert( 0 );
 627       return TGSI_OPCODE_NOP;
 628    }
 629 }
 630
 631
 632 static void
 633 compile_instruction(
 634    struct st_translate *t,
 635    const struct prog_instruction *inst )
 636 {
 637    struct ureg_program *ureg = t->ureg;
 638    GLuint i;
 639    struct ureg_dst dst[1];
 640    struct ureg_src src[4];
 641    unsigned num_dst;
 642    unsigned num_src;
 643
 644    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 645    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 646
 647    if (num_dst)
 648       dst[0] = translate_dst( t,
 649                               &inst->DstReg,
 650                               inst->SaturateMode );
 651
 652    for (i = 0; i < num_src; i++)
 653       src[i] = translate_src( t, &inst->SrcReg[i] );
 654
 655    switch( inst->Opcode ) {
 656    case OPCODE_SWZ:
 657       emit_swz( t, dst[0], &inst->SrcReg[0] );
 658       return;
 659
 660    case OPCODE_BGNLOOP:
 661    case OPCODE_CAL:
 662    case OPCODE_ELSE:
 663    case OPCODE_ENDLOOP:
 664    case OPCODE_IF:
 665       debug_assert(num_dst == 0);
 666       ureg_label_insn( ureg,
 667                        translate_opcode( inst->Opcode ),
 668                        src, num_src,
 669                        get_label( t, inst->BranchTarget ));
 670       return;
 671
 672    case OPCODE_TEX:
 673    case OPCODE_TXB:
 674    case OPCODE_TXD:
 675    case OPCODE_TXL:
 676    case OPCODE_TXP:
 677       src[num_src++] = t->samplers[inst->TexSrcUnit];
 678       ureg_tex_insn( ureg,
 679                      translate_opcode( inst->Opcode ),
 680                      dst, num_dst,
 681                      translate_texture_target( inst->TexSrcTarget,
 682                                                inst->TexShadow ),
 683                      src, num_src );
 684       return;
 685
 686    case OPCODE_SCS:
 687       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
 688       ureg_insn( ureg,
 689                  translate_opcode( inst->Opcode ),
 690                  dst, num_dst,
 691                  src, num_src );
 692       break;
 693
 694    case OPCODE_XPD:
 695       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
 696       ureg_insn( ureg,
 697                  translate_opcode( inst->Opcode ),
 698                  dst, num_dst,
 699                  src, num_src );
 700       break;
 701
 702    case OPCODE_NOISE1:
 703    case OPCODE_NOISE2:
 704    case OPCODE_NOISE3:
 705    case OPCODE_NOISE4:
 706       /* At some point, a motivated person could add a better
 707        * implementation of noise.  Currently not even the nvidia
 708        * binary drivers do anything more than this.  In any case, the
 709        * place to do this is in the GL state tracker, not the poor
 710        * driver.
 711        */
 712       ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
 713       break;
 714
 715    case OPCODE_DDY:
 716       emit_ddy( t, dst[0], &inst->SrcReg[0] );
 717       break;
 718
 719    default:
 720       ureg_insn( ureg,
 721                  translate_opcode( inst->Opcode ),
 722                  dst, num_dst,
 723                  src, num_src );
 724       break;
 725    }
 726 }
 727
 728
 729 /**
 730  * Emit the TGSI instructions to adjust the WPOS pixel center convention
 731  */
 732 static void
 733 emit_adjusted_wpos( struct st_translate *t,
 734                     const struct gl_program *program, GLfloat value)
 735 {
 736    struct ureg_program *ureg = t->ureg;
 737    struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
 738    struct ureg_src wpos_input = t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]];
 739
 740    ureg_ADD(ureg,
 741             ureg_writemask(wpos_temp, TGSI_WRITEMASK_X | TGSI_WRITEMASK_Y),
 742             wpos_input, ureg_imm1f(ureg, value));
 743
 744    t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]] = ureg_src(wpos_temp);
 745 }
 746
 747
 748 /**
 749  * Emit the TGSI instructions for inverting the WPOS y coordinate.
 750  */
 751 static void
 752 emit_inverted_wpos( struct st_translate *t,
 753                     const struct gl_program *program )
 754 {
 755    struct ureg_program *ureg = t->ureg;
 756
 757    /* Fragment program uses fragment position input.
 758     * Need to replace instances of INPUT[WPOS] with temp T
 759     * where T = INPUT[WPOS] by y is inverted.
 760     */
 761    static const gl_state_index winSizeState[STATE_LENGTH]
 762       = { STATE_INTERNAL, STATE_FB_SIZE, 0, 0, 0 };
 763
 764    /* XXX: note we are modifying the incoming shader here!  Need to
 765     * do this before emitting the constant decls below, or this
 766     * will be missed:
 767     */
 768    unsigned winHeightConst = _mesa_add_state_reference(program->Parameters,
 769                                                        winSizeState);
 770
 771    struct ureg_src winsize = ureg_DECL_constant( ureg, winHeightConst );
 772    struct ureg_dst wpos_temp;
 773    struct ureg_src wpos_input = t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]];
 774
 775    /* MOV wpos_temp, input[wpos]
 776     */
 777    if (wpos_input.File == TGSI_FILE_TEMPORARY)
 778       wpos_temp = ureg_dst(wpos_input);
 779    else {
 780       wpos_temp = ureg_DECL_temporary( ureg );
 781       ureg_MOV( ureg, wpos_temp, wpos_input );
 782    }
 783
 784    /* SUB wpos_temp.y, winsize_const, wpos_input
 785     */
 786    ureg_SUB( ureg,
 787              ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 788              winsize,
 789              wpos_input);
 790
 791    /* Use wpos_temp as position input from here on:
 792     */
 793    t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]] = ureg_src(wpos_temp);
 794 }
 795
 796
 797 /**
 798  * Emit fragment position/ooordinate code.
 799  */
 800 static void
 801 emit_wpos(struct st_context *st,
 802           struct st_translate *t,
 803           const struct gl_program *program,
 804           struct ureg_program *ureg)
 805 {
 806    const struct gl_fragment_program *fp =
 807       (const struct gl_fragment_program *) program;
 808    struct pipe_screen *pscreen = st->pipe->screen;
 809    boolean invert = FALSE;
 810
 811    if (fp->OriginUpperLeft) {
 812       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 813       }
 814       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 815          ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 816          invert = TRUE;
 817       }
 818       else
 819          assert(0);
 820    }
 821    else {
 822       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 823          ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 824       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 825          invert = TRUE;
 826       else
 827          assert(0);
 828    }
 829
 830    if (fp->PixelCenterInteger) {
 831       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER))
 832          ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 833       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER))
 834          emit_adjusted_wpos(t, program, invert ? 0.5f : -0.5f);
 835       else
 836          assert(0);
 837    }
 838    else {
 839       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 840       }
 841       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 842          ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 843          emit_adjusted_wpos(t, program, invert ? -0.5f : 0.5f);
 844       }
 845       else
 846          assert(0);
 847    }
 848
 849    /* we invert after adjustment so that we avoid the MOV to temporary,
 850     * and reuse the adjustment ADD instead */
 851    if (invert)
 852       emit_inverted_wpos(t, program);
 853 }
 854
 855
 856 /**
 857  * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
 858  * TGSI uses +1 for front, -1 for back.
 859  * This function converts the TGSI value to the GL value.  Simply clamping/
 860  * saturating the value to [0,1] does the job.
 861  */
 862 static void
 863 emit_face_var( struct st_translate *t,
 864                const struct gl_program *program )
 865 {
 866    struct ureg_program *ureg = t->ureg;
 867    struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
 868    struct ureg_src face_input = t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]];
 869
 870    /* MOV_SAT face_temp, input[face]
 871     */
 872    face_temp = ureg_saturate( face_temp );
 873    ureg_MOV( ureg, face_temp, face_input );
 874
 875    /* Use face_temp as face input from here on:
 876     */
 877    t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]] = ureg_src(face_temp);
 878 }
 879
 880
 881 static void
 882 emit_edgeflags( struct st_translate *t,
 883                  const struct gl_program *program )
 884 {
 885    struct ureg_program *ureg = t->ureg;
 886    struct ureg_dst edge_dst = t->outputs[t->outputMapping[VERT_RESULT_EDGE]];
 887    struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
 888
 889    ureg_MOV( ureg, edge_dst, edge_src );
 890 }
 891
 892
 893 /**
 894  * Translate Mesa program to TGSI format.
 895  * \param program  the program to translate
 896  * \param numInputs  number of input registers used
 897  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 898  *                      input indexes
 899  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 900  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 901  *                            each input
 902  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 903  * \param numOutputs  number of output registers used
 904  * \param outputMapping  maps Mesa fragment program outputs to TGSI
 905  *                       generic outputs
 906  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
 907  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
 908  *                             each output
 909  *
 910  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
 911  */
 912 enum pipe_error
 913 st_translate_mesa_program(
 914    GLcontext *ctx,
 915    uint procType,
 916    struct ureg_program *ureg,
 917    const struct gl_program *program,
 918    GLuint numInputs,
 919    const GLuint inputMapping[],
 920    const ubyte inputSemanticName[],
 921    const ubyte inputSemanticIndex[],
 922    const GLuint interpMode[],
 923    GLuint numOutputs,
 924    const GLuint outputMapping[],
 925    const ubyte outputSemanticName[],
 926    const ubyte outputSemanticIndex[],
 927    boolean passthrough_edgeflags )
 928 {
 929    struct st_translate translate, *t;
 930    unsigned i;
 931    enum pipe_error ret = PIPE_OK;
 932
 933    assert(numInputs <= Elements(t->inputs));
 934    assert(numOutputs <= Elements(t->outputs));
 935
 936    t = &translate;
 937    memset(t, 0, sizeof *t);
 938
 939    t->procType = procType;
 940    t->inputMapping = inputMapping;
 941    t->outputMapping = outputMapping;
 942    t->ureg = ureg;
 943    t->pointSizeOutIndex = -1;
 944    t->prevInstWrotePointSize = GL_FALSE;
 945
 946    /*_mesa_print_program(program);*/
 947
 948    /*
 949     * Declare input attributes.
 950     */
 951    if (procType == TGSI_PROCESSOR_FRAGMENT) {
 952       for (i = 0; i < numInputs; i++) {
 953          if (program->InputFlags[0] & PROG_PARAM_BIT_CYL_WRAP) {
 954             t->inputs[i] = ureg_DECL_fs_input_cyl(ureg,
 955                                                   inputSemanticName[i],
 956                                                   inputSemanticIndex[i],
 957                                                   interpMode[i],
 958                                                   TGSI_CYLINDRICAL_WRAP_X);
 959          }
 960          else {
 961             t->inputs[i] = ureg_DECL_fs_input(ureg,
 962                                               inputSemanticName[i],
 963                                               inputSemanticIndex[i],
 964                                               interpMode[i]);
 965          }
 966       }
 967
 968       if (program->InputsRead & FRAG_BIT_WPOS) {
 969          /* Must do this after setting up t->inputs, and before
 970           * emitting constant references, below:
 971           */
 972          emit_wpos(st_context(ctx), t, program, ureg);
 973       }
 974
 975       if (program->InputsRead & FRAG_BIT_FACE) {
 976          emit_face_var( t, program );
 977       }
 978
 979       /*
 980        * Declare output attributes.
 981        */
 982       for (i = 0; i < numOutputs; i++) {
 983          switch (outputSemanticName[i]) {
 984          case TGSI_SEMANTIC_POSITION:
 985             t->outputs[i] = ureg_DECL_output( ureg,
 986                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
 987                                               outputSemanticIndex[i] );
 988
 989             t->outputs[i] = ureg_writemask( t->outputs[i],
 990                                             TGSI_WRITEMASK_Z );
 991             break;
 992          case TGSI_SEMANTIC_COLOR:
 993             t->outputs[i] = ureg_DECL_output( ureg,
 994                                               TGSI_SEMANTIC_COLOR,
 995                                               outputSemanticIndex[i] );
 996             break;
 997          default:
 998             debug_assert(0);
 999             return 0;
1000          }
1001       }
1002    }
1003    else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1004       for (i = 0; i < numInputs; i++) {
1005          t->inputs[i] = ureg_DECL_gs_input(ureg,
1006                                            i,
1007                                            inputSemanticName[i],
1008                                            inputSemanticIndex[i]);
1009       }
1010
1011       for (i = 0; i < numOutputs; i++) {
1012          t->outputs[i] = ureg_DECL_output( ureg,
1013                                            outputSemanticName[i],
1014                                            outputSemanticIndex[i] );
1015       }
1016    }
1017    else {
1018       assert(procType == TGSI_PROCESSOR_VERTEX);
1019
1020       for (i = 0; i < numInputs; i++) {
1021          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1022       }
1023
1024       for (i = 0; i < numOutputs; i++) {
1025          t->outputs[i] = ureg_DECL_output( ureg,
1026                                            outputSemanticName[i],
1027                                            outputSemanticIndex[i] );
1028          if ((outputSemanticName[i] == TGSI_SEMANTIC_PSIZE) && program->Id) {
1029             /* Writing to the point size result register requires special
1030              * handling to implement clamping.
1031              */
1032             static const gl_state_index pointSizeClampState[STATE_LENGTH]
1033                = { STATE_INTERNAL, STATE_POINT_SIZE_IMPL_CLAMP, 0, 0, 0 };
1034                /* XXX: note we are modifying the incoming shader here!  Need to
1035                * do this before emitting the constant decls below, or this
1036                * will be missed:
1037                */
1038             unsigned pointSizeClampConst =
1039                _mesa_add_state_reference(program->Parameters,
1040                                          pointSizeClampState);
1041             struct ureg_dst psizregtemp = ureg_DECL_temporary( ureg );
1042             t->pointSizeConst = ureg_DECL_constant( ureg, pointSizeClampConst );
1043             t->pointSizeResult = t->outputs[i];
1044             t->pointSizeOutIndex = i;
1045             t->outputs[i] = psizregtemp;
1046          }
1047       }
1048       if (passthrough_edgeflags)
1049          emit_edgeflags( t, program );
1050    }
1051
1052    /* Declare address register.
1053     */
1054    if (program->NumAddressRegs > 0) {
1055       debug_assert( program->NumAddressRegs == 1 );
1056       t->address[0] = ureg_DECL_address( ureg );
1057    }
1058
1059    /* Emit constants and immediates.  Mesa uses a single index space
1060     * for these, so we put all the translated regs in t->constants.
1061     */
1062    if (program->Parameters) {
1063       t->constants = CALLOC( program->Parameters->NumParameters,
1064                              sizeof t->constants[0] );
1065       if (t->constants == NULL) {
1066          ret = PIPE_ERROR_OUT_OF_MEMORY;
1067          goto out;
1068       }
1069
1070       for (i = 0; i < program->Parameters->NumParameters; i++) {
1071          switch (program->Parameters->Parameters[i].Type) {
1072          case PROGRAM_ENV_PARAM:
1073          case PROGRAM_LOCAL_PARAM:
1074          case PROGRAM_STATE_VAR:
1075          case PROGRAM_NAMED_PARAM:
1076          case PROGRAM_UNIFORM:
1077             t->constants[i] = ureg_DECL_constant( ureg, i );
1078             break;
1079
1080             /* Emit immediates only when there is no address register
1081              * in use.  FIXME: Be smarter and recognize param arrays:
1082              * indirect addressing is only valid within the referenced
1083              * array.
1084              */
1085          case PROGRAM_CONSTANT:
1086             if (program->NumAddressRegs > 0)
1087                t->constants[i] = ureg_DECL_constant( ureg, i );
1088             else
1089                t->constants[i] =
1090                   ureg_DECL_immediate( ureg,
1091                                        program->Parameters->ParameterValues[i],
1092                                        4 );
1093             break;
1094          default:
1095             break;
1096          }
1097       }
1098    }
1099
1100    /* texture samplers */
1101    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
1102       if (program->SamplersUsed & (1 << i)) {
1103          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1104       }
1105    }
1106
1107    /* Emit each instruction in turn:
1108     */
1109    for (i = 0; i < program->NumInstructions; i++) {
1110       set_insn_start( t, ureg_get_instruction_number( ureg ));
1111       compile_instruction( t, &program->Instructions[i] );
1112
1113       if (t->prevInstWrotePointSize && program->Id) {
1114          /* The previous instruction wrote to the (fake) vertex point size
1115           * result register.  Now we need to clamp that value to the min/max
1116           * point size range, putting the result into the real point size
1117           * register.
1118           * Note that we can't do this easily at the end of program due to
1119           * possible early return.
1120           */
1121          set_insn_start( t, ureg_get_instruction_number( ureg ));
1122          ureg_MAX( t->ureg,
1123                    ureg_writemask(t->outputs[t->pointSizeOutIndex], WRITEMASK_X),
1124                    ureg_src(t->outputs[t->pointSizeOutIndex]),
1125                    ureg_swizzle(t->pointSizeConst, 1,1,1,1));
1126          ureg_MIN( t->ureg, ureg_writemask(t->pointSizeResult, WRITEMASK_X),
1127                    ureg_src(t->outputs[t->pointSizeOutIndex]),
1128                    ureg_swizzle(t->pointSizeConst, 2,2,2,2));
1129       }
1130       t->prevInstWrotePointSize = GL_FALSE;
1131    }
1132
1133    /* Fix up all emitted labels:
1134     */
1135    for (i = 0; i < t->labels_count; i++) {
1136       ureg_fixup_label( ureg,
1137                         t->labels[i].token,
1138                         t->insn[t->labels[i].branch_target] );
1139    }
1140
1141 out:
1142    FREE(t->insn);
1143    FREE(t->labels);
1144    FREE(t->constants);
1145
1146    if (t->error) {
1147       debug_printf("%s: translate error flag set\n", __FUNCTION__);
1148    }
1149
1150    return ret;
1151 }
1152
1153
1154 /**
1155  * Tokens cannot be free with free otherwise the builtin gallium
1156  * malloc debugging will get confused.
1157  */
1158 void
1159 st_free_tokens(const struct tgsi_token *tokens)
1160 {
1161    FREE((void *)tokens);
1162 }