2 * Copyright (C) 2020 Collabora, Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 #define RETURN_PACKED(str) { \
29 memcpy(&temp, &str, sizeof(str)); \
33 /* This file contains the final passes of the compiler. Running after
34 * scheduling and RA, the IR is now finalized, so we need to emit it to actual
35 * bits on the wire (as well as fixup branches) */
38 bi_pack_header(bi_clause
*clause
, bi_clause
*next
, bool is_fragment
)
40 struct bifrost_header header
= {
41 .back_to_back
= clause
->back_to_back
,
42 .no_end_of_shader
= (next
!= NULL
),
43 .elide_writes
= is_fragment
,
44 .branch_cond
= clause
->branch_conditional
,
45 .datareg_writebarrier
= clause
->data_register_write_barrier
,
46 .datareg
= clause
->data_register
,
47 .scoreboard_deps
= next
? next
->dependencies
: 0,
48 .scoreboard_index
= clause
->scoreboard_id
,
49 .clause_type
= clause
->clause_type
,
50 .next_clause_type
= next
? next
->clause_type
: 0,
55 header
.branch_cond
|= header
.back_to_back
;
58 memcpy(&u
, &header
, sizeof(header
));
62 /* The uniform/constant slot allows loading a contiguous 64-bit immediate or
63 * pushed uniform per bundle. Figure out which one we need in the bundle (the
64 * scheduler needs to ensure we only have one type per bundle), validate
65 * everything, and rewrite away the register/uniform indices to use 3-bit
66 * sources directly. */
69 bi_lookup_constant(bi_clause
*clause
, uint64_t cons
, bool *hi
, bool b64
)
71 uint64_t want
= (cons
>> 4);
73 for (unsigned i
= 0; i
< clause
->constant_count
; ++i
) {
74 /* Only check top 60-bits since that's what's actually embedded
75 * in the clause, the bottom 4-bits are bundle-inline */
77 uint64_t candidates
[2] = {
78 clause
->constants
[i
] >> 4,
79 clause
->constants
[i
] >> 36
82 /* For <64-bit mode, we treat lo/hi separately */
85 candidates
[0] &= (0xFFFFFFFF >> 4);
87 if (candidates
[0] == want
)
90 if (candidates
[1] == want
&& !b64
) {
96 unreachable("Invalid constant accessed");
100 bi_constant_field(unsigned idx
)
104 const unsigned values
[] = {
108 return values
[idx
] << 4;
112 bi_assign_uniform_constant_single(
115 bi_instruction
*ins
, bool assigned
, bool fast_zero
)
120 if (ins
->type
== BI_BLEND
) {
122 regs
->uniform_constant
= 0x8;
126 bi_foreach_src(ins
, s
) {
127 if (s
== 0 && (ins
->type
== BI_LOAD_VAR_ADDRESS
|| ins
->type
== BI_LOAD_ATTR
)) continue;
129 if (ins
->src
[s
] & BIR_INDEX_CONSTANT
) {
130 /* Let direct addresses through */
131 if (ins
->type
== BI_LOAD_VAR
)
135 bool b64
= nir_alu_type_get_type_size(ins
->src_types
[s
]) > 32;
136 uint64_t cons
= bi_get_immediate(ins
, s
);
137 unsigned idx
= bi_lookup_constant(clause
, cons
, &hi
, b64
);
138 unsigned lo
= clause
->constants
[idx
] & 0xF;
139 unsigned f
= bi_constant_field(idx
) | lo
;
141 if (assigned
&& regs
->uniform_constant
!= f
)
142 unreachable("Mismatched uniform/const field: imm");
144 regs
->uniform_constant
= f
;
145 ins
->src
[s
] = BIR_INDEX_PASS
| (hi
? BIFROST_SRC_CONST_HI
: BIFROST_SRC_CONST_LO
);
147 } else if (ins
->src
[s
] & BIR_INDEX_ZERO
&& (ins
->type
== BI_LOAD_UNIFORM
|| ins
->type
== BI_LOAD_VAR
)) {
148 /* XXX: HACK UNTIL WE HAVE HI MATCHING DUE TO OVERFLOW XXX */
149 ins
->src
[s
] = BIR_INDEX_PASS
| BIFROST_SRC_CONST_HI
;
150 } else if (ins
->src
[s
] & BIR_INDEX_ZERO
&& !fast_zero
) {
151 /* FMAs have a fast zero port, ADD needs to use the
152 * uniform/const port's special 0 mode handled here */
155 if (assigned
&& regs
->uniform_constant
!= f
)
156 unreachable("Mismatched uniform/const field: 0");
158 regs
->uniform_constant
= f
;
159 ins
->src
[s
] = BIR_INDEX_PASS
| BIFROST_SRC_CONST_LO
;
161 } else if (ins
->src
[s
] & BIR_INDEX_ZERO
&& fast_zero
) {
162 ins
->src
[s
] = BIR_INDEX_PASS
| BIFROST_SRC_STAGE
;
163 } else if (s
& BIR_INDEX_UNIFORM
) {
164 unreachable("Push uniforms not implemented yet");
172 bi_assign_uniform_constant(
178 bi_assign_uniform_constant_single(regs
, clause
, bundle
.fma
, false, true);
180 bi_assign_uniform_constant_single(regs
, clause
, bundle
.add
, assigned
, false);
183 /* Assigns a port for reading, before anything is written */
186 bi_assign_port_read(bi_registers
*regs
, unsigned src
)
188 /* We only assign for registers */
189 if (!(src
& BIR_INDEX_REGISTER
))
192 unsigned reg
= src
& ~BIR_INDEX_REGISTER
;
194 /* Check if we already assigned the port */
195 for (unsigned i
= 0; i
<= 1; ++i
) {
196 if (regs
->port
[i
] == reg
&& regs
->enabled
[i
])
200 if (regs
->port
[3] == reg
&& regs
->read_port3
)
205 for (unsigned i
= 0; i
<= 1; ++i
) {
206 if (!regs
->enabled
[i
]) {
208 regs
->enabled
[i
] = true;
213 if (!regs
->read_port3
) {
215 regs
->read_port3
= true;
219 bi_print_ports(regs
, stderr
);
220 unreachable("Failed to find a free port for src");
224 bi_assign_ports(bi_bundle
*now
, bi_bundle
*prev
)
226 /* We assign ports for the main register mechanism. Special ops
227 * use the data registers, which has its own mechanism entirely
228 * and thus gets skipped over here. */
230 unsigned read_dreg
= now
->add
&&
231 bi_class_props
[now
->add
->type
] & BI_DATA_REG_SRC
;
233 unsigned write_dreg
= prev
->add
&&
234 bi_class_props
[prev
->add
->type
] & BI_DATA_REG_DEST
;
236 /* First, assign reads */
239 bi_foreach_src(now
->fma
, src
)
240 bi_assign_port_read(&now
->regs
, now
->fma
->src
[src
]);
243 bi_foreach_src(now
->add
, src
) {
244 if (!(src
== 0 && read_dreg
))
245 bi_assign_port_read(&now
->regs
, now
->add
->src
[src
]);
249 /* Next, assign writes */
251 if (prev
->add
&& prev
->add
->dest
& BIR_INDEX_REGISTER
&& !write_dreg
) {
252 now
->regs
.port
[2] = prev
->add
->dest
& ~BIR_INDEX_REGISTER
;
253 now
->regs
.write_add
= true;
256 if (prev
->fma
&& prev
->fma
->dest
& BIR_INDEX_REGISTER
) {
257 unsigned r
= prev
->fma
->dest
& ~BIR_INDEX_REGISTER
;
259 if (now
->regs
.write_add
) {
260 /* Scheduler constraint: cannot read 3 and write 2 */
261 assert(!now
->regs
.read_port3
);
262 now
->regs
.port
[3] = r
;
264 now
->regs
.port
[2] = r
;
267 now
->regs
.write_fma
= true;
270 /* Finally, ensure port 1 > port 0 for the 63-x trick to function */
272 if (now
->regs
.enabled
[0] && now
->regs
.enabled
[1] && now
->regs
.port
[1] < now
->regs
.port
[0]) {
273 unsigned temp
= now
->regs
.port
[0];
274 now
->regs
.port
[0] = now
->regs
.port
[1];
275 now
->regs
.port
[1] = temp
;
281 /* Determines the register control field, ignoring the first? flag */
283 static enum bifrost_reg_control
284 bi_pack_register_ctrl_lo(bi_registers r
)
288 assert(!r
.read_port3
);
289 return BIFROST_WRITE_ADD_P2_FMA_P3
;
292 return BIFROST_WRITE_FMA_P2_READ_P3
;
294 return BIFROST_WRITE_FMA_P2
;
296 } else if (r
.write_add
) {
298 return BIFROST_WRITE_ADD_P2_READ_P3
;
300 return BIFROST_WRITE_ADD_P2
;
301 } else if (r
.read_port3
)
302 return BIFROST_READ_P3
;
304 return BIFROST_REG_NONE
;
307 /* Ditto but account for the first? flag this time */
309 static enum bifrost_reg_control
310 bi_pack_register_ctrl(bi_registers r
)
312 enum bifrost_reg_control ctrl
= bi_pack_register_ctrl_lo(r
);
314 if (r
.first_instruction
) {
315 if (ctrl
== BIFROST_REG_NONE
)
316 ctrl
= BIFROST_FIRST_NONE
;
317 else if (ctrl
== BIFROST_WRITE_FMA_P2_READ_P3
)
318 ctrl
= BIFROST_FIRST_WRITE_FMA_P2_READ_P3
;
320 ctrl
|= BIFROST_FIRST_NONE
;
327 bi_pack_registers(bi_registers regs
)
329 enum bifrost_reg_control ctrl
= bi_pack_register_ctrl(regs
);
330 struct bifrost_regs s
= { 0 };
333 if (regs
.enabled
[1]) {
334 /* Gotta save that bit!~ Required by the 63-x trick */
335 assert(regs
.port
[1] > regs
.port
[0]);
336 assert(regs
.enabled
[0]);
338 /* Do the 63-x trick, see docs/disasm */
339 if (regs
.port
[0] > 31) {
340 regs
.port
[0] = 63 - regs
.port
[0];
341 regs
.port
[1] = 63 - regs
.port
[1];
344 assert(regs
.port
[0] <= 31);
345 assert(regs
.port
[1] <= 63);
348 s
.reg1
= regs
.port
[1];
349 s
.reg0
= regs
.port
[0];
351 /* Port 1 disabled, so set to zero and use port 1 for ctrl */
355 if (regs
.enabled
[0]) {
356 /* Bit 0 upper bit of port 0 */
357 s
.reg1
|= (regs
.port
[0] >> 5);
359 /* Rest of port 0 in usual spot */
360 s
.reg0
= (regs
.port
[0] & 0b11111);
362 /* Bit 1 set if port 0 also disabled */
367 /* When port 3 isn't used, we have to set it to port 2, and vice versa,
368 * or INSTR_INVALID_ENC is raised. The reason is unknown. */
370 bool has_port2
= regs
.write_fma
|| regs
.write_add
;
371 bool has_port3
= regs
.read_port3
|| (regs
.write_fma
&& regs
.write_add
);
374 regs
.port
[3] = regs
.port
[2];
377 regs
.port
[2] = regs
.port
[3];
379 s
.reg3
= regs
.port
[3];
380 s
.reg2
= regs
.port
[2];
381 s
.uniform_const
= regs
.uniform_constant
;
383 memcpy(&packed
, &s
, sizeof(s
));
388 bi_set_data_register(bi_clause
*clause
, unsigned idx
)
390 assert(idx
& BIR_INDEX_REGISTER
);
391 unsigned reg
= idx
& ~BIR_INDEX_REGISTER
;
393 clause
->data_register
= reg
;
397 bi_read_data_register(bi_clause
*clause
, bi_instruction
*ins
)
399 bi_set_data_register(clause
, ins
->src
[0]);
403 bi_write_data_register(bi_clause
*clause
, bi_instruction
*ins
)
405 bi_set_data_register(clause
, ins
->dest
);
408 static enum bifrost_packed_src
409 bi_get_src_reg_port(bi_registers
*regs
, unsigned src
)
411 unsigned reg
= src
& ~BIR_INDEX_REGISTER
;
413 if (regs
->port
[0] == reg
&& regs
->enabled
[0])
414 return BIFROST_SRC_PORT0
;
415 else if (regs
->port
[1] == reg
&& regs
->enabled
[1])
416 return BIFROST_SRC_PORT1
;
417 else if (regs
->port
[3] == reg
&& regs
->read_port3
)
418 return BIFROST_SRC_PORT3
;
420 unreachable("Tried to access register with no port");
423 static enum bifrost_packed_src
424 bi_get_src(bi_instruction
*ins
, bi_registers
*regs
, unsigned s
)
426 unsigned src
= ins
->src
[s
];
428 if (src
& BIR_INDEX_REGISTER
)
429 return bi_get_src_reg_port(regs
, src
);
430 else if (src
& BIR_INDEX_PASS
)
431 return src
& ~BIR_INDEX_PASS
;
433 bi_print_instruction(ins
, stderr
);
434 unreachable("Unknown src in above instruction");
438 /* Constructs a packed 2-bit swizzle for a 16-bit vec2 source. Source must be
439 * 16-bit and written components must correspond to valid swizzles (component x
443 bi_swiz16(bi_instruction
*ins
, unsigned src
)
445 assert(nir_alu_type_get_type_size(ins
->src_types
[src
]) == 16);
446 unsigned swizzle
= 0;
448 for (unsigned c
= 0; c
< 2; ++c
) {
449 if (!bi_writes_component(ins
, src
)) continue;
451 unsigned k
= ins
->swizzle
[src
][c
];
460 bi_pack_fma_fma(bi_instruction
*ins
, bi_registers
*regs
)
462 /* (-a)(-b) = ab, so we only need one negate bit */
463 bool negate_mul
= ins
->src_neg
[0] ^ ins
->src_neg
[1];
465 if (ins
->op
.mscale
) {
466 assert(!(ins
->src_abs
[0] && ins
->src_abs
[1]));
467 assert(!ins
->src_abs
[2] || !ins
->src_neg
[3] || !ins
->src_abs
[3]);
469 /* We can have exactly one abs, and can flip the multiplication
470 * to make it fit if we have to */
471 bool flip_ab
= ins
->src_abs
[1];
473 struct bifrost_fma_mscale pack
= {
474 .src0
= bi_get_src(ins
, regs
, flip_ab
? 1 : 0),
475 .src1
= bi_get_src(ins
, regs
, flip_ab
? 0 : 1),
476 .src2
= bi_get_src(ins
, regs
, 2),
477 .src3
= bi_get_src(ins
, regs
, 3),
480 .src0_abs
= ins
->src_abs
[0] || ins
->src_abs
[1],
481 .src1_neg
= negate_mul
,
482 .src2_neg
= ins
->src_neg
[2],
483 .op
= BIFROST_FMA_OP_MSCALE
,
487 } else if (ins
->dest_type
== nir_type_float32
) {
488 struct bifrost_fma_fma pack
= {
489 .src0
= bi_get_src(ins
, regs
, 0),
490 .src1
= bi_get_src(ins
, regs
, 1),
491 .src2
= bi_get_src(ins
, regs
, 2),
492 .src0_abs
= ins
->src_abs
[0],
493 .src1_abs
= ins
->src_abs
[1],
494 .src2_abs
= ins
->src_abs
[2],
495 .src0_neg
= negate_mul
,
496 .src2_neg
= ins
->src_neg
[2],
497 .outmod
= ins
->outmod
,
498 .roundmode
= ins
->roundmode
,
499 .op
= BIFROST_FMA_OP_FMA
503 } else if (ins
->dest_type
== nir_type_float16
) {
504 struct bifrost_fma_fma16 pack
= {
505 .src0
= bi_get_src(ins
, regs
, 0),
506 .src1
= bi_get_src(ins
, regs
, 1),
507 .src2
= bi_get_src(ins
, regs
, 2),
508 .swizzle_0
= bi_swiz16(ins
, 0),
509 .swizzle_1
= bi_swiz16(ins
, 1),
510 .swizzle_2
= bi_swiz16(ins
, 2),
511 .src0_neg
= negate_mul
,
512 .src2_neg
= ins
->src_neg
[2],
513 .outmod
= ins
->outmod
,
514 .roundmode
= ins
->roundmode
,
515 .op
= BIFROST_FMA_OP_FMA16
520 unreachable("Invalid fma dest type");
525 bi_pack_fma_addmin_f32(bi_instruction
*ins
, bi_registers
*regs
)
528 (ins
->type
== BI_ADD
) ? BIFROST_FMA_OP_FADD32
:
529 (ins
->op
.minmax
== BI_MINMAX_MIN
) ? BIFROST_FMA_OP_FMIN32
:
530 BIFROST_FMA_OP_FMAX32
;
532 struct bifrost_fma_add pack
= {
533 .src0
= bi_get_src(ins
, regs
, 0),
534 .src1
= bi_get_src(ins
, regs
, 1),
535 .src0_abs
= ins
->src_abs
[0],
536 .src1_abs
= ins
->src_abs
[1],
537 .src0_neg
= ins
->src_neg
[0],
538 .src1_neg
= ins
->src_neg
[1],
540 .outmod
= ins
->outmod
,
541 .roundmode
= (ins
->type
== BI_ADD
) ? ins
->roundmode
: ins
->minmax
,
549 bi_pack_fp16_abs(bi_instruction
*ins
, bi_registers
*regs
, bool *flip
)
551 /* Absolute values are packed in a quirky way. Let k = src1 < src0. Let
552 * l be an auxiliary bit we encode. Then the hardware determines:
557 * Since add/min/max are commutative, this saves a bit by using the
558 * order of the operands as a bit (k). To pack this, first note:
560 * (l && k) implies (l || k).
562 * That is, if the second argument is abs'd, then the first argument
563 * also has abs. So there are three cases:
565 * Case 0: Neither src has absolute value. Then we have l = k = 0.
567 * Case 1: Exactly one src has absolute value. Assign that source to
568 * src0 and the other source to src1. Compute k = src1 < src0 based on
569 * that assignment. Then l = ~k.
571 * Case 2: Both sources have absolute value. Then we have l = k = 1.
572 * Note to force k = 1 requires that (src1 < src0) OR (src0 < src1).
573 * That is, this encoding is only valid if src1 and src0 are distinct.
574 * This is a scheduling restriction (XXX); if an op of this type
575 * requires both identical sources to have abs value, then we must
576 * schedule to ADD (which does not use this ordering trick).
579 unsigned abs_0
= ins
->src_abs
[0], abs_1
= ins
->src_abs
[1];
580 unsigned src_0
= bi_get_src(ins
, regs
, 0);
581 unsigned src_1
= bi_get_src(ins
, regs
, 1);
583 assert(!(abs_0
&& abs_1
&& src_0
== src_1
));
585 if (!abs_0
&& !abs_1
) {
586 /* Force k = 0 <===> NOT(src1 < src0) */
587 *flip
= (src_1
< src_0
);
589 } else if (abs_0
&& !abs_1
) {
590 return src_1
>= src_0
;
591 } else if (abs_1
&& !abs_0
) {
593 return src_0
>= src_1
;
595 *flip
= !(src_1
< src_0
);
601 bi_pack_fmadd_min_f16(bi_instruction
*ins
, bi_registers
*regs
, bool FMA
)
604 (!FMA
) ? ((ins
->op
.minmax
== BI_MINMAX_MIN
) ?
605 BIFROST_ADD_OP_FMIN16
: BIFROST_ADD_OP_FMAX16
) :
606 (ins
->type
== BI_ADD
) ? BIFROST_FMA_OP_FADD16
:
607 (ins
->op
.minmax
== BI_MINMAX_MIN
) ? BIFROST_FMA_OP_FMIN16
:
608 BIFROST_FMA_OP_FMAX16
;
611 bool l
= bi_pack_fp16_abs(ins
, regs
, &flip
);
612 unsigned src_0
= bi_get_src(ins
, regs
, 0);
613 unsigned src_1
= bi_get_src(ins
, regs
, 1);
616 struct bifrost_fma_add_minmax16 pack
= {
617 .src0
= flip
? src_1
: src_0
,
618 .src1
= flip
? src_0
: src_1
,
619 .src0_neg
= ins
->src_neg
[flip
? 1 : 0],
620 .src1_neg
= ins
->src_neg
[flip
? 0 : 1],
621 .src0_swizzle
= bi_swiz16(ins
, flip
? 1 : 0),
622 .src1_swizzle
= bi_swiz16(ins
, flip
? 0 : 1),
624 .outmod
= ins
->outmod
,
625 .mode
= (ins
->type
== BI_ADD
) ? ins
->roundmode
: ins
->minmax
,
631 /* Can't have modes for fp16 */
632 assert(ins
->outmod
== 0);
634 struct bifrost_add_fmin16 pack
= {
635 .src0
= flip
? src_1
: src_0
,
636 .src1
= flip
? src_0
: src_1
,
637 .src0_neg
= ins
->src_neg
[flip
? 1 : 0],
638 .src1_neg
= ins
->src_neg
[flip
? 0 : 1],
640 .src0_swizzle
= bi_swiz16(ins
, flip
? 1 : 0),
641 .src1_swizzle
= bi_swiz16(ins
, flip
? 0 : 1),
651 bi_pack_fma_addmin(bi_instruction
*ins
, bi_registers
*regs
)
653 if (ins
->dest_type
== nir_type_float32
)
654 return bi_pack_fma_addmin_f32(ins
, regs
);
655 else if(ins
->dest_type
== nir_type_float16
)
656 return bi_pack_fmadd_min_f16(ins
, regs
, true);
658 unreachable("Unknown FMA/ADD type");
662 bi_pack_fma_1src(bi_instruction
*ins
, bi_registers
*regs
, unsigned op
)
664 struct bifrost_fma_inst pack
= {
665 .src0
= bi_get_src(ins
, regs
, 0),
673 bi_pack_fma_2src(bi_instruction
*ins
, bi_registers
*regs
, unsigned op
)
675 struct bifrost_fma_2src pack
= {
676 .src0
= bi_get_src(ins
, regs
, 0),
677 .src1
= bi_get_src(ins
, regs
, 1),
685 bi_pack_add_1src(bi_instruction
*ins
, bi_registers
*regs
, unsigned op
)
687 struct bifrost_add_inst pack
= {
688 .src0
= bi_get_src(ins
, regs
, 0),
695 static enum bifrost_csel_cond
696 bi_cond_to_csel(enum bi_cond cond
, bool *flip
, bool *invert
, nir_alu_type T
)
698 nir_alu_type B
= nir_alu_type_get_base_type(T
);
699 unsigned idx
= (B
== nir_type_float
) ? 0 :
700 ((B
== nir_type_int
) ? 1 : 2);
706 const enum bifrost_csel_cond ops
[] = {
717 const enum bifrost_csel_cond ops
[] = {
728 const enum bifrost_csel_cond ops
[] = {
731 BIFROST_IEQ_F
/* sign is irrelevant */
737 unreachable("Invalid op for csel");
742 bi_pack_fma_csel(bi_instruction
*ins
, bi_registers
*regs
)
744 /* TODO: Use csel3 as well */
745 bool flip
= false, invert
= false;
747 enum bifrost_csel_cond cond
=
748 bi_cond_to_csel(ins
->cond
, &flip
, &invert
, ins
->src_types
[0]);
750 unsigned size
= nir_alu_type_get_type_size(ins
->dest_type
);
752 unsigned cmp_0
= (flip
? 1 : 0);
753 unsigned cmp_1
= (flip
? 0 : 1);
754 unsigned res_0
= (invert
? 3 : 2);
755 unsigned res_1
= (invert
? 2 : 3);
757 struct bifrost_csel4 pack
= {
758 .src0
= bi_get_src(ins
, regs
, cmp_0
),
759 .src1
= bi_get_src(ins
, regs
, cmp_1
),
760 .src2
= bi_get_src(ins
, regs
, res_0
),
761 .src3
= bi_get_src(ins
, regs
, res_1
),
763 .op
= (size
== 16) ? BIFROST_FMA_OP_CSEL4_V16
:
771 bi_pack_fma_frexp(bi_instruction
*ins
, bi_registers
*regs
)
773 unsigned op
= BIFROST_FMA_OP_FREXPE_LOG
;
774 return bi_pack_fma_1src(ins
, regs
, op
);
778 bi_pack_fma_reduce(bi_instruction
*ins
, bi_registers
*regs
)
780 if (ins
->op
.reduce
== BI_REDUCE_ADD_FREXPM
) {
781 return bi_pack_fma_2src(ins
, regs
, BIFROST_FMA_OP_ADD_FREXPM
);
783 unreachable("Invalid reduce op");
787 /* We have a single convert opcode in the IR but a number of opcodes that could
788 * come out. In particular we have native opcodes for:
790 * [ui]16 --> [fui]32 -- int16_to_32
791 * f16 --> f32 -- float16_to_32
792 * f32 --> f16 -- float32_to_16
793 * f32 --> [ui]32 -- float32_to_int
794 * [ui]32 --> f32 -- int_to_float32
795 * [fui]16 --> [fui]16 -- f2i_i2f16
799 bi_pack_convert(bi_instruction
*ins
, bi_registers
*regs
, bool FMA
)
801 nir_alu_type from_base
= nir_alu_type_get_base_type(ins
->src_types
[0]);
802 unsigned from_size
= nir_alu_type_get_type_size(ins
->src_types
[0]);
803 bool from_unsigned
= from_base
== nir_type_uint
;
805 nir_alu_type to_base
= nir_alu_type_get_base_type(ins
->dest_type
);
806 unsigned to_size
= nir_alu_type_get_type_size(ins
->dest_type
);
807 bool to_unsigned
= to_base
== nir_type_uint
;
808 bool to_float
= to_base
== nir_type_float
;
811 assert((from_base
!= to_base
) || (from_size
!= to_size
));
812 assert((MAX2(from_size
, to_size
) / MIN2(from_size
, to_size
)) <= 2);
814 /* f32 to f16 is special */
815 if (from_size
== 32 && to_size
== 16 && from_base
== nir_type_float
&& to_base
== from_base
) {
816 /* TODO: second vectorized source? */
817 struct bifrost_fma_2src pfma
= {
818 .src0
= bi_get_src(ins
, regs
, 0),
819 .src1
= BIFROST_SRC_STAGE
, /* 0 */
820 .op
= BIFROST_FMA_FLOAT32_TO_16
823 struct bifrost_add_2src padd
= {
824 .src0
= bi_get_src(ins
, regs
, 0),
825 .src1
= BIFROST_SRC_STAGE
, /* 0 */
826 .op
= BIFROST_ADD_FLOAT32_TO_16
836 /* Otherwise, figure out the mode */
839 if (from_size
== 16 && to_size
== 32) {
840 unsigned component
= ins
->swizzle
[0][0];
841 assert(component
<= 1);
843 if (from_base
== nir_type_float
)
844 op
= BIFROST_CONVERT_5(component
);
846 op
= BIFROST_CONVERT_4(from_unsigned
, component
, to_float
);
849 unsigned swizzle
= (from_size
== 16) ? bi_swiz16(ins
, 0) : 0;
850 bool is_unsigned
= from_unsigned
;
852 if (from_base
== nir_type_float
) {
853 assert(to_base
!= nir_type_float
);
854 is_unsigned
= to_unsigned
;
856 if (from_size
== 32 && to_size
== 32)
857 mode
= BIFROST_CONV_F32_TO_I32
;
858 else if (from_size
== 16 && to_size
== 16)
859 mode
= BIFROST_CONV_F16_TO_I16
;
861 unreachable("Invalid float conversion");
863 assert(to_base
== nir_type_float
);
864 assert(from_size
== to_size
);
867 mode
= BIFROST_CONV_I32_TO_F32
;
868 else if (to_size
== 16)
869 mode
= BIFROST_CONV_I16_TO_F16
;
871 unreachable("Invalid int conversion");
874 /* Fixup swizzle for 32-bit only modes */
876 if (mode
== BIFROST_CONV_I32_TO_F32
)
878 else if (mode
== BIFROST_CONV_F32_TO_I32
)
881 op
= BIFROST_CONVERT(is_unsigned
, ins
->roundmode
, swizzle
, mode
);
883 /* Unclear what the top bit is for... maybe 16-bit related */
884 bool mode2
= mode
== BIFROST_CONV_F16_TO_I16
;
885 bool mode6
= mode
== BIFROST_CONV_I16_TO_F16
;
887 if (!(mode2
|| mode6
))
892 return bi_pack_fma_1src(ins
, regs
, BIFROST_FMA_CONVERT
| op
);
894 return bi_pack_add_1src(ins
, regs
, BIFROST_ADD_CONVERT
| op
);
898 bi_pack_fma_select(bi_instruction
*ins
, bi_registers
*regs
)
900 unsigned size
= nir_alu_type_get_type_size(ins
->src_types
[0]);
903 unsigned swiz
= (ins
->swizzle
[0][0] | (ins
->swizzle
[1][0] << 1));
904 unsigned op
= BIFROST_FMA_SEL_16(swiz
);
905 return bi_pack_fma_2src(ins
, regs
, op
);
906 } else if (size
== 8) {
909 for (unsigned c
= 0; c
< 4; ++c
) {
910 if (ins
->swizzle
[c
][0]) {
911 /* Ensure lowering restriction is met */
912 assert(ins
->swizzle
[c
][0] == 2);
917 struct bifrost_fma_sel8 pack
= {
918 .src0
= bi_get_src(ins
, regs
, 0),
919 .src1
= bi_get_src(ins
, regs
, 1),
920 .src2
= bi_get_src(ins
, regs
, 2),
921 .src3
= bi_get_src(ins
, regs
, 3),
923 .op
= BIFROST_FMA_OP_SEL8
928 unreachable("Unimplemented");
932 static enum bifrost_fcmp_cond
933 bi_fcmp_cond(enum bi_cond cond
)
936 case BI_COND_LT
: return BIFROST_OLT
;
937 case BI_COND_LE
: return BIFROST_OLE
;
938 case BI_COND_GE
: return BIFROST_OGE
;
939 case BI_COND_GT
: return BIFROST_OGT
;
940 case BI_COND_EQ
: return BIFROST_OEQ
;
941 case BI_COND_NE
: return BIFROST_UNE
;
942 default: unreachable("Unknown bi_cond");
946 /* a <?> b <==> b <flip(?)> a (TODO: NaN behaviour?) */
948 static enum bifrost_fcmp_cond
949 bi_flip_fcmp(enum bifrost_fcmp_cond cond
)
964 unreachable("Unknown fcmp cond");
969 bi_pack_fma_cmp(bi_instruction
*ins
, bi_registers
*regs
)
971 nir_alu_type Tl
= ins
->src_types
[0];
972 nir_alu_type Tr
= ins
->src_types
[1];
974 if (Tl
== nir_type_float32
|| Tr
== nir_type_float32
) {
975 /* TODO: Mixed 32/16 cmp */
978 enum bifrost_fcmp_cond cond
= bi_fcmp_cond(ins
->cond
);
980 /* Only src1 has neg, so we arrange:
983 * -a < -b <===> a > b
984 * -a < b <===> a > -b
985 * TODO: Is this NaN-precise?
988 bool flip
= ins
->src_neg
[0];
989 bool neg
= ins
->src_neg
[0] ^ ins
->src_neg
[1];
992 cond
= bi_flip_fcmp(cond
);
994 struct bifrost_fma_fcmp pack
= {
995 .src0
= bi_get_src(ins
, regs
, 0),
996 .src1
= bi_get_src(ins
, regs
, 1),
997 .src0_abs
= ins
->src_abs
[0],
998 .src1_abs
= ins
->src_abs
[1],
1003 .op
= BIFROST_FMA_OP_FCMP_GL
1006 RETURN_PACKED(pack
);
1007 } else if (Tl
== nir_type_float16
&& Tr
== nir_type_float16
) {
1009 bool l
= bi_pack_fp16_abs(ins
, regs
, &flip
);
1010 enum bifrost_fcmp_cond cond
= bi_fcmp_cond(ins
->cond
);
1013 cond
= bi_flip_fcmp(cond
);
1015 struct bifrost_fma_fcmp16 pack
= {
1016 .src0
= bi_get_src(ins
, regs
, flip
? 1 : 0),
1017 .src1
= bi_get_src(ins
, regs
, flip
? 0 : 1),
1018 .src0_swizzle
= bi_swiz16(ins
, flip
? 1 : 0),
1019 .src1_swizzle
= bi_swiz16(ins
, flip
? 0 : 1),
1023 .op
= BIFROST_FMA_OP_FCMP_GL_16
,
1026 RETURN_PACKED(pack
);
1028 unreachable("Unknown cmp type");
1033 bi_fma_bitwise_op(enum bi_bitwise_op op
, bool rshift
)
1037 /* Via De Morgan's */
1039 BIFROST_FMA_OP_RSHIFT_NAND
:
1040 BIFROST_FMA_OP_LSHIFT_NAND
;
1041 case BI_BITWISE_AND
:
1043 BIFROST_FMA_OP_RSHIFT_AND
:
1044 BIFROST_FMA_OP_LSHIFT_AND
;
1045 case BI_BITWISE_XOR
:
1046 /* Shift direction handled out of band */
1047 return BIFROST_FMA_OP_RSHIFT_XOR
;
1049 unreachable("Unknown op");
1054 bi_pack_fma_bitwise(bi_instruction
*ins
, bi_registers
*regs
)
1056 unsigned size
= nir_alu_type_get_type_size(ins
->dest_type
);
1059 bool invert_0
= ins
->bitwise
.src_invert
[0];
1060 bool invert_1
= ins
->bitwise
.src_invert
[1];
1062 if (ins
->op
.bitwise
== BI_BITWISE_OR
) {
1063 /* Becomes NAND, so via De Morgan's:
1064 * f(A) | f(B) = ~(~f(A) & ~f(B))
1065 * = NAND(~f(A), ~f(B))
1068 invert_0
= !invert_0
;
1069 invert_1
= !invert_1
;
1070 } else if (ins
->op
.bitwise
== BI_BITWISE_XOR
) {
1071 /* ~A ^ ~B = ~(A ^ ~B) = ~(~(A ^ B)) = A ^ B
1072 * ~A ^ B = ~(A ^ B) = A ^ ~B
1075 invert_0
^= invert_1
;
1078 /* invert_1 ends up specifying shift direction */
1079 invert_1
= !ins
->bitwise
.rshift
;
1082 struct bifrost_shift_fma pack
= {
1083 .src0
= bi_get_src(ins
, regs
, 0),
1084 .src1
= bi_get_src(ins
, regs
, 1),
1085 .src2
= bi_get_src(ins
, regs
, 2),
1086 .half
= (size
== 32) ? 0 : (size
== 16) ? 0x7 : (size
== 8) ? 0x4 : 0,
1088 .invert_1
= invert_0
,
1089 .invert_2
= invert_1
,
1090 .op
= bi_fma_bitwise_op(ins
->op
.bitwise
, ins
->bitwise
.rshift
)
1093 RETURN_PACKED(pack
);
1097 bi_pack_fma_round(bi_instruction
*ins
, bi_registers
*regs
)
1099 bool fp16
= ins
->dest_type
== nir_type_float16
;
1100 assert(fp16
|| ins
->dest_type
== nir_type_float32
);
1103 ? BIFROST_FMA_ROUND_16(ins
->roundmode
, bi_swiz16(ins
, 0))
1104 : BIFROST_FMA_ROUND_32(ins
->roundmode
);
1106 return bi_pack_fma_1src(ins
, regs
, op
);
1110 bi_pack_fma_imath(bi_instruction
*ins
, bi_registers
*regs
)
1112 /* Scheduler: only ADD can have 8/16-bit imath */
1113 assert(ins
->dest_type
== nir_type_int32
|| ins
->dest_type
== nir_type_uint32
);
1115 unsigned op
= ins
->op
.imath
== BI_IMATH_ADD
1116 ? BIFROST_FMA_IADD_32
1117 : BIFROST_FMA_ISUB_32
;
1119 return bi_pack_fma_2src(ins
, regs
, op
);
1123 bi_pack_fma(bi_clause
*clause
, bi_bundle bundle
, bi_registers
*regs
)
1126 return BIFROST_FMA_NOP
;
1128 switch (bundle
.fma
->type
) {
1130 return bi_pack_fma_addmin(bundle
.fma
, regs
);
1132 return bi_pack_fma_cmp(bundle
.fma
, regs
);
1134 return bi_pack_fma_bitwise(bundle
.fma
, regs
);
1136 return bi_pack_convert(bundle
.fma
, regs
, true);
1138 return bi_pack_fma_csel(bundle
.fma
, regs
);
1140 return bi_pack_fma_fma(bundle
.fma
, regs
);
1142 return bi_pack_fma_frexp(bundle
.fma
, regs
);
1144 return bi_pack_fma_imath(bundle
.fma
, regs
);
1146 return bi_pack_fma_addmin(bundle
.fma
, regs
);
1148 return bi_pack_fma_1src(bundle
.fma
, regs
, BIFROST_FMA_OP_MOV
);
1150 unreachable("Packing todo");
1152 return bi_pack_fma_select(bundle
.fma
, regs
);
1154 return bi_pack_fma_round(bundle
.fma
, regs
);
1156 return bi_pack_fma_reduce(bundle
.fma
, regs
);
1158 unreachable("Cannot encode class as FMA");
1163 bi_pack_add_ld_vary(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
)
1165 unsigned size
= nir_alu_type_get_type_size(ins
->dest_type
);
1166 assert(size
== 32 || size
== 16);
1168 unsigned op
= (size
== 32) ?
1169 BIFROST_ADD_OP_LD_VAR_32
:
1170 BIFROST_ADD_OP_LD_VAR_16
;
1172 unsigned packed_addr
= 0;
1174 if (ins
->src
[0] & BIR_INDEX_CONSTANT
) {
1175 /* Direct uses address field directly */
1176 packed_addr
= bi_get_immediate(ins
, 0);
1178 /* Indirect gets an extra source */
1179 packed_addr
= bi_get_src(ins
, regs
, 0) | 0b11000;
1182 /* The destination is thrown in the data register */
1183 assert(ins
->dest
& BIR_INDEX_REGISTER
);
1184 clause
->data_register
= ins
->dest
& ~BIR_INDEX_REGISTER
;
1186 unsigned channels
= ins
->vector_channels
;
1187 assert(channels
>= 1 && channels
<= 4);
1189 struct bifrost_ld_var pack
= {
1190 .src0
= bi_get_src(ins
, regs
, 1),
1191 .addr
= packed_addr
,
1192 .channels
= MALI_POSITIVE(channels
),
1193 .interp_mode
= ins
->load_vary
.interp_mode
,
1194 .reuse
= ins
->load_vary
.reuse
,
1195 .flat
= ins
->load_vary
.flat
,
1199 RETURN_PACKED(pack
);
1203 bi_pack_add_2src(bi_instruction
*ins
, bi_registers
*regs
, unsigned op
)
1205 struct bifrost_add_2src pack
= {
1206 .src0
= bi_get_src(ins
, regs
, 0),
1207 .src1
= bi_get_src(ins
, regs
, 1),
1211 RETURN_PACKED(pack
);
1215 bi_pack_add_addmin_f32(bi_instruction
*ins
, bi_registers
*regs
)
1218 (ins
->type
== BI_ADD
) ? BIFROST_ADD_OP_FADD32
:
1219 (ins
->op
.minmax
== BI_MINMAX_MIN
) ? BIFROST_ADD_OP_FMIN32
:
1220 BIFROST_ADD_OP_FMAX32
;
1222 struct bifrost_add_faddmin pack
= {
1223 .src0
= bi_get_src(ins
, regs
, 0),
1224 .src1
= bi_get_src(ins
, regs
, 1),
1225 .src0_abs
= ins
->src_abs
[0],
1226 .src1_abs
= ins
->src_abs
[1],
1227 .src0_neg
= ins
->src_neg
[0],
1228 .src1_neg
= ins
->src_neg
[1],
1229 .outmod
= ins
->outmod
,
1230 .mode
= (ins
->type
== BI_ADD
) ? ins
->roundmode
: ins
->minmax
,
1234 RETURN_PACKED(pack
);
1238 bi_pack_add_add_f16(bi_instruction
*ins
, bi_registers
*regs
)
1240 /* ADD.v2f16 can't have outmod */
1241 assert(ins
->outmod
== BIFROST_NONE
);
1243 struct bifrost_add_faddmin pack
= {
1244 .src0
= bi_get_src(ins
, regs
, 0),
1245 .src1
= bi_get_src(ins
, regs
, 1),
1246 .src0_abs
= ins
->src_abs
[0],
1247 .src1_abs
= ins
->src_abs
[1],
1248 .src0_neg
= ins
->src_neg
[0],
1249 .src1_neg
= ins
->src_neg
[1],
1250 .select
= bi_swiz16(ins
, 0), /* swizzle_0 */
1251 .outmod
= bi_swiz16(ins
, 1), /* swizzle_1 */
1252 .mode
= ins
->roundmode
,
1253 .op
= BIFROST_ADD_OP_FADD16
1256 RETURN_PACKED(pack
);
1260 bi_pack_add_addmin(bi_instruction
*ins
, bi_registers
*regs
)
1262 if (ins
->dest_type
== nir_type_float32
)
1263 return bi_pack_add_addmin_f32(ins
, regs
);
1264 else if (ins
->dest_type
== nir_type_float16
) {
1265 if (ins
->type
== BI_ADD
)
1266 return bi_pack_add_add_f16(ins
, regs
);
1268 return bi_pack_fmadd_min_f16(ins
, regs
, false);
1270 unreachable("Unknown FMA/ADD type");
1274 bi_pack_add_ld_ubo(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
)
1276 assert(ins
->vector_channels
>= 1 && ins
->vector_channels
<= 4);
1278 const unsigned ops
[4] = {
1279 BIFROST_ADD_OP_LD_UBO_1
,
1280 BIFROST_ADD_OP_LD_UBO_2
,
1281 BIFROST_ADD_OP_LD_UBO_3
,
1282 BIFROST_ADD_OP_LD_UBO_4
1285 bi_write_data_register(clause
, ins
);
1286 return bi_pack_add_2src(ins
, regs
, ops
[ins
->vector_channels
- 1]);
1289 static enum bifrost_ldst_type
1290 bi_pack_ldst_type(nir_alu_type T
)
1293 case nir_type_float16
: return BIFROST_LDST_F16
;
1294 case nir_type_float32
: return BIFROST_LDST_F32
;
1295 case nir_type_int32
: return BIFROST_LDST_I32
;
1296 case nir_type_uint32
: return BIFROST_LDST_U32
;
1297 default: unreachable("Invalid type loaded");
1302 bi_pack_add_ld_var_addr(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
)
1304 struct bifrost_ld_var_addr pack
= {
1305 .src0
= bi_get_src(ins
, regs
, 1),
1306 .src1
= bi_get_src(ins
, regs
, 2),
1307 .location
= bi_get_immediate(ins
, 0),
1308 .type
= bi_pack_ldst_type(ins
->src_types
[3]),
1309 .op
= BIFROST_ADD_OP_LD_VAR_ADDR
1312 bi_write_data_register(clause
, ins
);
1313 RETURN_PACKED(pack
);
1317 bi_pack_add_ld_attr(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
)
1319 assert(ins
->vector_channels
>= 0 && ins
->vector_channels
<= 4);
1321 struct bifrost_ld_attr pack
= {
1322 .src0
= bi_get_src(ins
, regs
, 1),
1323 .src1
= bi_get_src(ins
, regs
, 2),
1324 .location
= bi_get_immediate(ins
, 0),
1325 .channels
= MALI_POSITIVE(ins
->vector_channels
),
1326 .type
= bi_pack_ldst_type(ins
->dest_type
),
1327 .op
= BIFROST_ADD_OP_LD_ATTR
1330 bi_write_data_register(clause
, ins
);
1331 RETURN_PACKED(pack
);
1335 bi_pack_add_st_vary(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
)
1337 assert(ins
->vector_channels
>= 1 && ins
->vector_channels
<= 4);
1339 struct bifrost_st_vary pack
= {
1340 .src0
= bi_get_src(ins
, regs
, 1),
1341 .src1
= bi_get_src(ins
, regs
, 2),
1342 .src2
= bi_get_src(ins
, regs
, 3),
1343 .channels
= MALI_POSITIVE(ins
->vector_channels
),
1344 .op
= BIFROST_ADD_OP_ST_VAR
1347 bi_read_data_register(clause
, ins
);
1348 RETURN_PACKED(pack
);
1352 bi_pack_add_atest(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
)
1354 bool fp16
= (ins
->src_types
[1] == nir_type_float16
);
1356 struct bifrost_add_atest pack
= {
1357 .src0
= bi_get_src(ins
, regs
, 0),
1358 .src1
= bi_get_src(ins
, regs
, 1),
1360 .component
= fp16
? ins
->swizzle
[1][0] : 1, /* Set for fp32 */
1361 .op
= BIFROST_ADD_OP_ATEST
,
1364 /* Despite *also* writing with the usual mechanism... quirky and
1365 * perhaps unnecessary, but let's match the blob */
1366 clause
->data_register
= ins
->dest
& ~BIR_INDEX_REGISTER
;
1368 RETURN_PACKED(pack
);
1372 bi_pack_add_blend(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
)
1374 struct bifrost_add_inst pack
= {
1375 .src0
= bi_get_src(ins
, regs
, 1),
1376 .op
= BIFROST_ADD_OP_BLEND
1379 /* TODO: Pack location in uniform_const */
1380 assert(ins
->blend_location
== 0);
1382 bi_read_data_register(clause
, ins
);
1383 RETURN_PACKED(pack
);
1387 bi_pack_add_special(bi_instruction
*ins
, bi_registers
*regs
)
1390 bool fp16
= ins
->dest_type
== nir_type_float16
;
1391 bool Y
= ins
->swizzle
[0][0];
1393 if (ins
->op
.special
== BI_SPECIAL_FRCP
) {
1395 (Y
? BIFROST_ADD_OP_FRCP_FAST_F16_Y
:
1396 BIFROST_ADD_OP_FRCP_FAST_F16_X
) :
1397 BIFROST_ADD_OP_FRCP_FAST_F32
;
1398 } else if (ins
->op
.special
== BI_SPECIAL_FRSQ
) {
1400 (Y
? BIFROST_ADD_OP_FRSQ_FAST_F16_Y
:
1401 BIFROST_ADD_OP_FRSQ_FAST_F16_X
) :
1402 BIFROST_ADD_OP_FRSQ_FAST_F32
;
1404 } else if (ins
->op
.special
== BI_SPECIAL_EXP2_LOW
) {
1406 op
= BIFROST_ADD_OP_FEXP2_FAST
;
1408 unreachable("Unknown special op");
1411 return bi_pack_add_1src(ins
, regs
, op
);
1415 bi_pack_add_table(bi_instruction
*ins
, bi_registers
*regs
)
1418 assert(ins
->dest_type
== nir_type_float32
);
1420 op
= BIFROST_ADD_OP_LOG2_HELP
;
1421 return bi_pack_add_1src(ins
, regs
, op
);
1424 bi_pack_add_tex_compact(bi_clause
*clause
, bi_instruction
*ins
, bi_registers
*regs
, gl_shader_stage stage
)
1426 bool f16
= ins
->dest_type
== nir_type_float16
;
1427 bool vtx
= stage
!= MESA_SHADER_FRAGMENT
;
1429 struct bifrost_tex_compact pack
= {
1430 .src0
= bi_get_src(ins
, regs
, 0),
1431 .src1
= bi_get_src(ins
, regs
, 1),
1432 .op
= f16
? BIFROST_ADD_OP_TEX_COMPACT_F16(vtx
) :
1433 BIFROST_ADD_OP_TEX_COMPACT_F32(vtx
),
1434 .compute_lod
= !vtx
,
1435 .tex_index
= ins
->texture
.texture_index
,
1436 .sampler_index
= ins
->texture
.sampler_index
1439 bi_write_data_register(clause
, ins
);
1440 RETURN_PACKED(pack
);
1444 bi_pack_add_select(bi_instruction
*ins
, bi_registers
*regs
)
1446 unsigned size
= nir_alu_type_get_type_size(ins
->src_types
[0]);
1449 unsigned swiz
= (ins
->swizzle
[0][0] | (ins
->swizzle
[1][0] << 1));
1450 unsigned op
= BIFROST_ADD_SEL_16(swiz
);
1451 return bi_pack_add_2src(ins
, regs
, op
);
1454 static enum bifrost_discard_cond
1455 bi_cond_to_discard(enum bi_cond cond
, bool *flip
)
1462 return BIFROST_DISCARD_FLT
;
1467 return BIFROST_DISCARD_FLE
;
1469 return BIFROST_DISCARD_FNE
;
1471 return BIFROST_DISCARD_FEQ
;
1473 unreachable("Invalid op for discard");
1478 bi_pack_add_discard(bi_instruction
*ins
, bi_registers
*regs
)
1480 bool fp16
= ins
->src_types
[0] == nir_type_float16
;
1481 assert(fp16
|| ins
->src_types
[0] == nir_type_float32
);
1484 enum bifrost_discard_cond cond
= bi_cond_to_discard(ins
->cond
, &flip
);
1486 struct bifrost_add_discard pack
= {
1487 .src0
= bi_get_src(ins
, regs
, flip
? 1 : 0),
1488 .src1
= bi_get_src(ins
, regs
, flip
? 0 : 1),
1490 .src0_select
= fp16
? ins
->swizzle
[0][0] : 0,
1491 .src1_select
= fp16
? ins
->swizzle
[1][0] : 0,
1492 .fp32
= fp16
? 0 : 1,
1493 .op
= BIFROST_ADD_OP_DISCARD
1496 RETURN_PACKED(pack
);
1499 static enum bifrost_icmp_cond
1500 bi_cond_to_icmp(enum bi_cond cond
, bool *flip
, bool is_unsigned
, bool is_16
)
1507 return is_unsigned
? (is_16
? BIFROST_ICMP_IGE
: BIFROST_ICMP_UGT
)
1513 return is_unsigned
? BIFROST_ICMP_UGE
:
1514 (is_16
? BIFROST_ICMP_UGT
: BIFROST_ICMP_IGE
);
1516 return BIFROST_ICMP_NEQ
;
1518 return BIFROST_ICMP_EQ
;
1520 unreachable("Invalid op for icmp");
1525 bi_pack_add_icmp32(bi_instruction
*ins
, bi_registers
*regs
, bool flip
,
1526 enum bifrost_icmp_cond cond
)
1528 struct bifrost_add_icmp pack
= {
1529 .src0
= bi_get_src(ins
, regs
, flip
? 1 : 0),
1530 .src1
= bi_get_src(ins
, regs
, flip
? 0 : 1),
1534 .op
= BIFROST_ADD_OP_ICMP_32
1537 RETURN_PACKED(pack
);
1541 bi_pack_add_icmp16(bi_instruction
*ins
, bi_registers
*regs
, bool flip
,
1542 enum bifrost_icmp_cond cond
)
1544 struct bifrost_add_icmp16 pack
= {
1545 .src0
= bi_get_src(ins
, regs
, flip
? 1 : 0),
1546 .src1
= bi_get_src(ins
, regs
, flip
? 0 : 1),
1547 .src0_swizzle
= bi_swiz16(ins
, flip
? 1 : 0),
1548 .src1_swizzle
= bi_swiz16(ins
, flip
? 0 : 1),
1551 .op
= BIFROST_ADD_OP_ICMP_16
1554 RETURN_PACKED(pack
);
1558 bi_pack_add_cmp(bi_instruction
*ins
, bi_registers
*regs
)
1560 nir_alu_type Tl
= ins
->src_types
[0];
1561 nir_alu_type Tr
= ins
->src_types
[1];
1562 nir_alu_type Bl
= nir_alu_type_get_base_type(Tl
);
1564 if (Bl
== nir_type_uint
|| Bl
== nir_type_int
) {
1566 unsigned sz
= nir_alu_type_get_type_size(Tl
);
1570 enum bifrost_icmp_cond cond
= bi_cond_to_icmp(
1571 sz
== 16 ? /*bi_invert_cond*/(ins
->cond
) : ins
->cond
,
1572 &flip
, Bl
== nir_type_uint
, sz
== 16);
1575 return bi_pack_add_icmp32(ins
, regs
, flip
, cond
);
1577 return bi_pack_add_icmp16(ins
, regs
, flip
, cond
);
1579 unreachable("TODO");
1581 unreachable("TODO");
1586 bi_pack_add_imath(bi_instruction
*ins
, bi_registers
*regs
)
1588 /* TODO: 32+16 add */
1589 assert(ins
->src_types
[0] == ins
->src_types
[1]);
1590 unsigned sz
= nir_alu_type_get_type_size(ins
->src_types
[0]);
1591 enum bi_imath_op p
= ins
->op
.imath
;
1596 op
= (p
== BI_IMATH_ADD
) ? BIFROST_ADD_IADD_8
:
1598 } else if (sz
== 16) {
1599 op
= (p
== BI_IMATH_ADD
) ? BIFROST_ADD_IADD_16
:
1600 BIFROST_ADD_ISUB_16
;
1601 } else if (sz
== 32) {
1602 op
= (p
== BI_IMATH_ADD
) ? BIFROST_ADD_IADD_32
:
1603 BIFROST_ADD_ISUB_32
;
1605 unreachable("64-bit todo");
1608 return bi_pack_add_2src(ins
, regs
, op
);
1612 bi_pack_add(bi_clause
*clause
, bi_bundle bundle
, bi_registers
*regs
, gl_shader_stage stage
)
1615 return BIFROST_ADD_NOP
;
1617 switch (bundle
.add
->type
) {
1619 return bi_pack_add_addmin(bundle
.add
, regs
);
1621 return bi_pack_add_atest(clause
, bundle
.add
, regs
);
1623 unreachable("Packing todo");
1625 return bi_pack_add_cmp(bundle
.add
, regs
);
1627 return bi_pack_add_blend(clause
, bundle
.add
, regs
);
1629 unreachable("Packing todo");
1631 return bi_pack_convert(bundle
.add
, regs
, false);
1633 return bi_pack_add_discard(bundle
.add
, regs
);
1635 unreachable("Packing todo");
1637 return bi_pack_add_imath(bundle
.add
, regs
);
1639 unreachable("Packing todo");
1641 return bi_pack_add_ld_attr(clause
, bundle
.add
, regs
);
1642 case BI_LOAD_UNIFORM
:
1643 return bi_pack_add_ld_ubo(clause
, bundle
.add
, regs
);
1645 return bi_pack_add_ld_vary(clause
, bundle
.add
, regs
);
1646 case BI_LOAD_VAR_ADDRESS
:
1647 return bi_pack_add_ld_var_addr(clause
, bundle
.add
, regs
);
1649 return bi_pack_add_addmin(bundle
.add
, regs
);
1653 unreachable("Packing todo");
1655 return bi_pack_add_st_vary(clause
, bundle
.add
, regs
);
1657 return bi_pack_add_special(bundle
.add
, regs
);
1659 return bi_pack_add_table(bundle
.add
, regs
);
1661 return bi_pack_add_select(bundle
.add
, regs
);
1663 if (bundle
.add
->op
.texture
== BI_TEX_COMPACT
)
1664 return bi_pack_add_tex_compact(clause
, bundle
.add
, regs
, stage
);
1666 unreachable("Unknown tex type");
1668 unreachable("Packing todo");
1670 unreachable("Cannot encode class as ADD");
1674 struct bi_packed_bundle
{
1679 static struct bi_packed_bundle
1680 bi_pack_bundle(bi_clause
*clause
, bi_bundle bundle
, bi_bundle prev
, bool first_bundle
, gl_shader_stage stage
)
1682 bi_assign_ports(&bundle
, &prev
);
1683 bi_assign_uniform_constant(clause
, &bundle
.regs
, bundle
);
1684 bundle
.regs
.first_instruction
= first_bundle
;
1686 uint64_t reg
= bi_pack_registers(bundle
.regs
);
1687 uint64_t fma
= bi_pack_fma(clause
, bundle
, &bundle
.regs
);
1688 uint64_t add
= bi_pack_add(clause
, bundle
, &bundle
.regs
, stage
);
1690 struct bi_packed_bundle packed
= {
1691 .lo
= reg
| (fma
<< 35) | ((add
& 0b111111) << 58),
1698 /* Packs the next two constants as a dedicated constant quadword at the end of
1699 * the clause, returning the number packed. */
1702 bi_pack_constants(bi_context
*ctx
, bi_clause
*clause
,
1704 struct util_dynarray
*emission
)
1706 /* After these two, are we done? Determines tag */
1707 bool done
= clause
->constant_count
<= (index
+ 2);
1708 bool only
= clause
->constant_count
<= (index
+ 1);
1711 assert(index
== 0 && clause
->bundle_count
== 1);
1714 uint64_t hi
= clause
->constants
[index
+ 0] >> 60ull;
1716 struct bifrost_fmt_constant quad
= {
1717 .pos
= 0, /* TODO */
1718 .tag
= done
? BIFROST_FMTC_FINAL
: BIFROST_FMTC_CONSTANTS
,
1719 .imm_1
= clause
->constants
[index
+ 0] >> 4,
1720 .imm_2
= ((hi
< 8) ? (hi
<< 60ull) : 0) >> 4,
1723 /* XXX: On G71, Connor observed that the difference of the top 4 bits
1724 * of the second constant with the first must be less than 8, otherwise
1725 * we have to swap them. On G52, I'm able to reproduce a similar issue
1726 * but with a different workaround (modeled above with a single
1727 * constant, unclear how to workaround for multiple constants.) Further
1728 * investigation needed. Possibly an errata. XXX */
1730 util_dynarray_append(emission
, struct bifrost_fmt_constant
, quad
);
1736 bi_pack_clause(bi_context
*ctx
, bi_clause
*clause
, bi_clause
*next
,
1737 struct util_dynarray
*emission
, gl_shader_stage stage
)
1739 struct bi_packed_bundle ins_1
= bi_pack_bundle(clause
, clause
->bundles
[0], clause
->bundles
[0], true, stage
);
1740 assert(clause
->bundle_count
== 1);
1742 /* Used to decide if we elide writes */
1743 bool is_fragment
= ctx
->stage
== MESA_SHADER_FRAGMENT
;
1745 /* State for packing constants throughout */
1746 unsigned constant_index
= 0;
1748 struct bifrost_fmt1 quad_1
= {
1749 .tag
= clause
->constant_count
? BIFROST_FMT1_CONSTANTS
: BIFROST_FMT1_FINAL
,
1750 .header
= bi_pack_header(clause
, next
, is_fragment
),
1752 .ins_2
= ins_1
.hi
& ((1 << 11) - 1),
1753 .ins_0
= (ins_1
.hi
>> 11) & 0b111,
1756 util_dynarray_append(emission
, struct bifrost_fmt1
, quad_1
);
1758 /* Pack the remaining constants */
1760 while (constant_index
< clause
->constant_count
) {
1761 constant_index
+= bi_pack_constants(ctx
, clause
,
1762 constant_index
, emission
);
1767 bi_next_clause(bi_context
*ctx
, pan_block
*block
, bi_clause
*clause
)
1769 /* Try the next clause in this block */
1770 if (clause
->link
.next
!= &((bi_block
*) block
)->clauses
)
1771 return list_first_entry(&(clause
->link
), bi_clause
, link
);
1773 /* Try the next block, or the one after that if it's empty, etc .*/
1774 pan_block
*next_block
= pan_next_block(block
);
1776 bi_foreach_block_from(ctx
, next_block
, block
) {
1777 bi_block
*blk
= (bi_block
*) block
;
1779 if (!list_is_empty(&blk
->clauses
))
1780 return list_first_entry(&(blk
->clauses
), bi_clause
, link
);
1787 bi_pack(bi_context
*ctx
, struct util_dynarray
*emission
)
1789 util_dynarray_init(emission
, NULL
);
1791 bi_foreach_block(ctx
, _block
) {
1792 bi_block
*block
= (bi_block
*) _block
;
1794 bi_foreach_clause_in_block(block
, clause
) {
1795 bi_clause
*next
= bi_next_clause(ctx
, _block
, clause
);
1796 bi_pack_clause(ctx
, clause
, next
, emission
, ctx
->stage
);