src/panfrost/bifrost/bi_schedule.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "compiler.h"
  28
  29 /* Finds the clause type required or return none */
  30
  31 static bool
  32 bi_is_fragz(bi_instruction *ins)
  33 {
  34         if (!(ins->src[0] & BIR_INDEX_CONSTANT))
  35                 return false;
  36
  37         return (ins->constant.u32 == BIFROST_FRAGZ);
  38 }
  39
  40 static enum bifrost_clause_type
  41 bi_clause_type_for_ins(bi_instruction *ins)
  42 {
  43         unsigned T = ins->type;
  44
  45         /* Only high latency ops impose clause types */
  46         if (!(bi_class_props[T] & BI_SCHED_HI_LATENCY))
  47                 return BIFROST_CLAUSE_NONE;
  48
  49         switch (T) {
  50         case BI_BRANCH:
  51         case BI_DISCARD:
  52                 return BIFROST_CLAUSE_NONE;
  53
  54         case BI_LOAD_VAR:
  55                 if (bi_is_fragz(ins))
  56                         return BIFROST_CLAUSE_FRAGZ;
  57
  58                 return BIFROST_CLAUSE_LOAD_VARY;
  59
  60         case BI_LOAD_UNIFORM:
  61         case BI_LOAD_ATTR:
  62         case BI_LOAD_VAR_ADDRESS:
  63                 return BIFROST_CLAUSE_UBO;
  64
  65         case BI_TEX:
  66                 return BIFROST_CLAUSE_TEX;
  67
  68         case BI_LOAD:
  69                 return BIFROST_CLAUSE_SSBO_LOAD;
  70
  71         case BI_STORE:
  72         case BI_STORE_VAR:
  73                 return BIFROST_CLAUSE_SSBO_STORE;
  74
  75         case BI_BLEND:
  76                 return BIFROST_CLAUSE_BLEND;
  77
  78         case BI_ATEST:
  79                 return BIFROST_CLAUSE_ATEST;
  80
  81         default:
  82                 unreachable("Invalid high-latency class");
  83         }
  84 }
  85
  86 /* There is an encoding restriction against FMA fp16 add/min/max
  87  * having both sources with abs(..) with a duplicated source. This is
  88  * due to the packing being order-sensitive, so the ports must end up distinct
  89  * to handle both having abs(..). The swizzle doesn't matter here. Note
  90  * BIR_INDEX_REGISTER generally should not be used pre-schedule (TODO: enforce
  91  * this).
  92  */
  93
  94 static bool
  95 bi_ambiguous_abs(bi_instruction *ins)
  96 {
  97         bool classy = bi_class_props[ins->type] & BI_NO_ABS_ABS_FP16_FMA;
  98         bool typey = ins->dest_type == nir_type_float16;
  99         bool absy = ins->src_abs[0] && ins->src_abs[1];
 100
 101         return classy && typey && absy;
 102 }
 103
 104 /* New Bifrost (which?) don't seem to have ICMP on FMA */
 105 static bool
 106 bi_icmp(bi_instruction *ins)
 107 {
 108         bool ic = nir_alu_type_get_base_type(ins->src_types[0]) != nir_type_float;
 109         return ic && (ins->type == BI_CMP);
 110 }
 111
 112 /* No 8/16-bit IADD/ISUB on FMA */
 113 static bool
 114 bi_imath_small(bi_instruction *ins)
 115 {
 116         bool sz = nir_alu_type_get_type_size(ins->src_types[0]) < 32;
 117         return sz && (ins->type == BI_IMATH);
 118 }
 119
 120 /* Lowers FMOV to ADD #0, since FMOV doesn't exist on the h/w and this is the
 121  * latest time it's sane to lower (it's useful to distinguish before, but we'll
 122  * need this handle during scheduling to ensure the ports get modeled
 123  * correctly with respect to the new zero source) */
 124
 125 static void
 126 bi_lower_fmov(bi_instruction *ins)
 127 {
 128         if (ins->type != BI_FMOV)
 129                 return;
 130
 131         ins->type = BI_ADD;
 132         ins->src[1] = BIR_INDEX_ZERO;
 133         ins->src_types[1] = ins->src_types[0];
 134 }
 135
 136 /* Eventually, we'll need a proper scheduling, grouping instructions
 137  * into clauses and ordering/assigning grouped instructions to the
 138  * appropriate FMA/ADD slots. Right now we do the dumbest possible
 139  * thing just to have the scheduler stubbed out so we can focus on
 140  * codegen */
 141
 142 void
 143 bi_schedule(bi_context *ctx)
 144 {
 145         unsigned ids = 0;
 146         unsigned last_id = 0;
 147         bool is_first = true;
 148
 149         bi_foreach_block(ctx, block) {
 150                 bi_block *bblock = (bi_block *) block;
 151
 152                 list_inithead(&bblock->clauses);
 153
 154                 bi_foreach_instr_in_block(bblock, ins) {
 155                         /* Convenient time to lower */
 156                         bi_lower_fmov(ins);
 157
 158                         unsigned props = bi_class_props[ins->type];
 159
 160                         bi_clause *u = rzalloc(ctx, bi_clause);
 161                         u->bundle_count = 1;
 162
 163                         /* Check for scheduling restrictions */
 164
 165                         bool can_fma = props & BI_SCHED_FMA;
 166                         bool can_add = props & BI_SCHED_ADD;
 167
 168                         can_fma &= !bi_ambiguous_abs(ins);
 169                         can_fma &= !bi_icmp(ins);
 170                         can_fma &= !bi_imath_small(ins);
 171
 172                         assert(can_fma || can_add);
 173
 174                         if (can_fma)
 175                                 u->bundles[0].fma = ins;
 176                         else
 177                                 u->bundles[0].add = ins;
 178
 179                         u->scoreboard_id = ids++;
 180
 181                         if (is_first)
 182                                 is_first = false;
 183                         else {
 184                                 /* Rule: first instructions cannot have write barriers */
 185                                 u->dependencies |= (1 << last_id);
 186                                 u->data_register_write_barrier = true;
 187                         }
 188
 189                         if (ins->type == BI_ATEST)
 190                                 u->dependencies |= (1 << 6);
 191
 192                         if (ins->type == BI_BLEND)
 193                                 u->dependencies |= (1 << 6) | (1 << 7);
 194
 195                         ids = ids & 1;
 196                         last_id = u->scoreboard_id;
 197                         u->back_to_back = false;
 198
 199                         u->constant_count = 1;
 200                         u->constants[0] = ins->constant.u64;
 201
 202                         /* No indirect jumps yet */
 203                         if (ins->type == BI_BRANCH)
 204                                 u->branch_constant = true;
 205
 206                         u->clause_type = bi_clause_type_for_ins(ins);
 207
 208                         list_addtail(&u->link, &bblock->clauses);
 209                 }
 210
 211                 bblock->scheduled = true;
 212         }
 213 }