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pan/bi: Fix branch condition typesize
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "util/u_debug.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "bifrost_nir.h"
36 #include "compiler.h"
37 #include "bi_quirks.h"
38 #include "bi_print.h"
39
40 static const struct debug_named_value debug_options[] = {
41 {"msgs", BIFROST_DBG_MSGS, "Print debug messages"},
42 {"shaders", BIFROST_DBG_SHADERS, "Dump shaders in NIR and MIR"},
43 DEBUG_NAMED_VALUE_END
44 };
45
46 DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug, "BIFROST_MESA_DEBUG", debug_options, 0)
47
48 int bifrost_debug = 0;
49
50 #define DBG(fmt, ...) \
51 do { if (bifrost_debug & BIFROST_DBG_MSGS) \
52 fprintf(stderr, "%s:%d: "fmt, \
53 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
54
55 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
56 static bi_instruction *bi_emit_branch(bi_context *ctx);
57
58 static void
59 emit_jump(bi_context *ctx, nir_jump_instr *instr)
60 {
61 bi_instruction *branch = bi_emit_branch(ctx);
62
63 switch (instr->type) {
64 case nir_jump_break:
65 branch->branch_target = ctx->break_block;
66 break;
67 case nir_jump_continue:
68 branch->branch_target = ctx->continue_block;
69 break;
70 default:
71 unreachable("Unhandled jump type");
72 }
73
74 pan_block_add_successor(&ctx->current_block->base, &branch->branch_target->base);
75 }
76
77 static bi_instruction
78 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
79 {
80 bi_instruction load = {
81 .type = T,
82 .vector_channels = instr->num_components,
83 .src = { BIR_INDEX_CONSTANT },
84 .src_types = { nir_type_uint32 },
85 .constant = { .u64 = nir_intrinsic_base(instr) },
86 };
87
88 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
89
90 if (info->has_dest)
91 load.dest = pan_dest_index(&instr->dest);
92
93 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
94 load.dest_type = nir_intrinsic_type(instr);
95
96 nir_src *offset = nir_get_io_offset_src(instr);
97
98 if (nir_src_is_const(*offset))
99 load.constant.u64 += nir_src_as_uint(*offset);
100 else
101 load.src[0] = pan_src_index(offset);
102
103 return load;
104 }
105
106 static void
107 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
108 {
109 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
110 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
111 ins.load_vary.reuse = false; /* TODO */
112 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
113 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
114
115 if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
116 /* Zero it out for direct */
117 ins.src[1] = BIR_INDEX_ZERO;
118 } else {
119 /* R61 contains sample mask stuff, TODO RA XXX */
120 ins.src[1] = BIR_INDEX_REGISTER | 61;
121 }
122
123 bi_emit(ctx, ins);
124 }
125
126 static void
127 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
128 {
129 if (!ctx->emitted_atest) {
130 bi_instruction ins = {
131 .type = BI_ATEST,
132 .src = {
133 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
134 pan_src_index(&instr->src[0])
135 },
136 .src_types = {
137 nir_type_uint32,
138 nir_intrinsic_type(instr)
139 },
140 .swizzle = {
141 { 0 },
142 { 3, 0 } /* swizzle out the alpha */
143 },
144 .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
145 .dest_type = nir_type_uint32,
146 };
147
148 bi_emit(ctx, ins);
149 ctx->emitted_atest = true;
150 }
151
152 bi_instruction blend = {
153 .type = BI_BLEND,
154 .blend_location = nir_intrinsic_base(instr),
155 .src = {
156 pan_src_index(&instr->src[0]),
157 BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
158 },
159 .src_types = {
160 nir_intrinsic_type(instr),
161 nir_type_uint32
162 },
163 .swizzle = {
164 { 0, 1, 2, 3 },
165 { 0 }
166 },
167 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
168 .dest_type = nir_type_uint32,
169 .vector_channels = 4
170 };
171
172 assert(blend.blend_location < BIFROST_MAX_RENDER_TARGET_COUNT);
173 assert(ctx->blend_types);
174 assert(blend.src_types[0]);
175 ctx->blend_types[blend.blend_location] = blend.src_types[0];
176
177 bi_emit(ctx, blend);
178 }
179
180 static bi_instruction
181 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
182 {
183 bi_instruction ld = bi_load(T, instr);
184 ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
185 ld.src[2] = BIR_INDEX_REGISTER | 62;
186 ld.src[3] = 0;
187 ld.src_types[1] = nir_type_uint32;
188 ld.src_types[2] = nir_type_uint32;
189 ld.src_types[3] = nir_intrinsic_type(instr);
190 return ld;
191 }
192
193 static void
194 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
195 {
196 bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
197 address.dest = bi_make_temp(ctx);
198 address.dest_type = nir_type_uint32;
199 address.vector_channels = 3;
200
201 unsigned nr = nir_intrinsic_src_components(instr, 0);
202 assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
203
204 bi_instruction st = {
205 .type = BI_STORE_VAR,
206 .src = {
207 pan_src_index(&instr->src[0]),
208 address.dest, address.dest, address.dest,
209 },
210 .src_types = {
211 nir_type_uint32,
212 nir_type_uint32, nir_type_uint32, nir_type_uint32,
213 },
214 .swizzle = {
215 { 0 },
216 { 0 }, { 1 }, { 2}
217 },
218 .vector_channels = nr,
219 };
220
221 for (unsigned i = 0; i < nr; ++i)
222 st.swizzle[0][i] = i;
223
224 bi_emit(ctx, address);
225 bi_emit(ctx, st);
226 }
227
228 static void
229 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
230 {
231 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
232 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
233
234 /* TODO: Indirect access, since we need to multiply by the element
235 * size. I believe we can get this lowering automatically via
236 * nir_lower_io (as mul instructions) with the proper options, but this
237 * is TODO */
238 assert(ld.src[0] & BIR_INDEX_CONSTANT);
239 ld.constant.u64 += ctx->sysvals.sysval_count;
240 ld.constant.u64 *= 16;
241
242 bi_emit(ctx, ld);
243 }
244
245 static void
246 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
247 unsigned nr_components, unsigned offset)
248 {
249 nir_dest nir_dest;
250
251 /* Figure out which uniform this is */
252 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
253 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
254
255 /* Sysvals are prefix uniforms */
256 unsigned uniform = ((uintptr_t) val) - 1;
257
258 /* Emit the read itself -- this is never indirect */
259
260 bi_instruction load = {
261 .type = BI_LOAD_UNIFORM,
262 .vector_channels = nr_components,
263 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
264 .src_types = { nir_type_uint32, nir_type_uint32 },
265 .constant = { (uniform * 16) + offset },
266 .dest = pan_dest_index(&nir_dest),
267 .dest_type = nir_type_uint32, /* TODO */
268 };
269
270 bi_emit(ctx, load);
271 }
272
273 /* gl_FragCoord.xy = u16_to_f32(R59.xy) + 0.5
274 * gl_FragCoord.z = ld_vary(fragz)
275 * gl_FragCoord.w = ld_vary(fragw)
276 */
277
278 static void
279 bi_emit_ld_frag_coord(bi_context *ctx, nir_intrinsic_instr *instr)
280 {
281 /* Future proofing for mediump fragcoord at some point.. */
282 nir_alu_type T = nir_type_float32;
283
284 /* First, sketch a combine */
285 bi_instruction combine = {
286 .type = BI_COMBINE,
287 .dest_type = nir_type_uint32,
288 .dest = pan_dest_index(&instr->dest),
289 .src_types = { T, T, T, T },
290 };
291
292 /* Second, handle xy */
293 for (unsigned i = 0; i < 2; ++i) {
294 bi_instruction conv = {
295 .type = BI_CONVERT,
296 .dest_type = T,
297 .dest = bi_make_temp(ctx),
298 .src = {
299 /* TODO: RA XXX */
300 BIR_INDEX_REGISTER | 59
301 },
302 .src_types = { nir_type_uint16 },
303 .swizzle = { { i } }
304 };
305
306 bi_instruction add = {
307 .type = BI_ADD,
308 .dest_type = T,
309 .dest = bi_make_temp(ctx),
310 .src = { conv.dest, BIR_INDEX_CONSTANT },
311 .src_types = { T, T },
312 };
313
314 float half = 0.5;
315 memcpy(&add.constant.u32, &half, sizeof(float));
316
317 bi_emit(ctx, conv);
318 bi_emit(ctx, add);
319
320 combine.src[i] = add.dest;
321 }
322
323 /* Third, zw */
324 for (unsigned i = 0; i < 2; ++i) {
325 bi_instruction load = {
326 .type = BI_LOAD_VAR,
327 .load_vary = {
328 .interp_mode = BIFROST_INTERP_DEFAULT,
329 .reuse = false,
330 .flat = true
331 },
332 .vector_channels = 1,
333 .dest_type = nir_type_float32,
334 .dest = bi_make_temp(ctx),
335 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
336 .src_types = { nir_type_uint32, nir_type_uint32 },
337 .constant = {
338 .u32 = (i == 0) ? BIFROST_FRAGZ : BIFROST_FRAGW
339 }
340 };
341
342 bi_emit(ctx, load);
343
344 combine.src[i + 2] = load.dest;
345 }
346
347 /* Finally, emit the combine */
348 bi_emit(ctx, combine);
349 }
350
351 static void
352 bi_emit_discard(bi_context *ctx, nir_intrinsic_instr *instr)
353 {
354 /* Goofy lowering */
355 bi_instruction discard = {
356 .type = BI_DISCARD,
357 .cond = BI_COND_EQ,
358 .src_types = { nir_type_uint32, nir_type_uint32 },
359 .src = { BIR_INDEX_ZERO, BIR_INDEX_ZERO },
360 };
361
362 bi_emit(ctx, discard);
363 }
364
365 static void
366 bi_fuse_cond(bi_instruction *csel, nir_alu_src cond,
367 unsigned *constants_left, unsigned *constant_shift,
368 unsigned comps, bool float_only);
369
370 static void
371 bi_emit_discard_if(bi_context *ctx, nir_intrinsic_instr *instr)
372 {
373 nir_src cond = instr->src[0];
374 nir_alu_type T = nir_type_uint | nir_src_bit_size(cond);
375
376 bi_instruction discard = {
377 .type = BI_DISCARD,
378 .cond = BI_COND_NE,
379 .src_types = { T, T },
380 .src = {
381 pan_src_index(&cond),
382 BIR_INDEX_ZERO
383 },
384 };
385
386 /* Try to fuse in the condition */
387 unsigned constants_left = 1, constant_shift = 0;
388
389 /* Scalar so no swizzle */
390 nir_alu_src wrap = {
391 .src = instr->src[0]
392 };
393
394 /* May or may not succeed but we're optimistic */
395 bi_fuse_cond(&discard, wrap, &constants_left, &constant_shift, 1, true);
396
397 bi_emit(ctx, discard);
398 }
399
400 static void
401 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
402 {
403
404 switch (instr->intrinsic) {
405 case nir_intrinsic_load_barycentric_pixel:
406 /* stub */
407 break;
408 case nir_intrinsic_load_interpolated_input:
409 case nir_intrinsic_load_input:
410 if (ctx->stage == MESA_SHADER_FRAGMENT)
411 bi_emit_ld_vary(ctx, instr);
412 else if (ctx->stage == MESA_SHADER_VERTEX)
413 bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
414 else {
415 unreachable("Unsupported shader stage");
416 }
417 break;
418
419 case nir_intrinsic_store_output:
420 if (ctx->stage == MESA_SHADER_FRAGMENT)
421 bi_emit_frag_out(ctx, instr);
422 else if (ctx->stage == MESA_SHADER_VERTEX)
423 bi_emit_st_vary(ctx, instr);
424 else
425 unreachable("Unsupported shader stage");
426 break;
427
428 case nir_intrinsic_load_uniform:
429 bi_emit_ld_uniform(ctx, instr);
430 break;
431
432 case nir_intrinsic_load_frag_coord:
433 bi_emit_ld_frag_coord(ctx, instr);
434 break;
435
436 case nir_intrinsic_discard:
437 bi_emit_discard(ctx, instr);
438 break;
439
440 case nir_intrinsic_discard_if:
441 bi_emit_discard_if(ctx, instr);
442 break;
443
444 case nir_intrinsic_load_ssbo_address:
445 bi_emit_sysval(ctx, &instr->instr, 1, 0);
446 break;
447
448 case nir_intrinsic_get_buffer_size:
449 bi_emit_sysval(ctx, &instr->instr, 1, 8);
450 break;
451
452 case nir_intrinsic_load_viewport_scale:
453 case nir_intrinsic_load_viewport_offset:
454 case nir_intrinsic_load_num_work_groups:
455 case nir_intrinsic_load_sampler_lod_parameters_pan:
456 bi_emit_sysval(ctx, &instr->instr, 3, 0);
457 break;
458
459 default:
460 unreachable("Unknown intrinsic");
461 break;
462 }
463 }
464
465 static void
466 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
467 {
468 /* Make sure we've been lowered */
469 assert(instr->def.num_components == 1);
470
471 bi_instruction move = {
472 .type = BI_MOV,
473 .dest = pan_ssa_index(&instr->def),
474 .dest_type = instr->def.bit_size | nir_type_uint,
475 .src = {
476 BIR_INDEX_CONSTANT
477 },
478 .src_types = {
479 instr->def.bit_size | nir_type_uint,
480 },
481 .constant = {
482 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
483 }
484 };
485
486 bi_emit(ctx, move);
487 }
488
489 #define BI_CASE_CMP(op) \
490 case op##8: \
491 case op##16: \
492 case op##32: \
493
494 static enum bi_class
495 bi_class_for_nir_alu(nir_op op)
496 {
497 switch (op) {
498 case nir_op_fadd:
499 case nir_op_fsub:
500 return BI_ADD;
501
502 case nir_op_iadd:
503 case nir_op_isub:
504 return BI_IMATH;
505
506 case nir_op_iand:
507 case nir_op_ior:
508 case nir_op_ixor:
509 return BI_BITWISE;
510
511 BI_CASE_CMP(nir_op_flt)
512 BI_CASE_CMP(nir_op_fge)
513 BI_CASE_CMP(nir_op_feq)
514 BI_CASE_CMP(nir_op_fne)
515 BI_CASE_CMP(nir_op_ilt)
516 BI_CASE_CMP(nir_op_ige)
517 BI_CASE_CMP(nir_op_ieq)
518 BI_CASE_CMP(nir_op_ine)
519 return BI_CMP;
520
521 case nir_op_b8csel:
522 case nir_op_b16csel:
523 case nir_op_b32csel:
524 return BI_CSEL;
525
526 case nir_op_i2i8:
527 case nir_op_i2i16:
528 case nir_op_i2i32:
529 case nir_op_i2i64:
530 case nir_op_u2u8:
531 case nir_op_u2u16:
532 case nir_op_u2u32:
533 case nir_op_u2u64:
534 case nir_op_f2i16:
535 case nir_op_f2i32:
536 case nir_op_f2i64:
537 case nir_op_f2u16:
538 case nir_op_f2u32:
539 case nir_op_f2u64:
540 case nir_op_i2f16:
541 case nir_op_i2f32:
542 case nir_op_i2f64:
543 case nir_op_u2f16:
544 case nir_op_u2f32:
545 case nir_op_u2f64:
546 case nir_op_f2f16:
547 case nir_op_f2f32:
548 case nir_op_f2f64:
549 case nir_op_f2fmp:
550 return BI_CONVERT;
551
552 case nir_op_vec2:
553 case nir_op_vec3:
554 case nir_op_vec4:
555 return BI_COMBINE;
556
557 case nir_op_vec8:
558 case nir_op_vec16:
559 unreachable("should've been lowered");
560
561 case nir_op_ffma:
562 case nir_op_fmul:
563 return BI_FMA;
564
565 case nir_op_imin:
566 case nir_op_imax:
567 case nir_op_umin:
568 case nir_op_umax:
569 case nir_op_fmin:
570 case nir_op_fmax:
571 return BI_MINMAX;
572
573 case nir_op_fsat:
574 case nir_op_fneg:
575 case nir_op_fabs:
576 return BI_FMOV;
577 case nir_op_mov:
578 return BI_MOV;
579
580 case nir_op_fround_even:
581 case nir_op_fceil:
582 case nir_op_ffloor:
583 case nir_op_ftrunc:
584 return BI_ROUND;
585
586 case nir_op_frcp:
587 case nir_op_frsq:
588 return BI_SPECIAL;
589
590 default:
591 unreachable("Unknown ALU op");
592 }
593 }
594
595 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
596 * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
597 * optimizations). Otherwise it will bail (when used for primary code
598 * generation). */
599
600 static enum bi_cond
601 bi_cond_for_nir(nir_op op, bool soft)
602 {
603 switch (op) {
604 BI_CASE_CMP(nir_op_flt)
605 BI_CASE_CMP(nir_op_ilt)
606 return BI_COND_LT;
607
608 BI_CASE_CMP(nir_op_fge)
609 BI_CASE_CMP(nir_op_ige)
610 return BI_COND_GE;
611
612 BI_CASE_CMP(nir_op_feq)
613 BI_CASE_CMP(nir_op_ieq)
614 return BI_COND_EQ;
615
616 BI_CASE_CMP(nir_op_fne)
617 BI_CASE_CMP(nir_op_ine)
618 return BI_COND_NE;
619 default:
620 if (soft)
621 return BI_COND_ALWAYS;
622 else
623 unreachable("Invalid compare");
624 }
625 }
626
627 static void
628 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
629 unsigned *constants_left, unsigned *constant_shift, unsigned comps)
630 {
631 unsigned bits = nir_src_bit_size(instr->src[i].src);
632 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
633
634 alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
635 | bits;
636
637 /* Try to inline a constant */
638 if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
639 uint64_t mask = (1ull << dest_bits) - 1;
640 uint64_t cons = nir_src_as_uint(instr->src[i].src);
641
642 /* Try to reuse a constant */
643 for (unsigned i = 0; i < (*constant_shift); i += dest_bits) {
644 if (((alu->constant.u64 >> i) & mask) == cons) {
645 alu->src[to] = BIR_INDEX_CONSTANT | i;
646 return;
647 }
648 }
649
650 alu->constant.u64 |= cons << *constant_shift;
651 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
652 --(*constants_left);
653 (*constant_shift) += MAX2(dest_bits, 32); /* lo/hi */
654 return;
655 }
656
657 alu->src[to] = pan_src_index(&instr->src[i].src);
658
659 /* Copy swizzle for all vectored components, replicating last component
660 * to fill undersized */
661
662 unsigned vec = alu->type == BI_COMBINE ? 1 :
663 MAX2(1, 32 / dest_bits);
664
665 for (unsigned j = 0; j < vec; ++j)
666 alu->swizzle[to][j] = instr->src[i].swizzle[MIN2(j, comps - 1)];
667 }
668
669 static void
670 bi_fuse_cond(bi_instruction *csel, nir_alu_src cond,
671 unsigned *constants_left, unsigned *constant_shift,
672 unsigned comps, bool float_only)
673 {
674 /* Bail for vector weirdness */
675 if (cond.swizzle[0] != 0)
676 return;
677
678 if (!cond.src.is_ssa)
679 return;
680
681 nir_ssa_def *def = cond.src.ssa;
682 nir_instr *parent = def->parent_instr;
683
684 if (parent->type != nir_instr_type_alu)
685 return;
686
687 nir_alu_instr *alu = nir_instr_as_alu(parent);
688
689 /* Try to match a condition */
690 enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
691
692 if (bcond == BI_COND_ALWAYS)
693 return;
694
695 /* Some instructions can't compare ints */
696 if (float_only) {
697 nir_alu_type T = nir_op_infos[alu->op].input_types[0];
698 T = nir_alu_type_get_base_type(T);
699
700 if (T != nir_type_float)
701 return;
702 }
703
704 /* We found one, let's fuse it in */
705 csel->cond = bcond;
706 bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift, comps);
707 bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift, comps);
708 }
709
710 static void
711 emit_alu(bi_context *ctx, nir_alu_instr *instr)
712 {
713 /* Try some special functions */
714 switch (instr->op) {
715 case nir_op_fexp2:
716 bi_emit_fexp2(ctx, instr);
717 return;
718 case nir_op_flog2:
719 bi_emit_flog2(ctx, instr);
720 return;
721 default:
722 break;
723 }
724
725 /* Otherwise, assume it's something we can handle normally */
726 bi_instruction alu = {
727 .type = bi_class_for_nir_alu(instr->op),
728 .dest = pan_dest_index(&instr->dest.dest),
729 .dest_type = nir_op_infos[instr->op].output_type
730 | nir_dest_bit_size(instr->dest.dest),
731 };
732
733 /* TODO: Implement lowering of special functions for older Bifrost */
734 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
735
736 unsigned comps = nir_dest_num_components(instr->dest.dest);
737
738 if (alu.type != BI_COMBINE)
739 assert(comps <= MAX2(1, 32 / comps));
740
741 if (!instr->dest.dest.is_ssa) {
742 for (unsigned i = 0; i < comps; ++i)
743 assert(instr->dest.write_mask);
744 }
745
746 /* We inline constants as we go. This tracks how many constants have
747 * been inlined, since we're limited to 64-bits of constants per
748 * instruction */
749
750 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
751 unsigned constants_left = (64 / dest_bits);
752 unsigned constant_shift = 0;
753
754 if (alu.type == BI_COMBINE)
755 constants_left = 0;
756
757 /* Copy sources */
758
759 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
760 assert(num_inputs <= ARRAY_SIZE(alu.src));
761
762 for (unsigned i = 0; i < num_inputs; ++i) {
763 unsigned f = 0;
764
765 if (i && alu.type == BI_CSEL)
766 f++;
767
768 bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift, comps);
769 }
770
771 /* Op-specific fixup */
772 switch (instr->op) {
773 case nir_op_fmul:
774 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
775 alu.src_types[2] = alu.src_types[1];
776 break;
777 case nir_op_fsat:
778 alu.outmod = BIFROST_SAT; /* FMOV */
779 break;
780 case nir_op_fneg:
781 alu.src_neg[0] = true; /* FMOV */
782 break;
783 case nir_op_fabs:
784 alu.src_abs[0] = true; /* FMOV */
785 break;
786 case nir_op_fsub:
787 alu.src_neg[1] = true; /* FADD */
788 break;
789 case nir_op_iadd:
790 alu.op.imath = BI_IMATH_ADD;
791 break;
792 case nir_op_isub:
793 alu.op.imath = BI_IMATH_SUB;
794 break;
795 case nir_op_fmax:
796 case nir_op_imax:
797 case nir_op_umax:
798 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
799 break;
800 case nir_op_frcp:
801 alu.op.special = BI_SPECIAL_FRCP;
802 break;
803 case nir_op_frsq:
804 alu.op.special = BI_SPECIAL_FRSQ;
805 break;
806 BI_CASE_CMP(nir_op_flt)
807 BI_CASE_CMP(nir_op_ilt)
808 BI_CASE_CMP(nir_op_fge)
809 BI_CASE_CMP(nir_op_ige)
810 BI_CASE_CMP(nir_op_feq)
811 BI_CASE_CMP(nir_op_ieq)
812 BI_CASE_CMP(nir_op_fne)
813 BI_CASE_CMP(nir_op_ine)
814 alu.cond = bi_cond_for_nir(instr->op, false);
815 break;
816 case nir_op_fround_even:
817 alu.roundmode = BIFROST_RTE;
818 break;
819 case nir_op_fceil:
820 alu.roundmode = BIFROST_RTP;
821 break;
822 case nir_op_ffloor:
823 alu.roundmode = BIFROST_RTN;
824 break;
825 case nir_op_ftrunc:
826 alu.roundmode = BIFROST_RTZ;
827 break;
828 case nir_op_iand:
829 alu.op.bitwise = BI_BITWISE_AND;
830 break;
831 case nir_op_ior:
832 alu.op.bitwise = BI_BITWISE_OR;
833 break;
834 case nir_op_ixor:
835 alu.op.bitwise = BI_BITWISE_XOR;
836 break;
837 default:
838 break;
839 }
840
841 if (alu.type == BI_CSEL) {
842 /* Default to csel3 */
843 alu.cond = BI_COND_NE;
844 alu.src[1] = BIR_INDEX_ZERO;
845 alu.src_types[1] = alu.src_types[0];
846
847 /* TODO: Reenable cond fusing when we can split up registers
848 * when scheduling */
849 #if 0
850 bi_fuse_cond(&alu, instr->src[0],
851 &constants_left, &constant_shift, comps, false);
852 #endif
853 } else if (alu.type == BI_BITWISE) {
854 /* Implicit shift argument... at some point we should fold */
855 alu.src[2] = BIR_INDEX_ZERO;
856 alu.src_types[2] = alu.src_types[1];
857 }
858
859 bi_emit(ctx, alu);
860 }
861
862 /* TEX_COMPACT instructions assume normal 2D f32 operation but are more
863 * space-efficient and with simpler RA/scheduling requirements*/
864
865 static void
866 emit_tex_compact(bi_context *ctx, nir_tex_instr *instr)
867 {
868 bi_instruction tex = {
869 .type = BI_TEX,
870 .op = { .texture = BI_TEX_COMPACT },
871 .texture = {
872 .texture_index = instr->texture_index,
873 .sampler_index = instr->sampler_index,
874 },
875 .dest = pan_dest_index(&instr->dest),
876 .dest_type = instr->dest_type,
877 .src_types = { nir_type_float32, nir_type_float32 },
878 .vector_channels = 4
879 };
880
881 for (unsigned i = 0; i < instr->num_srcs; ++i) {
882 int index = pan_src_index(&instr->src[i].src);
883
884 /* We were checked ahead-of-time */
885 if (instr->src[i].src_type == nir_tex_src_lod)
886 continue;
887
888 assert (instr->src[i].src_type == nir_tex_src_coord);
889
890 tex.src[0] = index;
891 tex.src[1] = index;
892 tex.swizzle[0][0] = 0;
893 tex.swizzle[1][0] = 1;
894 }
895
896 bi_emit(ctx, tex);
897 }
898
899 static void
900 emit_tex_full(bi_context *ctx, nir_tex_instr *instr)
901 {
902 unreachable("stub");
903 }
904
905 /* Normal textures ops are tex for frag shaders and txl for vertex shaders with
906 * lod a constant 0. Anything else needs a full texture op. */
907
908 static bool
909 bi_is_normal_tex(gl_shader_stage stage, nir_tex_instr *instr)
910 {
911 if (stage == MESA_SHADER_FRAGMENT)
912 return instr->op == nir_texop_tex;
913
914 if (instr->op != nir_texop_txl)
915 return false;
916
917 for (unsigned i = 0; i < instr->num_srcs; ++i) {
918 if (instr->src[i].src_type != nir_tex_src_lod)
919 continue;
920
921 nir_src src = instr->src[i].src;
922
923 if (!nir_src_is_const(src))
924 continue;
925
926 if (nir_src_as_uint(src) != 0)
927 continue;
928 }
929
930 return true;
931 }
932
933 static void
934 emit_tex(bi_context *ctx, nir_tex_instr *instr)
935 {
936 nir_alu_type base = nir_alu_type_get_base_type(instr->dest_type);
937 unsigned sz = nir_dest_bit_size(instr->dest);
938 instr->dest_type = base | sz;
939
940 bool is_normal = bi_is_normal_tex(ctx->stage, instr);
941 bool is_2d = instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
942 instr->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL;
943 bool is_f = base == nir_type_float && (sz == 16 || sz == 32);
944
945 bool is_compact = is_normal && is_2d && is_f && !instr->is_shadow;
946
947 if (is_compact)
948 emit_tex_compact(ctx, instr);
949 else
950 emit_tex_full(ctx, instr);
951 }
952
953 static void
954 emit_instr(bi_context *ctx, struct nir_instr *instr)
955 {
956 switch (instr->type) {
957 case nir_instr_type_load_const:
958 emit_load_const(ctx, nir_instr_as_load_const(instr));
959 break;
960
961 case nir_instr_type_intrinsic:
962 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
963 break;
964
965 case nir_instr_type_alu:
966 emit_alu(ctx, nir_instr_as_alu(instr));
967 break;
968
969 case nir_instr_type_tex:
970 emit_tex(ctx, nir_instr_as_tex(instr));
971 break;
972
973 case nir_instr_type_jump:
974 emit_jump(ctx, nir_instr_as_jump(instr));
975 break;
976
977 case nir_instr_type_ssa_undef:
978 /* Spurious */
979 break;
980
981 default:
982 unreachable("Unhandled instruction type");
983 break;
984 }
985 }
986
987
988
989 static bi_block *
990 create_empty_block(bi_context *ctx)
991 {
992 bi_block *blk = rzalloc(ctx, bi_block);
993
994 blk->base.predecessors = _mesa_set_create(blk,
995 _mesa_hash_pointer,
996 _mesa_key_pointer_equal);
997
998 blk->base.name = ctx->block_name_count++;
999
1000 return blk;
1001 }
1002
1003 static bi_block *
1004 emit_block(bi_context *ctx, nir_block *block)
1005 {
1006 if (ctx->after_block) {
1007 ctx->current_block = ctx->after_block;
1008 ctx->after_block = NULL;
1009 } else {
1010 ctx->current_block = create_empty_block(ctx);
1011 }
1012
1013 list_addtail(&ctx->current_block->base.link, &ctx->blocks);
1014 list_inithead(&ctx->current_block->base.instructions);
1015
1016 nir_foreach_instr(instr, block) {
1017 emit_instr(ctx, instr);
1018 ++ctx->instruction_count;
1019 }
1020
1021 return ctx->current_block;
1022 }
1023
1024 /* Emits an unconditional branch to the end of the current block, returning a
1025 * pointer so the user can fill in details */
1026
1027 static bi_instruction *
1028 bi_emit_branch(bi_context *ctx)
1029 {
1030 bi_instruction branch = {
1031 .type = BI_BRANCH,
1032 .cond = BI_COND_ALWAYS
1033 };
1034
1035 return bi_emit(ctx, branch);
1036 }
1037
1038 /* Sets a condition for a branch by examing the NIR condition. If we're
1039 * familiar with the condition, we unwrap it to fold it into the branch
1040 * instruction. Otherwise, we consume the condition directly. We
1041 * generally use 1-bit booleans which allows us to use small types for
1042 * the conditions.
1043 */
1044
1045 static void
1046 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
1047 {
1048 /* TODO: Try to unwrap instead of always bailing */
1049 branch->src[0] = pan_src_index(cond);
1050 branch->src[1] = BIR_INDEX_ZERO;
1051 branch->src_types[0] = branch->src_types[1] = nir_type_uint |
1052 nir_src_bit_size(*cond);
1053 branch->cond = invert ? BI_COND_EQ : BI_COND_NE;
1054 }
1055
1056 static void
1057 emit_if(bi_context *ctx, nir_if *nif)
1058 {
1059 bi_block *before_block = ctx->current_block;
1060
1061 /* Speculatively emit the branch, but we can't fill it in until later */
1062 bi_instruction *then_branch = bi_emit_branch(ctx);
1063 bi_set_branch_cond(then_branch, &nif->condition, true);
1064
1065 /* Emit the two subblocks. */
1066 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
1067 bi_block *end_then_block = ctx->current_block;
1068
1069 /* Emit a jump from the end of the then block to the end of the else */
1070 bi_instruction *then_exit = bi_emit_branch(ctx);
1071
1072 /* Emit second block, and check if it's empty */
1073
1074 int count_in = ctx->instruction_count;
1075 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
1076 bi_block *end_else_block = ctx->current_block;
1077 ctx->after_block = create_empty_block(ctx);
1078
1079 /* Now that we have the subblocks emitted, fix up the branches */
1080
1081 assert(then_block);
1082 assert(else_block);
1083
1084 if (ctx->instruction_count == count_in) {
1085 /* The else block is empty, so don't emit an exit jump */
1086 bi_remove_instruction(then_exit);
1087 then_branch->branch_target = ctx->after_block;
1088 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base); /* fallthrough */
1089 } else {
1090 then_branch->branch_target = else_block;
1091 then_exit->branch_target = ctx->after_block;
1092 pan_block_add_successor(&end_then_block->base, &then_exit->branch_target->base);
1093 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
1094 }
1095
1096 pan_block_add_successor(&before_block->base, &then_branch->branch_target->base); /* then_branch */
1097 pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
1098 }
1099
1100 static void
1101 emit_loop(bi_context *ctx, nir_loop *nloop)
1102 {
1103 /* Remember where we are */
1104 bi_block *start_block = ctx->current_block;
1105
1106 bi_block *saved_break = ctx->break_block;
1107 bi_block *saved_continue = ctx->continue_block;
1108
1109 ctx->continue_block = create_empty_block(ctx);
1110 ctx->break_block = create_empty_block(ctx);
1111 ctx->after_block = ctx->continue_block;
1112
1113 /* Emit the body itself */
1114 emit_cf_list(ctx, &nloop->body);
1115
1116 /* Branch back to loop back */
1117 bi_instruction *br_back = bi_emit_branch(ctx);
1118 br_back->branch_target = ctx->continue_block;
1119 pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
1120 pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
1121
1122 ctx->after_block = ctx->break_block;
1123
1124 /* Pop off */
1125 ctx->break_block = saved_break;
1126 ctx->continue_block = saved_continue;
1127 ++ctx->loop_count;
1128 }
1129
1130 static bi_block *
1131 emit_cf_list(bi_context *ctx, struct exec_list *list)
1132 {
1133 bi_block *start_block = NULL;
1134
1135 foreach_list_typed(nir_cf_node, node, node, list) {
1136 switch (node->type) {
1137 case nir_cf_node_block: {
1138 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
1139
1140 if (!start_block)
1141 start_block = block;
1142
1143 break;
1144 }
1145
1146 case nir_cf_node_if:
1147 emit_if(ctx, nir_cf_node_as_if(node));
1148 break;
1149
1150 case nir_cf_node_loop:
1151 emit_loop(ctx, nir_cf_node_as_loop(node));
1152 break;
1153
1154 default:
1155 unreachable("Unknown control flow");
1156 }
1157 }
1158
1159 return start_block;
1160 }
1161
1162 static int
1163 glsl_type_size(const struct glsl_type *type, bool bindless)
1164 {
1165 return glsl_count_attribute_slots(type, false);
1166 }
1167
1168 static void
1169 bi_optimize_nir(nir_shader *nir)
1170 {
1171 bool progress;
1172 unsigned lower_flrp = 16 | 32 | 64;
1173
1174 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
1175 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
1176
1177 nir_lower_tex_options lower_tex_options = {
1178 .lower_txs_lod = true,
1179 .lower_txp = ~0,
1180 .lower_tex_without_implicit_lod = true,
1181 .lower_txd = true,
1182 };
1183
1184 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
1185 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1186 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1187
1188 do {
1189 progress = false;
1190
1191 NIR_PASS(progress, nir, nir_lower_var_copies);
1192 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
1193
1194 NIR_PASS(progress, nir, nir_copy_prop);
1195 NIR_PASS(progress, nir, nir_opt_remove_phis);
1196 NIR_PASS(progress, nir, nir_opt_dce);
1197 NIR_PASS(progress, nir, nir_opt_dead_cf);
1198 NIR_PASS(progress, nir, nir_opt_cse);
1199 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
1200 NIR_PASS(progress, nir, nir_opt_algebraic);
1201 NIR_PASS(progress, nir, nir_opt_constant_folding);
1202
1203 if (lower_flrp != 0) {
1204 bool lower_flrp_progress = false;
1205 NIR_PASS(lower_flrp_progress,
1206 nir,
1207 nir_lower_flrp,
1208 lower_flrp,
1209 false /* always_precise */,
1210 nir->options->lower_ffma);
1211 if (lower_flrp_progress) {
1212 NIR_PASS(progress, nir,
1213 nir_opt_constant_folding);
1214 progress = true;
1215 }
1216
1217 /* Nothing should rematerialize any flrps, so we only
1218 * need to do this lowering once.
1219 */
1220 lower_flrp = 0;
1221 }
1222
1223 NIR_PASS(progress, nir, nir_opt_undef);
1224 NIR_PASS(progress, nir, nir_opt_loop_unroll,
1225 nir_var_shader_in |
1226 nir_var_shader_out |
1227 nir_var_function_temp);
1228 } while (progress);
1229
1230 NIR_PASS(progress, nir, nir_opt_algebraic_late);
1231 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
1232 NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
1233 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1234 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1235
1236 /* Take us out of SSA */
1237 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
1238 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
1239 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
1240 }
1241
1242 void
1243 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
1244 {
1245 bifrost_debug = debug_get_option_bifrost_debug();
1246
1247 bi_context *ctx = rzalloc(NULL, bi_context);
1248 ctx->nir = nir;
1249 ctx->stage = nir->info.stage;
1250 ctx->quirks = bifrost_get_quirks(product_id);
1251 list_inithead(&ctx->blocks);
1252
1253 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
1254 * (so we don't accidentally duplicate the epilogue since mesa/st has
1255 * messed with our I/O quite a bit already) */
1256
1257 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1258
1259 if (ctx->stage == MESA_SHADER_VERTEX) {
1260 NIR_PASS_V(nir, nir_lower_viewport_transform);
1261 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
1262 }
1263
1264 NIR_PASS_V(nir, nir_split_var_copies);
1265 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
1266 NIR_PASS_V(nir, nir_lower_var_copies);
1267 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1268 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
1269 NIR_PASS_V(nir, nir_lower_ssbo);
1270 NIR_PASS_V(nir, nir_lower_mediump_outputs);
1271
1272 bi_optimize_nir(nir);
1273
1274 if (bifrost_debug & BIFROST_DBG_SHADERS) {
1275 nir_print_shader(nir, stdout);
1276 }
1277
1278 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
1279 program->sysval_count = ctx->sysvals.sysval_count;
1280 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
1281 ctx->blend_types = program->blend_types;
1282
1283 nir_foreach_function(func, nir) {
1284 if (!func->impl)
1285 continue;
1286
1287 ctx->impl = func->impl;
1288 emit_cf_list(ctx, &func->impl->body);
1289 break; /* TODO: Multi-function shaders */
1290 }
1291
1292 bi_foreach_block(ctx, _block) {
1293 bi_block *block = (bi_block *) _block;
1294 bi_lower_combine(ctx, block);
1295 }
1296
1297 bool progress = false;
1298
1299 do {
1300 progress = false;
1301
1302 bi_foreach_block(ctx, _block) {
1303 bi_block *block = (bi_block *) _block;
1304 progress |= bi_opt_dead_code_eliminate(ctx, block);
1305 }
1306 } while(progress);
1307
1308 if (bifrost_debug & BIFROST_DBG_SHADERS)
1309 bi_print_shader(ctx, stdout);
1310 bi_schedule(ctx);
1311 bi_register_allocate(ctx);
1312 if (bifrost_debug & BIFROST_DBG_SHADERS)
1313 bi_print_shader(ctx, stdout);
1314 bi_pack(ctx, &program->compiled);
1315
1316 if (bifrost_debug & BIFROST_DBG_SHADERS)
1317 disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1318
1319 ralloc_free(ctx);
1320 }