ed8741ddb5a5eb07d4098942eb5a0f6275229b05
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "util/u_debug.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "bifrost_nir.h"
36 #include "compiler.h"
37 #include "bi_quirks.h"
38 #include "bi_print.h"
39
40 static const struct debug_named_value debug_options[] = {
41 {"msgs", BIFROST_DBG_MSGS, "Print debug messages"},
42 {"shaders", BIFROST_DBG_SHADERS, "Dump shaders in NIR and MIR"},
43 DEBUG_NAMED_VALUE_END
44 };
45
46 DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug, "BIFROST_MESA_DEBUG", debug_options, 0)
47
48 int bifrost_debug = 0;
49
50 #define DBG(fmt, ...) \
51 do { if (bifrost_debug & BIFROST_DBG_MSGS) \
52 fprintf(stderr, "%s:%d: "fmt, \
53 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
54
55 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
56 static bi_instruction *bi_emit_branch(bi_context *ctx);
57
58 static void
59 emit_jump(bi_context *ctx, nir_jump_instr *instr)
60 {
61 bi_instruction *branch = bi_emit_branch(ctx);
62
63 switch (instr->type) {
64 case nir_jump_break:
65 branch->branch_target = ctx->break_block;
66 break;
67 case nir_jump_continue:
68 branch->branch_target = ctx->continue_block;
69 break;
70 default:
71 unreachable("Unhandled jump type");
72 }
73
74 pan_block_add_successor(&ctx->current_block->base, &branch->branch_target->base);
75 }
76
77 static bi_instruction
78 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
79 {
80 bi_instruction load = {
81 .type = T,
82 .vector_channels = instr->num_components,
83 .src = { BIR_INDEX_CONSTANT },
84 .src_types = { nir_type_uint32 },
85 .constant = { .u64 = nir_intrinsic_base(instr) },
86 };
87
88 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
89
90 if (info->has_dest)
91 load.dest = pan_dest_index(&instr->dest);
92
93 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
94 load.dest_type = nir_intrinsic_type(instr);
95
96 nir_src *offset = nir_get_io_offset_src(instr);
97
98 if (nir_src_is_const(*offset))
99 load.constant.u64 += nir_src_as_uint(*offset);
100 else
101 load.src[0] = pan_src_index(offset);
102
103 return load;
104 }
105
106 static void
107 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
108 {
109 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
110 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
111 ins.load_vary.reuse = false; /* TODO */
112 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
113 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
114
115 if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
116 /* Zero it out for direct */
117 ins.src[1] = BIR_INDEX_ZERO;
118 } else {
119 /* R61 contains sample mask stuff, TODO RA XXX */
120 ins.src[1] = BIR_INDEX_REGISTER | 61;
121 }
122
123 bi_emit(ctx, ins);
124 }
125
126 static void
127 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
128 {
129 if (!ctx->emitted_atest) {
130 bi_instruction ins = {
131 .type = BI_ATEST,
132 .src = {
133 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
134 pan_src_index(&instr->src[0])
135 },
136 .src_types = {
137 nir_type_uint32,
138 nir_intrinsic_type(instr)
139 },
140 .swizzle = {
141 { 0 },
142 { 3, 0 } /* swizzle out the alpha */
143 },
144 .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
145 .dest_type = nir_type_uint32,
146 };
147
148 bi_emit(ctx, ins);
149 ctx->emitted_atest = true;
150 }
151
152 bi_instruction blend = {
153 .type = BI_BLEND,
154 .blend_location = nir_intrinsic_base(instr),
155 .src = {
156 pan_src_index(&instr->src[0]),
157 BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
158 },
159 .src_types = {
160 nir_intrinsic_type(instr),
161 nir_type_uint32
162 },
163 .swizzle = {
164 { 0, 1, 2, 3 },
165 { 0 }
166 },
167 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
168 .dest_type = nir_type_uint32,
169 .vector_channels = 4
170 };
171
172 assert(blend.blend_location < BIFROST_MAX_RENDER_TARGET_COUNT);
173 assert(ctx->blend_types);
174 assert(blend.src_types[0]);
175 ctx->blend_types[blend.blend_location] = blend.src_types[0];
176
177 bi_emit(ctx, blend);
178 }
179
180 static bi_instruction
181 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
182 {
183 bi_instruction ld = bi_load(T, instr);
184 ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
185 ld.src[2] = BIR_INDEX_REGISTER | 62;
186 ld.src[3] = 0;
187 ld.src_types[1] = nir_type_uint32;
188 ld.src_types[2] = nir_type_uint32;
189 ld.src_types[3] = nir_intrinsic_type(instr);
190 return ld;
191 }
192
193 static void
194 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
195 {
196 bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
197 address.dest = bi_make_temp(ctx);
198 address.dest_type = nir_type_uint32;
199 address.vector_channels = 3;
200
201 unsigned nr = nir_intrinsic_src_components(instr, 0);
202 assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
203
204 bi_instruction st = {
205 .type = BI_STORE_VAR,
206 .src = {
207 pan_src_index(&instr->src[0]),
208 address.dest, address.dest, address.dest,
209 },
210 .src_types = {
211 nir_type_uint32,
212 nir_type_uint32, nir_type_uint32, nir_type_uint32,
213 },
214 .swizzle = {
215 { 0 },
216 { 0 }, { 1 }, { 2}
217 },
218 .vector_channels = nr,
219 };
220
221 for (unsigned i = 0; i < nr; ++i)
222 st.swizzle[0][i] = i;
223
224 bi_emit(ctx, address);
225 bi_emit(ctx, st);
226 }
227
228 static void
229 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
230 {
231 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
232 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
233
234 /* TODO: Indirect access, since we need to multiply by the element
235 * size. I believe we can get this lowering automatically via
236 * nir_lower_io (as mul instructions) with the proper options, but this
237 * is TODO */
238 assert(ld.src[0] & BIR_INDEX_CONSTANT);
239 ld.constant.u64 += ctx->sysvals.sysval_count;
240 ld.constant.u64 *= 16;
241
242 bi_emit(ctx, ld);
243 }
244
245 static void
246 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
247 unsigned nr_components, unsigned offset)
248 {
249 nir_dest nir_dest;
250
251 /* Figure out which uniform this is */
252 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
253 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
254
255 /* Sysvals are prefix uniforms */
256 unsigned uniform = ((uintptr_t) val) - 1;
257
258 /* Emit the read itself -- this is never indirect */
259
260 bi_instruction load = {
261 .type = BI_LOAD_UNIFORM,
262 .vector_channels = nr_components,
263 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
264 .src_types = { nir_type_uint32, nir_type_uint32 },
265 .constant = { (uniform * 16) + offset },
266 .dest = pan_dest_index(&nir_dest),
267 .dest_type = nir_type_uint32, /* TODO */
268 };
269
270 bi_emit(ctx, load);
271 }
272
273 /* gl_FragCoord.xy = u16_to_f32(R59.xy) + 0.5
274 * gl_FragCoord.z = ld_vary(fragz)
275 * gl_FragCoord.w = ld_vary(fragw)
276 */
277
278 static void
279 bi_emit_ld_frag_coord(bi_context *ctx, nir_intrinsic_instr *instr)
280 {
281 /* Future proofing for mediump fragcoord at some point.. */
282 nir_alu_type T = nir_type_float32;
283
284 /* First, sketch a combine */
285 bi_instruction combine = {
286 .type = BI_COMBINE,
287 .dest_type = nir_type_uint32,
288 .dest = pan_dest_index(&instr->dest),
289 .src_types = { T, T, T, T },
290 };
291
292 /* Second, handle xy */
293 for (unsigned i = 0; i < 2; ++i) {
294 bi_instruction conv = {
295 .type = BI_CONVERT,
296 .dest_type = T,
297 .dest = bi_make_temp(ctx),
298 .src = {
299 /* TODO: RA XXX */
300 BIR_INDEX_REGISTER | 59
301 },
302 .src_types = { nir_type_uint16 },
303 .swizzle = { { i } }
304 };
305
306 bi_instruction add = {
307 .type = BI_ADD,
308 .dest_type = T,
309 .dest = bi_make_temp(ctx),
310 .src = { conv.dest, BIR_INDEX_CONSTANT },
311 .src_types = { T, T },
312 };
313
314 float half = 0.5;
315 memcpy(&add.constant.u32, &half, sizeof(float));
316
317 bi_emit(ctx, conv);
318 bi_emit(ctx, add);
319
320 combine.src[i] = add.dest;
321 }
322
323 /* Third, zw */
324 for (unsigned i = 0; i < 2; ++i) {
325 bi_instruction load = {
326 .type = BI_LOAD_VAR,
327 .load_vary = {
328 .interp_mode = BIFROST_INTERP_DEFAULT,
329 .reuse = false,
330 .flat = true
331 },
332 .vector_channels = 1,
333 .dest_type = nir_type_float32,
334 .dest = bi_make_temp(ctx),
335 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
336 .src_types = { nir_type_uint32, nir_type_uint32 },
337 .constant = {
338 .u32 = (i == 0) ? BIFROST_FRAGZ : BIFROST_FRAGW
339 }
340 };
341
342 bi_emit(ctx, load);
343
344 combine.src[i + 2] = load.dest;
345 }
346
347 /* Finally, emit the combine */
348 bi_emit(ctx, combine);
349 }
350
351 static void
352 bi_emit_discard(bi_context *ctx, nir_intrinsic_instr *instr)
353 {
354 /* Goofy lowering */
355 bi_instruction discard = {
356 .type = BI_DISCARD,
357 .cond = BI_COND_EQ,
358 .src_types = { nir_type_uint32, nir_type_uint32 },
359 .src = { BIR_INDEX_ZERO, BIR_INDEX_ZERO },
360 };
361
362 bi_emit(ctx, discard);
363 }
364
365 static void
366 bi_fuse_cond(bi_instruction *csel, nir_alu_src cond,
367 unsigned *constants_left, unsigned *constant_shift,
368 unsigned comps, bool float_only);
369
370 static void
371 bi_emit_discard_if(bi_context *ctx, nir_intrinsic_instr *instr)
372 {
373 nir_src cond = instr->src[0];
374 nir_alu_type T = nir_type_uint | nir_src_bit_size(cond);
375
376 bi_instruction discard = {
377 .type = BI_DISCARD,
378 .cond = BI_COND_NE,
379 .src_types = { T, T },
380 .src = {
381 pan_src_index(&cond),
382 BIR_INDEX_ZERO
383 },
384 };
385
386 /* Try to fuse in the condition */
387 unsigned constants_left = 1, constant_shift = 0;
388
389 /* Scalar so no swizzle */
390 nir_alu_src wrap = {
391 .src = instr->src[0]
392 };
393
394 /* May or may not succeed but we're optimistic */
395 bi_fuse_cond(&discard, wrap, &constants_left, &constant_shift, 1, true);
396
397 bi_emit(ctx, discard);
398 }
399
400 static void
401 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
402 {
403
404 switch (instr->intrinsic) {
405 case nir_intrinsic_load_barycentric_pixel:
406 /* stub */
407 break;
408 case nir_intrinsic_load_interpolated_input:
409 case nir_intrinsic_load_input:
410 if (ctx->stage == MESA_SHADER_FRAGMENT)
411 bi_emit_ld_vary(ctx, instr);
412 else if (ctx->stage == MESA_SHADER_VERTEX)
413 bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
414 else {
415 unreachable("Unsupported shader stage");
416 }
417 break;
418
419 case nir_intrinsic_store_output:
420 if (ctx->stage == MESA_SHADER_FRAGMENT)
421 bi_emit_frag_out(ctx, instr);
422 else if (ctx->stage == MESA_SHADER_VERTEX)
423 bi_emit_st_vary(ctx, instr);
424 else
425 unreachable("Unsupported shader stage");
426 break;
427
428 case nir_intrinsic_load_uniform:
429 bi_emit_ld_uniform(ctx, instr);
430 break;
431
432 case nir_intrinsic_load_frag_coord:
433 bi_emit_ld_frag_coord(ctx, instr);
434 break;
435
436 case nir_intrinsic_discard:
437 bi_emit_discard(ctx, instr);
438 break;
439
440 case nir_intrinsic_discard_if:
441 bi_emit_discard_if(ctx, instr);
442 break;
443
444 case nir_intrinsic_load_ssbo_address:
445 bi_emit_sysval(ctx, &instr->instr, 1, 0);
446 break;
447
448 case nir_intrinsic_get_buffer_size:
449 bi_emit_sysval(ctx, &instr->instr, 1, 8);
450 break;
451
452 case nir_intrinsic_load_viewport_scale:
453 case nir_intrinsic_load_viewport_offset:
454 case nir_intrinsic_load_num_work_groups:
455 case nir_intrinsic_load_sampler_lod_parameters_pan:
456 bi_emit_sysval(ctx, &instr->instr, 3, 0);
457 break;
458
459 default:
460 unreachable("Unknown intrinsic");
461 break;
462 }
463 }
464
465 static void
466 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
467 {
468 /* Make sure we've been lowered */
469 assert(instr->def.num_components <= (32 / instr->def.bit_size));
470
471 /* Accumulate all the channels of the constant, as if we did an
472 * implicit SEL over them */
473 uint32_t acc = 0;
474
475 for (unsigned i = 0; i < instr->def.num_components; ++i) {
476 unsigned v = nir_const_value_as_uint(instr->value[i], instr->def.bit_size);
477 acc |= (v << (i * instr->def.bit_size));
478 }
479
480 bi_instruction move = {
481 .type = BI_MOV,
482 .dest = pan_ssa_index(&instr->def),
483 .dest_type = nir_type_uint32,
484 .src = {
485 BIR_INDEX_CONSTANT
486 },
487 .src_types = {
488 nir_type_uint32,
489 },
490 .constant = {
491 .u32 = acc
492 }
493 };
494
495 bi_emit(ctx, move);
496 }
497
498 #define BI_CASE_CMP(op) \
499 case op##8: \
500 case op##16: \
501 case op##32: \
502
503 static enum bi_class
504 bi_class_for_nir_alu(nir_op op)
505 {
506 switch (op) {
507 case nir_op_fadd:
508 case nir_op_fsub:
509 return BI_ADD;
510
511 case nir_op_iadd:
512 case nir_op_isub:
513 return BI_IMATH;
514
515 case nir_op_imul:
516 return BI_IMUL;
517
518 case nir_op_iand:
519 case nir_op_ior:
520 case nir_op_ixor:
521 case nir_op_inot:
522 case nir_op_ishl:
523 return BI_BITWISE;
524
525 BI_CASE_CMP(nir_op_flt)
526 BI_CASE_CMP(nir_op_fge)
527 BI_CASE_CMP(nir_op_feq)
528 BI_CASE_CMP(nir_op_fne)
529 BI_CASE_CMP(nir_op_ilt)
530 BI_CASE_CMP(nir_op_ige)
531 BI_CASE_CMP(nir_op_ieq)
532 BI_CASE_CMP(nir_op_ine)
533 BI_CASE_CMP(nir_op_uge)
534 return BI_CMP;
535
536 case nir_op_b8csel:
537 case nir_op_b16csel:
538 case nir_op_b32csel:
539 return BI_CSEL;
540
541 case nir_op_i2i8:
542 case nir_op_i2i16:
543 case nir_op_i2i32:
544 case nir_op_i2i64:
545 case nir_op_u2u8:
546 case nir_op_u2u16:
547 case nir_op_u2u32:
548 case nir_op_u2u64:
549 case nir_op_f2i16:
550 case nir_op_f2i32:
551 case nir_op_f2i64:
552 case nir_op_f2u16:
553 case nir_op_f2u32:
554 case nir_op_f2u64:
555 case nir_op_i2f16:
556 case nir_op_i2f32:
557 case nir_op_i2f64:
558 case nir_op_u2f16:
559 case nir_op_u2f32:
560 case nir_op_u2f64:
561 case nir_op_f2f16:
562 case nir_op_f2f32:
563 case nir_op_f2f64:
564 case nir_op_f2fmp:
565 return BI_CONVERT;
566
567 case nir_op_vec2:
568 case nir_op_vec3:
569 case nir_op_vec4:
570 return BI_COMBINE;
571
572 case nir_op_vec8:
573 case nir_op_vec16:
574 unreachable("should've been lowered");
575
576 case nir_op_ffma:
577 case nir_op_fmul:
578 return BI_FMA;
579
580 case nir_op_imin:
581 case nir_op_imax:
582 case nir_op_umin:
583 case nir_op_umax:
584 case nir_op_fmin:
585 case nir_op_fmax:
586 return BI_MINMAX;
587
588 case nir_op_fsat:
589 case nir_op_fneg:
590 case nir_op_fabs:
591 return BI_FMOV;
592 case nir_op_mov:
593 return BI_MOV;
594
595 case nir_op_fround_even:
596 case nir_op_fceil:
597 case nir_op_ffloor:
598 case nir_op_ftrunc:
599 return BI_ROUND;
600
601 case nir_op_frcp:
602 case nir_op_frsq:
603 case nir_op_iabs:
604 return BI_SPECIAL;
605
606 default:
607 unreachable("Unknown ALU op");
608 }
609 }
610
611 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
612 * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
613 * optimizations). Otherwise it will bail (when used for primary code
614 * generation). */
615
616 static enum bi_cond
617 bi_cond_for_nir(nir_op op, bool soft)
618 {
619 switch (op) {
620 BI_CASE_CMP(nir_op_flt)
621 BI_CASE_CMP(nir_op_ilt)
622 return BI_COND_LT;
623
624 BI_CASE_CMP(nir_op_fge)
625 BI_CASE_CMP(nir_op_ige)
626 BI_CASE_CMP(nir_op_uge)
627 return BI_COND_GE;
628
629 BI_CASE_CMP(nir_op_feq)
630 BI_CASE_CMP(nir_op_ieq)
631 return BI_COND_EQ;
632
633 BI_CASE_CMP(nir_op_fne)
634 BI_CASE_CMP(nir_op_ine)
635 return BI_COND_NE;
636 default:
637 if (soft)
638 return BI_COND_ALWAYS;
639 else
640 unreachable("Invalid compare");
641 }
642 }
643
644 static void
645 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
646 unsigned *constants_left, unsigned *constant_shift, unsigned comps)
647 {
648 unsigned bits = nir_src_bit_size(instr->src[i].src);
649 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
650
651 alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
652 | bits;
653
654 /* Try to inline a constant */
655 if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
656 uint64_t mask = (1ull << dest_bits) - 1;
657 uint64_t cons = nir_src_as_uint(instr->src[i].src);
658
659 /* Try to reuse a constant */
660 for (unsigned i = 0; i < (*constant_shift); i += dest_bits) {
661 if (((alu->constant.u64 >> i) & mask) == cons) {
662 alu->src[to] = BIR_INDEX_CONSTANT | i;
663 return;
664 }
665 }
666
667 alu->constant.u64 |= cons << *constant_shift;
668 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
669 --(*constants_left);
670 (*constant_shift) += MAX2(dest_bits, 32); /* lo/hi */
671 return;
672 }
673
674 alu->src[to] = pan_src_index(&instr->src[i].src);
675
676 /* Copy swizzle for all vectored components, replicating last component
677 * to fill undersized */
678
679 unsigned vec = alu->type == BI_COMBINE ? 1 :
680 MAX2(1, 32 / dest_bits);
681
682 for (unsigned j = 0; j < vec; ++j)
683 alu->swizzle[to][j] = instr->src[i].swizzle[MIN2(j, comps - 1)];
684 }
685
686 static void
687 bi_fuse_cond(bi_instruction *csel, nir_alu_src cond,
688 unsigned *constants_left, unsigned *constant_shift,
689 unsigned comps, bool float_only)
690 {
691 /* Bail for vector weirdness */
692 if (cond.swizzle[0] != 0)
693 return;
694
695 if (!cond.src.is_ssa)
696 return;
697
698 nir_ssa_def *def = cond.src.ssa;
699 nir_instr *parent = def->parent_instr;
700
701 if (parent->type != nir_instr_type_alu)
702 return;
703
704 nir_alu_instr *alu = nir_instr_as_alu(parent);
705
706 /* Try to match a condition */
707 enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
708
709 if (bcond == BI_COND_ALWAYS)
710 return;
711
712 /* Some instructions can't compare ints */
713 if (float_only) {
714 nir_alu_type T = nir_op_infos[alu->op].input_types[0];
715 T = nir_alu_type_get_base_type(T);
716
717 if (T != nir_type_float)
718 return;
719 }
720
721 /* We found one, let's fuse it in */
722 csel->cond = bcond;
723 bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift, comps);
724 bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift, comps);
725 }
726
727 static void
728 emit_alu(bi_context *ctx, nir_alu_instr *instr)
729 {
730 /* Try some special functions */
731 switch (instr->op) {
732 case nir_op_fexp2:
733 bi_emit_fexp2(ctx, instr);
734 return;
735 case nir_op_flog2:
736 bi_emit_flog2(ctx, instr);
737 return;
738 default:
739 break;
740 }
741
742 /* Otherwise, assume it's something we can handle normally */
743 bi_instruction alu = {
744 .type = bi_class_for_nir_alu(instr->op),
745 .dest = pan_dest_index(&instr->dest.dest),
746 .dest_type = nir_op_infos[instr->op].output_type
747 | nir_dest_bit_size(instr->dest.dest),
748 };
749
750 /* TODO: Implement lowering of special functions for older Bifrost */
751 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
752
753 unsigned comps = nir_dest_num_components(instr->dest.dest);
754
755 if (alu.type != BI_COMBINE)
756 assert(comps <= MAX2(1, 32 / comps));
757
758 if (!instr->dest.dest.is_ssa) {
759 for (unsigned i = 0; i < comps; ++i)
760 assert(instr->dest.write_mask);
761 }
762
763 /* We inline constants as we go. This tracks how many constants have
764 * been inlined, since we're limited to 64-bits of constants per
765 * instruction */
766
767 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
768 unsigned constants_left = (64 / dest_bits);
769 unsigned constant_shift = 0;
770
771 if (alu.type == BI_COMBINE)
772 constants_left = 0;
773
774 /* Copy sources */
775
776 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
777 assert(num_inputs <= ARRAY_SIZE(alu.src));
778
779 for (unsigned i = 0; i < num_inputs; ++i) {
780 unsigned f = 0;
781
782 if (i && alu.type == BI_CSEL)
783 f++;
784
785 bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift, comps);
786 }
787
788 /* Op-specific fixup */
789 switch (instr->op) {
790 case nir_op_fmul:
791 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
792 alu.src_types[2] = alu.src_types[1];
793 break;
794 case nir_op_fsat:
795 alu.outmod = BIFROST_SAT; /* FMOV */
796 break;
797 case nir_op_fneg:
798 alu.src_neg[0] = true; /* FMOV */
799 break;
800 case nir_op_fabs:
801 alu.src_abs[0] = true; /* FMOV */
802 break;
803 case nir_op_fsub:
804 alu.src_neg[1] = true; /* FADD */
805 break;
806 case nir_op_iadd:
807 alu.op.imath = BI_IMATH_ADD;
808 break;
809 case nir_op_isub:
810 alu.op.imath = BI_IMATH_SUB;
811 break;
812 case nir_op_iabs:
813 alu.op.special = BI_SPECIAL_IABS;
814 break;
815 case nir_op_inot:
816 /* no dedicated bitwise not, but we can invert sources. convert to ~a | 0 */
817 alu.op.bitwise = BI_BITWISE_OR;
818 alu.bitwise.src_invert[0] = true;
819 alu.src[1] = BIR_INDEX_ZERO;
820 /* zero shift */
821 alu.src[2] = BIR_INDEX_ZERO;
822 alu.src_types[2] = alu.src_types[1];
823 break;
824 case nir_op_ishl:
825 alu.op.bitwise = BI_BITWISE_OR;
826 /* move src1 to src2 and replace with zero. underlying op is (src0 << src2) | src1 */
827 alu.src[2] = alu.src[1];
828 alu.src_types[2] = alu.src_types[1];
829 alu.src[1] = BIR_INDEX_ZERO;
830 break;
831 case nir_op_imul:
832 alu.op.imul = BI_IMUL_IMUL;
833 break;
834 case nir_op_fmax:
835 case nir_op_imax:
836 case nir_op_umax:
837 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
838 break;
839 case nir_op_frcp:
840 alu.op.special = BI_SPECIAL_FRCP;
841 break;
842 case nir_op_frsq:
843 alu.op.special = BI_SPECIAL_FRSQ;
844 break;
845 BI_CASE_CMP(nir_op_flt)
846 BI_CASE_CMP(nir_op_ilt)
847 BI_CASE_CMP(nir_op_fge)
848 BI_CASE_CMP(nir_op_ige)
849 BI_CASE_CMP(nir_op_feq)
850 BI_CASE_CMP(nir_op_ieq)
851 BI_CASE_CMP(nir_op_fne)
852 BI_CASE_CMP(nir_op_ine)
853 BI_CASE_CMP(nir_op_uge)
854 alu.cond = bi_cond_for_nir(instr->op, false);
855 break;
856 case nir_op_fround_even:
857 alu.roundmode = BIFROST_RTE;
858 break;
859 case nir_op_fceil:
860 alu.roundmode = BIFROST_RTP;
861 break;
862 case nir_op_ffloor:
863 alu.roundmode = BIFROST_RTN;
864 break;
865 case nir_op_ftrunc:
866 alu.roundmode = BIFROST_RTZ;
867 break;
868 case nir_op_iand:
869 alu.op.bitwise = BI_BITWISE_AND;
870 /* zero shift */
871 alu.src[2] = BIR_INDEX_ZERO;
872 alu.src_types[2] = alu.src_types[1];
873 break;
874 case nir_op_ior:
875 alu.op.bitwise = BI_BITWISE_OR;
876 /* zero shift */
877 alu.src[2] = BIR_INDEX_ZERO;
878 alu.src_types[2] = alu.src_types[1];
879 break;
880 case nir_op_ixor:
881 alu.op.bitwise = BI_BITWISE_XOR;
882 /* zero shift */
883 alu.src[2] = BIR_INDEX_ZERO;
884 alu.src_types[2] = alu.src_types[1];
885 break;
886 case nir_op_f2i32:
887 alu.roundmode = BIFROST_RTZ;
888 break;
889
890 case nir_op_f2f16:
891 case nir_op_i2i16:
892 case nir_op_u2u16: {
893 if (nir_src_bit_size(instr->src[0].src) != 32)
894 break;
895
896 /* Should have been const folded */
897 assert(!nir_src_is_const(instr->src[0].src));
898
899 alu.src_types[1] = alu.src_types[0];
900 alu.src[1] = alu.src[0];
901
902 unsigned last = nir_dest_num_components(instr->dest.dest) - 1;
903 assert(last <= 1);
904
905 alu.swizzle[1][0] = instr->src[0].swizzle[last];
906 break;
907 }
908
909 default:
910 break;
911 }
912
913 if (alu.type == BI_CSEL) {
914 /* Default to csel3 */
915 alu.cond = BI_COND_NE;
916 alu.src[1] = BIR_INDEX_ZERO;
917 alu.src_types[1] = alu.src_types[0];
918
919 /* TODO: Reenable cond fusing when we can split up registers
920 * when scheduling */
921 #if 0
922 bi_fuse_cond(&alu, instr->src[0],
923 &constants_left, &constant_shift, comps, false);
924 #endif
925 }
926
927 bi_emit(ctx, alu);
928 }
929
930 /* TEX_COMPACT instructions assume normal 2D f32 operation but are more
931 * space-efficient and with simpler RA/scheduling requirements*/
932
933 static void
934 emit_tex_compact(bi_context *ctx, nir_tex_instr *instr)
935 {
936 bi_instruction tex = {
937 .type = BI_TEX,
938 .op = { .texture = BI_TEX_COMPACT },
939 .texture = {
940 .texture_index = instr->texture_index,
941 .sampler_index = instr->sampler_index,
942 },
943 .dest = pan_dest_index(&instr->dest),
944 .dest_type = instr->dest_type,
945 .src_types = { nir_type_float32, nir_type_float32 },
946 .vector_channels = 4
947 };
948
949 for (unsigned i = 0; i < instr->num_srcs; ++i) {
950 int index = pan_src_index(&instr->src[i].src);
951
952 /* We were checked ahead-of-time */
953 if (instr->src[i].src_type == nir_tex_src_lod)
954 continue;
955
956 assert (instr->src[i].src_type == nir_tex_src_coord);
957
958 tex.src[0] = index;
959 tex.src[1] = index;
960 tex.swizzle[0][0] = 0;
961 tex.swizzle[1][0] = 1;
962 }
963
964 bi_emit(ctx, tex);
965 }
966
967 static void
968 emit_tex_full(bi_context *ctx, nir_tex_instr *instr)
969 {
970 unreachable("stub");
971 }
972
973 /* Normal textures ops are tex for frag shaders and txl for vertex shaders with
974 * lod a constant 0. Anything else needs a full texture op. */
975
976 static bool
977 bi_is_normal_tex(gl_shader_stage stage, nir_tex_instr *instr)
978 {
979 if (stage == MESA_SHADER_FRAGMENT)
980 return instr->op == nir_texop_tex;
981
982 if (instr->op != nir_texop_txl)
983 return false;
984
985 for (unsigned i = 0; i < instr->num_srcs; ++i) {
986 if (instr->src[i].src_type != nir_tex_src_lod)
987 continue;
988
989 nir_src src = instr->src[i].src;
990
991 if (!nir_src_is_const(src))
992 continue;
993
994 if (nir_src_as_uint(src) != 0)
995 continue;
996 }
997
998 return true;
999 }
1000
1001 static void
1002 emit_tex(bi_context *ctx, nir_tex_instr *instr)
1003 {
1004 nir_alu_type base = nir_alu_type_get_base_type(instr->dest_type);
1005 unsigned sz = nir_dest_bit_size(instr->dest);
1006 instr->dest_type = base | sz;
1007
1008 bool is_normal = bi_is_normal_tex(ctx->stage, instr);
1009 bool is_2d = instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
1010 instr->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL;
1011 bool is_f = base == nir_type_float && (sz == 16 || sz == 32);
1012
1013 bool is_compact = is_normal && is_2d && is_f && !instr->is_shadow;
1014
1015 if (is_compact)
1016 emit_tex_compact(ctx, instr);
1017 else
1018 emit_tex_full(ctx, instr);
1019 }
1020
1021 static void
1022 emit_instr(bi_context *ctx, struct nir_instr *instr)
1023 {
1024 switch (instr->type) {
1025 case nir_instr_type_load_const:
1026 emit_load_const(ctx, nir_instr_as_load_const(instr));
1027 break;
1028
1029 case nir_instr_type_intrinsic:
1030 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1031 break;
1032
1033 case nir_instr_type_alu:
1034 emit_alu(ctx, nir_instr_as_alu(instr));
1035 break;
1036
1037 case nir_instr_type_tex:
1038 emit_tex(ctx, nir_instr_as_tex(instr));
1039 break;
1040
1041 case nir_instr_type_jump:
1042 emit_jump(ctx, nir_instr_as_jump(instr));
1043 break;
1044
1045 case nir_instr_type_ssa_undef:
1046 /* Spurious */
1047 break;
1048
1049 default:
1050 unreachable("Unhandled instruction type");
1051 break;
1052 }
1053 }
1054
1055
1056
1057 static bi_block *
1058 create_empty_block(bi_context *ctx)
1059 {
1060 bi_block *blk = rzalloc(ctx, bi_block);
1061
1062 blk->base.predecessors = _mesa_set_create(blk,
1063 _mesa_hash_pointer,
1064 _mesa_key_pointer_equal);
1065
1066 return blk;
1067 }
1068
1069 static bi_block *
1070 emit_block(bi_context *ctx, nir_block *block)
1071 {
1072 if (ctx->after_block) {
1073 ctx->current_block = ctx->after_block;
1074 ctx->after_block = NULL;
1075 } else {
1076 ctx->current_block = create_empty_block(ctx);
1077 }
1078
1079 list_addtail(&ctx->current_block->base.link, &ctx->blocks);
1080 list_inithead(&ctx->current_block->base.instructions);
1081
1082 nir_foreach_instr(instr, block) {
1083 emit_instr(ctx, instr);
1084 ++ctx->instruction_count;
1085 }
1086
1087 return ctx->current_block;
1088 }
1089
1090 /* Emits an unconditional branch to the end of the current block, returning a
1091 * pointer so the user can fill in details */
1092
1093 static bi_instruction *
1094 bi_emit_branch(bi_context *ctx)
1095 {
1096 bi_instruction branch = {
1097 .type = BI_BRANCH,
1098 .cond = BI_COND_ALWAYS
1099 };
1100
1101 return bi_emit(ctx, branch);
1102 }
1103
1104 /* Sets a condition for a branch by examing the NIR condition. If we're
1105 * familiar with the condition, we unwrap it to fold it into the branch
1106 * instruction. Otherwise, we consume the condition directly. We
1107 * generally use 1-bit booleans which allows us to use small types for
1108 * the conditions.
1109 */
1110
1111 static void
1112 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
1113 {
1114 /* TODO: Try to unwrap instead of always bailing */
1115 branch->src[0] = pan_src_index(cond);
1116 branch->src[1] = BIR_INDEX_ZERO;
1117 branch->src_types[0] = branch->src_types[1] = nir_type_uint |
1118 nir_src_bit_size(*cond);
1119 branch->cond = invert ? BI_COND_EQ : BI_COND_NE;
1120 }
1121
1122 static void
1123 emit_if(bi_context *ctx, nir_if *nif)
1124 {
1125 bi_block *before_block = ctx->current_block;
1126
1127 /* Speculatively emit the branch, but we can't fill it in until later */
1128 bi_instruction *then_branch = bi_emit_branch(ctx);
1129 bi_set_branch_cond(then_branch, &nif->condition, true);
1130
1131 /* Emit the two subblocks. */
1132 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
1133 bi_block *end_then_block = ctx->current_block;
1134
1135 /* Emit a jump from the end of the then block to the end of the else */
1136 bi_instruction *then_exit = bi_emit_branch(ctx);
1137
1138 /* Emit second block, and check if it's empty */
1139
1140 int count_in = ctx->instruction_count;
1141 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
1142 bi_block *end_else_block = ctx->current_block;
1143 ctx->after_block = create_empty_block(ctx);
1144
1145 /* Now that we have the subblocks emitted, fix up the branches */
1146
1147 assert(then_block);
1148 assert(else_block);
1149
1150 if (ctx->instruction_count == count_in) {
1151 /* The else block is empty, so don't emit an exit jump */
1152 bi_remove_instruction(then_exit);
1153 then_branch->branch_target = ctx->after_block;
1154 pan_block_add_successor(&end_then_block->base, &ctx->after_block->base); /* fallthrough */
1155 } else {
1156 then_branch->branch_target = else_block;
1157 then_exit->branch_target = ctx->after_block;
1158 pan_block_add_successor(&end_then_block->base, &then_exit->branch_target->base);
1159 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
1160 }
1161
1162 pan_block_add_successor(&before_block->base, &then_branch->branch_target->base); /* then_branch */
1163 pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
1164 }
1165
1166 static void
1167 emit_loop(bi_context *ctx, nir_loop *nloop)
1168 {
1169 /* Remember where we are */
1170 bi_block *start_block = ctx->current_block;
1171
1172 bi_block *saved_break = ctx->break_block;
1173 bi_block *saved_continue = ctx->continue_block;
1174
1175 ctx->continue_block = create_empty_block(ctx);
1176 ctx->break_block = create_empty_block(ctx);
1177 ctx->after_block = ctx->continue_block;
1178
1179 /* Emit the body itself */
1180 emit_cf_list(ctx, &nloop->body);
1181
1182 /* Branch back to loop back */
1183 bi_instruction *br_back = bi_emit_branch(ctx);
1184 br_back->branch_target = ctx->continue_block;
1185 pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
1186 pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
1187
1188 ctx->after_block = ctx->break_block;
1189
1190 /* Pop off */
1191 ctx->break_block = saved_break;
1192 ctx->continue_block = saved_continue;
1193 ++ctx->loop_count;
1194 }
1195
1196 static bi_block *
1197 emit_cf_list(bi_context *ctx, struct exec_list *list)
1198 {
1199 bi_block *start_block = NULL;
1200
1201 foreach_list_typed(nir_cf_node, node, node, list) {
1202 switch (node->type) {
1203 case nir_cf_node_block: {
1204 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
1205
1206 if (!start_block)
1207 start_block = block;
1208
1209 break;
1210 }
1211
1212 case nir_cf_node_if:
1213 emit_if(ctx, nir_cf_node_as_if(node));
1214 break;
1215
1216 case nir_cf_node_loop:
1217 emit_loop(ctx, nir_cf_node_as_loop(node));
1218 break;
1219
1220 default:
1221 unreachable("Unknown control flow");
1222 }
1223 }
1224
1225 return start_block;
1226 }
1227
1228 static int
1229 glsl_type_size(const struct glsl_type *type, bool bindless)
1230 {
1231 return glsl_count_attribute_slots(type, false);
1232 }
1233
1234 static void
1235 bi_optimize_nir(nir_shader *nir)
1236 {
1237 bool progress;
1238 unsigned lower_flrp = 16 | 32 | 64;
1239
1240 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
1241 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
1242
1243 nir_lower_tex_options lower_tex_options = {
1244 .lower_txs_lod = true,
1245 .lower_txp = ~0,
1246 .lower_tex_without_implicit_lod = true,
1247 .lower_txd = true,
1248 };
1249
1250 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
1251 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1252 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1253
1254 do {
1255 progress = false;
1256
1257 NIR_PASS(progress, nir, nir_lower_var_copies);
1258 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
1259
1260 NIR_PASS(progress, nir, nir_copy_prop);
1261 NIR_PASS(progress, nir, nir_opt_remove_phis);
1262 NIR_PASS(progress, nir, nir_opt_dce);
1263 NIR_PASS(progress, nir, nir_opt_dead_cf);
1264 NIR_PASS(progress, nir, nir_opt_cse);
1265 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
1266 NIR_PASS(progress, nir, nir_opt_algebraic);
1267 NIR_PASS(progress, nir, nir_opt_constant_folding);
1268
1269 if (lower_flrp != 0) {
1270 bool lower_flrp_progress = false;
1271 NIR_PASS(lower_flrp_progress,
1272 nir,
1273 nir_lower_flrp,
1274 lower_flrp,
1275 false /* always_precise */,
1276 nir->options->lower_ffma);
1277 if (lower_flrp_progress) {
1278 NIR_PASS(progress, nir,
1279 nir_opt_constant_folding);
1280 progress = true;
1281 }
1282
1283 /* Nothing should rematerialize any flrps, so we only
1284 * need to do this lowering once.
1285 */
1286 lower_flrp = 0;
1287 }
1288
1289 NIR_PASS(progress, nir, nir_opt_undef);
1290 NIR_PASS(progress, nir, nir_opt_loop_unroll,
1291 nir_var_shader_in |
1292 nir_var_shader_out |
1293 nir_var_function_temp);
1294 } while (progress);
1295
1296 NIR_PASS(progress, nir, nir_opt_algebraic_late);
1297 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
1298 NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
1299 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1300 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1301
1302 /* Take us out of SSA */
1303 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
1304 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
1305 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
1306 }
1307
1308 void
1309 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
1310 {
1311 bifrost_debug = debug_get_option_bifrost_debug();
1312
1313 bi_context *ctx = rzalloc(NULL, bi_context);
1314 ctx->nir = nir;
1315 ctx->stage = nir->info.stage;
1316 ctx->quirks = bifrost_get_quirks(product_id);
1317 list_inithead(&ctx->blocks);
1318
1319 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
1320 * (so we don't accidentally duplicate the epilogue since mesa/st has
1321 * messed with our I/O quite a bit already) */
1322
1323 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1324
1325 if (ctx->stage == MESA_SHADER_VERTEX) {
1326 NIR_PASS_V(nir, nir_lower_viewport_transform);
1327 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
1328 }
1329
1330 NIR_PASS_V(nir, nir_split_var_copies);
1331 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
1332 NIR_PASS_V(nir, nir_lower_var_copies);
1333 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1334 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
1335 glsl_type_size, 0);
1336 NIR_PASS_V(nir, nir_lower_ssbo);
1337 NIR_PASS_V(nir, nir_lower_mediump_outputs);
1338
1339 bi_optimize_nir(nir);
1340
1341 if (bifrost_debug & BIFROST_DBG_SHADERS) {
1342 nir_print_shader(nir, stdout);
1343 }
1344
1345 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
1346 program->sysval_count = ctx->sysvals.sysval_count;
1347 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
1348 ctx->blend_types = program->blend_types;
1349
1350 nir_foreach_function(func, nir) {
1351 if (!func->impl)
1352 continue;
1353
1354 ctx->impl = func->impl;
1355 emit_cf_list(ctx, &func->impl->body);
1356 break; /* TODO: Multi-function shaders */
1357 }
1358
1359 unsigned block_source_count = 0;
1360
1361 bi_foreach_block(ctx, _block) {
1362 bi_block *block = (bi_block *) _block;
1363
1364 /* Name blocks now that we're done emitting so the order is
1365 * consistent */
1366 block->base.name = block_source_count++;
1367
1368 bi_lower_combine(ctx, block);
1369 }
1370
1371 bool progress = false;
1372
1373 do {
1374 progress = false;
1375
1376 bi_foreach_block(ctx, _block) {
1377 bi_block *block = (bi_block *) _block;
1378 progress |= bi_opt_dead_code_eliminate(ctx, block);
1379 }
1380 } while(progress);
1381
1382 if (bifrost_debug & BIFROST_DBG_SHADERS)
1383 bi_print_shader(ctx, stdout);
1384 bi_schedule(ctx);
1385 bi_register_allocate(ctx);
1386 if (bifrost_debug & BIFROST_DBG_SHADERS)
1387 bi_print_shader(ctx, stdout);
1388 bi_pack(ctx, &program->compiled);
1389
1390 if (bifrost_debug & BIFROST_DBG_SHADERS)
1391 disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1392
1393 ralloc_free(ctx);
1394 }