src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "main/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 106
 107         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 108                 /* Zero it out for direct */
 109                 ins.src[1] = BIR_INDEX_ZERO;
 110         } else {
 111                 /* R61 contains sample mask stuff, TODO RA XXX */
 112                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 113         }
 114
 115         bi_emit(ctx, ins);
 116 }
 117
 118 static void
 119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 120 {
 121         if (!ctx->emitted_atest) {
 122                 bi_instruction ins = {
 123                         .type = BI_ATEST,
 124                         .src = {
 125                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 126                                 bir_src_index(&instr->src[0])
 127                         },
 128                         .src_types = {
 129                                 nir_type_uint32,
 130                                 nir_type_float32
 131                         },
 132                         .swizzle = {
 133                                 { 0 },
 134                                 { 3, 0 } /* swizzle out the alpha */
 135                         },
 136                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 137                         .dest_type = nir_type_uint32,
 138                         .writemask = 0xF
 139                 };
 140
 141                 bi_emit(ctx, ins);
 142                 bi_schedule_barrier(ctx);
 143                 ctx->emitted_atest = true;
 144         }
 145
 146         bi_instruction blend = {
 147                 .type = BI_BLEND,
 148                 .blend_location = nir_intrinsic_base(instr),
 149                 .src = {
 150                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 151                         bir_src_index(&instr->src[0])
 152                 },
 153                 .src_types = {
 154                         nir_type_uint32,
 155                         nir_type_float32,
 156                 },
 157                 .swizzle = {
 158                         { 0 },
 159                         { 0, 1, 2, 3 }
 160                 },
 161                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 162                 .dest_type = nir_type_uint32,
 163                 .writemask = 0xF
 164         };
 165
 166         bi_emit(ctx, blend);
 167         bi_schedule_barrier(ctx);
 168 }
 169
 170 static bi_instruction
 171 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
 172 {
 173         bi_instruction ld = bi_load(T, instr);
 174         ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
 175         ld.src[2] = BIR_INDEX_REGISTER | 62;
 176         ld.src[3] = 0;
 177         ld.src_types[1] = nir_type_uint32;
 178         ld.src_types[2] = nir_type_uint32;
 179         ld.src_types[3] = nir_intrinsic_type(instr);
 180         return ld;
 181 }
 182
 183 static void
 184 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 185 {
 186         bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
 187         address.dest = bi_make_temp(ctx);
 188         address.dest_type = nir_type_uint32;
 189         address.writemask = (1 << 12) - 1;
 190
 191         bi_instruction st = {
 192                 .type = BI_STORE_VAR,
 193                 .src = {
 194                         bir_src_index(&instr->src[0]),
 195                         address.dest, address.dest, address.dest,
 196                 },
 197                 .src_types = {
 198                         nir_type_uint32,
 199                         nir_type_uint32, nir_type_uint32, nir_type_uint32,
 200                 },
 201                 .swizzle = {
 202                         { 0, 1, 2, 3 },
 203                         { 0 }, { 1 }, { 2}
 204                 },
 205                 .store_channels = 4, /* TODO: WRITEMASK */
 206         };
 207
 208         bi_emit(ctx, address);
 209         bi_emit(ctx, st);
 210 }
 211
 212 static void
 213 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 214 {
 215         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 216         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 217
 218         /* TODO: Indirect access, since we need to multiply by the element
 219          * size. I believe we can get this lowering automatically via
 220          * nir_lower_io (as mul instructions) with the proper options, but this
 221          * is TODO */
 222         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 223         ld.constant.u64 += ctx->sysvals.sysval_count;
 224         ld.constant.u64 *= 16;
 225
 226         bi_emit(ctx, ld);
 227 }
 228
 229 static void
 230 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 231                 unsigned nr_components, unsigned offset)
 232 {
 233         nir_dest nir_dest;
 234
 235         /* Figure out which uniform this is */
 236         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 237         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 238
 239         /* Sysvals are prefix uniforms */
 240         unsigned uniform = ((uintptr_t) val) - 1;
 241
 242         /* Emit the read itself -- this is never indirect */
 243
 244         bi_instruction load = {
 245                 .type = BI_LOAD_UNIFORM,
 246                 .writemask = (1 << (nr_components * 4)) - 1,
 247                 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
 248                 .constant = { (uniform * 16) + offset },
 249                 .dest = bir_dest_index(&nir_dest),
 250                 .dest_type = nir_type_uint32, /* TODO */
 251         };
 252
 253         bi_emit(ctx, load);
 254 }
 255
 256 static void
 257 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 258 {
 259
 260         switch (instr->intrinsic) {
 261         case nir_intrinsic_load_barycentric_pixel:
 262                 /* stub */
 263                 break;
 264         case nir_intrinsic_load_interpolated_input:
 265         case nir_intrinsic_load_input:
 266                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 267                         bi_emit_ld_vary(ctx, instr);
 268                 else if (ctx->stage == MESA_SHADER_VERTEX)
 269                         bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
 270                 else {
 271                         unreachable("Unsupported shader stage");
 272                 }
 273                 break;
 274
 275         case nir_intrinsic_store_output:
 276                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 277                         bi_emit_frag_out(ctx, instr);
 278                 else if (ctx->stage == MESA_SHADER_VERTEX)
 279                         bi_emit_st_vary(ctx, instr);
 280                 else
 281                         unreachable("Unsupported shader stage");
 282                 break;
 283
 284         case nir_intrinsic_load_uniform:
 285                 bi_emit_ld_uniform(ctx, instr);
 286                 break;
 287
 288         case nir_intrinsic_load_ssbo_address:
 289                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 290                 break;
 291
 292         case nir_intrinsic_get_buffer_size:
 293                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 294                 break;
 295
 296         case nir_intrinsic_load_viewport_scale:
 297         case nir_intrinsic_load_viewport_offset:
 298         case nir_intrinsic_load_num_work_groups:
 299         case nir_intrinsic_load_sampler_lod_parameters_pan:
 300                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 301                 break;
 302
 303         default:
 304                 /* todo */
 305                 break;
 306         }
 307 }
 308
 309 static void
 310 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 311 {
 312         /* Make sure we've been lowered */
 313         assert(instr->def.num_components == 1);
 314
 315         bi_instruction move = {
 316                 .type = BI_MOV,
 317                 .dest = bir_ssa_index(&instr->def),
 318                 .dest_type = instr->def.bit_size | nir_type_uint,
 319                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 320                 .src = {
 321                         BIR_INDEX_CONSTANT
 322                 },
 323                 .constant = {
 324                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 325                 }
 326         };
 327
 328         bi_emit(ctx, move);
 329 }
 330
 331 static enum bi_class
 332 bi_class_for_nir_alu(nir_op op)
 333 {
 334         switch (op) {
 335         case nir_op_iadd:
 336         case nir_op_fadd:
 337         case nir_op_fsub:
 338                 return BI_ADD;
 339         case nir_op_isub:
 340                 return BI_ISUB;
 341
 342         case nir_op_flt:
 343         case nir_op_fge:
 344         case nir_op_feq:
 345         case nir_op_fne:
 346         case nir_op_ilt:
 347         case nir_op_ige:
 348         case nir_op_ieq:
 349         case nir_op_ine:
 350                 return BI_CMP;
 351
 352         case nir_op_bcsel:
 353                 return BI_CSEL;
 354
 355         case nir_op_i2i8:
 356         case nir_op_i2i16:
 357         case nir_op_i2i32:
 358         case nir_op_i2i64:
 359         case nir_op_u2u8:
 360         case nir_op_u2u16:
 361         case nir_op_u2u32:
 362         case nir_op_u2u64:
 363         case nir_op_f2i16:
 364         case nir_op_f2i32:
 365         case nir_op_f2i64:
 366         case nir_op_f2u16:
 367         case nir_op_f2u32:
 368         case nir_op_f2u64:
 369         case nir_op_i2f16:
 370         case nir_op_i2f32:
 371         case nir_op_i2f64:
 372         case nir_op_u2f16:
 373         case nir_op_u2f32:
 374         case nir_op_u2f64:
 375                 return BI_CONVERT;
 376
 377         case nir_op_ffma:
 378         case nir_op_fmul:
 379                 return BI_FMA;
 380
 381         case nir_op_imin:
 382         case nir_op_imax:
 383         case nir_op_umin:
 384         case nir_op_umax:
 385         case nir_op_fmin:
 386         case nir_op_fmax:
 387                 return BI_MINMAX;
 388
 389         case nir_op_fsat:
 390         case nir_op_fneg:
 391         case nir_op_fabs:
 392                 return BI_FMOV;
 393         case nir_op_mov:
 394                 return BI_MOV;
 395
 396         case nir_op_frcp:
 397         case nir_op_frsq:
 398         case nir_op_fsin:
 399         case nir_op_fcos:
 400                 return BI_SPECIAL;
 401
 402         default:
 403                 unreachable("Unknown ALU op");
 404         }
 405 }
 406
 407 static enum bi_cond
 408 bi_cond_for_nir(nir_op op)
 409 {
 410         switch (op) {
 411         case nir_op_flt:
 412         case nir_op_ilt:
 413                 return BI_COND_LT;
 414         case nir_op_fge:
 415         case nir_op_ige:
 416                 return BI_COND_GE;
 417         case nir_op_feq:
 418         case nir_op_ieq:
 419                 return BI_COND_EQ;
 420         case nir_op_fne:
 421         case nir_op_ine:
 422                 return BI_COND_NE;
 423         default:
 424                 unreachable("Invalid compare");
 425         }
 426 }
 427
 428 static void
 429 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 430 {
 431         /* Assume it's something we can handle normally */
 432         bi_instruction alu = {
 433                 .type = bi_class_for_nir_alu(instr->op),
 434                 .dest = bir_dest_index(&instr->dest.dest),
 435                 .dest_type = nir_op_infos[instr->op].output_type
 436                         | nir_dest_bit_size(instr->dest.dest),
 437         };
 438
 439         /* TODO: Implement lowering of special functions for older Bifrost */
 440         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 441
 442         if (instr->dest.dest.is_ssa) {
 443                 /* Construct a writemask */
 444                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 445                 unsigned comps = instr->dest.dest.ssa.num_components;
 446                 assert(comps == 1);
 447                 unsigned bits = bits_per_comp * comps;
 448                 unsigned bytes = MAX2(bits / 8, 1);
 449                 alu.writemask = (1 << bytes) - 1;
 450         } else {
 451                 unsigned comp_mask = instr->dest.write_mask;
 452
 453                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 454                                 comp_mask);
 455         }
 456
 457         /* We inline constants as we go. This tracks how many constants have
 458          * been inlined, since we're limited to 64-bits of constants per
 459          * instruction */
 460
 461         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 462         unsigned constants_left = (64 / dest_bits);
 463         unsigned constant_shift = 0;
 464
 465         /* Copy sources */
 466
 467         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 468         assert(num_inputs <= ARRAY_SIZE(alu.src));
 469
 470         for (unsigned i = 0; i < num_inputs; ++i) {
 471                 unsigned bits = nir_src_bit_size(instr->src[i].src);
 472                 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
 473                         | bits;
 474
 475                 /* Try to inline a constant */
 476                 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
 477                         alu.constant.u64 |=
 478                                 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
 479
 480                         alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
 481                         --constants_left;
 482                         constant_shift += dest_bits;
 483                         continue;
 484                 }
 485
 486                 alu.src[i] = bir_src_index(&instr->src[i].src);
 487
 488                 /* We assert scalarization above */
 489                 alu.swizzle[i][0] = instr->src[i].swizzle[0];
 490         }
 491
 492         /* Op-specific fixup */
 493         switch (instr->op) {
 494         case nir_op_fmul:
 495                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 496                 break;
 497         case nir_op_fsat:
 498                 alu.outmod = BIFROST_SAT; /* FMOV */
 499                 break;
 500         case nir_op_fneg:
 501                 alu.src_neg[0] = true; /* FMOV */
 502                 break;
 503         case nir_op_fabs:
 504                 alu.src_abs[0] = true; /* FMOV */
 505                 break;
 506         case nir_op_fsub:
 507                 alu.src_neg[1] = true; /* FADD */
 508                 break;
 509         case nir_op_fmax:
 510         case nir_op_imax:
 511         case nir_op_umax:
 512                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 513                 break;
 514         case nir_op_frcp:
 515                 alu.op.special = BI_SPECIAL_FRCP;
 516                 break;
 517         case nir_op_frsq:
 518                 alu.op.special = BI_SPECIAL_FRSQ;
 519                 break;
 520         case nir_op_fsin:
 521                 alu.op.special = BI_SPECIAL_FSIN;
 522                 break;
 523         case nir_op_fcos:
 524                 alu.op.special = BI_SPECIAL_FCOS;
 525                 break;
 526         case nir_op_flt:
 527         case nir_op_ilt:
 528         case nir_op_fge:
 529         case nir_op_ige:
 530         case nir_op_feq:
 531         case nir_op_ieq:
 532         case nir_op_fne:
 533         case nir_op_ine:
 534                 alu.op.compare = bi_cond_for_nir(instr->op);
 535                 break;
 536         default:
 537                 break;
 538         }
 539
 540         bi_emit(ctx, alu);
 541 }
 542
 543 static void
 544 emit_instr(bi_context *ctx, struct nir_instr *instr)
 545 {
 546         switch (instr->type) {
 547         case nir_instr_type_load_const:
 548                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 549                 break;
 550
 551         case nir_instr_type_intrinsic:
 552                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 553                 break;
 554
 555         case nir_instr_type_alu:
 556                 emit_alu(ctx, nir_instr_as_alu(instr));
 557                 break;
 558
 559 #if 0
 560         case nir_instr_type_tex:
 561                 emit_tex(ctx, nir_instr_as_tex(instr));
 562                 break;
 563 #endif
 564
 565         case nir_instr_type_jump:
 566                 emit_jump(ctx, nir_instr_as_jump(instr));
 567                 break;
 568
 569         case nir_instr_type_ssa_undef:
 570                 /* Spurious */
 571                 break;
 572
 573         default:
 574                 //unreachable("Unhandled instruction type");
 575                 break;
 576         }
 577 }
 578
 579
 580
 581 static bi_block *
 582 create_empty_block(bi_context *ctx)
 583 {
 584         bi_block *blk = rzalloc(ctx, bi_block);
 585
 586         blk->base.predecessors = _mesa_set_create(blk,
 587                         _mesa_hash_pointer,
 588                         _mesa_key_pointer_equal);
 589
 590         blk->base.name = ctx->block_name_count++;
 591
 592         return blk;
 593 }
 594
 595 static void
 596 bi_schedule_barrier(bi_context *ctx)
 597 {
 598         bi_block *temp = ctx->after_block;
 599         ctx->after_block = create_empty_block(ctx);
 600         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 601         list_inithead(&ctx->after_block->base.instructions);
 602         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 603         ctx->current_block = ctx->after_block;
 604         ctx->after_block = temp;
 605 }
 606
 607 static bi_block *
 608 emit_block(bi_context *ctx, nir_block *block)
 609 {
 610         if (ctx->after_block) {
 611                 ctx->current_block = ctx->after_block;
 612                 ctx->after_block = NULL;
 613         } else {
 614                 ctx->current_block = create_empty_block(ctx);
 615         }
 616
 617         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 618         list_inithead(&ctx->current_block->base.instructions);
 619
 620         nir_foreach_instr(instr, block) {
 621                 emit_instr(ctx, instr);
 622                 ++ctx->instruction_count;
 623         }
 624
 625         return ctx->current_block;
 626 }
 627
 628 /* Emits an unconditional branch to the end of the current block, returning a
 629  * pointer so the user can fill in details */
 630
 631 static bi_instruction *
 632 bi_emit_branch(bi_context *ctx)
 633 {
 634         bi_instruction branch = {
 635                 .type = BI_BRANCH,
 636                 .branch = {
 637                         .cond = BI_COND_ALWAYS
 638                 }
 639         };
 640
 641         return bi_emit(ctx, branch);
 642 }
 643
 644 /* Sets a condition for a branch by examing the NIR condition. If we're
 645  * familiar with the condition, we unwrap it to fold it into the branch
 646  * instruction. Otherwise, we consume the condition directly. We
 647  * generally use 1-bit booleans which allows us to use small types for
 648  * the conditions.
 649  */
 650
 651 static void
 652 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 653 {
 654         /* TODO: Try to unwrap instead of always bailing */
 655         branch->src[0] = bir_src_index(cond);
 656         branch->src[1] = BIR_INDEX_ZERO;
 657         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 658         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 659 }
 660
 661 static void
 662 emit_if(bi_context *ctx, nir_if *nif)
 663 {
 664         bi_block *before_block = ctx->current_block;
 665
 666         /* Speculatively emit the branch, but we can't fill it in until later */
 667         bi_instruction *then_branch = bi_emit_branch(ctx);
 668         bi_set_branch_cond(then_branch, &nif->condition, true);
 669
 670         /* Emit the two subblocks. */
 671         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 672         bi_block *end_then_block = ctx->current_block;
 673
 674         /* Emit a jump from the end of the then block to the end of the else */
 675         bi_instruction *then_exit = bi_emit_branch(ctx);
 676
 677         /* Emit second block, and check if it's empty */
 678
 679         int count_in = ctx->instruction_count;
 680         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 681         bi_block *end_else_block = ctx->current_block;
 682         ctx->after_block = create_empty_block(ctx);
 683
 684         /* Now that we have the subblocks emitted, fix up the branches */
 685
 686         assert(then_block);
 687         assert(else_block);
 688
 689         if (ctx->instruction_count == count_in) {
 690                 /* The else block is empty, so don't emit an exit jump */
 691                 bi_remove_instruction(then_exit);
 692                 then_branch->branch.target = ctx->after_block;
 693         } else {
 694                 then_branch->branch.target = else_block;
 695                 then_exit->branch.target = ctx->after_block;
 696                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 697         }
 698
 699         /* Wire up the successors */
 700
 701         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 702
 703         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 704         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 705 }
 706
 707 static void
 708 emit_loop(bi_context *ctx, nir_loop *nloop)
 709 {
 710         /* Remember where we are */
 711         bi_block *start_block = ctx->current_block;
 712
 713         bi_block *saved_break = ctx->break_block;
 714         bi_block *saved_continue = ctx->continue_block;
 715
 716         ctx->continue_block = create_empty_block(ctx);
 717         ctx->break_block = create_empty_block(ctx);
 718         ctx->after_block = ctx->continue_block;
 719
 720         /* Emit the body itself */
 721         emit_cf_list(ctx, &nloop->body);
 722
 723         /* Branch back to loop back */
 724         bi_instruction *br_back = bi_emit_branch(ctx);
 725         br_back->branch.target = ctx->continue_block;
 726         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 727         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 728
 729         ctx->after_block = ctx->break_block;
 730
 731         /* Pop off */
 732         ctx->break_block = saved_break;
 733         ctx->continue_block = saved_continue;
 734         ++ctx->loop_count;
 735 }
 736
 737 static bi_block *
 738 emit_cf_list(bi_context *ctx, struct exec_list *list)
 739 {
 740         bi_block *start_block = NULL;
 741
 742         foreach_list_typed(nir_cf_node, node, node, list) {
 743                 switch (node->type) {
 744                 case nir_cf_node_block: {
 745                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 746
 747                         if (!start_block)
 748                                 start_block = block;
 749
 750                         break;
 751                 }
 752
 753                 case nir_cf_node_if:
 754                         emit_if(ctx, nir_cf_node_as_if(node));
 755                         break;
 756
 757                 case nir_cf_node_loop:
 758                         emit_loop(ctx, nir_cf_node_as_loop(node));
 759                         break;
 760
 761                 default:
 762                         unreachable("Unknown control flow");
 763                 }
 764         }
 765
 766         return start_block;
 767 }
 768
 769 static int
 770 glsl_type_size(const struct glsl_type *type, bool bindless)
 771 {
 772         return glsl_count_attribute_slots(type, false);
 773 }
 774
 775 static void
 776 bi_optimize_nir(nir_shader *nir)
 777 {
 778         bool progress;
 779         unsigned lower_flrp = 16 | 32 | 64;
 780
 781         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 782         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 783
 784         nir_lower_tex_options lower_tex_options = {
 785                 .lower_txs_lod = true,
 786                 .lower_txp = ~0,
 787                 .lower_tex_without_implicit_lod = true,
 788                 .lower_txd = true,
 789         };
 790
 791         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 792         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 793         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 794
 795         do {
 796                 progress = false;
 797
 798                 NIR_PASS(progress, nir, nir_lower_var_copies);
 799                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 800
 801                 NIR_PASS(progress, nir, nir_copy_prop);
 802                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 803                 NIR_PASS(progress, nir, nir_opt_dce);
 804                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 805                 NIR_PASS(progress, nir, nir_opt_cse);
 806                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 807                 NIR_PASS(progress, nir, nir_opt_algebraic);
 808                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 809
 810                 if (lower_flrp != 0) {
 811                         bool lower_flrp_progress = false;
 812                         NIR_PASS(lower_flrp_progress,
 813                                  nir,
 814                                  nir_lower_flrp,
 815                                  lower_flrp,
 816                                  false /* always_precise */,
 817                                  nir->options->lower_ffma);
 818                         if (lower_flrp_progress) {
 819                                 NIR_PASS(progress, nir,
 820                                          nir_opt_constant_folding);
 821                                 progress = true;
 822                         }
 823
 824                         /* Nothing should rematerialize any flrps, so we only
 825                          * need to do this lowering once.
 826                          */
 827                         lower_flrp = 0;
 828                 }
 829
 830                 NIR_PASS(progress, nir, nir_opt_undef);
 831                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 832                          nir_var_shader_in |
 833                          nir_var_shader_out |
 834                          nir_var_function_temp);
 835         } while (progress);
 836
 837         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 838         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 839         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 840         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 841
 842         /* Take us out of SSA */
 843         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 844         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 845
 846         /* We're a primary scalar architecture but there's enough vector that
 847          * we use a vector IR so let's not also deal with scalar hacks on top
 848          * of the vector hacks */
 849
 850         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 851         NIR_PASS(progress, nir, nir_lower_vec_to_movs);
 852         NIR_PASS(progress, nir, nir_opt_dce);
 853 }
 854
 855 static void
 856 bi_insert_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp)
 857 {
 858         bi_instruction move = {
 859                 .type = BI_MOV,
 860                 .dest = parent->dest,
 861                 .dest_type = nir_type_uint32,
 862                 .writemask = (0xF << (4 * comp)),
 863                 .src = { parent->src[0] },
 864                 .src_types = { nir_type_uint32 },
 865                 .swizzle = { { comp } }
 866         };
 867
 868         bi_emit_before(ctx, parent, move);
 869 }
 870
 871 static void
 872 bi_lower_mov(bi_context *ctx, bi_block *block)
 873 {
 874         bi_foreach_instr_in_block_safe(block, ins) {
 875                 if (ins->type != BI_MOV) continue;
 876                 if (util_bitcount(ins->writemask) <= 4) continue;
 877
 878                 for (unsigned i = 0; i < 4; ++i) {
 879                         unsigned quad = (ins->writemask >> (4 * i)) & 0xF;
 880
 881                         if (quad == 0)
 882                                 continue;
 883                         else if (quad == 0xF)
 884                                 bi_insert_mov32(ctx, ins, i);
 885                         else
 886                                 unreachable("TODO: Lowering <32bit moves");
 887                 }
 888
 889                 bi_remove_instruction(ins);
 890         }
 891 }
 892
 893 void
 894 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 895 {
 896         bi_context *ctx = rzalloc(NULL, bi_context);
 897         ctx->nir = nir;
 898         ctx->stage = nir->info.stage;
 899         ctx->quirks = bifrost_get_quirks(product_id);
 900         list_inithead(&ctx->blocks);
 901
 902         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 903          * (so we don't accidentally duplicate the epilogue since mesa/st has
 904          * messed with our I/O quite a bit already) */
 905
 906         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 907
 908         if (ctx->stage == MESA_SHADER_VERTEX) {
 909                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 910                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 911         }
 912
 913         NIR_PASS_V(nir, nir_split_var_copies);
 914         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 915         NIR_PASS_V(nir, nir_lower_var_copies);
 916         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 917         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 918         NIR_PASS_V(nir, nir_lower_ssbo);
 919
 920         bi_optimize_nir(nir);
 921         nir_print_shader(nir, stdout);
 922
 923         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 924         program->sysval_count = ctx->sysvals.sysval_count;
 925         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 926
 927         nir_foreach_function(func, nir) {
 928                 if (!func->impl)
 929                         continue;
 930
 931                 ctx->impl = func->impl;
 932                 emit_cf_list(ctx, &func->impl->body);
 933                 break; /* TODO: Multi-function shaders */
 934         }
 935
 936         bi_foreach_block(ctx, _block) {
 937                 bi_block *block = (bi_block *) _block;
 938                 bi_lower_mov(ctx, block);
 939         }
 940
 941         bool progress = false;
 942
 943         do {
 944                 progress = false;
 945
 946                 bi_foreach_block(ctx, _block) {
 947                         bi_block *block = (bi_block *) _block;
 948                         progress |= bi_opt_dead_code_eliminate(ctx, block);
 949                 }
 950         } while(progress);
 951
 952         bi_print_shader(ctx, stdout);
 953         bi_schedule(ctx);
 954         bi_register_allocate(ctx);
 955         bi_print_shader(ctx, stdout);
 956         bi_pack(ctx, &program->compiled);
 957         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
 958
 959         ralloc_free(ctx);
 960 }