2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "util/u_debug.h"
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "bifrost_nir.h"
37 #include "bi_quirks.h"
40 static const struct debug_named_value debug_options
[] = {
41 {"msgs", BIFROST_DBG_MSGS
, "Print debug messages"},
42 {"shaders", BIFROST_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
46 DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug
, "BIFROST_MESA_DEBUG", debug_options
, 0)
48 int bifrost_debug
= 0;
50 #define DBG(fmt, ...) \
51 do { if (bifrost_debug & BIFROST_DBG_MSGS) \
52 fprintf(stderr, "%s:%d: "fmt, \
53 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
55 static bi_block
*emit_cf_list(bi_context
*ctx
, struct exec_list
*list
);
56 static bi_instruction
*bi_emit_branch(bi_context
*ctx
);
59 emit_jump(bi_context
*ctx
, nir_jump_instr
*instr
)
61 bi_instruction
*branch
= bi_emit_branch(ctx
);
63 switch (instr
->type
) {
65 branch
->branch_target
= ctx
->break_block
;
67 case nir_jump_continue
:
68 branch
->branch_target
= ctx
->continue_block
;
71 unreachable("Unhandled jump type");
74 pan_block_add_successor(&ctx
->current_block
->base
, &branch
->branch_target
->base
);
78 bi_load(enum bi_class T
, nir_intrinsic_instr
*instr
)
80 bi_instruction load
= {
82 .vector_channels
= instr
->num_components
,
83 .src
= { BIR_INDEX_CONSTANT
},
84 .src_types
= { nir_type_uint32
},
85 .constant
= { .u64
= nir_intrinsic_base(instr
) },
88 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
91 load
.dest
= pan_dest_index(&instr
->dest
);
93 if (info
->has_dest
&& info
->index_map
[NIR_INTRINSIC_TYPE
] > 0)
94 load
.dest_type
= nir_intrinsic_type(instr
);
96 nir_src
*offset
= nir_get_io_offset_src(instr
);
98 if (nir_src_is_const(*offset
))
99 load
.constant
.u64
+= nir_src_as_uint(*offset
);
101 load
.src
[0] = pan_src_index(offset
);
107 bi_emit_ld_vary(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
109 bi_instruction ins
= bi_load(BI_LOAD_VAR
, instr
);
110 ins
.load_vary
.interp_mode
= BIFROST_INTERP_DEFAULT
; /* TODO */
111 ins
.load_vary
.reuse
= false; /* TODO */
112 ins
.load_vary
.flat
= instr
->intrinsic
!= nir_intrinsic_load_interpolated_input
;
113 ins
.dest_type
= nir_type_float
| nir_dest_bit_size(instr
->dest
);
115 if (nir_src_is_const(*nir_get_io_offset_src(instr
))) {
116 /* Zero it out for direct */
117 ins
.src
[1] = BIR_INDEX_ZERO
;
119 /* R61 contains sample mask stuff, TODO RA XXX */
120 ins
.src
[1] = BIR_INDEX_REGISTER
| 61;
127 bi_emit_frag_out(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
129 if (!ctx
->emitted_atest
) {
130 bi_instruction ins
= {
133 BIR_INDEX_REGISTER
| 60 /* TODO: RA */,
134 pan_src_index(&instr
->src
[0])
138 nir_intrinsic_type(instr
)
142 { 3, 0 } /* swizzle out the alpha */
144 .dest
= BIR_INDEX_REGISTER
| 60 /* TODO: RA */,
145 .dest_type
= nir_type_uint32
,
149 ctx
->emitted_atest
= true;
152 bi_instruction blend
= {
154 .blend_location
= nir_intrinsic_base(instr
),
156 pan_src_index(&instr
->src
[0]),
157 BIR_INDEX_REGISTER
| 60 /* Can this be arbitrary? */,
160 nir_intrinsic_type(instr
),
167 .dest
= BIR_INDEX_REGISTER
| 48 /* Looks like magic */,
168 .dest_type
= nir_type_uint32
,
172 assert(blend
.blend_location
< BIFROST_MAX_RENDER_TARGET_COUNT
);
173 assert(ctx
->blend_types
);
174 assert(blend
.src_types
[0]);
175 ctx
->blend_types
[blend
.blend_location
] = blend
.src_types
[0];
180 static bi_instruction
181 bi_load_with_r61(enum bi_class T
, nir_intrinsic_instr
*instr
)
183 bi_instruction ld
= bi_load(T
, instr
);
184 ld
.src
[1] = BIR_INDEX_REGISTER
| 61; /* TODO: RA */
185 ld
.src
[2] = BIR_INDEX_REGISTER
| 62;
187 ld
.src_types
[1] = nir_type_uint32
;
188 ld
.src_types
[2] = nir_type_uint32
;
189 ld
.src_types
[3] = nir_intrinsic_type(instr
);
194 bi_emit_st_vary(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
196 bi_instruction address
= bi_load_with_r61(BI_LOAD_VAR_ADDRESS
, instr
);
197 address
.dest
= bi_make_temp(ctx
);
198 address
.dest_type
= nir_type_uint32
;
199 address
.vector_channels
= 3;
201 unsigned nr
= nir_intrinsic_src_components(instr
, 0);
202 assert(nir_intrinsic_write_mask(instr
) == ((1 << nr
) - 1));
204 bi_instruction st
= {
205 .type
= BI_STORE_VAR
,
207 pan_src_index(&instr
->src
[0]),
208 address
.dest
, address
.dest
, address
.dest
,
212 nir_type_uint32
, nir_type_uint32
, nir_type_uint32
,
218 .vector_channels
= nr
,
221 for (unsigned i
= 0; i
< nr
; ++i
)
222 st
.swizzle
[0][i
] = i
;
224 bi_emit(ctx
, address
);
229 bi_emit_ld_uniform(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
231 bi_instruction ld
= bi_load(BI_LOAD_UNIFORM
, instr
);
232 ld
.src
[1] = BIR_INDEX_ZERO
; /* TODO: UBO index */
234 /* TODO: Indirect access, since we need to multiply by the element
235 * size. I believe we can get this lowering automatically via
236 * nir_lower_io (as mul instructions) with the proper options, but this
238 assert(ld
.src
[0] & BIR_INDEX_CONSTANT
);
239 ld
.constant
.u64
+= ctx
->sysvals
.sysval_count
;
240 ld
.constant
.u64
*= 16;
246 bi_emit_sysval(bi_context
*ctx
, nir_instr
*instr
,
247 unsigned nr_components
, unsigned offset
)
251 /* Figure out which uniform this is */
252 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
253 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
255 /* Sysvals are prefix uniforms */
256 unsigned uniform
= ((uintptr_t) val
) - 1;
258 /* Emit the read itself -- this is never indirect */
260 bi_instruction load
= {
261 .type
= BI_LOAD_UNIFORM
,
262 .vector_channels
= nr_components
,
263 .src
= { BIR_INDEX_CONSTANT
, BIR_INDEX_ZERO
},
264 .src_types
= { nir_type_uint32
, nir_type_uint32
},
265 .constant
= { (uniform
* 16) + offset
},
266 .dest
= pan_dest_index(&nir_dest
),
267 .dest_type
= nir_type_uint32
, /* TODO */
273 /* gl_FragCoord.xy = u16_to_f32(R59.xy) + 0.5
274 * gl_FragCoord.z = ld_vary(fragz)
275 * gl_FragCoord.w = ld_vary(fragw)
279 bi_emit_ld_frag_coord(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
281 /* Future proofing for mediump fragcoord at some point.. */
282 nir_alu_type T
= nir_type_float32
;
284 /* First, sketch a combine */
285 bi_instruction combine
= {
287 .dest_type
= nir_type_uint32
,
288 .dest
= pan_dest_index(&instr
->dest
),
289 .src_types
= { T
, T
, T
, T
},
292 /* Second, handle xy */
293 for (unsigned i
= 0; i
< 2; ++i
) {
294 bi_instruction conv
= {
297 .dest
= bi_make_temp(ctx
),
300 BIR_INDEX_REGISTER
| 59
302 .src_types
= { nir_type_uint16
},
306 bi_instruction add
= {
309 .dest
= bi_make_temp(ctx
),
310 .src
= { conv
.dest
, BIR_INDEX_CONSTANT
},
311 .src_types
= { T
, T
},
315 memcpy(&add
.constant
.u32
, &half
, sizeof(float));
320 combine
.src
[i
] = add
.dest
;
324 for (unsigned i
= 0; i
< 2; ++i
) {
325 bi_instruction load
= {
328 .interp_mode
= BIFROST_INTERP_DEFAULT
,
332 .vector_channels
= 1,
333 .dest_type
= nir_type_float32
,
334 .dest
= bi_make_temp(ctx
),
335 .src
= { BIR_INDEX_CONSTANT
, BIR_INDEX_ZERO
},
336 .src_types
= { nir_type_uint32
, nir_type_uint32
},
338 .u32
= (i
== 0) ? BIFROST_FRAGZ
: BIFROST_FRAGW
344 combine
.src
[i
+ 2] = load
.dest
;
347 /* Finally, emit the combine */
348 bi_emit(ctx
, combine
);
352 bi_emit_discard(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
355 bi_instruction discard
= {
358 .src_types
= { nir_type_uint32
, nir_type_uint32
},
359 .src
= { BIR_INDEX_ZERO
, BIR_INDEX_ZERO
},
362 bi_emit(ctx
, discard
);
366 bi_fuse_cond(bi_instruction
*csel
, nir_alu_src cond
,
367 unsigned *constants_left
, unsigned *constant_shift
,
368 unsigned comps
, bool float_only
);
371 bi_emit_discard_if(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
373 nir_src cond
= instr
->src
[0];
374 nir_alu_type T
= nir_type_uint
| nir_src_bit_size(cond
);
376 bi_instruction discard
= {
379 .src_types
= { T
, T
},
381 pan_src_index(&cond
),
386 /* Try to fuse in the condition */
387 unsigned constants_left
= 1, constant_shift
= 0;
389 /* Scalar so no swizzle */
394 /* May or may not succeed but we're optimistic */
395 bi_fuse_cond(&discard
, wrap
, &constants_left
, &constant_shift
, 1, true);
397 bi_emit(ctx
, discard
);
401 emit_intrinsic(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
404 switch (instr
->intrinsic
) {
405 case nir_intrinsic_load_barycentric_pixel
:
408 case nir_intrinsic_load_interpolated_input
:
409 case nir_intrinsic_load_input
:
410 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
411 bi_emit_ld_vary(ctx
, instr
);
412 else if (ctx
->stage
== MESA_SHADER_VERTEX
)
413 bi_emit(ctx
, bi_load_with_r61(BI_LOAD_ATTR
, instr
));
415 unreachable("Unsupported shader stage");
419 case nir_intrinsic_store_output
:
420 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
421 bi_emit_frag_out(ctx
, instr
);
422 else if (ctx
->stage
== MESA_SHADER_VERTEX
)
423 bi_emit_st_vary(ctx
, instr
);
425 unreachable("Unsupported shader stage");
428 case nir_intrinsic_load_uniform
:
429 bi_emit_ld_uniform(ctx
, instr
);
432 case nir_intrinsic_load_frag_coord
:
433 bi_emit_ld_frag_coord(ctx
, instr
);
436 case nir_intrinsic_discard
:
437 bi_emit_discard(ctx
, instr
);
440 case nir_intrinsic_discard_if
:
441 bi_emit_discard_if(ctx
, instr
);
444 case nir_intrinsic_load_ssbo_address
:
445 bi_emit_sysval(ctx
, &instr
->instr
, 1, 0);
448 case nir_intrinsic_get_buffer_size
:
449 bi_emit_sysval(ctx
, &instr
->instr
, 1, 8);
452 case nir_intrinsic_load_viewport_scale
:
453 case nir_intrinsic_load_viewport_offset
:
454 case nir_intrinsic_load_num_work_groups
:
455 case nir_intrinsic_load_sampler_lod_parameters_pan
:
456 bi_emit_sysval(ctx
, &instr
->instr
, 3, 0);
460 unreachable("Unknown intrinsic");
466 emit_load_const(bi_context
*ctx
, nir_load_const_instr
*instr
)
468 /* Make sure we've been lowered */
469 assert(instr
->def
.num_components
== 1);
471 bi_instruction move
= {
473 .dest
= pan_ssa_index(&instr
->def
),
474 .dest_type
= instr
->def
.bit_size
| nir_type_uint
,
479 instr
->def
.bit_size
| nir_type_uint
,
482 .u64
= nir_const_value_as_uint(instr
->value
[0], instr
->def
.bit_size
)
489 #define BI_CASE_CMP(op) \
495 bi_class_for_nir_alu(nir_op op
)
511 BI_CASE_CMP(nir_op_flt
)
512 BI_CASE_CMP(nir_op_fge
)
513 BI_CASE_CMP(nir_op_feq
)
514 BI_CASE_CMP(nir_op_fne
)
515 BI_CASE_CMP(nir_op_ilt
)
516 BI_CASE_CMP(nir_op_ige
)
517 BI_CASE_CMP(nir_op_ieq
)
518 BI_CASE_CMP(nir_op_ine
)
559 unreachable("should've been lowered");
580 case nir_op_fround_even
:
591 unreachable("Unknown ALU op");
595 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
596 * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
597 * optimizations). Otherwise it will bail (when used for primary code
601 bi_cond_for_nir(nir_op op
, bool soft
)
604 BI_CASE_CMP(nir_op_flt
)
605 BI_CASE_CMP(nir_op_ilt
)
608 BI_CASE_CMP(nir_op_fge
)
609 BI_CASE_CMP(nir_op_ige
)
612 BI_CASE_CMP(nir_op_feq
)
613 BI_CASE_CMP(nir_op_ieq
)
616 BI_CASE_CMP(nir_op_fne
)
617 BI_CASE_CMP(nir_op_ine
)
621 return BI_COND_ALWAYS
;
623 unreachable("Invalid compare");
628 bi_copy_src(bi_instruction
*alu
, nir_alu_instr
*instr
, unsigned i
, unsigned to
,
629 unsigned *constants_left
, unsigned *constant_shift
, unsigned comps
)
631 unsigned bits
= nir_src_bit_size(instr
->src
[i
].src
);
632 unsigned dest_bits
= nir_dest_bit_size(instr
->dest
.dest
);
634 alu
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
]
637 /* Try to inline a constant */
638 if (nir_src_is_const(instr
->src
[i
].src
) && *constants_left
&& (dest_bits
== bits
)) {
639 uint64_t mask
= (1ull << dest_bits
) - 1;
640 uint64_t cons
= nir_src_as_uint(instr
->src
[i
].src
);
642 /* Try to reuse a constant */
643 for (unsigned i
= 0; i
< (*constant_shift
); i
+= dest_bits
) {
644 if (((alu
->constant
.u64
>> i
) & mask
) == cons
) {
645 alu
->src
[to
] = BIR_INDEX_CONSTANT
| i
;
650 alu
->constant
.u64
|= cons
<< *constant_shift
;
651 alu
->src
[to
] = BIR_INDEX_CONSTANT
| (*constant_shift
);
653 (*constant_shift
) += MAX2(dest_bits
, 32); /* lo/hi */
657 alu
->src
[to
] = pan_src_index(&instr
->src
[i
].src
);
659 /* Copy swizzle for all vectored components, replicating last component
660 * to fill undersized */
662 unsigned vec
= alu
->type
== BI_COMBINE
? 1 :
663 MAX2(1, 32 / dest_bits
);
665 for (unsigned j
= 0; j
< vec
; ++j
)
666 alu
->swizzle
[to
][j
] = instr
->src
[i
].swizzle
[MIN2(j
, comps
- 1)];
670 bi_fuse_cond(bi_instruction
*csel
, nir_alu_src cond
,
671 unsigned *constants_left
, unsigned *constant_shift
,
672 unsigned comps
, bool float_only
)
674 /* Bail for vector weirdness */
675 if (cond
.swizzle
[0] != 0)
678 if (!cond
.src
.is_ssa
)
681 nir_ssa_def
*def
= cond
.src
.ssa
;
682 nir_instr
*parent
= def
->parent_instr
;
684 if (parent
->type
!= nir_instr_type_alu
)
687 nir_alu_instr
*alu
= nir_instr_as_alu(parent
);
689 /* Try to match a condition */
690 enum bi_cond bcond
= bi_cond_for_nir(alu
->op
, true);
692 if (bcond
== BI_COND_ALWAYS
)
695 /* Some instructions can't compare ints */
697 nir_alu_type T
= nir_op_infos
[alu
->op
].input_types
[0];
698 T
= nir_alu_type_get_base_type(T
);
700 if (T
!= nir_type_float
)
704 /* We found one, let's fuse it in */
706 bi_copy_src(csel
, alu
, 0, 0, constants_left
, constant_shift
, comps
);
707 bi_copy_src(csel
, alu
, 1, 1, constants_left
, constant_shift
, comps
);
711 emit_alu(bi_context
*ctx
, nir_alu_instr
*instr
)
713 /* Try some special functions */
716 bi_emit_fexp2(ctx
, instr
);
719 bi_emit_flog2(ctx
, instr
);
725 /* Otherwise, assume it's something we can handle normally */
726 bi_instruction alu
= {
727 .type
= bi_class_for_nir_alu(instr
->op
),
728 .dest
= pan_dest_index(&instr
->dest
.dest
),
729 .dest_type
= nir_op_infos
[instr
->op
].output_type
730 | nir_dest_bit_size(instr
->dest
.dest
),
733 /* TODO: Implement lowering of special functions for older Bifrost */
734 assert((alu
.type
!= BI_SPECIAL
) || !(ctx
->quirks
& BIFROST_NO_FAST_OP
));
736 unsigned comps
= nir_dest_num_components(instr
->dest
.dest
);
738 if (alu
.type
!= BI_COMBINE
)
739 assert(comps
<= MAX2(1, 32 / comps
));
741 if (!instr
->dest
.dest
.is_ssa
) {
742 for (unsigned i
= 0; i
< comps
; ++i
)
743 assert(instr
->dest
.write_mask
);
746 /* We inline constants as we go. This tracks how many constants have
747 * been inlined, since we're limited to 64-bits of constants per
750 unsigned dest_bits
= nir_dest_bit_size(instr
->dest
.dest
);
751 unsigned constants_left
= (64 / dest_bits
);
752 unsigned constant_shift
= 0;
754 if (alu
.type
== BI_COMBINE
)
759 unsigned num_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
760 assert(num_inputs
<= ARRAY_SIZE(alu
.src
));
762 for (unsigned i
= 0; i
< num_inputs
; ++i
) {
765 if (i
&& alu
.type
== BI_CSEL
)
768 bi_copy_src(&alu
, instr
, i
, i
+ f
, &constants_left
, &constant_shift
, comps
);
771 /* Op-specific fixup */
774 alu
.src
[2] = BIR_INDEX_ZERO
; /* FMA */
775 alu
.src_types
[2] = alu
.src_types
[1];
778 alu
.outmod
= BIFROST_SAT
; /* FMOV */
781 alu
.src_neg
[0] = true; /* FMOV */
784 alu
.src_abs
[0] = true; /* FMOV */
787 alu
.src_neg
[1] = true; /* FADD */
790 alu
.op
.imath
= BI_IMATH_ADD
;
793 alu
.op
.imath
= BI_IMATH_SUB
;
798 alu
.op
.minmax
= BI_MINMAX_MAX
; /* MINMAX */
801 alu
.op
.special
= BI_SPECIAL_FRCP
;
804 alu
.op
.special
= BI_SPECIAL_FRSQ
;
806 BI_CASE_CMP(nir_op_flt
)
807 BI_CASE_CMP(nir_op_ilt
)
808 BI_CASE_CMP(nir_op_fge
)
809 BI_CASE_CMP(nir_op_ige
)
810 BI_CASE_CMP(nir_op_feq
)
811 BI_CASE_CMP(nir_op_ieq
)
812 BI_CASE_CMP(nir_op_fne
)
813 BI_CASE_CMP(nir_op_ine
)
814 alu
.cond
= bi_cond_for_nir(instr
->op
, false);
816 case nir_op_fround_even
:
817 alu
.roundmode
= BIFROST_RTE
;
820 alu
.roundmode
= BIFROST_RTP
;
823 alu
.roundmode
= BIFROST_RTN
;
826 alu
.roundmode
= BIFROST_RTZ
;
829 alu
.op
.bitwise
= BI_BITWISE_AND
;
832 alu
.op
.bitwise
= BI_BITWISE_OR
;
835 alu
.op
.bitwise
= BI_BITWISE_XOR
;
841 if (nir_src_bit_size(instr
->src
[0].src
) != 32)
844 /* Should have been const folded */
845 assert(!nir_src_is_const(instr
->src
[0].src
));
847 alu
.src_types
[1] = alu
.src_types
[0];
848 alu
.src
[1] = alu
.src
[0];
850 unsigned last
= nir_dest_num_components(instr
->dest
.dest
) - 1;
853 alu
.swizzle
[1][0] = instr
->src
[0].swizzle
[last
];
861 if (alu
.type
== BI_CSEL
) {
862 /* Default to csel3 */
863 alu
.cond
= BI_COND_NE
;
864 alu
.src
[1] = BIR_INDEX_ZERO
;
865 alu
.src_types
[1] = alu
.src_types
[0];
867 /* TODO: Reenable cond fusing when we can split up registers
870 bi_fuse_cond(&alu
, instr
->src
[0],
871 &constants_left
, &constant_shift
, comps
, false);
873 } else if (alu
.type
== BI_BITWISE
) {
874 /* Implicit shift argument... at some point we should fold */
875 alu
.src
[2] = BIR_INDEX_ZERO
;
876 alu
.src_types
[2] = alu
.src_types
[1];
882 /* TEX_COMPACT instructions assume normal 2D f32 operation but are more
883 * space-efficient and with simpler RA/scheduling requirements*/
886 emit_tex_compact(bi_context
*ctx
, nir_tex_instr
*instr
)
888 bi_instruction tex
= {
890 .op
= { .texture
= BI_TEX_COMPACT
},
892 .texture_index
= instr
->texture_index
,
893 .sampler_index
= instr
->sampler_index
,
895 .dest
= pan_dest_index(&instr
->dest
),
896 .dest_type
= instr
->dest_type
,
897 .src_types
= { nir_type_float32
, nir_type_float32
},
901 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
902 int index
= pan_src_index(&instr
->src
[i
].src
);
904 /* We were checked ahead-of-time */
905 if (instr
->src
[i
].src_type
== nir_tex_src_lod
)
908 assert (instr
->src
[i
].src_type
== nir_tex_src_coord
);
912 tex
.swizzle
[0][0] = 0;
913 tex
.swizzle
[1][0] = 1;
920 emit_tex_full(bi_context
*ctx
, nir_tex_instr
*instr
)
925 /* Normal textures ops are tex for frag shaders and txl for vertex shaders with
926 * lod a constant 0. Anything else needs a full texture op. */
929 bi_is_normal_tex(gl_shader_stage stage
, nir_tex_instr
*instr
)
931 if (stage
== MESA_SHADER_FRAGMENT
)
932 return instr
->op
== nir_texop_tex
;
934 if (instr
->op
!= nir_texop_txl
)
937 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
938 if (instr
->src
[i
].src_type
!= nir_tex_src_lod
)
941 nir_src src
= instr
->src
[i
].src
;
943 if (!nir_src_is_const(src
))
946 if (nir_src_as_uint(src
) != 0)
954 emit_tex(bi_context
*ctx
, nir_tex_instr
*instr
)
956 nir_alu_type base
= nir_alu_type_get_base_type(instr
->dest_type
);
957 unsigned sz
= nir_dest_bit_size(instr
->dest
);
958 instr
->dest_type
= base
| sz
;
960 bool is_normal
= bi_is_normal_tex(ctx
->stage
, instr
);
961 bool is_2d
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
962 instr
->sampler_dim
== GLSL_SAMPLER_DIM_EXTERNAL
;
963 bool is_f
= base
== nir_type_float
&& (sz
== 16 || sz
== 32);
965 bool is_compact
= is_normal
&& is_2d
&& is_f
&& !instr
->is_shadow
;
968 emit_tex_compact(ctx
, instr
);
970 emit_tex_full(ctx
, instr
);
974 emit_instr(bi_context
*ctx
, struct nir_instr
*instr
)
976 switch (instr
->type
) {
977 case nir_instr_type_load_const
:
978 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
981 case nir_instr_type_intrinsic
:
982 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
985 case nir_instr_type_alu
:
986 emit_alu(ctx
, nir_instr_as_alu(instr
));
989 case nir_instr_type_tex
:
990 emit_tex(ctx
, nir_instr_as_tex(instr
));
993 case nir_instr_type_jump
:
994 emit_jump(ctx
, nir_instr_as_jump(instr
));
997 case nir_instr_type_ssa_undef
:
1002 unreachable("Unhandled instruction type");
1010 create_empty_block(bi_context
*ctx
)
1012 bi_block
*blk
= rzalloc(ctx
, bi_block
);
1014 blk
->base
.predecessors
= _mesa_set_create(blk
,
1016 _mesa_key_pointer_equal
);
1022 emit_block(bi_context
*ctx
, nir_block
*block
)
1024 if (ctx
->after_block
) {
1025 ctx
->current_block
= ctx
->after_block
;
1026 ctx
->after_block
= NULL
;
1028 ctx
->current_block
= create_empty_block(ctx
);
1031 list_addtail(&ctx
->current_block
->base
.link
, &ctx
->blocks
);
1032 list_inithead(&ctx
->current_block
->base
.instructions
);
1034 nir_foreach_instr(instr
, block
) {
1035 emit_instr(ctx
, instr
);
1036 ++ctx
->instruction_count
;
1039 return ctx
->current_block
;
1042 /* Emits an unconditional branch to the end of the current block, returning a
1043 * pointer so the user can fill in details */
1045 static bi_instruction
*
1046 bi_emit_branch(bi_context
*ctx
)
1048 bi_instruction branch
= {
1050 .cond
= BI_COND_ALWAYS
1053 return bi_emit(ctx
, branch
);
1056 /* Sets a condition for a branch by examing the NIR condition. If we're
1057 * familiar with the condition, we unwrap it to fold it into the branch
1058 * instruction. Otherwise, we consume the condition directly. We
1059 * generally use 1-bit booleans which allows us to use small types for
1064 bi_set_branch_cond(bi_instruction
*branch
, nir_src
*cond
, bool invert
)
1066 /* TODO: Try to unwrap instead of always bailing */
1067 branch
->src
[0] = pan_src_index(cond
);
1068 branch
->src
[1] = BIR_INDEX_ZERO
;
1069 branch
->src_types
[0] = branch
->src_types
[1] = nir_type_uint
|
1070 nir_src_bit_size(*cond
);
1071 branch
->cond
= invert
? BI_COND_EQ
: BI_COND_NE
;
1075 emit_if(bi_context
*ctx
, nir_if
*nif
)
1077 bi_block
*before_block
= ctx
->current_block
;
1079 /* Speculatively emit the branch, but we can't fill it in until later */
1080 bi_instruction
*then_branch
= bi_emit_branch(ctx
);
1081 bi_set_branch_cond(then_branch
, &nif
->condition
, true);
1083 /* Emit the two subblocks. */
1084 bi_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
1085 bi_block
*end_then_block
= ctx
->current_block
;
1087 /* Emit a jump from the end of the then block to the end of the else */
1088 bi_instruction
*then_exit
= bi_emit_branch(ctx
);
1090 /* Emit second block, and check if it's empty */
1092 int count_in
= ctx
->instruction_count
;
1093 bi_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
1094 bi_block
*end_else_block
= ctx
->current_block
;
1095 ctx
->after_block
= create_empty_block(ctx
);
1097 /* Now that we have the subblocks emitted, fix up the branches */
1102 if (ctx
->instruction_count
== count_in
) {
1103 /* The else block is empty, so don't emit an exit jump */
1104 bi_remove_instruction(then_exit
);
1105 then_branch
->branch_target
= ctx
->after_block
;
1106 pan_block_add_successor(&end_then_block
->base
, &ctx
->after_block
->base
); /* fallthrough */
1108 then_branch
->branch_target
= else_block
;
1109 then_exit
->branch_target
= ctx
->after_block
;
1110 pan_block_add_successor(&end_then_block
->base
, &then_exit
->branch_target
->base
);
1111 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
); /* fallthrough */
1114 pan_block_add_successor(&before_block
->base
, &then_branch
->branch_target
->base
); /* then_branch */
1115 pan_block_add_successor(&before_block
->base
, &then_block
->base
); /* fallthrough */
1119 emit_loop(bi_context
*ctx
, nir_loop
*nloop
)
1121 /* Remember where we are */
1122 bi_block
*start_block
= ctx
->current_block
;
1124 bi_block
*saved_break
= ctx
->break_block
;
1125 bi_block
*saved_continue
= ctx
->continue_block
;
1127 ctx
->continue_block
= create_empty_block(ctx
);
1128 ctx
->break_block
= create_empty_block(ctx
);
1129 ctx
->after_block
= ctx
->continue_block
;
1131 /* Emit the body itself */
1132 emit_cf_list(ctx
, &nloop
->body
);
1134 /* Branch back to loop back */
1135 bi_instruction
*br_back
= bi_emit_branch(ctx
);
1136 br_back
->branch_target
= ctx
->continue_block
;
1137 pan_block_add_successor(&start_block
->base
, &ctx
->continue_block
->base
);
1138 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->continue_block
->base
);
1140 ctx
->after_block
= ctx
->break_block
;
1143 ctx
->break_block
= saved_break
;
1144 ctx
->continue_block
= saved_continue
;
1149 emit_cf_list(bi_context
*ctx
, struct exec_list
*list
)
1151 bi_block
*start_block
= NULL
;
1153 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1154 switch (node
->type
) {
1155 case nir_cf_node_block
: {
1156 bi_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
1159 start_block
= block
;
1164 case nir_cf_node_if
:
1165 emit_if(ctx
, nir_cf_node_as_if(node
));
1168 case nir_cf_node_loop
:
1169 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1173 unreachable("Unknown control flow");
1181 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
1183 return glsl_count_attribute_slots(type
, false);
1187 bi_optimize_nir(nir_shader
*nir
)
1190 unsigned lower_flrp
= 16 | 32 | 64;
1192 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
1193 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
1195 nir_lower_tex_options lower_tex_options
= {
1196 .lower_txs_lod
= true,
1198 .lower_tex_without_implicit_lod
= true,
1202 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
1203 NIR_PASS(progress
, nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
1204 NIR_PASS(progress
, nir
, nir_lower_load_const_to_scalar
);
1209 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
1210 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
1212 NIR_PASS(progress
, nir
, nir_copy_prop
);
1213 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
1214 NIR_PASS(progress
, nir
, nir_opt_dce
);
1215 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
1216 NIR_PASS(progress
, nir
, nir_opt_cse
);
1217 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
1218 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
1219 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
1221 if (lower_flrp
!= 0) {
1222 bool lower_flrp_progress
= false;
1223 NIR_PASS(lower_flrp_progress
,
1227 false /* always_precise */,
1228 nir
->options
->lower_ffma
);
1229 if (lower_flrp_progress
) {
1230 NIR_PASS(progress
, nir
,
1231 nir_opt_constant_folding
);
1235 /* Nothing should rematerialize any flrps, so we only
1236 * need to do this lowering once.
1241 NIR_PASS(progress
, nir
, nir_opt_undef
);
1242 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
1244 nir_var_shader_out
|
1245 nir_var_function_temp
);
1248 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
1249 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
1250 NIR_PASS(progress
, nir
, bifrost_nir_lower_algebraic_late
);
1251 NIR_PASS(progress
, nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
1252 NIR_PASS(progress
, nir
, nir_lower_load_const_to_scalar
);
1254 /* Take us out of SSA */
1255 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
1256 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
1257 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
1261 bifrost_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, unsigned product_id
)
1263 bifrost_debug
= debug_get_option_bifrost_debug();
1265 bi_context
*ctx
= rzalloc(NULL
, bi_context
);
1267 ctx
->stage
= nir
->info
.stage
;
1268 ctx
->quirks
= bifrost_get_quirks(product_id
);
1269 list_inithead(&ctx
->blocks
);
1271 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
1272 * (so we don't accidentally duplicate the epilogue since mesa/st has
1273 * messed with our I/O quite a bit already) */
1275 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
1277 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1278 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
1279 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
1282 NIR_PASS_V(nir
, nir_split_var_copies
);
1283 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
1284 NIR_PASS_V(nir
, nir_lower_var_copies
);
1285 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
1286 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
1287 NIR_PASS_V(nir
, nir_lower_ssbo
);
1288 NIR_PASS_V(nir
, nir_lower_mediump_outputs
);
1290 bi_optimize_nir(nir
);
1292 if (bifrost_debug
& BIFROST_DBG_SHADERS
) {
1293 nir_print_shader(nir
, stdout
);
1296 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
1297 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
1298 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
1299 ctx
->blend_types
= program
->blend_types
;
1301 nir_foreach_function(func
, nir
) {
1305 ctx
->impl
= func
->impl
;
1306 emit_cf_list(ctx
, &func
->impl
->body
);
1307 break; /* TODO: Multi-function shaders */
1310 unsigned block_source_count
= 0;
1312 bi_foreach_block(ctx
, _block
) {
1313 bi_block
*block
= (bi_block
*) _block
;
1315 /* Name blocks now that we're done emitting so the order is
1317 block
->base
.name
= block_source_count
++;
1319 bi_lower_combine(ctx
, block
);
1322 bool progress
= false;
1327 bi_foreach_block(ctx
, _block
) {
1328 bi_block
*block
= (bi_block
*) _block
;
1329 progress
|= bi_opt_dead_code_eliminate(ctx
, block
);
1333 if (bifrost_debug
& BIFROST_DBG_SHADERS
)
1334 bi_print_shader(ctx
, stdout
);
1336 bi_register_allocate(ctx
);
1337 if (bifrost_debug
& BIFROST_DBG_SHADERS
)
1338 bi_print_shader(ctx
, stdout
);
1339 bi_pack(ctx
, &program
->compiled
);
1341 if (bifrost_debug
& BIFROST_DBG_SHADERS
)
1342 disassemble_bifrost(stdout
, program
->compiled
.data
, program
->compiled
.size
, true);