src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "main/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 106
 107         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 108                 /* Zero it out for direct */
 109                 ins.src[1] = BIR_INDEX_ZERO;
 110         } else {
 111                 /* R61 contains sample mask stuff, TODO RA XXX */
 112                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 113         }
 114
 115         bi_emit(ctx, ins);
 116 }
 117
 118 static void
 119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 120 {
 121         if (!ctx->emitted_atest) {
 122                 bi_instruction ins = {
 123                         .type = BI_ATEST,
 124                         .src = {
 125                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 126                                 bir_src_index(&instr->src[0])
 127                         },
 128                         .src_types = {
 129                                 nir_type_uint32,
 130                                 nir_type_float32
 131                         },
 132                         .swizzle = {
 133                                 { 0 },
 134                                 { 3, 0 } /* swizzle out the alpha */
 135                         },
 136                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 137                         .dest_type = nir_type_uint32,
 138                         .writemask = 0xF
 139                 };
 140
 141                 bi_emit(ctx, ins);
 142                 bi_schedule_barrier(ctx);
 143                 ctx->emitted_atest = true;
 144         }
 145
 146         bi_instruction blend = {
 147                 .type = BI_BLEND,
 148                 .blend_location = nir_intrinsic_base(instr),
 149                 .src = {
 150                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 151                         bir_src_index(&instr->src[0])
 152                 },
 153                 .src_types = {
 154                         nir_type_uint32,
 155                         nir_type_float32,
 156                 },
 157                 .swizzle = {
 158                         { 0 },
 159                         { 0, 1, 2, 3 }
 160                 },
 161                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 162                 .dest_type = nir_type_uint32,
 163                 .writemask = 0xF
 164         };
 165
 166         bi_emit(ctx, blend);
 167         bi_schedule_barrier(ctx);
 168 }
 169
 170 static bi_instruction
 171 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
 172 {
 173         bi_instruction ld = bi_load(T, instr);
 174         ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
 175         ld.src[2] = BIR_INDEX_REGISTER | 62;
 176         ld.src[3] = 0;
 177         ld.src_types[1] = nir_type_uint32;
 178         ld.src_types[2] = nir_type_uint32;
 179         ld.src_types[3] = nir_intrinsic_type(instr);
 180         return ld;
 181 }
 182
 183 static void
 184 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 185 {
 186         bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
 187         address.dest = bi_make_temp(ctx);
 188         address.dest_type = nir_type_uint32;
 189         address.writemask = (1 << 12) - 1;
 190
 191         bi_instruction st = {
 192                 .type = BI_STORE_VAR,
 193                 .src = {
 194                         bir_src_index(&instr->src[0]),
 195                         address.dest, address.dest, address.dest,
 196                 },
 197                 .src_types = {
 198                         nir_type_uint32,
 199                         nir_type_uint32, nir_type_uint32, nir_type_uint32,
 200                 },
 201                 .swizzle = {
 202                         { 0, 1, 2, 3 },
 203                         { 0 }, { 1 }, { 2}
 204                 },
 205                 .store_channels = 4, /* TODO: WRITEMASK */
 206         };
 207
 208         bi_emit(ctx, address);
 209         bi_emit(ctx, st);
 210 }
 211
 212 static void
 213 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 214 {
 215         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 216         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 217
 218         /* TODO: Indirect access, since we need to multiply by the element
 219          * size. I believe we can get this lowering automatically via
 220          * nir_lower_io (as mul instructions) with the proper options, but this
 221          * is TODO */
 222         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 223         ld.constant.u64 += ctx->sysvals.sysval_count;
 224         ld.constant.u64 *= 16;
 225
 226         bi_emit(ctx, ld);
 227 }
 228
 229 static void
 230 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 231                 unsigned nr_components, unsigned offset)
 232 {
 233         nir_dest nir_dest;
 234
 235         /* Figure out which uniform this is */
 236         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 237         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 238
 239         /* Sysvals are prefix uniforms */
 240         unsigned uniform = ((uintptr_t) val) - 1;
 241
 242         /* Emit the read itself -- this is never indirect */
 243
 244         bi_instruction load = {
 245                 .type = BI_LOAD_UNIFORM,
 246                 .writemask = (1 << (nr_components * 4)) - 1,
 247                 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
 248                 .constant = { (uniform * 16) + offset },
 249                 .dest = bir_dest_index(&nir_dest),
 250                 .dest_type = nir_type_uint32, /* TODO */
 251         };
 252
 253         bi_emit(ctx, load);
 254 }
 255
 256 static void
 257 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 258 {
 259
 260         switch (instr->intrinsic) {
 261         case nir_intrinsic_load_barycentric_pixel:
 262                 /* stub */
 263                 break;
 264         case nir_intrinsic_load_interpolated_input:
 265         case nir_intrinsic_load_input:
 266                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 267                         bi_emit_ld_vary(ctx, instr);
 268                 else if (ctx->stage == MESA_SHADER_VERTEX)
 269                         bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
 270                 else {
 271                         unreachable("Unsupported shader stage");
 272                 }
 273                 break;
 274
 275         case nir_intrinsic_store_output:
 276                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 277                         bi_emit_frag_out(ctx, instr);
 278                 else if (ctx->stage == MESA_SHADER_VERTEX)
 279                         bi_emit_st_vary(ctx, instr);
 280                 else
 281                         unreachable("Unsupported shader stage");
 282                 break;
 283
 284         case nir_intrinsic_load_uniform:
 285                 bi_emit_ld_uniform(ctx, instr);
 286                 break;
 287
 288         case nir_intrinsic_load_ssbo_address:
 289                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 290                 break;
 291
 292         case nir_intrinsic_get_buffer_size:
 293                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 294                 break;
 295
 296         case nir_intrinsic_load_viewport_scale:
 297         case nir_intrinsic_load_viewport_offset:
 298         case nir_intrinsic_load_num_work_groups:
 299         case nir_intrinsic_load_sampler_lod_parameters_pan:
 300                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 301                 break;
 302
 303         default:
 304                 /* todo */
 305                 break;
 306         }
 307 }
 308
 309 static void
 310 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 311 {
 312         /* Make sure we've been lowered */
 313         assert(instr->def.num_components == 1);
 314
 315         bi_instruction move = {
 316                 .type = BI_MOV,
 317                 .dest = bir_ssa_index(&instr->def),
 318                 .dest_type = instr->def.bit_size | nir_type_uint,
 319                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 320                 .src = {
 321                         BIR_INDEX_CONSTANT
 322                 },
 323                 .constant = {
 324                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 325                 }
 326         };
 327
 328         bi_emit(ctx, move);
 329 }
 330
 331 #define BI_CASE_CMP(op) \
 332         case op##8: \
 333         case op##16: \
 334         case op##32: \
 335
 336 static enum bi_class
 337 bi_class_for_nir_alu(nir_op op)
 338 {
 339         switch (op) {
 340         case nir_op_iadd:
 341         case nir_op_fadd:
 342         case nir_op_fsub:
 343                 return BI_ADD;
 344         case nir_op_isub:
 345                 return BI_ISUB;
 346
 347         BI_CASE_CMP(nir_op_flt)
 348         BI_CASE_CMP(nir_op_fge)
 349         BI_CASE_CMP(nir_op_feq)
 350         BI_CASE_CMP(nir_op_fne)
 351         BI_CASE_CMP(nir_op_ilt)
 352         BI_CASE_CMP(nir_op_ige)
 353         BI_CASE_CMP(nir_op_ieq)
 354         BI_CASE_CMP(nir_op_ine)
 355                 return BI_CMP;
 356
 357         case nir_op_b8csel:
 358         case nir_op_b16csel:
 359         case nir_op_b32csel:
 360                 return BI_CSEL;
 361
 362         case nir_op_i2i8:
 363         case nir_op_i2i16:
 364         case nir_op_i2i32:
 365         case nir_op_i2i64:
 366         case nir_op_u2u8:
 367         case nir_op_u2u16:
 368         case nir_op_u2u32:
 369         case nir_op_u2u64:
 370         case nir_op_f2i16:
 371         case nir_op_f2i32:
 372         case nir_op_f2i64:
 373         case nir_op_f2u16:
 374         case nir_op_f2u32:
 375         case nir_op_f2u64:
 376         case nir_op_i2f16:
 377         case nir_op_i2f32:
 378         case nir_op_i2f64:
 379         case nir_op_u2f16:
 380         case nir_op_u2f32:
 381         case nir_op_u2f64:
 382                 return BI_CONVERT;
 383
 384         case nir_op_ffma:
 385         case nir_op_fmul:
 386                 return BI_FMA;
 387
 388         case nir_op_imin:
 389         case nir_op_imax:
 390         case nir_op_umin:
 391         case nir_op_umax:
 392         case nir_op_fmin:
 393         case nir_op_fmax:
 394                 return BI_MINMAX;
 395
 396         case nir_op_fsat:
 397         case nir_op_fneg:
 398         case nir_op_fabs:
 399                 return BI_FMOV;
 400         case nir_op_mov:
 401                 return BI_MOV;
 402
 403         case nir_op_frcp:
 404         case nir_op_frsq:
 405         case nir_op_fsin:
 406         case nir_op_fcos:
 407                 return BI_SPECIAL;
 408
 409         default:
 410                 unreachable("Unknown ALU op");
 411         }
 412 }
 413
 414 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
 415  * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
 416  * optimizations). Otherwise it will bail (when used for primary code
 417  * generation). */
 418
 419 static enum bi_cond
 420 bi_cond_for_nir(nir_op op, bool soft)
 421 {
 422         switch (op) {
 423         BI_CASE_CMP(nir_op_flt)
 424         BI_CASE_CMP(nir_op_ilt)
 425                 return BI_COND_LT;
 426
 427         BI_CASE_CMP(nir_op_fge)
 428         BI_CASE_CMP(nir_op_ige)
 429                 return BI_COND_GE;
 430
 431         BI_CASE_CMP(nir_op_feq)
 432         BI_CASE_CMP(nir_op_ieq)
 433                 return BI_COND_EQ;
 434
 435         BI_CASE_CMP(nir_op_fne)
 436         BI_CASE_CMP(nir_op_ine)
 437                 return BI_COND_NE;
 438         default:
 439                 if (soft)
 440                         return BI_COND_ALWAYS;
 441                 else
 442                         unreachable("Invalid compare");
 443         }
 444 }
 445
 446 static void
 447 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
 448                 unsigned *constants_left, unsigned *constant_shift)
 449 {
 450         unsigned bits = nir_src_bit_size(instr->src[i].src);
 451         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 452
 453         alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
 454                 | bits;
 455
 456         /* Try to inline a constant */
 457         if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
 458                 alu->constant.u64 |=
 459                         (nir_src_as_uint(instr->src[i].src)) << *constant_shift;
 460
 461                 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
 462                 --(*constants_left);
 463                 (*constant_shift) += dest_bits;
 464                 return;
 465         }
 466
 467         alu->src[to] = bir_src_index(&instr->src[i].src);
 468
 469         /* We assert scalarization above */
 470         alu->swizzle[to][0] = instr->src[i].swizzle[0];
 471 }
 472
 473 static void
 474 bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
 475                 unsigned *constants_left, unsigned *constant_shift)
 476 {
 477         /* Bail for vector weirdness */
 478         if (cond.swizzle[0] != 0)
 479                 return;
 480
 481         if (!cond.src.is_ssa)
 482                 return;
 483
 484         nir_ssa_def *def = cond.src.ssa;
 485         nir_instr *parent = def->parent_instr;
 486
 487         if (parent->type != nir_instr_type_alu)
 488                 return;
 489
 490         nir_alu_instr *alu = nir_instr_as_alu(parent);
 491
 492         /* Try to match a condition */
 493         enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
 494
 495         if (bcond == BI_COND_ALWAYS)
 496                 return;
 497
 498         /* We found one, let's fuse it in */
 499         csel->csel_cond = bcond;
 500         bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift);
 501         bi_copy_src(csel, alu, 1, 3, constants_left, constant_shift);
 502 }
 503
 504 static void
 505 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 506 {
 507         /* Assume it's something we can handle normally */
 508         bi_instruction alu = {
 509                 .type = bi_class_for_nir_alu(instr->op),
 510                 .dest = bir_dest_index(&instr->dest.dest),
 511                 .dest_type = nir_op_infos[instr->op].output_type
 512                         | nir_dest_bit_size(instr->dest.dest),
 513         };
 514
 515         /* TODO: Implement lowering of special functions for older Bifrost */
 516         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 517
 518         if (instr->dest.dest.is_ssa) {
 519                 /* Construct a writemask */
 520                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 521                 unsigned comps = instr->dest.dest.ssa.num_components;
 522                 assert(comps == 1);
 523                 unsigned bits = bits_per_comp * comps;
 524                 unsigned bytes = bits / 8;
 525                 alu.writemask = (1 << bytes) - 1;
 526         } else {
 527                 unsigned comp_mask = instr->dest.write_mask;
 528
 529                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 530                                 comp_mask);
 531         }
 532
 533         /* We inline constants as we go. This tracks how many constants have
 534          * been inlined, since we're limited to 64-bits of constants per
 535          * instruction */
 536
 537         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 538         unsigned constants_left = (64 / dest_bits);
 539         unsigned constant_shift = 0;
 540
 541         /* Copy sources */
 542
 543         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 544         assert(num_inputs <= ARRAY_SIZE(alu.src));
 545
 546         for (unsigned i = 0; i < num_inputs; ++i)
 547                 bi_copy_src(&alu, instr, i, i, &constants_left, &constant_shift);
 548
 549         /* Op-specific fixup */
 550         switch (instr->op) {
 551         case nir_op_fmul:
 552                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 553                 break;
 554         case nir_op_fsat:
 555                 alu.outmod = BIFROST_SAT; /* FMOV */
 556                 break;
 557         case nir_op_fneg:
 558                 alu.src_neg[0] = true; /* FMOV */
 559                 break;
 560         case nir_op_fabs:
 561                 alu.src_abs[0] = true; /* FMOV */
 562                 break;
 563         case nir_op_fsub:
 564                 alu.src_neg[1] = true; /* FADD */
 565                 break;
 566         case nir_op_fmax:
 567         case nir_op_imax:
 568         case nir_op_umax:
 569                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 570                 break;
 571         case nir_op_frcp:
 572                 alu.op.special = BI_SPECIAL_FRCP;
 573                 break;
 574         case nir_op_frsq:
 575                 alu.op.special = BI_SPECIAL_FRSQ;
 576                 break;
 577         case nir_op_fsin:
 578                 alu.op.special = BI_SPECIAL_FSIN;
 579                 break;
 580         case nir_op_fcos:
 581                 alu.op.special = BI_SPECIAL_FCOS;
 582                 break;
 583         BI_CASE_CMP(nir_op_flt)
 584         BI_CASE_CMP(nir_op_ilt)
 585         BI_CASE_CMP(nir_op_fge)
 586         BI_CASE_CMP(nir_op_ige)
 587         BI_CASE_CMP(nir_op_feq)
 588         BI_CASE_CMP(nir_op_ieq)
 589         BI_CASE_CMP(nir_op_fne)
 590         BI_CASE_CMP(nir_op_ine)
 591                 alu.op.compare = bi_cond_for_nir(instr->op, false);
 592                 break;
 593         default:
 594                 break;
 595         }
 596
 597         if (alu.type == BI_CSEL) {
 598                 bi_fuse_csel_cond(&alu, instr->src[0],
 599                                 &constants_left, &constant_shift);
 600         }
 601
 602         bi_emit(ctx, alu);
 603 }
 604
 605 static void
 606 emit_instr(bi_context *ctx, struct nir_instr *instr)
 607 {
 608         switch (instr->type) {
 609         case nir_instr_type_load_const:
 610                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 611                 break;
 612
 613         case nir_instr_type_intrinsic:
 614                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 615                 break;
 616
 617         case nir_instr_type_alu:
 618                 emit_alu(ctx, nir_instr_as_alu(instr));
 619                 break;
 620
 621 #if 0
 622         case nir_instr_type_tex:
 623                 emit_tex(ctx, nir_instr_as_tex(instr));
 624                 break;
 625 #endif
 626
 627         case nir_instr_type_jump:
 628                 emit_jump(ctx, nir_instr_as_jump(instr));
 629                 break;
 630
 631         case nir_instr_type_ssa_undef:
 632                 /* Spurious */
 633                 break;
 634
 635         default:
 636                 //unreachable("Unhandled instruction type");
 637                 break;
 638         }
 639 }
 640
 641
 642
 643 static bi_block *
 644 create_empty_block(bi_context *ctx)
 645 {
 646         bi_block *blk = rzalloc(ctx, bi_block);
 647
 648         blk->base.predecessors = _mesa_set_create(blk,
 649                         _mesa_hash_pointer,
 650                         _mesa_key_pointer_equal);
 651
 652         blk->base.name = ctx->block_name_count++;
 653
 654         return blk;
 655 }
 656
 657 static void
 658 bi_schedule_barrier(bi_context *ctx)
 659 {
 660         bi_block *temp = ctx->after_block;
 661         ctx->after_block = create_empty_block(ctx);
 662         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 663         list_inithead(&ctx->after_block->base.instructions);
 664         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 665         ctx->current_block = ctx->after_block;
 666         ctx->after_block = temp;
 667 }
 668
 669 static bi_block *
 670 emit_block(bi_context *ctx, nir_block *block)
 671 {
 672         if (ctx->after_block) {
 673                 ctx->current_block = ctx->after_block;
 674                 ctx->after_block = NULL;
 675         } else {
 676                 ctx->current_block = create_empty_block(ctx);
 677         }
 678
 679         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 680         list_inithead(&ctx->current_block->base.instructions);
 681
 682         nir_foreach_instr(instr, block) {
 683                 emit_instr(ctx, instr);
 684                 ++ctx->instruction_count;
 685         }
 686
 687         return ctx->current_block;
 688 }
 689
 690 /* Emits an unconditional branch to the end of the current block, returning a
 691  * pointer so the user can fill in details */
 692
 693 static bi_instruction *
 694 bi_emit_branch(bi_context *ctx)
 695 {
 696         bi_instruction branch = {
 697                 .type = BI_BRANCH,
 698                 .branch = {
 699                         .cond = BI_COND_ALWAYS
 700                 }
 701         };
 702
 703         return bi_emit(ctx, branch);
 704 }
 705
 706 /* Sets a condition for a branch by examing the NIR condition. If we're
 707  * familiar with the condition, we unwrap it to fold it into the branch
 708  * instruction. Otherwise, we consume the condition directly. We
 709  * generally use 1-bit booleans which allows us to use small types for
 710  * the conditions.
 711  */
 712
 713 static void
 714 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 715 {
 716         /* TODO: Try to unwrap instead of always bailing */
 717         branch->src[0] = bir_src_index(cond);
 718         branch->src[1] = BIR_INDEX_ZERO;
 719         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 720         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 721 }
 722
 723 static void
 724 emit_if(bi_context *ctx, nir_if *nif)
 725 {
 726         bi_block *before_block = ctx->current_block;
 727
 728         /* Speculatively emit the branch, but we can't fill it in until later */
 729         bi_instruction *then_branch = bi_emit_branch(ctx);
 730         bi_set_branch_cond(then_branch, &nif->condition, true);
 731
 732         /* Emit the two subblocks. */
 733         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 734         bi_block *end_then_block = ctx->current_block;
 735
 736         /* Emit a jump from the end of the then block to the end of the else */
 737         bi_instruction *then_exit = bi_emit_branch(ctx);
 738
 739         /* Emit second block, and check if it's empty */
 740
 741         int count_in = ctx->instruction_count;
 742         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 743         bi_block *end_else_block = ctx->current_block;
 744         ctx->after_block = create_empty_block(ctx);
 745
 746         /* Now that we have the subblocks emitted, fix up the branches */
 747
 748         assert(then_block);
 749         assert(else_block);
 750
 751         if (ctx->instruction_count == count_in) {
 752                 /* The else block is empty, so don't emit an exit jump */
 753                 bi_remove_instruction(then_exit);
 754                 then_branch->branch.target = ctx->after_block;
 755         } else {
 756                 then_branch->branch.target = else_block;
 757                 then_exit->branch.target = ctx->after_block;
 758                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 759         }
 760
 761         /* Wire up the successors */
 762
 763         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 764
 765         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 766         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 767 }
 768
 769 static void
 770 emit_loop(bi_context *ctx, nir_loop *nloop)
 771 {
 772         /* Remember where we are */
 773         bi_block *start_block = ctx->current_block;
 774
 775         bi_block *saved_break = ctx->break_block;
 776         bi_block *saved_continue = ctx->continue_block;
 777
 778         ctx->continue_block = create_empty_block(ctx);
 779         ctx->break_block = create_empty_block(ctx);
 780         ctx->after_block = ctx->continue_block;
 781
 782         /* Emit the body itself */
 783         emit_cf_list(ctx, &nloop->body);
 784
 785         /* Branch back to loop back */
 786         bi_instruction *br_back = bi_emit_branch(ctx);
 787         br_back->branch.target = ctx->continue_block;
 788         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 789         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 790
 791         ctx->after_block = ctx->break_block;
 792
 793         /* Pop off */
 794         ctx->break_block = saved_break;
 795         ctx->continue_block = saved_continue;
 796         ++ctx->loop_count;
 797 }
 798
 799 static bi_block *
 800 emit_cf_list(bi_context *ctx, struct exec_list *list)
 801 {
 802         bi_block *start_block = NULL;
 803
 804         foreach_list_typed(nir_cf_node, node, node, list) {
 805                 switch (node->type) {
 806                 case nir_cf_node_block: {
 807                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 808
 809                         if (!start_block)
 810                                 start_block = block;
 811
 812                         break;
 813                 }
 814
 815                 case nir_cf_node_if:
 816                         emit_if(ctx, nir_cf_node_as_if(node));
 817                         break;
 818
 819                 case nir_cf_node_loop:
 820                         emit_loop(ctx, nir_cf_node_as_loop(node));
 821                         break;
 822
 823                 default:
 824                         unreachable("Unknown control flow");
 825                 }
 826         }
 827
 828         return start_block;
 829 }
 830
 831 static int
 832 glsl_type_size(const struct glsl_type *type, bool bindless)
 833 {
 834         return glsl_count_attribute_slots(type, false);
 835 }
 836
 837 static void
 838 bi_optimize_nir(nir_shader *nir)
 839 {
 840         bool progress;
 841         unsigned lower_flrp = 16 | 32 | 64;
 842
 843         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 844         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 845
 846         nir_lower_tex_options lower_tex_options = {
 847                 .lower_txs_lod = true,
 848                 .lower_txp = ~0,
 849                 .lower_tex_without_implicit_lod = true,
 850                 .lower_txd = true,
 851         };
 852
 853         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 854         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 855         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 856
 857         do {
 858                 progress = false;
 859
 860                 NIR_PASS(progress, nir, nir_lower_var_copies);
 861                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 862
 863                 NIR_PASS(progress, nir, nir_copy_prop);
 864                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 865                 NIR_PASS(progress, nir, nir_opt_dce);
 866                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 867                 NIR_PASS(progress, nir, nir_opt_cse);
 868                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 869                 NIR_PASS(progress, nir, nir_opt_algebraic);
 870                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 871
 872                 if (lower_flrp != 0) {
 873                         bool lower_flrp_progress = false;
 874                         NIR_PASS(lower_flrp_progress,
 875                                  nir,
 876                                  nir_lower_flrp,
 877                                  lower_flrp,
 878                                  false /* always_precise */,
 879                                  nir->options->lower_ffma);
 880                         if (lower_flrp_progress) {
 881                                 NIR_PASS(progress, nir,
 882                                          nir_opt_constant_folding);
 883                                 progress = true;
 884                         }
 885
 886                         /* Nothing should rematerialize any flrps, so we only
 887                          * need to do this lowering once.
 888                          */
 889                         lower_flrp = 0;
 890                 }
 891
 892                 NIR_PASS(progress, nir, nir_opt_undef);
 893                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 894                          nir_var_shader_in |
 895                          nir_var_shader_out |
 896                          nir_var_function_temp);
 897         } while (progress);
 898
 899         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 900         NIR_PASS(progress, nir, nir_lower_bool_to_int32);
 901         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 902         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 903         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 904
 905         /* Take us out of SSA */
 906         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 907         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 908
 909         /* We're a primary scalar architecture but there's enough vector that
 910          * we use a vector IR so let's not also deal with scalar hacks on top
 911          * of the vector hacks */
 912
 913         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 914         NIR_PASS(progress, nir, nir_lower_vec_to_movs);
 915         NIR_PASS(progress, nir, nir_opt_dce);
 916 }
 917
 918 static void
 919 bi_insert_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp)
 920 {
 921         bi_instruction move = {
 922                 .type = BI_MOV,
 923                 .dest = parent->dest,
 924                 .dest_type = nir_type_uint32,
 925                 .writemask = (0xF << (4 * comp)),
 926                 .src = { parent->src[0] },
 927                 .src_types = { nir_type_uint32 },
 928                 .swizzle = { { comp } }
 929         };
 930
 931         bi_emit_before(ctx, parent, move);
 932 }
 933
 934 static void
 935 bi_lower_mov(bi_context *ctx, bi_block *block)
 936 {
 937         bi_foreach_instr_in_block_safe(block, ins) {
 938                 if (ins->type != BI_MOV) continue;
 939                 if (util_bitcount(ins->writemask) <= 4) continue;
 940
 941                 for (unsigned i = 0; i < 4; ++i) {
 942                         unsigned quad = (ins->writemask >> (4 * i)) & 0xF;
 943
 944                         if (quad == 0)
 945                                 continue;
 946                         else if (quad == 0xF)
 947                                 bi_insert_mov32(ctx, ins, i);
 948                         else
 949                                 unreachable("TODO: Lowering <32bit moves");
 950                 }
 951
 952                 bi_remove_instruction(ins);
 953         }
 954 }
 955
 956 void
 957 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 958 {
 959         bi_context *ctx = rzalloc(NULL, bi_context);
 960         ctx->nir = nir;
 961         ctx->stage = nir->info.stage;
 962         ctx->quirks = bifrost_get_quirks(product_id);
 963         list_inithead(&ctx->blocks);
 964
 965         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 966          * (so we don't accidentally duplicate the epilogue since mesa/st has
 967          * messed with our I/O quite a bit already) */
 968
 969         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 970
 971         if (ctx->stage == MESA_SHADER_VERTEX) {
 972                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 973                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 974         }
 975
 976         NIR_PASS_V(nir, nir_split_var_copies);
 977         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 978         NIR_PASS_V(nir, nir_lower_var_copies);
 979         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 980         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 981         NIR_PASS_V(nir, nir_lower_ssbo);
 982
 983         bi_optimize_nir(nir);
 984         nir_print_shader(nir, stdout);
 985
 986         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 987         program->sysval_count = ctx->sysvals.sysval_count;
 988         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 989
 990         nir_foreach_function(func, nir) {
 991                 if (!func->impl)
 992                         continue;
 993
 994                 ctx->impl = func->impl;
 995                 emit_cf_list(ctx, &func->impl->body);
 996                 break; /* TODO: Multi-function shaders */
 997         }
 998
 999         bi_foreach_block(ctx, _block) {
1000                 bi_block *block = (bi_block *) _block;
1001                 bi_lower_mov(ctx, block);
1002         }
1003
1004         bool progress = false;
1005
1006         do {
1007                 progress = false;
1008
1009                 bi_foreach_block(ctx, _block) {
1010                         bi_block *block = (bi_block *) _block;
1011                         progress |= bi_opt_dead_code_eliminate(ctx, block);
1012                 }
1013         } while(progress);
1014
1015         bi_print_shader(ctx, stdout);
1016         bi_schedule(ctx);
1017         bi_register_allocate(ctx);
1018         bi_print_shader(ctx, stdout);
1019         bi_pack(ctx, &program->compiled);
1020         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1021
1022         ralloc_free(ctx);
1023 }