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pan/bi: Lower gl_FragCoord
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "util/u_debug.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "bifrost_nir.h"
36 #include "compiler.h"
37 #include "bi_quirks.h"
38 #include "bi_print.h"
39
40 static const struct debug_named_value debug_options[] = {
41 {"msgs", BIFROST_DBG_MSGS, "Print debug messages"},
42 {"shaders", BIFROST_DBG_SHADERS, "Dump shaders in NIR and MIR"},
43 DEBUG_NAMED_VALUE_END
44 };
45
46 DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug, "BIFROST_MESA_DEBUG", debug_options, 0)
47
48 int bifrost_debug = 0;
49
50 #define DBG(fmt, ...) \
51 do { if (bifrost_debug & BIFROST_DBG_MSGS) \
52 fprintf(stderr, "%s:%d: "fmt, \
53 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
54
55 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
56 static bi_instruction *bi_emit_branch(bi_context *ctx);
57 static void bi_schedule_barrier(bi_context *ctx);
58
59 static void
60 emit_jump(bi_context *ctx, nir_jump_instr *instr)
61 {
62 bi_instruction *branch = bi_emit_branch(ctx);
63
64 switch (instr->type) {
65 case nir_jump_break:
66 branch->branch.target = ctx->break_block;
67 break;
68 case nir_jump_continue:
69 branch->branch.target = ctx->continue_block;
70 break;
71 default:
72 unreachable("Unhandled jump type");
73 }
74
75 pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
76 }
77
78 static bi_instruction
79 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
80 {
81 bi_instruction load = {
82 .type = T,
83 .vector_channels = instr->num_components,
84 .src = { BIR_INDEX_CONSTANT },
85 .src_types = { nir_type_uint32 },
86 .constant = { .u64 = nir_intrinsic_base(instr) },
87 };
88
89 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
90
91 if (info->has_dest)
92 load.dest = pan_dest_index(&instr->dest);
93
94 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
95 load.dest_type = nir_intrinsic_type(instr);
96
97 nir_src *offset = nir_get_io_offset_src(instr);
98
99 if (nir_src_is_const(*offset))
100 load.constant.u64 += nir_src_as_uint(*offset);
101 else
102 load.src[0] = pan_src_index(offset);
103
104 return load;
105 }
106
107 static void
108 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
109 {
110 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
111 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
112 ins.load_vary.reuse = false; /* TODO */
113 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
114 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
115
116 if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
117 /* Zero it out for direct */
118 ins.src[1] = BIR_INDEX_ZERO;
119 } else {
120 /* R61 contains sample mask stuff, TODO RA XXX */
121 ins.src[1] = BIR_INDEX_REGISTER | 61;
122 }
123
124 bi_emit(ctx, ins);
125 }
126
127 static void
128 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
129 {
130 if (!ctx->emitted_atest) {
131 bi_instruction ins = {
132 .type = BI_ATEST,
133 .src = {
134 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
135 pan_src_index(&instr->src[0])
136 },
137 .src_types = {
138 nir_type_uint32,
139 nir_intrinsic_type(instr)
140 },
141 .swizzle = {
142 { 0 },
143 { 3, 0 } /* swizzle out the alpha */
144 },
145 .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
146 .dest_type = nir_type_uint32,
147 };
148
149 bi_emit(ctx, ins);
150 bi_schedule_barrier(ctx);
151 ctx->emitted_atest = true;
152 }
153
154 bi_instruction blend = {
155 .type = BI_BLEND,
156 .blend_location = nir_intrinsic_base(instr),
157 .src = {
158 pan_src_index(&instr->src[0]),
159 BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
160 },
161 .src_types = {
162 nir_intrinsic_type(instr),
163 nir_type_uint32
164 },
165 .swizzle = {
166 { 0, 1, 2, 3 },
167 { 0 }
168 },
169 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
170 .dest_type = nir_type_uint32,
171 .vector_channels = 4
172 };
173
174 assert(blend.blend_location < BIFROST_MAX_RENDER_TARGET_COUNT);
175 assert(ctx->blend_types);
176 assert(blend.src_types[0]);
177 ctx->blend_types[blend.blend_location] = blend.src_types[0];
178
179 bi_emit(ctx, blend);
180 bi_schedule_barrier(ctx);
181 }
182
183 static bi_instruction
184 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
185 {
186 bi_instruction ld = bi_load(T, instr);
187 ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
188 ld.src[2] = BIR_INDEX_REGISTER | 62;
189 ld.src[3] = 0;
190 ld.src_types[1] = nir_type_uint32;
191 ld.src_types[2] = nir_type_uint32;
192 ld.src_types[3] = nir_intrinsic_type(instr);
193 return ld;
194 }
195
196 static void
197 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
198 {
199 bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
200 address.dest = bi_make_temp(ctx);
201 address.dest_type = nir_type_uint32;
202 address.vector_channels = 3;
203
204 unsigned nr = nir_intrinsic_src_components(instr, 0);
205 assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
206
207 bi_instruction st = {
208 .type = BI_STORE_VAR,
209 .src = {
210 pan_src_index(&instr->src[0]),
211 address.dest, address.dest, address.dest,
212 },
213 .src_types = {
214 nir_type_uint32,
215 nir_type_uint32, nir_type_uint32, nir_type_uint32,
216 },
217 .swizzle = {
218 { 0 },
219 { 0 }, { 1 }, { 2}
220 },
221 .vector_channels = nr,
222 };
223
224 for (unsigned i = 0; i < nr; ++i)
225 st.swizzle[0][i] = i;
226
227 bi_emit(ctx, address);
228 bi_emit(ctx, st);
229 }
230
231 static void
232 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
233 {
234 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
235 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
236
237 /* TODO: Indirect access, since we need to multiply by the element
238 * size. I believe we can get this lowering automatically via
239 * nir_lower_io (as mul instructions) with the proper options, but this
240 * is TODO */
241 assert(ld.src[0] & BIR_INDEX_CONSTANT);
242 ld.constant.u64 += ctx->sysvals.sysval_count;
243 ld.constant.u64 *= 16;
244
245 bi_emit(ctx, ld);
246 }
247
248 static void
249 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
250 unsigned nr_components, unsigned offset)
251 {
252 nir_dest nir_dest;
253
254 /* Figure out which uniform this is */
255 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
256 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
257
258 /* Sysvals are prefix uniforms */
259 unsigned uniform = ((uintptr_t) val) - 1;
260
261 /* Emit the read itself -- this is never indirect */
262
263 bi_instruction load = {
264 .type = BI_LOAD_UNIFORM,
265 .vector_channels = nr_components,
266 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
267 .src_types = { nir_type_uint32, nir_type_uint32 },
268 .constant = { (uniform * 16) + offset },
269 .dest = pan_dest_index(&nir_dest),
270 .dest_type = nir_type_uint32, /* TODO */
271 };
272
273 bi_emit(ctx, load);
274 }
275
276 /* gl_FragCoord.xy = u16_to_f32(R59.xy) + 0.5
277 * gl_FragCoord.z = ld_vary(fragz)
278 * gl_FragCoord.w = ld_vary(fragw)
279 */
280
281 static void
282 bi_emit_ld_frag_coord(bi_context *ctx, nir_intrinsic_instr *instr)
283 {
284 /* Future proofing for mediump fragcoord at some point.. */
285 nir_alu_type T = nir_type_float32;
286
287 /* First, sketch a combine */
288 bi_instruction combine = {
289 .type = BI_COMBINE,
290 .dest_type = nir_type_uint32,
291 .dest = pan_dest_index(&instr->dest),
292 .src_types = { T, T, T, T },
293 };
294
295 /* Second, handle xy */
296 for (unsigned i = 0; i < 2; ++i) {
297 bi_instruction conv = {
298 .type = BI_CONVERT,
299 .dest_type = T,
300 .dest = bi_make_temp(ctx),
301 .src = {
302 /* TODO: RA XXX */
303 BIR_INDEX_REGISTER | 59
304 },
305 .src_types = { nir_type_uint16 },
306 .swizzle = { { i } }
307 };
308
309 bi_instruction add = {
310 .type = BI_ADD,
311 .dest_type = T,
312 .dest = bi_make_temp(ctx),
313 .src = { conv.dest, BIR_INDEX_CONSTANT },
314 .src_types = { T, T },
315 };
316
317 float half = 0.5;
318 memcpy(&add.constant.u32, &half, sizeof(float));
319
320 bi_emit(ctx, conv);
321 bi_emit(ctx, add);
322
323 combine.src[i] = add.dest;
324 }
325
326 /* Third, zw */
327 for (unsigned i = 0; i < 2; ++i) {
328 bi_instruction load = {
329 .type = BI_LOAD_VAR,
330 .load_vary = {
331 .interp_mode = BIFROST_INTERP_DEFAULT,
332 .reuse = false,
333 .flat = true
334 },
335 .vector_channels = 1,
336 .dest_type = nir_type_float32,
337 .dest = bi_make_temp(ctx),
338 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
339 .src_types = { nir_type_uint32, nir_type_uint32 },
340 .constant = {
341 .u32 = (i == 0) ? BIFROST_FRAGZ : BIFROST_FRAGW
342 }
343 };
344
345 bi_emit(ctx, load);
346
347 combine.src[i + 2] = load.dest;
348 }
349
350 /* Finally, emit the combine */
351 bi_emit(ctx, combine);
352 }
353
354 static void
355 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
356 {
357
358 switch (instr->intrinsic) {
359 case nir_intrinsic_load_barycentric_pixel:
360 /* stub */
361 break;
362 case nir_intrinsic_load_interpolated_input:
363 case nir_intrinsic_load_input:
364 if (ctx->stage == MESA_SHADER_FRAGMENT)
365 bi_emit_ld_vary(ctx, instr);
366 else if (ctx->stage == MESA_SHADER_VERTEX)
367 bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
368 else {
369 unreachable("Unsupported shader stage");
370 }
371 break;
372
373 case nir_intrinsic_store_output:
374 if (ctx->stage == MESA_SHADER_FRAGMENT)
375 bi_emit_frag_out(ctx, instr);
376 else if (ctx->stage == MESA_SHADER_VERTEX)
377 bi_emit_st_vary(ctx, instr);
378 else
379 unreachable("Unsupported shader stage");
380 break;
381
382 case nir_intrinsic_load_uniform:
383 bi_emit_ld_uniform(ctx, instr);
384 break;
385
386 case nir_intrinsic_load_frag_coord:
387 bi_emit_ld_frag_coord(ctx, instr);
388 break;
389
390 case nir_intrinsic_load_ssbo_address:
391 bi_emit_sysval(ctx, &instr->instr, 1, 0);
392 break;
393
394 case nir_intrinsic_get_buffer_size:
395 bi_emit_sysval(ctx, &instr->instr, 1, 8);
396 break;
397
398 case nir_intrinsic_load_viewport_scale:
399 case nir_intrinsic_load_viewport_offset:
400 case nir_intrinsic_load_num_work_groups:
401 case nir_intrinsic_load_sampler_lod_parameters_pan:
402 bi_emit_sysval(ctx, &instr->instr, 3, 0);
403 break;
404
405 default:
406 unreachable("Unknown intrinsic");
407 break;
408 }
409 }
410
411 static void
412 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
413 {
414 /* Make sure we've been lowered */
415 assert(instr->def.num_components == 1);
416
417 bi_instruction move = {
418 .type = BI_MOV,
419 .dest = pan_ssa_index(&instr->def),
420 .dest_type = instr->def.bit_size | nir_type_uint,
421 .src = {
422 BIR_INDEX_CONSTANT
423 },
424 .src_types = {
425 instr->def.bit_size | nir_type_uint,
426 },
427 .constant = {
428 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
429 }
430 };
431
432 bi_emit(ctx, move);
433 }
434
435 #define BI_CASE_CMP(op) \
436 case op##8: \
437 case op##16: \
438 case op##32: \
439
440 static enum bi_class
441 bi_class_for_nir_alu(nir_op op)
442 {
443 switch (op) {
444 case nir_op_iadd:
445 case nir_op_fadd:
446 case nir_op_fsub:
447 return BI_ADD;
448 case nir_op_isub:
449 return BI_ISUB;
450
451 case nir_op_iand:
452 case nir_op_ior:
453 case nir_op_ixor:
454 return BI_BITWISE;
455
456 BI_CASE_CMP(nir_op_flt)
457 BI_CASE_CMP(nir_op_fge)
458 BI_CASE_CMP(nir_op_feq)
459 BI_CASE_CMP(nir_op_fne)
460 BI_CASE_CMP(nir_op_ilt)
461 BI_CASE_CMP(nir_op_ige)
462 BI_CASE_CMP(nir_op_ieq)
463 BI_CASE_CMP(nir_op_ine)
464 return BI_CMP;
465
466 case nir_op_b8csel:
467 case nir_op_b16csel:
468 case nir_op_b32csel:
469 return BI_CSEL;
470
471 case nir_op_i2i8:
472 case nir_op_i2i16:
473 case nir_op_i2i32:
474 case nir_op_i2i64:
475 case nir_op_u2u8:
476 case nir_op_u2u16:
477 case nir_op_u2u32:
478 case nir_op_u2u64:
479 case nir_op_f2i16:
480 case nir_op_f2i32:
481 case nir_op_f2i64:
482 case nir_op_f2u16:
483 case nir_op_f2u32:
484 case nir_op_f2u64:
485 case nir_op_i2f16:
486 case nir_op_i2f32:
487 case nir_op_i2f64:
488 case nir_op_u2f16:
489 case nir_op_u2f32:
490 case nir_op_u2f64:
491 case nir_op_f2f16:
492 case nir_op_f2f32:
493 case nir_op_f2f64:
494 case nir_op_f2fmp:
495 return BI_CONVERT;
496
497 case nir_op_vec2:
498 case nir_op_vec3:
499 case nir_op_vec4:
500 return BI_COMBINE;
501
502 case nir_op_vec8:
503 case nir_op_vec16:
504 unreachable("should've been lowered");
505
506 case nir_op_ffma:
507 case nir_op_fmul:
508 return BI_FMA;
509
510 case nir_op_imin:
511 case nir_op_imax:
512 case nir_op_umin:
513 case nir_op_umax:
514 case nir_op_fmin:
515 case nir_op_fmax:
516 return BI_MINMAX;
517
518 case nir_op_fsat:
519 case nir_op_fneg:
520 case nir_op_fabs:
521 return BI_FMOV;
522 case nir_op_mov:
523 return BI_MOV;
524
525 case nir_op_fround_even:
526 case nir_op_fceil:
527 case nir_op_ffloor:
528 case nir_op_ftrunc:
529 return BI_ROUND;
530
531 case nir_op_frcp:
532 case nir_op_frsq:
533 return BI_SPECIAL;
534
535 default:
536 unreachable("Unknown ALU op");
537 }
538 }
539
540 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
541 * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
542 * optimizations). Otherwise it will bail (when used for primary code
543 * generation). */
544
545 static enum bi_cond
546 bi_cond_for_nir(nir_op op, bool soft)
547 {
548 switch (op) {
549 BI_CASE_CMP(nir_op_flt)
550 BI_CASE_CMP(nir_op_ilt)
551 return BI_COND_LT;
552
553 BI_CASE_CMP(nir_op_fge)
554 BI_CASE_CMP(nir_op_ige)
555 return BI_COND_GE;
556
557 BI_CASE_CMP(nir_op_feq)
558 BI_CASE_CMP(nir_op_ieq)
559 return BI_COND_EQ;
560
561 BI_CASE_CMP(nir_op_fne)
562 BI_CASE_CMP(nir_op_ine)
563 return BI_COND_NE;
564 default:
565 if (soft)
566 return BI_COND_ALWAYS;
567 else
568 unreachable("Invalid compare");
569 }
570 }
571
572 static void
573 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
574 unsigned *constants_left, unsigned *constant_shift, unsigned comps)
575 {
576 unsigned bits = nir_src_bit_size(instr->src[i].src);
577 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
578
579 alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
580 | bits;
581
582 /* Try to inline a constant */
583 if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
584 uint64_t mask = (1ull << dest_bits) - 1;
585 uint64_t cons = nir_src_as_uint(instr->src[i].src);
586
587 /* Try to reuse a constant */
588 for (unsigned i = 0; i < (*constant_shift); i += dest_bits) {
589 if (((alu->constant.u64 >> i) & mask) == cons) {
590 alu->src[to] = BIR_INDEX_CONSTANT | i;
591 return;
592 }
593 }
594
595 alu->constant.u64 |= cons << *constant_shift;
596 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
597 --(*constants_left);
598 (*constant_shift) += MAX2(dest_bits, 32); /* lo/hi */
599 return;
600 }
601
602 alu->src[to] = pan_src_index(&instr->src[i].src);
603
604 /* Copy swizzle for all vectored components, replicating last component
605 * to fill undersized */
606
607 unsigned vec = alu->type == BI_COMBINE ? 1 :
608 MAX2(1, 32 / dest_bits);
609
610 for (unsigned j = 0; j < vec; ++j)
611 alu->swizzle[to][j] = instr->src[i].swizzle[MIN2(j, comps - 1)];
612 }
613
614 static void
615 bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
616 unsigned *constants_left, unsigned *constant_shift, unsigned comps)
617 {
618 /* Bail for vector weirdness */
619 if (cond.swizzle[0] != 0)
620 return;
621
622 if (!cond.src.is_ssa)
623 return;
624
625 nir_ssa_def *def = cond.src.ssa;
626 nir_instr *parent = def->parent_instr;
627
628 if (parent->type != nir_instr_type_alu)
629 return;
630
631 nir_alu_instr *alu = nir_instr_as_alu(parent);
632
633 /* Try to match a condition */
634 enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
635
636 if (bcond == BI_COND_ALWAYS)
637 return;
638
639 /* We found one, let's fuse it in */
640 csel->cond = bcond;
641 bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift, comps);
642 bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift, comps);
643 }
644
645 static void
646 emit_alu(bi_context *ctx, nir_alu_instr *instr)
647 {
648 /* Try some special functions */
649 switch (instr->op) {
650 case nir_op_fexp2:
651 bi_emit_fexp2(ctx, instr);
652 return;
653 case nir_op_flog2:
654 bi_emit_flog2(ctx, instr);
655 return;
656 default:
657 break;
658 }
659
660 /* Otherwise, assume it's something we can handle normally */
661 bi_instruction alu = {
662 .type = bi_class_for_nir_alu(instr->op),
663 .dest = pan_dest_index(&instr->dest.dest),
664 .dest_type = nir_op_infos[instr->op].output_type
665 | nir_dest_bit_size(instr->dest.dest),
666 };
667
668 /* TODO: Implement lowering of special functions for older Bifrost */
669 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
670
671 unsigned comps = nir_dest_num_components(instr->dest.dest);
672
673 if (alu.type != BI_COMBINE)
674 assert(comps <= MAX2(1, 32 / comps));
675
676 if (!instr->dest.dest.is_ssa) {
677 for (unsigned i = 0; i < comps; ++i)
678 assert(instr->dest.write_mask);
679 }
680
681 /* We inline constants as we go. This tracks how many constants have
682 * been inlined, since we're limited to 64-bits of constants per
683 * instruction */
684
685 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
686 unsigned constants_left = (64 / dest_bits);
687 unsigned constant_shift = 0;
688
689 if (alu.type == BI_COMBINE)
690 constants_left = 0;
691
692 /* Copy sources */
693
694 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
695 assert(num_inputs <= ARRAY_SIZE(alu.src));
696
697 for (unsigned i = 0; i < num_inputs; ++i) {
698 unsigned f = 0;
699
700 if (i && alu.type == BI_CSEL)
701 f++;
702
703 bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift, comps);
704 }
705
706 /* Op-specific fixup */
707 switch (instr->op) {
708 case nir_op_fmul:
709 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
710 alu.src_types[2] = alu.src_types[1];
711 break;
712 case nir_op_fsat:
713 alu.outmod = BIFROST_SAT; /* FMOV */
714 break;
715 case nir_op_fneg:
716 alu.src_neg[0] = true; /* FMOV */
717 break;
718 case nir_op_fabs:
719 alu.src_abs[0] = true; /* FMOV */
720 break;
721 case nir_op_fsub:
722 alu.src_neg[1] = true; /* FADD */
723 break;
724 case nir_op_fmax:
725 case nir_op_imax:
726 case nir_op_umax:
727 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
728 break;
729 case nir_op_frcp:
730 alu.op.special = BI_SPECIAL_FRCP;
731 break;
732 case nir_op_frsq:
733 alu.op.special = BI_SPECIAL_FRSQ;
734 break;
735 BI_CASE_CMP(nir_op_flt)
736 BI_CASE_CMP(nir_op_ilt)
737 BI_CASE_CMP(nir_op_fge)
738 BI_CASE_CMP(nir_op_ige)
739 BI_CASE_CMP(nir_op_feq)
740 BI_CASE_CMP(nir_op_ieq)
741 BI_CASE_CMP(nir_op_fne)
742 BI_CASE_CMP(nir_op_ine)
743 alu.cond = bi_cond_for_nir(instr->op, false);
744 break;
745 case nir_op_fround_even:
746 alu.roundmode = BIFROST_RTE;
747 break;
748 case nir_op_fceil:
749 alu.roundmode = BIFROST_RTP;
750 break;
751 case nir_op_ffloor:
752 alu.roundmode = BIFROST_RTN;
753 break;
754 case nir_op_ftrunc:
755 alu.roundmode = BIFROST_RTZ;
756 break;
757 case nir_op_iand:
758 alu.op.bitwise = BI_BITWISE_AND;
759 break;
760 case nir_op_ior:
761 alu.op.bitwise = BI_BITWISE_OR;
762 break;
763 case nir_op_ixor:
764 alu.op.bitwise = BI_BITWISE_XOR;
765 break;
766 default:
767 break;
768 }
769
770 if (alu.type == BI_CSEL) {
771 /* Default to csel3 */
772 alu.cond = BI_COND_NE;
773 alu.src[1] = BIR_INDEX_ZERO;
774 alu.src_types[1] = alu.src_types[0];
775
776 bi_fuse_csel_cond(&alu, instr->src[0],
777 &constants_left, &constant_shift, comps);
778 } else if (alu.type == BI_BITWISE) {
779 /* Implicit shift argument... at some point we should fold */
780 alu.src[2] = BIR_INDEX_ZERO;
781 alu.src_types[2] = alu.src_types[1];
782 }
783
784 bi_emit(ctx, alu);
785 }
786
787 /* TEX_COMPACT instructions assume normal 2D f32 operation but are more
788 * space-efficient and with simpler RA/scheduling requirements*/
789
790 static void
791 emit_tex_compact(bi_context *ctx, nir_tex_instr *instr)
792 {
793 bi_instruction tex = {
794 .type = BI_TEX,
795 .op = { .texture = BI_TEX_COMPACT },
796 .texture = {
797 .texture_index = instr->texture_index,
798 .sampler_index = instr->sampler_index,
799 },
800 .dest = pan_dest_index(&instr->dest),
801 .dest_type = instr->dest_type,
802 .src_types = { nir_type_float32, nir_type_float32 },
803 .vector_channels = 4
804 };
805
806 for (unsigned i = 0; i < instr->num_srcs; ++i) {
807 int index = pan_src_index(&instr->src[i].src);
808 assert (instr->src[i].src_type == nir_tex_src_coord);
809
810 tex.src[0] = index;
811 tex.src[1] = index;
812 tex.swizzle[0][0] = 0;
813 tex.swizzle[1][0] = 1;
814 }
815
816 bi_emit(ctx, tex);
817 }
818
819 static void
820 emit_tex_full(bi_context *ctx, nir_tex_instr *instr)
821 {
822 unreachable("stub");
823 }
824
825 static void
826 emit_tex(bi_context *ctx, nir_tex_instr *instr)
827 {
828 nir_alu_type base = nir_alu_type_get_base_type(instr->dest_type);
829 unsigned sz = nir_dest_bit_size(instr->dest);
830 instr->dest_type = base | sz;
831
832 bool is_normal = instr->op == nir_texop_tex;
833 bool is_2d = instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
834 instr->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL;
835 bool is_f = base == nir_type_float && (sz == 16 || sz == 32);
836
837 bool is_compact = is_normal && is_2d && is_f && !instr->is_shadow;
838
839 if (is_compact)
840 emit_tex_compact(ctx, instr);
841 else
842 emit_tex_full(ctx, instr);
843 }
844
845 static void
846 emit_instr(bi_context *ctx, struct nir_instr *instr)
847 {
848 switch (instr->type) {
849 case nir_instr_type_load_const:
850 emit_load_const(ctx, nir_instr_as_load_const(instr));
851 break;
852
853 case nir_instr_type_intrinsic:
854 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
855 break;
856
857 case nir_instr_type_alu:
858 emit_alu(ctx, nir_instr_as_alu(instr));
859 break;
860
861 case nir_instr_type_tex:
862 emit_tex(ctx, nir_instr_as_tex(instr));
863 break;
864
865 case nir_instr_type_jump:
866 emit_jump(ctx, nir_instr_as_jump(instr));
867 break;
868
869 case nir_instr_type_ssa_undef:
870 /* Spurious */
871 break;
872
873 default:
874 unreachable("Unhandled instruction type");
875 break;
876 }
877 }
878
879
880
881 static bi_block *
882 create_empty_block(bi_context *ctx)
883 {
884 bi_block *blk = rzalloc(ctx, bi_block);
885
886 blk->base.predecessors = _mesa_set_create(blk,
887 _mesa_hash_pointer,
888 _mesa_key_pointer_equal);
889
890 blk->base.name = ctx->block_name_count++;
891
892 return blk;
893 }
894
895 static void
896 bi_schedule_barrier(bi_context *ctx)
897 {
898 bi_block *temp = ctx->after_block;
899 ctx->after_block = create_empty_block(ctx);
900 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
901 list_inithead(&ctx->after_block->base.instructions);
902 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
903 ctx->current_block = ctx->after_block;
904 ctx->after_block = temp;
905 }
906
907 static bi_block *
908 emit_block(bi_context *ctx, nir_block *block)
909 {
910 if (ctx->after_block) {
911 ctx->current_block = ctx->after_block;
912 ctx->after_block = NULL;
913 } else {
914 ctx->current_block = create_empty_block(ctx);
915 }
916
917 list_addtail(&ctx->current_block->base.link, &ctx->blocks);
918 list_inithead(&ctx->current_block->base.instructions);
919
920 nir_foreach_instr(instr, block) {
921 emit_instr(ctx, instr);
922 ++ctx->instruction_count;
923 }
924
925 return ctx->current_block;
926 }
927
928 /* Emits an unconditional branch to the end of the current block, returning a
929 * pointer so the user can fill in details */
930
931 static bi_instruction *
932 bi_emit_branch(bi_context *ctx)
933 {
934 bi_instruction branch = {
935 .type = BI_BRANCH,
936 .branch = {
937 .cond = BI_COND_ALWAYS
938 }
939 };
940
941 return bi_emit(ctx, branch);
942 }
943
944 /* Sets a condition for a branch by examing the NIR condition. If we're
945 * familiar with the condition, we unwrap it to fold it into the branch
946 * instruction. Otherwise, we consume the condition directly. We
947 * generally use 1-bit booleans which allows us to use small types for
948 * the conditions.
949 */
950
951 static void
952 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
953 {
954 /* TODO: Try to unwrap instead of always bailing */
955 branch->src[0] = pan_src_index(cond);
956 branch->src[1] = BIR_INDEX_ZERO;
957 branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
958 branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
959 }
960
961 static void
962 emit_if(bi_context *ctx, nir_if *nif)
963 {
964 bi_block *before_block = ctx->current_block;
965
966 /* Speculatively emit the branch, but we can't fill it in until later */
967 bi_instruction *then_branch = bi_emit_branch(ctx);
968 bi_set_branch_cond(then_branch, &nif->condition, true);
969
970 /* Emit the two subblocks. */
971 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
972 bi_block *end_then_block = ctx->current_block;
973
974 /* Emit a jump from the end of the then block to the end of the else */
975 bi_instruction *then_exit = bi_emit_branch(ctx);
976
977 /* Emit second block, and check if it's empty */
978
979 int count_in = ctx->instruction_count;
980 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
981 bi_block *end_else_block = ctx->current_block;
982 ctx->after_block = create_empty_block(ctx);
983
984 /* Now that we have the subblocks emitted, fix up the branches */
985
986 assert(then_block);
987 assert(else_block);
988
989 if (ctx->instruction_count == count_in) {
990 /* The else block is empty, so don't emit an exit jump */
991 bi_remove_instruction(then_exit);
992 then_branch->branch.target = ctx->after_block;
993 } else {
994 then_branch->branch.target = else_block;
995 then_exit->branch.target = ctx->after_block;
996 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
997 }
998
999 /* Wire up the successors */
1000
1001 pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
1002
1003 pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
1004 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
1005 }
1006
1007 static void
1008 emit_loop(bi_context *ctx, nir_loop *nloop)
1009 {
1010 /* Remember where we are */
1011 bi_block *start_block = ctx->current_block;
1012
1013 bi_block *saved_break = ctx->break_block;
1014 bi_block *saved_continue = ctx->continue_block;
1015
1016 ctx->continue_block = create_empty_block(ctx);
1017 ctx->break_block = create_empty_block(ctx);
1018 ctx->after_block = ctx->continue_block;
1019
1020 /* Emit the body itself */
1021 emit_cf_list(ctx, &nloop->body);
1022
1023 /* Branch back to loop back */
1024 bi_instruction *br_back = bi_emit_branch(ctx);
1025 br_back->branch.target = ctx->continue_block;
1026 pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
1027 pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
1028
1029 ctx->after_block = ctx->break_block;
1030
1031 /* Pop off */
1032 ctx->break_block = saved_break;
1033 ctx->continue_block = saved_continue;
1034 ++ctx->loop_count;
1035 }
1036
1037 static bi_block *
1038 emit_cf_list(bi_context *ctx, struct exec_list *list)
1039 {
1040 bi_block *start_block = NULL;
1041
1042 foreach_list_typed(nir_cf_node, node, node, list) {
1043 switch (node->type) {
1044 case nir_cf_node_block: {
1045 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
1046
1047 if (!start_block)
1048 start_block = block;
1049
1050 break;
1051 }
1052
1053 case nir_cf_node_if:
1054 emit_if(ctx, nir_cf_node_as_if(node));
1055 break;
1056
1057 case nir_cf_node_loop:
1058 emit_loop(ctx, nir_cf_node_as_loop(node));
1059 break;
1060
1061 default:
1062 unreachable("Unknown control flow");
1063 }
1064 }
1065
1066 return start_block;
1067 }
1068
1069 static int
1070 glsl_type_size(const struct glsl_type *type, bool bindless)
1071 {
1072 return glsl_count_attribute_slots(type, false);
1073 }
1074
1075 static void
1076 bi_optimize_nir(nir_shader *nir)
1077 {
1078 bool progress;
1079 unsigned lower_flrp = 16 | 32 | 64;
1080
1081 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
1082 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
1083
1084 nir_lower_tex_options lower_tex_options = {
1085 .lower_txs_lod = true,
1086 .lower_txp = ~0,
1087 .lower_tex_without_implicit_lod = true,
1088 .lower_txd = true,
1089 };
1090
1091 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
1092 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1093 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1094
1095 do {
1096 progress = false;
1097
1098 NIR_PASS(progress, nir, nir_lower_var_copies);
1099 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
1100
1101 NIR_PASS(progress, nir, nir_copy_prop);
1102 NIR_PASS(progress, nir, nir_opt_remove_phis);
1103 NIR_PASS(progress, nir, nir_opt_dce);
1104 NIR_PASS(progress, nir, nir_opt_dead_cf);
1105 NIR_PASS(progress, nir, nir_opt_cse);
1106 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
1107 NIR_PASS(progress, nir, nir_opt_algebraic);
1108 NIR_PASS(progress, nir, nir_opt_constant_folding);
1109
1110 if (lower_flrp != 0) {
1111 bool lower_flrp_progress = false;
1112 NIR_PASS(lower_flrp_progress,
1113 nir,
1114 nir_lower_flrp,
1115 lower_flrp,
1116 false /* always_precise */,
1117 nir->options->lower_ffma);
1118 if (lower_flrp_progress) {
1119 NIR_PASS(progress, nir,
1120 nir_opt_constant_folding);
1121 progress = true;
1122 }
1123
1124 /* Nothing should rematerialize any flrps, so we only
1125 * need to do this lowering once.
1126 */
1127 lower_flrp = 0;
1128 }
1129
1130 NIR_PASS(progress, nir, nir_opt_undef);
1131 NIR_PASS(progress, nir, nir_opt_loop_unroll,
1132 nir_var_shader_in |
1133 nir_var_shader_out |
1134 nir_var_function_temp);
1135 } while (progress);
1136
1137 NIR_PASS(progress, nir, nir_opt_algebraic_late);
1138 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
1139 NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
1140 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1141 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1142
1143 /* Take us out of SSA */
1144 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
1145 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
1146 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
1147 }
1148
1149 void
1150 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
1151 {
1152 bifrost_debug = debug_get_option_bifrost_debug();
1153
1154 bi_context *ctx = rzalloc(NULL, bi_context);
1155 ctx->nir = nir;
1156 ctx->stage = nir->info.stage;
1157 ctx->quirks = bifrost_get_quirks(product_id);
1158 list_inithead(&ctx->blocks);
1159
1160 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
1161 * (so we don't accidentally duplicate the epilogue since mesa/st has
1162 * messed with our I/O quite a bit already) */
1163
1164 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1165
1166 if (ctx->stage == MESA_SHADER_VERTEX) {
1167 NIR_PASS_V(nir, nir_lower_viewport_transform);
1168 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
1169 }
1170
1171 NIR_PASS_V(nir, nir_split_var_copies);
1172 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
1173 NIR_PASS_V(nir, nir_lower_var_copies);
1174 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1175 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
1176 NIR_PASS_V(nir, nir_lower_ssbo);
1177 NIR_PASS_V(nir, nir_lower_mediump_outputs);
1178
1179 bi_optimize_nir(nir);
1180
1181 if (bifrost_debug & BIFROST_DBG_SHADERS) {
1182 nir_print_shader(nir, stdout);
1183 }
1184
1185 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
1186 program->sysval_count = ctx->sysvals.sysval_count;
1187 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
1188 ctx->blend_types = program->blend_types;
1189
1190 nir_foreach_function(func, nir) {
1191 if (!func->impl)
1192 continue;
1193
1194 ctx->impl = func->impl;
1195 emit_cf_list(ctx, &func->impl->body);
1196 break; /* TODO: Multi-function shaders */
1197 }
1198
1199 bi_foreach_block(ctx, _block) {
1200 bi_block *block = (bi_block *) _block;
1201 bi_lower_combine(ctx, block);
1202 }
1203
1204 bool progress = false;
1205
1206 do {
1207 progress = false;
1208
1209 bi_foreach_block(ctx, _block) {
1210 bi_block *block = (bi_block *) _block;
1211 progress |= bi_opt_dead_code_eliminate(ctx, block);
1212 }
1213 } while(progress);
1214
1215 if (bifrost_debug & BIFROST_DBG_SHADERS)
1216 bi_print_shader(ctx, stdout);
1217 bi_schedule(ctx);
1218 bi_register_allocate(ctx);
1219 if (bifrost_debug & BIFROST_DBG_SHADERS)
1220 bi_print_shader(ctx, stdout);
1221 bi_pack(ctx, &program->compiled);
1222
1223 if (bifrost_debug & BIFROST_DBG_SHADERS)
1224 disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1225
1226 ralloc_free(ctx);
1227 }