2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "compiler/nir/nir_builder.h"
31 #include "util/u_debug.h"
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "bifrost_nir.h"
37 #include "bi_quirks.h"
40 static const struct debug_named_value debug_options
[] = {
41 {"msgs", BIFROST_DBG_MSGS
, "Print debug messages"},
42 {"shaders", BIFROST_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
46 DEBUG_GET_ONCE_FLAGS_OPTION(bifrost_debug
, "BIFROST_MESA_DEBUG", debug_options
, 0)
48 int bifrost_debug
= 0;
50 #define DBG(fmt, ...) \
51 do { if (bifrost_debug & BIFROST_DBG_MSGS) \
52 fprintf(stderr, "%s:%d: "fmt, \
53 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
55 static bi_block
*emit_cf_list(bi_context
*ctx
, struct exec_list
*list
);
56 static bi_instruction
*bi_emit_branch(bi_context
*ctx
);
57 static void bi_schedule_barrier(bi_context
*ctx
);
60 emit_jump(bi_context
*ctx
, nir_jump_instr
*instr
)
62 bi_instruction
*branch
= bi_emit_branch(ctx
);
64 switch (instr
->type
) {
66 branch
->branch_target
= ctx
->break_block
;
68 case nir_jump_continue
:
69 branch
->branch_target
= ctx
->continue_block
;
72 unreachable("Unhandled jump type");
75 pan_block_add_successor(&ctx
->current_block
->base
, &branch
->branch_target
->base
);
79 bi_load(enum bi_class T
, nir_intrinsic_instr
*instr
)
81 bi_instruction load
= {
83 .vector_channels
= instr
->num_components
,
84 .src
= { BIR_INDEX_CONSTANT
},
85 .src_types
= { nir_type_uint32
},
86 .constant
= { .u64
= nir_intrinsic_base(instr
) },
89 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
92 load
.dest
= pan_dest_index(&instr
->dest
);
94 if (info
->has_dest
&& info
->index_map
[NIR_INTRINSIC_TYPE
] > 0)
95 load
.dest_type
= nir_intrinsic_type(instr
);
97 nir_src
*offset
= nir_get_io_offset_src(instr
);
99 if (nir_src_is_const(*offset
))
100 load
.constant
.u64
+= nir_src_as_uint(*offset
);
102 load
.src
[0] = pan_src_index(offset
);
108 bi_emit_ld_vary(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
110 bi_instruction ins
= bi_load(BI_LOAD_VAR
, instr
);
111 ins
.load_vary
.interp_mode
= BIFROST_INTERP_DEFAULT
; /* TODO */
112 ins
.load_vary
.reuse
= false; /* TODO */
113 ins
.load_vary
.flat
= instr
->intrinsic
!= nir_intrinsic_load_interpolated_input
;
114 ins
.dest_type
= nir_type_float
| nir_dest_bit_size(instr
->dest
);
116 if (nir_src_is_const(*nir_get_io_offset_src(instr
))) {
117 /* Zero it out for direct */
118 ins
.src
[1] = BIR_INDEX_ZERO
;
120 /* R61 contains sample mask stuff, TODO RA XXX */
121 ins
.src
[1] = BIR_INDEX_REGISTER
| 61;
128 bi_emit_frag_out(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
130 if (!ctx
->emitted_atest
) {
131 bi_instruction ins
= {
134 BIR_INDEX_REGISTER
| 60 /* TODO: RA */,
135 pan_src_index(&instr
->src
[0])
139 nir_intrinsic_type(instr
)
143 { 3, 0 } /* swizzle out the alpha */
145 .dest
= BIR_INDEX_REGISTER
| 60 /* TODO: RA */,
146 .dest_type
= nir_type_uint32
,
150 bi_schedule_barrier(ctx
);
151 ctx
->emitted_atest
= true;
154 bi_instruction blend
= {
156 .blend_location
= nir_intrinsic_base(instr
),
158 pan_src_index(&instr
->src
[0]),
159 BIR_INDEX_REGISTER
| 60 /* Can this be arbitrary? */,
162 nir_intrinsic_type(instr
),
169 .dest
= BIR_INDEX_REGISTER
| 48 /* Looks like magic */,
170 .dest_type
= nir_type_uint32
,
174 assert(blend
.blend_location
< BIFROST_MAX_RENDER_TARGET_COUNT
);
175 assert(ctx
->blend_types
);
176 assert(blend
.src_types
[0]);
177 ctx
->blend_types
[blend
.blend_location
] = blend
.src_types
[0];
180 bi_schedule_barrier(ctx
);
183 static bi_instruction
184 bi_load_with_r61(enum bi_class T
, nir_intrinsic_instr
*instr
)
186 bi_instruction ld
= bi_load(T
, instr
);
187 ld
.src
[1] = BIR_INDEX_REGISTER
| 61; /* TODO: RA */
188 ld
.src
[2] = BIR_INDEX_REGISTER
| 62;
190 ld
.src_types
[1] = nir_type_uint32
;
191 ld
.src_types
[2] = nir_type_uint32
;
192 ld
.src_types
[3] = nir_intrinsic_type(instr
);
197 bi_emit_st_vary(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
199 bi_instruction address
= bi_load_with_r61(BI_LOAD_VAR_ADDRESS
, instr
);
200 address
.dest
= bi_make_temp(ctx
);
201 address
.dest_type
= nir_type_uint32
;
202 address
.vector_channels
= 3;
204 unsigned nr
= nir_intrinsic_src_components(instr
, 0);
205 assert(nir_intrinsic_write_mask(instr
) == ((1 << nr
) - 1));
207 bi_instruction st
= {
208 .type
= BI_STORE_VAR
,
210 pan_src_index(&instr
->src
[0]),
211 address
.dest
, address
.dest
, address
.dest
,
215 nir_type_uint32
, nir_type_uint32
, nir_type_uint32
,
221 .vector_channels
= nr
,
224 for (unsigned i
= 0; i
< nr
; ++i
)
225 st
.swizzle
[0][i
] = i
;
227 bi_emit(ctx
, address
);
232 bi_emit_ld_uniform(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
234 bi_instruction ld
= bi_load(BI_LOAD_UNIFORM
, instr
);
235 ld
.src
[1] = BIR_INDEX_ZERO
; /* TODO: UBO index */
237 /* TODO: Indirect access, since we need to multiply by the element
238 * size. I believe we can get this lowering automatically via
239 * nir_lower_io (as mul instructions) with the proper options, but this
241 assert(ld
.src
[0] & BIR_INDEX_CONSTANT
);
242 ld
.constant
.u64
+= ctx
->sysvals
.sysval_count
;
243 ld
.constant
.u64
*= 16;
249 bi_emit_sysval(bi_context
*ctx
, nir_instr
*instr
,
250 unsigned nr_components
, unsigned offset
)
254 /* Figure out which uniform this is */
255 int sysval
= panfrost_sysval_for_instr(instr
, &nir_dest
);
256 void *val
= _mesa_hash_table_u64_search(ctx
->sysvals
.sysval_to_id
, sysval
);
258 /* Sysvals are prefix uniforms */
259 unsigned uniform
= ((uintptr_t) val
) - 1;
261 /* Emit the read itself -- this is never indirect */
263 bi_instruction load
= {
264 .type
= BI_LOAD_UNIFORM
,
265 .vector_channels
= nr_components
,
266 .src
= { BIR_INDEX_CONSTANT
, BIR_INDEX_ZERO
},
267 .src_types
= { nir_type_uint32
, nir_type_uint32
},
268 .constant
= { (uniform
* 16) + offset
},
269 .dest
= pan_dest_index(&nir_dest
),
270 .dest_type
= nir_type_uint32
, /* TODO */
276 /* gl_FragCoord.xy = u16_to_f32(R59.xy) + 0.5
277 * gl_FragCoord.z = ld_vary(fragz)
278 * gl_FragCoord.w = ld_vary(fragw)
282 bi_emit_ld_frag_coord(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
284 /* Future proofing for mediump fragcoord at some point.. */
285 nir_alu_type T
= nir_type_float32
;
287 /* First, sketch a combine */
288 bi_instruction combine
= {
290 .dest_type
= nir_type_uint32
,
291 .dest
= pan_dest_index(&instr
->dest
),
292 .src_types
= { T
, T
, T
, T
},
295 /* Second, handle xy */
296 for (unsigned i
= 0; i
< 2; ++i
) {
297 bi_instruction conv
= {
300 .dest
= bi_make_temp(ctx
),
303 BIR_INDEX_REGISTER
| 59
305 .src_types
= { nir_type_uint16
},
309 bi_instruction add
= {
312 .dest
= bi_make_temp(ctx
),
313 .src
= { conv
.dest
, BIR_INDEX_CONSTANT
},
314 .src_types
= { T
, T
},
318 memcpy(&add
.constant
.u32
, &half
, sizeof(float));
323 combine
.src
[i
] = add
.dest
;
327 for (unsigned i
= 0; i
< 2; ++i
) {
328 bi_instruction load
= {
331 .interp_mode
= BIFROST_INTERP_DEFAULT
,
335 .vector_channels
= 1,
336 .dest_type
= nir_type_float32
,
337 .dest
= bi_make_temp(ctx
),
338 .src
= { BIR_INDEX_CONSTANT
, BIR_INDEX_ZERO
},
339 .src_types
= { nir_type_uint32
, nir_type_uint32
},
341 .u32
= (i
== 0) ? BIFROST_FRAGZ
: BIFROST_FRAGW
347 combine
.src
[i
+ 2] = load
.dest
;
350 /* Finally, emit the combine */
351 bi_emit(ctx
, combine
);
355 bi_emit_discard(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
358 bi_instruction discard
= {
361 .src_types
= { nir_type_uint32
, nir_type_uint32
},
362 .src
= { BIR_INDEX_ZERO
, BIR_INDEX_ZERO
},
365 bi_emit(ctx
, discard
);
369 bi_fuse_cond(bi_instruction
*csel
, nir_alu_src cond
,
370 unsigned *constants_left
, unsigned *constant_shift
,
371 unsigned comps
, bool float_only
);
374 bi_emit_discard_if(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
376 nir_src cond
= instr
->src
[0];
377 nir_alu_type T
= nir_type_uint
| nir_src_bit_size(cond
);
379 bi_instruction discard
= {
382 .src_types
= { T
, T
},
384 pan_src_index(&cond
),
389 /* Try to fuse in the condition */
390 unsigned constants_left
= 1, constant_shift
= 0;
392 /* Scalar so no swizzle */
397 /* May or may not succeed but we're optimistic */
398 bi_fuse_cond(&discard
, wrap
, &constants_left
, &constant_shift
, 1, true);
400 bi_emit(ctx
, discard
);
404 emit_intrinsic(bi_context
*ctx
, nir_intrinsic_instr
*instr
)
407 switch (instr
->intrinsic
) {
408 case nir_intrinsic_load_barycentric_pixel
:
411 case nir_intrinsic_load_interpolated_input
:
412 case nir_intrinsic_load_input
:
413 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
414 bi_emit_ld_vary(ctx
, instr
);
415 else if (ctx
->stage
== MESA_SHADER_VERTEX
)
416 bi_emit(ctx
, bi_load_with_r61(BI_LOAD_ATTR
, instr
));
418 unreachable("Unsupported shader stage");
422 case nir_intrinsic_store_output
:
423 if (ctx
->stage
== MESA_SHADER_FRAGMENT
)
424 bi_emit_frag_out(ctx
, instr
);
425 else if (ctx
->stage
== MESA_SHADER_VERTEX
)
426 bi_emit_st_vary(ctx
, instr
);
428 unreachable("Unsupported shader stage");
431 case nir_intrinsic_load_uniform
:
432 bi_emit_ld_uniform(ctx
, instr
);
435 case nir_intrinsic_load_frag_coord
:
436 bi_emit_ld_frag_coord(ctx
, instr
);
439 case nir_intrinsic_discard
:
440 bi_emit_discard(ctx
, instr
);
443 case nir_intrinsic_discard_if
:
444 bi_emit_discard_if(ctx
, instr
);
447 case nir_intrinsic_load_ssbo_address
:
448 bi_emit_sysval(ctx
, &instr
->instr
, 1, 0);
451 case nir_intrinsic_get_buffer_size
:
452 bi_emit_sysval(ctx
, &instr
->instr
, 1, 8);
455 case nir_intrinsic_load_viewport_scale
:
456 case nir_intrinsic_load_viewport_offset
:
457 case nir_intrinsic_load_num_work_groups
:
458 case nir_intrinsic_load_sampler_lod_parameters_pan
:
459 bi_emit_sysval(ctx
, &instr
->instr
, 3, 0);
463 unreachable("Unknown intrinsic");
469 emit_load_const(bi_context
*ctx
, nir_load_const_instr
*instr
)
471 /* Make sure we've been lowered */
472 assert(instr
->def
.num_components
== 1);
474 bi_instruction move
= {
476 .dest
= pan_ssa_index(&instr
->def
),
477 .dest_type
= instr
->def
.bit_size
| nir_type_uint
,
482 instr
->def
.bit_size
| nir_type_uint
,
485 .u64
= nir_const_value_as_uint(instr
->value
[0], instr
->def
.bit_size
)
492 #define BI_CASE_CMP(op) \
498 bi_class_for_nir_alu(nir_op op
)
514 BI_CASE_CMP(nir_op_flt
)
515 BI_CASE_CMP(nir_op_fge
)
516 BI_CASE_CMP(nir_op_feq
)
517 BI_CASE_CMP(nir_op_fne
)
518 BI_CASE_CMP(nir_op_ilt
)
519 BI_CASE_CMP(nir_op_ige
)
520 BI_CASE_CMP(nir_op_ieq
)
521 BI_CASE_CMP(nir_op_ine
)
562 unreachable("should've been lowered");
583 case nir_op_fround_even
:
594 unreachable("Unknown ALU op");
598 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
599 * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
600 * optimizations). Otherwise it will bail (when used for primary code
604 bi_cond_for_nir(nir_op op
, bool soft
)
607 BI_CASE_CMP(nir_op_flt
)
608 BI_CASE_CMP(nir_op_ilt
)
611 BI_CASE_CMP(nir_op_fge
)
612 BI_CASE_CMP(nir_op_ige
)
615 BI_CASE_CMP(nir_op_feq
)
616 BI_CASE_CMP(nir_op_ieq
)
619 BI_CASE_CMP(nir_op_fne
)
620 BI_CASE_CMP(nir_op_ine
)
624 return BI_COND_ALWAYS
;
626 unreachable("Invalid compare");
631 bi_copy_src(bi_instruction
*alu
, nir_alu_instr
*instr
, unsigned i
, unsigned to
,
632 unsigned *constants_left
, unsigned *constant_shift
, unsigned comps
)
634 unsigned bits
= nir_src_bit_size(instr
->src
[i
].src
);
635 unsigned dest_bits
= nir_dest_bit_size(instr
->dest
.dest
);
637 alu
->src_types
[to
] = nir_op_infos
[instr
->op
].input_types
[i
]
640 /* Try to inline a constant */
641 if (nir_src_is_const(instr
->src
[i
].src
) && *constants_left
&& (dest_bits
== bits
)) {
642 uint64_t mask
= (1ull << dest_bits
) - 1;
643 uint64_t cons
= nir_src_as_uint(instr
->src
[i
].src
);
645 /* Try to reuse a constant */
646 for (unsigned i
= 0; i
< (*constant_shift
); i
+= dest_bits
) {
647 if (((alu
->constant
.u64
>> i
) & mask
) == cons
) {
648 alu
->src
[to
] = BIR_INDEX_CONSTANT
| i
;
653 alu
->constant
.u64
|= cons
<< *constant_shift
;
654 alu
->src
[to
] = BIR_INDEX_CONSTANT
| (*constant_shift
);
656 (*constant_shift
) += MAX2(dest_bits
, 32); /* lo/hi */
660 alu
->src
[to
] = pan_src_index(&instr
->src
[i
].src
);
662 /* Copy swizzle for all vectored components, replicating last component
663 * to fill undersized */
665 unsigned vec
= alu
->type
== BI_COMBINE
? 1 :
666 MAX2(1, 32 / dest_bits
);
668 for (unsigned j
= 0; j
< vec
; ++j
)
669 alu
->swizzle
[to
][j
] = instr
->src
[i
].swizzle
[MIN2(j
, comps
- 1)];
673 bi_fuse_cond(bi_instruction
*csel
, nir_alu_src cond
,
674 unsigned *constants_left
, unsigned *constant_shift
,
675 unsigned comps
, bool float_only
)
677 /* Bail for vector weirdness */
678 if (cond
.swizzle
[0] != 0)
681 if (!cond
.src
.is_ssa
)
684 nir_ssa_def
*def
= cond
.src
.ssa
;
685 nir_instr
*parent
= def
->parent_instr
;
687 if (parent
->type
!= nir_instr_type_alu
)
690 nir_alu_instr
*alu
= nir_instr_as_alu(parent
);
692 /* Try to match a condition */
693 enum bi_cond bcond
= bi_cond_for_nir(alu
->op
, true);
695 if (bcond
== BI_COND_ALWAYS
)
698 /* Some instructions can't compare ints */
700 nir_alu_type T
= nir_op_infos
[alu
->op
].input_types
[0];
701 T
= nir_alu_type_get_base_type(T
);
703 if (T
!= nir_type_float
)
707 /* We found one, let's fuse it in */
709 bi_copy_src(csel
, alu
, 0, 0, constants_left
, constant_shift
, comps
);
710 bi_copy_src(csel
, alu
, 1, 1, constants_left
, constant_shift
, comps
);
714 emit_alu(bi_context
*ctx
, nir_alu_instr
*instr
)
716 /* Try some special functions */
719 bi_emit_fexp2(ctx
, instr
);
722 bi_emit_flog2(ctx
, instr
);
728 /* Otherwise, assume it's something we can handle normally */
729 bi_instruction alu
= {
730 .type
= bi_class_for_nir_alu(instr
->op
),
731 .dest
= pan_dest_index(&instr
->dest
.dest
),
732 .dest_type
= nir_op_infos
[instr
->op
].output_type
733 | nir_dest_bit_size(instr
->dest
.dest
),
736 /* TODO: Implement lowering of special functions for older Bifrost */
737 assert((alu
.type
!= BI_SPECIAL
) || !(ctx
->quirks
& BIFROST_NO_FAST_OP
));
739 unsigned comps
= nir_dest_num_components(instr
->dest
.dest
);
741 if (alu
.type
!= BI_COMBINE
)
742 assert(comps
<= MAX2(1, 32 / comps
));
744 if (!instr
->dest
.dest
.is_ssa
) {
745 for (unsigned i
= 0; i
< comps
; ++i
)
746 assert(instr
->dest
.write_mask
);
749 /* We inline constants as we go. This tracks how many constants have
750 * been inlined, since we're limited to 64-bits of constants per
753 unsigned dest_bits
= nir_dest_bit_size(instr
->dest
.dest
);
754 unsigned constants_left
= (64 / dest_bits
);
755 unsigned constant_shift
= 0;
757 if (alu
.type
== BI_COMBINE
)
762 unsigned num_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
763 assert(num_inputs
<= ARRAY_SIZE(alu
.src
));
765 for (unsigned i
= 0; i
< num_inputs
; ++i
) {
768 if (i
&& alu
.type
== BI_CSEL
)
771 bi_copy_src(&alu
, instr
, i
, i
+ f
, &constants_left
, &constant_shift
, comps
);
774 /* Op-specific fixup */
777 alu
.src
[2] = BIR_INDEX_ZERO
; /* FMA */
778 alu
.src_types
[2] = alu
.src_types
[1];
781 alu
.outmod
= BIFROST_SAT
; /* FMOV */
784 alu
.src_neg
[0] = true; /* FMOV */
787 alu
.src_abs
[0] = true; /* FMOV */
790 alu
.src_neg
[1] = true; /* FADD */
793 alu
.op
.imath
= BI_IMATH_ADD
;
796 alu
.op
.imath
= BI_IMATH_SUB
;
801 alu
.op
.minmax
= BI_MINMAX_MAX
; /* MINMAX */
804 alu
.op
.special
= BI_SPECIAL_FRCP
;
807 alu
.op
.special
= BI_SPECIAL_FRSQ
;
809 BI_CASE_CMP(nir_op_flt
)
810 BI_CASE_CMP(nir_op_ilt
)
811 BI_CASE_CMP(nir_op_fge
)
812 BI_CASE_CMP(nir_op_ige
)
813 BI_CASE_CMP(nir_op_feq
)
814 BI_CASE_CMP(nir_op_ieq
)
815 BI_CASE_CMP(nir_op_fne
)
816 BI_CASE_CMP(nir_op_ine
)
817 alu
.cond
= bi_cond_for_nir(instr
->op
, false);
819 case nir_op_fround_even
:
820 alu
.roundmode
= BIFROST_RTE
;
823 alu
.roundmode
= BIFROST_RTP
;
826 alu
.roundmode
= BIFROST_RTN
;
829 alu
.roundmode
= BIFROST_RTZ
;
832 alu
.op
.bitwise
= BI_BITWISE_AND
;
835 alu
.op
.bitwise
= BI_BITWISE_OR
;
838 alu
.op
.bitwise
= BI_BITWISE_XOR
;
844 if (alu
.type
== BI_CSEL
) {
845 /* Default to csel3 */
846 alu
.cond
= BI_COND_NE
;
847 alu
.src
[1] = BIR_INDEX_ZERO
;
848 alu
.src_types
[1] = alu
.src_types
[0];
850 /* TODO: Reenable cond fusing when we can split up registers
853 bi_fuse_cond(&alu
, instr
->src
[0],
854 &constants_left
, &constant_shift
, comps
, false);
856 } else if (alu
.type
== BI_BITWISE
) {
857 /* Implicit shift argument... at some point we should fold */
858 alu
.src
[2] = BIR_INDEX_ZERO
;
859 alu
.src_types
[2] = alu
.src_types
[1];
865 /* TEX_COMPACT instructions assume normal 2D f32 operation but are more
866 * space-efficient and with simpler RA/scheduling requirements*/
869 emit_tex_compact(bi_context
*ctx
, nir_tex_instr
*instr
)
871 bi_instruction tex
= {
873 .op
= { .texture
= BI_TEX_COMPACT
},
875 .texture_index
= instr
->texture_index
,
876 .sampler_index
= instr
->sampler_index
,
878 .dest
= pan_dest_index(&instr
->dest
),
879 .dest_type
= instr
->dest_type
,
880 .src_types
= { nir_type_float32
, nir_type_float32
},
884 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
885 int index
= pan_src_index(&instr
->src
[i
].src
);
887 /* We were checked ahead-of-time */
888 if (instr
->src
[i
].src_type
== nir_tex_src_lod
)
891 assert (instr
->src
[i
].src_type
== nir_tex_src_coord
);
895 tex
.swizzle
[0][0] = 0;
896 tex
.swizzle
[1][0] = 1;
903 emit_tex_full(bi_context
*ctx
, nir_tex_instr
*instr
)
908 /* Normal textures ops are tex for frag shaders and txl for vertex shaders with
909 * lod a constant 0. Anything else needs a full texture op. */
912 bi_is_normal_tex(gl_shader_stage stage
, nir_tex_instr
*instr
)
914 if (stage
== MESA_SHADER_FRAGMENT
)
915 return instr
->op
== nir_texop_tex
;
917 if (instr
->op
!= nir_texop_txl
)
920 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
921 if (instr
->src
[i
].src_type
!= nir_tex_src_lod
)
924 nir_src src
= instr
->src
[i
].src
;
926 if (!nir_src_is_const(src
))
929 if (nir_src_as_uint(src
) != 0)
937 emit_tex(bi_context
*ctx
, nir_tex_instr
*instr
)
939 nir_alu_type base
= nir_alu_type_get_base_type(instr
->dest_type
);
940 unsigned sz
= nir_dest_bit_size(instr
->dest
);
941 instr
->dest_type
= base
| sz
;
943 bool is_normal
= bi_is_normal_tex(ctx
->stage
, instr
);
944 bool is_2d
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
945 instr
->sampler_dim
== GLSL_SAMPLER_DIM_EXTERNAL
;
946 bool is_f
= base
== nir_type_float
&& (sz
== 16 || sz
== 32);
948 bool is_compact
= is_normal
&& is_2d
&& is_f
&& !instr
->is_shadow
;
951 emit_tex_compact(ctx
, instr
);
953 emit_tex_full(ctx
, instr
);
957 emit_instr(bi_context
*ctx
, struct nir_instr
*instr
)
959 switch (instr
->type
) {
960 case nir_instr_type_load_const
:
961 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
964 case nir_instr_type_intrinsic
:
965 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
968 case nir_instr_type_alu
:
969 emit_alu(ctx
, nir_instr_as_alu(instr
));
972 case nir_instr_type_tex
:
973 emit_tex(ctx
, nir_instr_as_tex(instr
));
976 case nir_instr_type_jump
:
977 emit_jump(ctx
, nir_instr_as_jump(instr
));
980 case nir_instr_type_ssa_undef
:
985 unreachable("Unhandled instruction type");
993 create_empty_block(bi_context
*ctx
)
995 bi_block
*blk
= rzalloc(ctx
, bi_block
);
997 blk
->base
.predecessors
= _mesa_set_create(blk
,
999 _mesa_key_pointer_equal
);
1001 blk
->base
.name
= ctx
->block_name_count
++;
1007 bi_schedule_barrier(bi_context
*ctx
)
1009 bi_block
*temp
= ctx
->after_block
;
1010 ctx
->after_block
= create_empty_block(ctx
);
1011 list_addtail(&ctx
->after_block
->base
.link
, &ctx
->blocks
);
1012 list_inithead(&ctx
->after_block
->base
.instructions
);
1013 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->after_block
->base
);
1014 ctx
->current_block
= ctx
->after_block
;
1015 ctx
->after_block
= temp
;
1019 emit_block(bi_context
*ctx
, nir_block
*block
)
1021 if (ctx
->after_block
) {
1022 ctx
->current_block
= ctx
->after_block
;
1023 ctx
->after_block
= NULL
;
1025 ctx
->current_block
= create_empty_block(ctx
);
1028 list_addtail(&ctx
->current_block
->base
.link
, &ctx
->blocks
);
1029 list_inithead(&ctx
->current_block
->base
.instructions
);
1031 nir_foreach_instr(instr
, block
) {
1032 emit_instr(ctx
, instr
);
1033 ++ctx
->instruction_count
;
1036 return ctx
->current_block
;
1039 /* Emits an unconditional branch to the end of the current block, returning a
1040 * pointer so the user can fill in details */
1042 static bi_instruction
*
1043 bi_emit_branch(bi_context
*ctx
)
1045 bi_instruction branch
= {
1047 .cond
= BI_COND_ALWAYS
1050 return bi_emit(ctx
, branch
);
1053 /* Sets a condition for a branch by examing the NIR condition. If we're
1054 * familiar with the condition, we unwrap it to fold it into the branch
1055 * instruction. Otherwise, we consume the condition directly. We
1056 * generally use 1-bit booleans which allows us to use small types for
1061 bi_set_branch_cond(bi_instruction
*branch
, nir_src
*cond
, bool invert
)
1063 /* TODO: Try to unwrap instead of always bailing */
1064 branch
->src
[0] = pan_src_index(cond
);
1065 branch
->src
[1] = BIR_INDEX_ZERO
;
1066 branch
->src_types
[0] = branch
->src_types
[1] = nir_type_uint16
;
1067 branch
->cond
= invert
? BI_COND_EQ
: BI_COND_NE
;
1071 emit_if(bi_context
*ctx
, nir_if
*nif
)
1073 bi_block
*before_block
= ctx
->current_block
;
1075 /* Speculatively emit the branch, but we can't fill it in until later */
1076 bi_instruction
*then_branch
= bi_emit_branch(ctx
);
1077 bi_set_branch_cond(then_branch
, &nif
->condition
, true);
1079 /* Emit the two subblocks. */
1080 bi_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
1081 bi_block
*end_then_block
= ctx
->current_block
;
1083 /* Emit a jump from the end of the then block to the end of the else */
1084 bi_instruction
*then_exit
= bi_emit_branch(ctx
);
1086 /* Emit second block, and check if it's empty */
1088 int count_in
= ctx
->instruction_count
;
1089 bi_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
1090 bi_block
*end_else_block
= ctx
->current_block
;
1091 ctx
->after_block
= create_empty_block(ctx
);
1093 /* Now that we have the subblocks emitted, fix up the branches */
1098 if (ctx
->instruction_count
== count_in
) {
1099 /* The else block is empty, so don't emit an exit jump */
1100 bi_remove_instruction(then_exit
);
1101 then_branch
->branch_target
= ctx
->after_block
;
1103 then_branch
->branch_target
= else_block
;
1104 then_exit
->branch_target
= ctx
->after_block
;
1105 pan_block_add_successor(&end_then_block
->base
, &then_exit
->branch_target
->base
);
1108 /* Wire up the successors */
1110 pan_block_add_successor(&before_block
->base
, &then_branch
->branch_target
->base
); /* then_branch */
1112 pan_block_add_successor(&before_block
->base
, &then_block
->base
); /* fallthrough */
1113 pan_block_add_successor(&end_else_block
->base
, &ctx
->after_block
->base
); /* fallthrough */
1117 emit_loop(bi_context
*ctx
, nir_loop
*nloop
)
1119 /* Remember where we are */
1120 bi_block
*start_block
= ctx
->current_block
;
1122 bi_block
*saved_break
= ctx
->break_block
;
1123 bi_block
*saved_continue
= ctx
->continue_block
;
1125 ctx
->continue_block
= create_empty_block(ctx
);
1126 ctx
->break_block
= create_empty_block(ctx
);
1127 ctx
->after_block
= ctx
->continue_block
;
1129 /* Emit the body itself */
1130 emit_cf_list(ctx
, &nloop
->body
);
1132 /* Branch back to loop back */
1133 bi_instruction
*br_back
= bi_emit_branch(ctx
);
1134 br_back
->branch_target
= ctx
->continue_block
;
1135 pan_block_add_successor(&start_block
->base
, &ctx
->continue_block
->base
);
1136 pan_block_add_successor(&ctx
->current_block
->base
, &ctx
->continue_block
->base
);
1138 ctx
->after_block
= ctx
->break_block
;
1141 ctx
->break_block
= saved_break
;
1142 ctx
->continue_block
= saved_continue
;
1147 emit_cf_list(bi_context
*ctx
, struct exec_list
*list
)
1149 bi_block
*start_block
= NULL
;
1151 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1152 switch (node
->type
) {
1153 case nir_cf_node_block
: {
1154 bi_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
1157 start_block
= block
;
1162 case nir_cf_node_if
:
1163 emit_if(ctx
, nir_cf_node_as_if(node
));
1166 case nir_cf_node_loop
:
1167 emit_loop(ctx
, nir_cf_node_as_loop(node
));
1171 unreachable("Unknown control flow");
1179 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
1181 return glsl_count_attribute_slots(type
, false);
1185 bi_optimize_nir(nir_shader
*nir
)
1188 unsigned lower_flrp
= 16 | 32 | 64;
1190 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
1191 NIR_PASS(progress
, nir
, nir_lower_idiv
, nir_lower_idiv_fast
);
1193 nir_lower_tex_options lower_tex_options
= {
1194 .lower_txs_lod
= true,
1196 .lower_tex_without_implicit_lod
= true,
1200 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
1201 NIR_PASS(progress
, nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
1202 NIR_PASS(progress
, nir
, nir_lower_load_const_to_scalar
);
1207 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
1208 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
1210 NIR_PASS(progress
, nir
, nir_copy_prop
);
1211 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
1212 NIR_PASS(progress
, nir
, nir_opt_dce
);
1213 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
1214 NIR_PASS(progress
, nir
, nir_opt_cse
);
1215 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
1216 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
1217 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
1219 if (lower_flrp
!= 0) {
1220 bool lower_flrp_progress
= false;
1221 NIR_PASS(lower_flrp_progress
,
1225 false /* always_precise */,
1226 nir
->options
->lower_ffma
);
1227 if (lower_flrp_progress
) {
1228 NIR_PASS(progress
, nir
,
1229 nir_opt_constant_folding
);
1233 /* Nothing should rematerialize any flrps, so we only
1234 * need to do this lowering once.
1239 NIR_PASS(progress
, nir
, nir_opt_undef
);
1240 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
1242 nir_var_shader_out
|
1243 nir_var_function_temp
);
1246 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
1247 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
1248 NIR_PASS(progress
, nir
, bifrost_nir_lower_algebraic_late
);
1249 NIR_PASS(progress
, nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
1250 NIR_PASS(progress
, nir
, nir_lower_load_const_to_scalar
);
1252 /* Take us out of SSA */
1253 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
1254 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
1255 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
1259 bifrost_compile_shader_nir(nir_shader
*nir
, panfrost_program
*program
, unsigned product_id
)
1261 bifrost_debug
= debug_get_option_bifrost_debug();
1263 bi_context
*ctx
= rzalloc(NULL
, bi_context
);
1265 ctx
->stage
= nir
->info
.stage
;
1266 ctx
->quirks
= bifrost_get_quirks(product_id
);
1267 list_inithead(&ctx
->blocks
);
1269 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
1270 * (so we don't accidentally duplicate the epilogue since mesa/st has
1271 * messed with our I/O quite a bit already) */
1273 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
1275 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1276 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
1277 NIR_PASS_V(nir
, nir_lower_point_size
, 1.0, 1024.0);
1280 NIR_PASS_V(nir
, nir_split_var_copies
);
1281 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
1282 NIR_PASS_V(nir
, nir_lower_var_copies
);
1283 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
1284 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
1285 NIR_PASS_V(nir
, nir_lower_ssbo
);
1286 NIR_PASS_V(nir
, nir_lower_mediump_outputs
);
1288 bi_optimize_nir(nir
);
1290 if (bifrost_debug
& BIFROST_DBG_SHADERS
) {
1291 nir_print_shader(nir
, stdout
);
1294 panfrost_nir_assign_sysvals(&ctx
->sysvals
, nir
);
1295 program
->sysval_count
= ctx
->sysvals
.sysval_count
;
1296 memcpy(program
->sysvals
, ctx
->sysvals
.sysvals
, sizeof(ctx
->sysvals
.sysvals
[0]) * ctx
->sysvals
.sysval_count
);
1297 ctx
->blend_types
= program
->blend_types
;
1299 nir_foreach_function(func
, nir
) {
1303 ctx
->impl
= func
->impl
;
1304 emit_cf_list(ctx
, &func
->impl
->body
);
1305 break; /* TODO: Multi-function shaders */
1308 bi_foreach_block(ctx
, _block
) {
1309 bi_block
*block
= (bi_block
*) _block
;
1310 bi_lower_combine(ctx
, block
);
1313 bool progress
= false;
1318 bi_foreach_block(ctx
, _block
) {
1319 bi_block
*block
= (bi_block
*) _block
;
1320 progress
|= bi_opt_dead_code_eliminate(ctx
, block
);
1324 if (bifrost_debug
& BIFROST_DBG_SHADERS
)
1325 bi_print_shader(ctx
, stdout
);
1327 bi_register_allocate(ctx
);
1328 if (bifrost_debug
& BIFROST_DBG_SHADERS
)
1329 bi_print_shader(ctx
, stdout
);
1330 bi_pack(ctx
, &program
->compiled
);
1332 if (bifrost_debug
& BIFROST_DBG_SHADERS
)
1333 disassemble_bifrost(stdout
, program
->compiled
.data
, program
->compiled
.size
, true);