src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "main/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 106
 107         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 108                 /* Zero it out for direct */
 109                 ins.src[1] = BIR_INDEX_ZERO;
 110         } else {
 111                 /* R61 contains sample mask stuff, TODO RA XXX */
 112                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 113         }
 114
 115         bi_emit(ctx, ins);
 116 }
 117
 118 static void
 119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 120 {
 121         if (!ctx->emitted_atest) {
 122                 bi_instruction ins = {
 123                         .type = BI_ATEST,
 124                         .src = {
 125                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 126                                 bir_src_index(&instr->src[0])
 127                         },
 128                         .src_types = {
 129                                 nir_type_uint32,
 130                                 nir_type_float32
 131                         },
 132                         .swizzle = {
 133                                 { 0 },
 134                                 { 3, 0 } /* swizzle out the alpha */
 135                         },
 136                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 137                         .dest_type = nir_type_uint32,
 138                         .writemask = 0xF
 139                 };
 140
 141                 bi_emit(ctx, ins);
 142                 bi_schedule_barrier(ctx);
 143                 ctx->emitted_atest = true;
 144         }
 145
 146         bi_instruction blend = {
 147                 .type = BI_BLEND,
 148                 .blend_location = nir_intrinsic_base(instr),
 149                 .src = {
 150                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 151                         bir_src_index(&instr->src[0])
 152                 },
 153                 .src_types = {
 154                         nir_type_uint32,
 155                         nir_type_float32,
 156                 },
 157                 .swizzle = {
 158                         { 0 },
 159                         { 0, 1, 2, 3 }
 160                 },
 161                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 162                 .dest_type = nir_type_uint32,
 163                 .writemask = 0xF
 164         };
 165
 166         bi_emit(ctx, blend);
 167         bi_schedule_barrier(ctx);
 168 }
 169
 170 static void
 171 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 172 {
 173         bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
 174         address.dest = bi_make_temp(ctx);
 175         address.dest_type = nir_type_uint64;
 176         address.writemask = (1 << 8) - 1;
 177
 178         bi_instruction st = {
 179                 .type = BI_STORE_VAR,
 180                 .src = {
 181                         address.dest,
 182                         bir_src_index(&instr->src[0])
 183                 },
 184                 .src_types = {
 185                         nir_type_uint64,
 186                         nir_type_uint32
 187                 },
 188                 .swizzle = {
 189                         { 0 },
 190                         { 0, 1, 2, 3 }
 191                 }
 192         };
 193
 194         bi_emit(ctx, address);
 195         bi_emit(ctx, st);
 196 }
 197
 198 static void
 199 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 200 {
 201         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 202         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 203
 204         /* TODO: Indirect access, since we need to multiply by the element
 205          * size. I believe we can get this lowering automatically via
 206          * nir_lower_io (as mul instructions) with the proper options, but this
 207          * is TODO */
 208         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 209         ld.constant.u64 += ctx->sysvals.sysval_count;
 210         ld.constant.u64 *= 16;
 211
 212         bi_emit(ctx, ld);
 213 }
 214
 215 static void
 216 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 217                 unsigned nr_components, unsigned offset)
 218 {
 219         nir_dest nir_dest;
 220
 221         /* Figure out which uniform this is */
 222         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 223         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 224
 225         /* Sysvals are prefix uniforms */
 226         unsigned uniform = ((uintptr_t) val) - 1;
 227
 228         /* Emit the read itself -- this is never indirect */
 229
 230         bi_instruction load = {
 231                 .type = BI_LOAD_UNIFORM,
 232                 .writemask = (1 << (nr_components * 4)) - 1,
 233                 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
 234                 .constant = { (uniform * 16) + offset },
 235                 .dest = bir_dest_index(&nir_dest),
 236                 .dest_type = nir_type_uint32, /* TODO */
 237         };
 238
 239         bi_emit(ctx, load);
 240 }
 241
 242 static void
 243 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 244 {
 245
 246         switch (instr->intrinsic) {
 247         case nir_intrinsic_load_barycentric_pixel:
 248                 /* stub */
 249                 break;
 250         case nir_intrinsic_load_interpolated_input:
 251         case nir_intrinsic_load_input:
 252                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 253                         bi_emit_ld_vary(ctx, instr);
 254                 else if (ctx->stage == MESA_SHADER_VERTEX)
 255                         bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
 256                 else {
 257                         unreachable("Unsupported shader stage");
 258                 }
 259                 break;
 260
 261         case nir_intrinsic_store_output:
 262                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 263                         bi_emit_frag_out(ctx, instr);
 264                 else if (ctx->stage == MESA_SHADER_VERTEX)
 265                         bi_emit_st_vary(ctx, instr);
 266                 else
 267                         unreachable("Unsupported shader stage");
 268                 break;
 269
 270         case nir_intrinsic_load_uniform:
 271                 bi_emit_ld_uniform(ctx, instr);
 272                 break;
 273
 274         case nir_intrinsic_load_ssbo_address:
 275                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 276                 break;
 277
 278         case nir_intrinsic_get_buffer_size:
 279                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 280                 break;
 281
 282         case nir_intrinsic_load_viewport_scale:
 283         case nir_intrinsic_load_viewport_offset:
 284         case nir_intrinsic_load_num_work_groups:
 285         case nir_intrinsic_load_sampler_lod_parameters_pan:
 286                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 287                 break;
 288
 289         default:
 290                 /* todo */
 291                 break;
 292         }
 293 }
 294
 295 static void
 296 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 297 {
 298         /* Make sure we've been lowered */
 299         assert(instr->def.num_components == 1);
 300
 301         bi_instruction move = {
 302                 .type = BI_MOV,
 303                 .dest = bir_ssa_index(&instr->def),
 304                 .dest_type = instr->def.bit_size | nir_type_uint,
 305                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 306                 .src = {
 307                         BIR_INDEX_CONSTANT
 308                 },
 309                 .constant = {
 310                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 311                 }
 312         };
 313
 314         bi_emit(ctx, move);
 315 }
 316
 317 static enum bi_class
 318 bi_class_for_nir_alu(nir_op op)
 319 {
 320         switch (op) {
 321         case nir_op_iadd:
 322         case nir_op_fadd:
 323         case nir_op_fsub:
 324                 return BI_ADD;
 325         case nir_op_isub:
 326                 return BI_ISUB;
 327
 328         case nir_op_flt:
 329         case nir_op_fge:
 330         case nir_op_feq:
 331         case nir_op_fne:
 332         case nir_op_ilt:
 333         case nir_op_ige:
 334         case nir_op_ieq:
 335         case nir_op_ine:
 336                 return BI_CMP;
 337
 338         case nir_op_bcsel:
 339                 return BI_CSEL;
 340
 341         case nir_op_i2i8:
 342         case nir_op_i2i16:
 343         case nir_op_i2i32:
 344         case nir_op_i2i64:
 345         case nir_op_u2u8:
 346         case nir_op_u2u16:
 347         case nir_op_u2u32:
 348         case nir_op_u2u64:
 349         case nir_op_f2i16:
 350         case nir_op_f2i32:
 351         case nir_op_f2i64:
 352         case nir_op_f2u16:
 353         case nir_op_f2u32:
 354         case nir_op_f2u64:
 355         case nir_op_i2f16:
 356         case nir_op_i2f32:
 357         case nir_op_i2f64:
 358         case nir_op_u2f16:
 359         case nir_op_u2f32:
 360         case nir_op_u2f64:
 361                 return BI_CONVERT;
 362
 363         case nir_op_ffma:
 364         case nir_op_fmul:
 365                 return BI_FMA;
 366
 367         case nir_op_imin:
 368         case nir_op_imax:
 369         case nir_op_umin:
 370         case nir_op_umax:
 371         case nir_op_fmin:
 372         case nir_op_fmax:
 373                 return BI_MINMAX;
 374
 375         case nir_op_fsat:
 376         case nir_op_fneg:
 377         case nir_op_fabs:
 378                 return BI_FMOV;
 379         case nir_op_mov:
 380                 return BI_MOV;
 381
 382         case nir_op_frcp:
 383         case nir_op_frsq:
 384         case nir_op_fsin:
 385         case nir_op_fcos:
 386                 return BI_SPECIAL;
 387
 388         default:
 389                 unreachable("Unknown ALU op");
 390         }
 391 }
 392
 393 static enum bi_cond
 394 bi_cond_for_nir(nir_op op)
 395 {
 396         switch (op) {
 397         case nir_op_flt:
 398         case nir_op_ilt:
 399                 return BI_COND_LT;
 400         case nir_op_fge:
 401         case nir_op_ige:
 402                 return BI_COND_GE;
 403         case nir_op_feq:
 404         case nir_op_ieq:
 405                 return BI_COND_EQ;
 406         case nir_op_fne:
 407         case nir_op_ine:
 408                 return BI_COND_NE;
 409         default:
 410                 unreachable("Invalid compare");
 411         }
 412 }
 413
 414 static void
 415 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 416 {
 417         /* Assume it's something we can handle normally */
 418         bi_instruction alu = {
 419                 .type = bi_class_for_nir_alu(instr->op),
 420                 .dest = bir_dest_index(&instr->dest.dest),
 421                 .dest_type = nir_op_infos[instr->op].output_type
 422                         | nir_dest_bit_size(instr->dest.dest),
 423         };
 424
 425         /* TODO: Implement lowering of special functions for older Bifrost */
 426         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 427
 428         if (instr->dest.dest.is_ssa) {
 429                 /* Construct a writemask */
 430                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 431                 unsigned comps = instr->dest.dest.ssa.num_components;
 432                 assert(comps == 1);
 433                 unsigned bits = bits_per_comp * comps;
 434                 unsigned bytes = MAX2(bits / 8, 1);
 435                 alu.writemask = (1 << bytes) - 1;
 436         } else {
 437                 unsigned comp_mask = instr->dest.write_mask;
 438
 439                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 440                                 comp_mask);
 441         }
 442
 443         /* We inline constants as we go. This tracks how many constants have
 444          * been inlined, since we're limited to 64-bits of constants per
 445          * instruction */
 446
 447         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 448         unsigned constants_left = (64 / dest_bits);
 449         unsigned constant_shift = 0;
 450
 451         /* Copy sources */
 452
 453         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 454         assert(num_inputs <= ARRAY_SIZE(alu.src));
 455
 456         for (unsigned i = 0; i < num_inputs; ++i) {
 457                 unsigned bits = nir_src_bit_size(instr->src[i].src);
 458                 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
 459                         | bits;
 460
 461                 /* Try to inline a constant */
 462                 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
 463                         alu.constant.u64 |=
 464                                 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
 465
 466                         alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
 467                         --constants_left;
 468                         constant_shift += dest_bits;
 469                         continue;
 470                 }
 471
 472                 alu.src[i] = bir_src_index(&instr->src[i].src);
 473
 474                 /* We assert scalarization above */
 475                 alu.swizzle[i][0] = instr->src[i].swizzle[0];
 476         }
 477
 478         /* Op-specific fixup */
 479         switch (instr->op) {
 480         case nir_op_fmul:
 481                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 482                 break;
 483         case nir_op_fsat:
 484                 alu.outmod = BIFROST_SAT; /* FMOV */
 485                 break;
 486         case nir_op_fneg:
 487                 alu.src_neg[0] = true; /* FMOV */
 488                 break;
 489         case nir_op_fabs:
 490                 alu.src_abs[0] = true; /* FMOV */
 491                 break;
 492         case nir_op_fsub:
 493                 alu.src_neg[1] = true; /* FADD */
 494                 break;
 495         case nir_op_fmax:
 496         case nir_op_imax:
 497         case nir_op_umax:
 498                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 499                 break;
 500         case nir_op_frcp:
 501                 alu.op.special = BI_SPECIAL_FRCP;
 502                 break;
 503         case nir_op_frsq:
 504                 alu.op.special = BI_SPECIAL_FRSQ;
 505                 break;
 506         case nir_op_fsin:
 507                 alu.op.special = BI_SPECIAL_FSIN;
 508                 break;
 509         case nir_op_fcos:
 510                 alu.op.special = BI_SPECIAL_FCOS;
 511                 break;
 512         case nir_op_flt:
 513         case nir_op_ilt:
 514         case nir_op_fge:
 515         case nir_op_ige:
 516         case nir_op_feq:
 517         case nir_op_ieq:
 518         case nir_op_fne:
 519         case nir_op_ine:
 520                 alu.op.compare = bi_cond_for_nir(instr->op);
 521                 break;
 522         default:
 523                 break;
 524         }
 525
 526         bi_emit(ctx, alu);
 527 }
 528
 529 static void
 530 emit_instr(bi_context *ctx, struct nir_instr *instr)
 531 {
 532         switch (instr->type) {
 533         case nir_instr_type_load_const:
 534                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 535                 break;
 536
 537         case nir_instr_type_intrinsic:
 538                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 539                 break;
 540
 541         case nir_instr_type_alu:
 542                 emit_alu(ctx, nir_instr_as_alu(instr));
 543                 break;
 544
 545 #if 0
 546         case nir_instr_type_tex:
 547                 emit_tex(ctx, nir_instr_as_tex(instr));
 548                 break;
 549 #endif
 550
 551         case nir_instr_type_jump:
 552                 emit_jump(ctx, nir_instr_as_jump(instr));
 553                 break;
 554
 555         case nir_instr_type_ssa_undef:
 556                 /* Spurious */
 557                 break;
 558
 559         default:
 560                 //unreachable("Unhandled instruction type");
 561                 break;
 562         }
 563 }
 564
 565
 566
 567 static bi_block *
 568 create_empty_block(bi_context *ctx)
 569 {
 570         bi_block *blk = rzalloc(ctx, bi_block);
 571
 572         blk->base.predecessors = _mesa_set_create(blk,
 573                         _mesa_hash_pointer,
 574                         _mesa_key_pointer_equal);
 575
 576         blk->base.name = ctx->block_name_count++;
 577
 578         return blk;
 579 }
 580
 581 static void
 582 bi_schedule_barrier(bi_context *ctx)
 583 {
 584         bi_block *temp = ctx->after_block;
 585         ctx->after_block = create_empty_block(ctx);
 586         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 587         list_inithead(&ctx->after_block->base.instructions);
 588         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 589         ctx->current_block = ctx->after_block;
 590         ctx->after_block = temp;
 591 }
 592
 593 static bi_block *
 594 emit_block(bi_context *ctx, nir_block *block)
 595 {
 596         if (ctx->after_block) {
 597                 ctx->current_block = ctx->after_block;
 598                 ctx->after_block = NULL;
 599         } else {
 600                 ctx->current_block = create_empty_block(ctx);
 601         }
 602
 603         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 604         list_inithead(&ctx->current_block->base.instructions);
 605
 606         nir_foreach_instr(instr, block) {
 607                 emit_instr(ctx, instr);
 608                 ++ctx->instruction_count;
 609         }
 610
 611         return ctx->current_block;
 612 }
 613
 614 /* Emits an unconditional branch to the end of the current block, returning a
 615  * pointer so the user can fill in details */
 616
 617 static bi_instruction *
 618 bi_emit_branch(bi_context *ctx)
 619 {
 620         bi_instruction branch = {
 621                 .type = BI_BRANCH,
 622                 .branch = {
 623                         .cond = BI_COND_ALWAYS
 624                 }
 625         };
 626
 627         return bi_emit(ctx, branch);
 628 }
 629
 630 /* Sets a condition for a branch by examing the NIR condition. If we're
 631  * familiar with the condition, we unwrap it to fold it into the branch
 632  * instruction. Otherwise, we consume the condition directly. We
 633  * generally use 1-bit booleans which allows us to use small types for
 634  * the conditions.
 635  */
 636
 637 static void
 638 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 639 {
 640         /* TODO: Try to unwrap instead of always bailing */
 641         branch->src[0] = bir_src_index(cond);
 642         branch->src[1] = BIR_INDEX_ZERO;
 643         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 644         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 645 }
 646
 647 static void
 648 emit_if(bi_context *ctx, nir_if *nif)
 649 {
 650         bi_block *before_block = ctx->current_block;
 651
 652         /* Speculatively emit the branch, but we can't fill it in until later */
 653         bi_instruction *then_branch = bi_emit_branch(ctx);
 654         bi_set_branch_cond(then_branch, &nif->condition, true);
 655
 656         /* Emit the two subblocks. */
 657         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 658         bi_block *end_then_block = ctx->current_block;
 659
 660         /* Emit a jump from the end of the then block to the end of the else */
 661         bi_instruction *then_exit = bi_emit_branch(ctx);
 662
 663         /* Emit second block, and check if it's empty */
 664
 665         int count_in = ctx->instruction_count;
 666         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 667         bi_block *end_else_block = ctx->current_block;
 668         ctx->after_block = create_empty_block(ctx);
 669
 670         /* Now that we have the subblocks emitted, fix up the branches */
 671
 672         assert(then_block);
 673         assert(else_block);
 674
 675         if (ctx->instruction_count == count_in) {
 676                 /* The else block is empty, so don't emit an exit jump */
 677                 bi_remove_instruction(then_exit);
 678                 then_branch->branch.target = ctx->after_block;
 679         } else {
 680                 then_branch->branch.target = else_block;
 681                 then_exit->branch.target = ctx->after_block;
 682                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 683         }
 684
 685         /* Wire up the successors */
 686
 687         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 688
 689         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 690         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 691 }
 692
 693 static void
 694 emit_loop(bi_context *ctx, nir_loop *nloop)
 695 {
 696         /* Remember where we are */
 697         bi_block *start_block = ctx->current_block;
 698
 699         bi_block *saved_break = ctx->break_block;
 700         bi_block *saved_continue = ctx->continue_block;
 701
 702         ctx->continue_block = create_empty_block(ctx);
 703         ctx->break_block = create_empty_block(ctx);
 704         ctx->after_block = ctx->continue_block;
 705
 706         /* Emit the body itself */
 707         emit_cf_list(ctx, &nloop->body);
 708
 709         /* Branch back to loop back */
 710         bi_instruction *br_back = bi_emit_branch(ctx);
 711         br_back->branch.target = ctx->continue_block;
 712         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 713         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 714
 715         ctx->after_block = ctx->break_block;
 716
 717         /* Pop off */
 718         ctx->break_block = saved_break;
 719         ctx->continue_block = saved_continue;
 720         ++ctx->loop_count;
 721 }
 722
 723 static bi_block *
 724 emit_cf_list(bi_context *ctx, struct exec_list *list)
 725 {
 726         bi_block *start_block = NULL;
 727
 728         foreach_list_typed(nir_cf_node, node, node, list) {
 729                 switch (node->type) {
 730                 case nir_cf_node_block: {
 731                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 732
 733                         if (!start_block)
 734                                 start_block = block;
 735
 736                         break;
 737                 }
 738
 739                 case nir_cf_node_if:
 740                         emit_if(ctx, nir_cf_node_as_if(node));
 741                         break;
 742
 743                 case nir_cf_node_loop:
 744                         emit_loop(ctx, nir_cf_node_as_loop(node));
 745                         break;
 746
 747                 default:
 748                         unreachable("Unknown control flow");
 749                 }
 750         }
 751
 752         return start_block;
 753 }
 754
 755 static int
 756 glsl_type_size(const struct glsl_type *type, bool bindless)
 757 {
 758         return glsl_count_attribute_slots(type, false);
 759 }
 760
 761 static void
 762 bi_optimize_nir(nir_shader *nir)
 763 {
 764         bool progress;
 765         unsigned lower_flrp = 16 | 32 | 64;
 766
 767         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 768         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 769
 770         nir_lower_tex_options lower_tex_options = {
 771                 .lower_txs_lod = true,
 772                 .lower_txp = ~0,
 773                 .lower_tex_without_implicit_lod = true,
 774                 .lower_txd = true,
 775         };
 776
 777         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 778         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 779         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 780
 781         do {
 782                 progress = false;
 783
 784                 NIR_PASS(progress, nir, nir_lower_var_copies);
 785                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 786
 787                 NIR_PASS(progress, nir, nir_copy_prop);
 788                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 789                 NIR_PASS(progress, nir, nir_opt_dce);
 790                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 791                 NIR_PASS(progress, nir, nir_opt_cse);
 792                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 793                 NIR_PASS(progress, nir, nir_opt_algebraic);
 794                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 795
 796                 if (lower_flrp != 0) {
 797                         bool lower_flrp_progress = false;
 798                         NIR_PASS(lower_flrp_progress,
 799                                  nir,
 800                                  nir_lower_flrp,
 801                                  lower_flrp,
 802                                  false /* always_precise */,
 803                                  nir->options->lower_ffma);
 804                         if (lower_flrp_progress) {
 805                                 NIR_PASS(progress, nir,
 806                                          nir_opt_constant_folding);
 807                                 progress = true;
 808                         }
 809
 810                         /* Nothing should rematerialize any flrps, so we only
 811                          * need to do this lowering once.
 812                          */
 813                         lower_flrp = 0;
 814                 }
 815
 816                 NIR_PASS(progress, nir, nir_opt_undef);
 817                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 818                          nir_var_shader_in |
 819                          nir_var_shader_out |
 820                          nir_var_function_temp);
 821         } while (progress);
 822
 823         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 824         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 825         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 826         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 827
 828         /* Take us out of SSA */
 829         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 830         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 831
 832         /* We're a primary scalar architecture but there's enough vector that
 833          * we use a vector IR so let's not also deal with scalar hacks on top
 834          * of the vector hacks */
 835
 836         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 837         NIR_PASS(progress, nir, nir_lower_vec_to_movs);
 838         NIR_PASS(progress, nir, nir_opt_dce);
 839 }
 840
 841 static void
 842 bi_insert_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp)
 843 {
 844         bi_instruction move = {
 845                 .type = BI_MOV,
 846                 .dest = parent->dest,
 847                 .dest_type = nir_type_uint32,
 848                 .writemask = (0xF << (4 * comp)),
 849                 .src = { parent->src[0] },
 850                 .src_types = { nir_type_uint32 },
 851                 .swizzle = { { comp } }
 852         };
 853
 854         bi_emit_before(ctx, parent, move);
 855 }
 856
 857 static void
 858 bi_lower_mov(bi_context *ctx, bi_block *block)
 859 {
 860         bi_foreach_instr_in_block_safe(block, ins) {
 861                 if (ins->type != BI_MOV) continue;
 862                 if (util_bitcount(ins->writemask) <= 4) continue;
 863
 864                 for (unsigned i = 0; i < 4; ++i) {
 865                         unsigned quad = (ins->writemask >> (4 * i)) & 0xF;
 866
 867                         if (quad == 0)
 868                                 continue;
 869                         else if (quad == 0xF)
 870                                 bi_insert_mov32(ctx, ins, i);
 871                         else
 872                                 unreachable("TODO: Lowering <32bit moves");
 873                 }
 874
 875                 bi_remove_instruction(ins);
 876         }
 877 }
 878
 879 void
 880 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 881 {
 882         bi_context *ctx = rzalloc(NULL, bi_context);
 883         ctx->nir = nir;
 884         ctx->stage = nir->info.stage;
 885         ctx->quirks = bifrost_get_quirks(product_id);
 886         list_inithead(&ctx->blocks);
 887
 888         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 889          * (so we don't accidentally duplicate the epilogue since mesa/st has
 890          * messed with our I/O quite a bit already) */
 891
 892         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 893
 894         if (ctx->stage == MESA_SHADER_VERTEX) {
 895                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 896                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 897         }
 898
 899         NIR_PASS_V(nir, nir_split_var_copies);
 900         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 901         NIR_PASS_V(nir, nir_lower_var_copies);
 902         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 903         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 904         NIR_PASS_V(nir, nir_lower_ssbo);
 905
 906         bi_optimize_nir(nir);
 907         nir_print_shader(nir, stdout);
 908
 909         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 910         program->sysval_count = ctx->sysvals.sysval_count;
 911         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 912
 913         nir_foreach_function(func, nir) {
 914                 if (!func->impl)
 915                         continue;
 916
 917                 ctx->impl = func->impl;
 918                 emit_cf_list(ctx, &func->impl->body);
 919                 break; /* TODO: Multi-function shaders */
 920         }
 921
 922         bi_foreach_block(ctx, _block) {
 923                 bi_block *block = (bi_block *) _block;
 924                 bi_lower_mov(ctx, block);
 925         }
 926
 927         bool progress = false;
 928
 929         do {
 930                 progress = false;
 931
 932                 bi_foreach_block(ctx, _block) {
 933                         bi_block *block = (bi_block *) _block;
 934                         progress |= bi_opt_dead_code_eliminate(ctx, block);
 935                 }
 936         } while(progress);
 937
 938         bi_print_shader(ctx, stdout);
 939         bi_schedule(ctx);
 940         bi_register_allocate(ctx);
 941         bi_print_shader(ctx, stdout);
 942         bi_pack(ctx, &program->compiled);
 943         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
 944
 945         ralloc_free(ctx);
 946 }