pan/bi: Handle special ops in NIR->BIR
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "main/imports.h"
31 #include "compiler/nir/nir_builder.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "compiler.h"
36 #include "bi_quirks.h"
37 #include "bi_print.h"
38
39 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
40 static bi_instruction *bi_emit_branch(bi_context *ctx);
41 static void bi_block_add_successor(bi_block *block, bi_block *successor);
42 static void bi_schedule_barrier(bi_context *ctx);
43
44 static void
45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
46 {
47 bi_instruction *branch = bi_emit_branch(ctx);
48
49 switch (instr->type) {
50 case nir_jump_break:
51 branch->branch.target = ctx->break_block;
52 break;
53 case nir_jump_continue:
54 branch->branch.target = ctx->continue_block;
55 break;
56 default:
57 unreachable("Unhandled jump type");
58 }
59
60 bi_block_add_successor(ctx->current_block, branch->branch.target);
61 }
62
63 /* Gets a bytemask for a complete vecN write */
64 static unsigned
65 bi_mask_for_channels_32(unsigned i)
66 {
67 return (1 << (4 * i)) - 1;
68 }
69
70 static bi_instruction
71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
72 {
73 bi_instruction load = {
74 .type = T,
75 .writemask = bi_mask_for_channels_32(instr->num_components),
76 .src = { BIR_INDEX_CONSTANT },
77 .constant = { .u64 = nir_intrinsic_base(instr) },
78 };
79
80 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
81
82 if (info->has_dest)
83 load.dest = bir_dest_index(&instr->dest);
84
85 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
86 load.dest_type = nir_intrinsic_type(instr);
87
88 nir_src *offset = nir_get_io_offset_src(instr);
89
90 if (nir_src_is_const(*offset))
91 load.constant.u64 += nir_src_as_uint(*offset);
92 else
93 load.src[0] = bir_src_index(offset);
94
95 return load;
96 }
97
98 static void
99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
100 {
101 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
102 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
103 ins.load_vary.reuse = false; /* TODO */
104 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
105 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest),
106 bi_emit(ctx, ins);
107 }
108
109 static void
110 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
111 {
112 if (!ctx->emitted_atest) {
113 bi_instruction ins = {
114 .type = BI_ATEST
115 };
116
117 bi_emit(ctx, ins);
118 bi_schedule_barrier(ctx);
119 ctx->emitted_atest = true;
120 }
121
122 bi_instruction blend = {
123 .type = BI_BLEND,
124 .blend_location = nir_intrinsic_base(instr),
125 .src = {
126 bir_src_index(&instr->src[0])
127 },
128 .swizzle = {
129 { 0, 1, 2, 3 }
130 }
131 };
132
133 bi_emit(ctx, blend);
134 bi_schedule_barrier(ctx);
135 }
136
137 static void
138 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
139 {
140 bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
141 address.dest = bi_make_temp(ctx);
142 address.dest_type = nir_type_uint64;
143 address.writemask = (1 << 8) - 1;
144
145 bi_instruction st = {
146 .type = BI_STORE_VAR,
147 .src = {
148 address.dest,
149 bir_src_index(&instr->src[0])
150 },
151 .swizzle = {
152 { 0, 1, 2, 3 }
153 }
154 };
155
156 bi_emit(ctx, address);
157 bi_emit(ctx, st);
158 }
159
160 static void
161 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
162 {
163 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
164 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
165 bi_emit(ctx, ld);
166 }
167
168 static void
169 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
170 {
171
172 switch (instr->intrinsic) {
173 case nir_intrinsic_load_barycentric_pixel:
174 /* stub */
175 break;
176 case nir_intrinsic_load_interpolated_input:
177 case nir_intrinsic_load_input:
178 if (ctx->stage == MESA_SHADER_FRAGMENT)
179 bi_emit_ld_vary(ctx, instr);
180 else if (ctx->stage == MESA_SHADER_VERTEX)
181 bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
182 else {
183 unreachable("Unsupported shader stage");
184 }
185 break;
186
187 case nir_intrinsic_store_output:
188 if (ctx->stage == MESA_SHADER_FRAGMENT)
189 bi_emit_frag_out(ctx, instr);
190 else if (ctx->stage == MESA_SHADER_VERTEX)
191 bi_emit_st_vary(ctx, instr);
192 else
193 unreachable("Unsupported shader stage");
194 break;
195
196 case nir_intrinsic_load_uniform:
197 bi_emit_ld_uniform(ctx, instr);
198 break;
199
200 default:
201 /* todo */
202 break;
203 }
204 }
205
206 static void
207 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
208 {
209 /* Make sure we've been lowered */
210 assert(instr->def.num_components == 1);
211
212 bi_instruction move = {
213 .type = BI_MOV,
214 .dest = bir_ssa_index(&instr->def),
215 .dest_type = instr->def.bit_size | nir_type_uint,
216 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
217 .src = {
218 BIR_INDEX_CONSTANT
219 },
220 .constant = {
221 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
222 }
223 };
224
225 bi_emit(ctx, move);
226 }
227
228 static enum bi_class
229 bi_class_for_nir_alu(nir_op op)
230 {
231 switch (op) {
232 case nir_op_iadd:
233 case nir_op_fadd:
234 return BI_ADD;
235
236 case nir_op_i2i8:
237 case nir_op_i2i16:
238 case nir_op_i2i32:
239 case nir_op_i2i64:
240 case nir_op_u2u8:
241 case nir_op_u2u16:
242 case nir_op_u2u32:
243 case nir_op_u2u64:
244 case nir_op_f2i16:
245 case nir_op_f2i32:
246 case nir_op_f2i64:
247 case nir_op_f2u16:
248 case nir_op_f2u32:
249 case nir_op_f2u64:
250 case nir_op_i2f16:
251 case nir_op_i2f32:
252 case nir_op_i2f64:
253 case nir_op_u2f16:
254 case nir_op_u2f32:
255 case nir_op_u2f64:
256 return BI_CONVERT;
257
258 case nir_op_fmul:
259 return BI_FMA;
260
261 case nir_op_imin:
262 case nir_op_imax:
263 case nir_op_umin:
264 case nir_op_umax:
265 case nir_op_fmin:
266 case nir_op_fmax:
267 return BI_MINMAX;
268
269 case nir_op_fsat:
270 case nir_op_mov:
271 return BI_MOV;
272
273 case nir_op_frcp:
274 case nir_op_frsq:
275 case nir_op_fsin:
276 case nir_op_fcos:
277 return BI_SPECIAL;
278
279 default:
280 unreachable("Unknown ALU op");
281 }
282 }
283
284 static void
285 emit_alu(bi_context *ctx, nir_alu_instr *instr)
286 {
287 /* Assume it's something we can handle normally */
288 bi_instruction alu = {
289 .type = bi_class_for_nir_alu(instr->op),
290 .dest = bir_dest_index(&instr->dest.dest),
291 .dest_type = nir_op_infos[instr->op].output_type
292 | nir_dest_bit_size(instr->dest.dest),
293 };
294
295 /* TODO: Implement lowering of special functions for older Bifrost */
296 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
297
298 if (instr->dest.dest.is_ssa) {
299 /* Construct a writemask */
300 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
301 unsigned comps = instr->dest.dest.ssa.num_components;
302 assert(comps == 1);
303 unsigned bits = bits_per_comp * comps;
304 unsigned bytes = MAX2(bits / 8, 1);
305 alu.writemask = (1 << bytes) - 1;
306 } else {
307 unsigned comp_mask = instr->dest.write_mask;
308
309 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
310 comp_mask);
311 }
312
313 /* We inline constants as we go. This tracks how many constants have
314 * been inlined, since we're limited to 64-bits of constants per
315 * instruction */
316
317 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
318 unsigned constants_left = (64 / dest_bits);
319 unsigned constant_shift = 0;
320
321 /* Copy sources */
322
323 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
324 assert(num_inputs <= ARRAY_SIZE(alu.src));
325
326 for (unsigned i = 0; i < num_inputs; ++i) {
327 unsigned bits = nir_src_bit_size(instr->src[i].src);
328 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
329 | bits;
330
331 /* Try to inline a constant */
332 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
333 alu.constant.u64 |=
334 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
335
336 alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
337 --constants_left;
338 constant_shift += dest_bits;
339 continue;
340 }
341
342 alu.src[i] = bir_src_index(&instr->src[i].src);
343
344 /* We assert scalarization above */
345 alu.swizzle[i][0] = instr->src[i].swizzle[0];
346 }
347
348 /* Op-specific fixup */
349 switch (instr->op) {
350 case nir_op_fmul:
351 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
352 break;
353 case nir_op_fsat:
354 alu.outmod = BIFROST_SAT; /* MOV */
355 break;
356 case nir_op_fmax:
357 case nir_op_imax:
358 case nir_op_umax:
359 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
360 break;
361 case nir_op_frcp:
362 alu.op.special = BI_SPECIAL_FRCP;
363 break;
364 case nir_op_frsq:
365 alu.op.special = BI_SPECIAL_FRSQ;
366 break;
367 case nir_op_fsin:
368 alu.op.special = BI_SPECIAL_FSIN;
369 break;
370 case nir_op_fcos:
371 alu.op.special = BI_SPECIAL_FCOS;
372 break;
373 default:
374 break;
375 }
376
377 bi_emit(ctx, alu);
378 }
379
380 static void
381 emit_instr(bi_context *ctx, struct nir_instr *instr)
382 {
383 switch (instr->type) {
384 case nir_instr_type_load_const:
385 emit_load_const(ctx, nir_instr_as_load_const(instr));
386 break;
387
388 case nir_instr_type_intrinsic:
389 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
390 break;
391
392 case nir_instr_type_alu:
393 emit_alu(ctx, nir_instr_as_alu(instr));
394 break;
395
396 #if 0
397 case nir_instr_type_tex:
398 emit_tex(ctx, nir_instr_as_tex(instr));
399 break;
400 #endif
401
402 case nir_instr_type_jump:
403 emit_jump(ctx, nir_instr_as_jump(instr));
404 break;
405
406 case nir_instr_type_ssa_undef:
407 /* Spurious */
408 break;
409
410 default:
411 //unreachable("Unhandled instruction type");
412 break;
413 }
414 }
415
416
417
418 static bi_block *
419 create_empty_block(bi_context *ctx)
420 {
421 bi_block *blk = rzalloc(ctx, bi_block);
422
423 blk->predecessors = _mesa_set_create(blk,
424 _mesa_hash_pointer,
425 _mesa_key_pointer_equal);
426
427 blk->name = ctx->block_name_count++;
428
429 return blk;
430 }
431
432 static void
433 bi_block_add_successor(bi_block *block, bi_block *successor)
434 {
435 assert(block);
436 assert(successor);
437
438 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); ++i) {
439 if (block->successors[i]) {
440 if (block->successors[i] == successor)
441 return;
442 else
443 continue;
444 }
445
446 block->successors[i] = successor;
447 _mesa_set_add(successor->predecessors, block);
448 return;
449 }
450
451 unreachable("Too many successors");
452 }
453
454 static void
455 bi_schedule_barrier(bi_context *ctx)
456 {
457 bi_block *temp = ctx->after_block;
458 ctx->after_block = create_empty_block(ctx);
459 list_addtail(&ctx->after_block->link, &ctx->blocks);
460 list_inithead(&ctx->after_block->instructions);
461 bi_block_add_successor(ctx->current_block, ctx->after_block);
462 ctx->current_block = ctx->after_block;
463 ctx->after_block = temp;
464 }
465
466 static bi_block *
467 emit_block(bi_context *ctx, nir_block *block)
468 {
469 if (ctx->after_block) {
470 ctx->current_block = ctx->after_block;
471 ctx->after_block = NULL;
472 } else {
473 ctx->current_block = create_empty_block(ctx);
474 }
475
476 list_addtail(&ctx->current_block->link, &ctx->blocks);
477 list_inithead(&ctx->current_block->instructions);
478
479 nir_foreach_instr(instr, block) {
480 emit_instr(ctx, instr);
481 ++ctx->instruction_count;
482 }
483
484 return ctx->current_block;
485 }
486
487 /* Emits an unconditional branch to the end of the current block, returning a
488 * pointer so the user can fill in details */
489
490 static bi_instruction *
491 bi_emit_branch(bi_context *ctx)
492 {
493 bi_instruction branch = {
494 .type = BI_BRANCH,
495 .branch = {
496 .cond = BI_COND_ALWAYS
497 }
498 };
499
500 return bi_emit(ctx, branch);
501 }
502
503 /* Sets a condition for a branch by examing the NIR condition. If we're
504 * familiar with the condition, we unwrap it to fold it into the branch
505 * instruction. Otherwise, we consume the condition directly. We
506 * generally use 1-bit booleans which allows us to use small types for
507 * the conditions.
508 */
509
510 static void
511 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
512 {
513 /* TODO: Try to unwrap instead of always bailing */
514 branch->src[0] = bir_src_index(cond);
515 branch->src[1] = BIR_INDEX_ZERO;
516 branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
517 branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
518 }
519
520 static void
521 emit_if(bi_context *ctx, nir_if *nif)
522 {
523 bi_block *before_block = ctx->current_block;
524
525 /* Speculatively emit the branch, but we can't fill it in until later */
526 bi_instruction *then_branch = bi_emit_branch(ctx);
527 bi_set_branch_cond(then_branch, &nif->condition, true);
528
529 /* Emit the two subblocks. */
530 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
531 bi_block *end_then_block = ctx->current_block;
532
533 /* Emit a jump from the end of the then block to the end of the else */
534 bi_instruction *then_exit = bi_emit_branch(ctx);
535
536 /* Emit second block, and check if it's empty */
537
538 int count_in = ctx->instruction_count;
539 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
540 bi_block *end_else_block = ctx->current_block;
541 ctx->after_block = create_empty_block(ctx);
542
543 /* Now that we have the subblocks emitted, fix up the branches */
544
545 assert(then_block);
546 assert(else_block);
547
548 if (ctx->instruction_count == count_in) {
549 /* The else block is empty, so don't emit an exit jump */
550 bi_remove_instruction(then_exit);
551 then_branch->branch.target = ctx->after_block;
552 } else {
553 then_branch->branch.target = else_block;
554 then_exit->branch.target = ctx->after_block;
555 bi_block_add_successor(end_then_block, then_exit->branch.target);
556 }
557
558 /* Wire up the successors */
559
560 bi_block_add_successor(before_block, then_branch->branch.target); /* then_branch */
561
562 bi_block_add_successor(before_block, then_block); /* fallthrough */
563 bi_block_add_successor(end_else_block, ctx->after_block); /* fallthrough */
564 }
565
566 static void
567 emit_loop(bi_context *ctx, nir_loop *nloop)
568 {
569 /* Remember where we are */
570 bi_block *start_block = ctx->current_block;
571
572 bi_block *saved_break = ctx->break_block;
573 bi_block *saved_continue = ctx->continue_block;
574
575 ctx->continue_block = create_empty_block(ctx);
576 ctx->break_block = create_empty_block(ctx);
577 ctx->after_block = ctx->continue_block;
578
579 /* Emit the body itself */
580 emit_cf_list(ctx, &nloop->body);
581
582 /* Branch back to loop back */
583 bi_instruction *br_back = bi_emit_branch(ctx);
584 br_back->branch.target = ctx->continue_block;
585 bi_block_add_successor(start_block, ctx->continue_block);
586 bi_block_add_successor(ctx->current_block, ctx->continue_block);
587
588 ctx->after_block = ctx->break_block;
589
590 /* Pop off */
591 ctx->break_block = saved_break;
592 ctx->continue_block = saved_continue;
593 ++ctx->loop_count;
594 }
595
596 static bi_block *
597 emit_cf_list(bi_context *ctx, struct exec_list *list)
598 {
599 bi_block *start_block = NULL;
600
601 foreach_list_typed(nir_cf_node, node, node, list) {
602 switch (node->type) {
603 case nir_cf_node_block: {
604 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
605
606 if (!start_block)
607 start_block = block;
608
609 break;
610 }
611
612 case nir_cf_node_if:
613 emit_if(ctx, nir_cf_node_as_if(node));
614 break;
615
616 case nir_cf_node_loop:
617 emit_loop(ctx, nir_cf_node_as_loop(node));
618 break;
619
620 default:
621 unreachable("Unknown control flow");
622 }
623 }
624
625 return start_block;
626 }
627
628 static int
629 glsl_type_size(const struct glsl_type *type, bool bindless)
630 {
631 return glsl_count_attribute_slots(type, false);
632 }
633
634 static void
635 bi_optimize_nir(nir_shader *nir)
636 {
637 bool progress;
638 unsigned lower_flrp = 16 | 32 | 64;
639
640 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
641 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
642
643 nir_lower_tex_options lower_tex_options = {
644 .lower_txs_lod = true,
645 .lower_txp = ~0,
646 .lower_tex_without_implicit_lod = true,
647 .lower_txd = true,
648 };
649
650 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
651 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
652 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
653
654 do {
655 progress = false;
656
657 NIR_PASS(progress, nir, nir_lower_var_copies);
658 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
659
660 NIR_PASS(progress, nir, nir_copy_prop);
661 NIR_PASS(progress, nir, nir_opt_remove_phis);
662 NIR_PASS(progress, nir, nir_opt_dce);
663 NIR_PASS(progress, nir, nir_opt_dead_cf);
664 NIR_PASS(progress, nir, nir_opt_cse);
665 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
666 NIR_PASS(progress, nir, nir_opt_algebraic);
667 NIR_PASS(progress, nir, nir_opt_constant_folding);
668
669 if (lower_flrp != 0) {
670 bool lower_flrp_progress = false;
671 NIR_PASS(lower_flrp_progress,
672 nir,
673 nir_lower_flrp,
674 lower_flrp,
675 false /* always_precise */,
676 nir->options->lower_ffma);
677 if (lower_flrp_progress) {
678 NIR_PASS(progress, nir,
679 nir_opt_constant_folding);
680 progress = true;
681 }
682
683 /* Nothing should rematerialize any flrps, so we only
684 * need to do this lowering once.
685 */
686 lower_flrp = 0;
687 }
688
689 NIR_PASS(progress, nir, nir_opt_undef);
690 NIR_PASS(progress, nir, nir_opt_loop_unroll,
691 nir_var_shader_in |
692 nir_var_shader_out |
693 nir_var_function_temp);
694 } while (progress);
695
696 NIR_PASS(progress, nir, nir_opt_algebraic_late);
697 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
698 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
699
700 /* Take us out of SSA */
701 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
702 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
703
704 /* We're a primary scalar architecture but there's enough vector that
705 * we use a vector IR so let's not also deal with scalar hacks on top
706 * of the vector hacks */
707
708 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
709 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
710 NIR_PASS(progress, nir, nir_opt_dce);
711 }
712
713 void
714 bifrost_compile_shader_nir(nir_shader *nir, bifrost_program *program, unsigned product_id)
715 {
716 bi_context *ctx = rzalloc(NULL, bi_context);
717 ctx->nir = nir;
718 ctx->stage = nir->info.stage;
719 ctx->quirks = bifrost_get_quirks(product_id);
720 list_inithead(&ctx->blocks);
721
722 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
723 * (so we don't accidentally duplicate the epilogue since mesa/st has
724 * messed with our I/O quite a bit already) */
725
726 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
727
728 if (ctx->stage == MESA_SHADER_VERTEX) {
729 NIR_PASS_V(nir, nir_lower_viewport_transform);
730 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
731 }
732
733 NIR_PASS_V(nir, nir_split_var_copies);
734 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
735 NIR_PASS_V(nir, nir_lower_var_copies);
736 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
737 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
738 NIR_PASS_V(nir, nir_lower_ssbo);
739
740 bi_optimize_nir(nir);
741 nir_print_shader(nir, stdout);
742
743 nir_foreach_function(func, nir) {
744 if (!func->impl)
745 continue;
746
747 ctx->impl = func->impl;
748 emit_cf_list(ctx, &func->impl->body);
749 break; /* TODO: Multi-function shaders */
750 }
751
752 bi_print_shader(ctx, stdout);
753 bi_schedule(ctx);
754
755 ralloc_free(ctx);
756 }