pan/bi: Disable lower_sub
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "main/imports.h"
31 #include "compiler/nir/nir_builder.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "compiler.h"
36 #include "bi_quirks.h"
37 #include "bi_print.h"
38
39 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
40 static bi_instruction *bi_emit_branch(bi_context *ctx);
41 static void bi_block_add_successor(bi_block *block, bi_block *successor);
42 static void bi_schedule_barrier(bi_context *ctx);
43
44 static void
45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
46 {
47 bi_instruction *branch = bi_emit_branch(ctx);
48
49 switch (instr->type) {
50 case nir_jump_break:
51 branch->branch.target = ctx->break_block;
52 break;
53 case nir_jump_continue:
54 branch->branch.target = ctx->continue_block;
55 break;
56 default:
57 unreachable("Unhandled jump type");
58 }
59
60 bi_block_add_successor(ctx->current_block, branch->branch.target);
61 }
62
63 /* Gets a bytemask for a complete vecN write */
64 static unsigned
65 bi_mask_for_channels_32(unsigned i)
66 {
67 return (1 << (4 * i)) - 1;
68 }
69
70 static bi_instruction
71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
72 {
73 bi_instruction load = {
74 .type = T,
75 .writemask = bi_mask_for_channels_32(instr->num_components),
76 .src = { BIR_INDEX_CONSTANT },
77 .constant = { .u64 = nir_intrinsic_base(instr) },
78 };
79
80 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
81
82 if (info->has_dest)
83 load.dest = bir_dest_index(&instr->dest);
84
85 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
86 load.dest_type = nir_intrinsic_type(instr);
87
88 nir_src *offset = nir_get_io_offset_src(instr);
89
90 if (nir_src_is_const(*offset))
91 load.constant.u64 += nir_src_as_uint(*offset);
92 else
93 load.src[0] = bir_src_index(offset);
94
95 return load;
96 }
97
98 static void
99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
100 {
101 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
102 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
103 ins.load_vary.reuse = false; /* TODO */
104 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
105 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest),
106 bi_emit(ctx, ins);
107 }
108
109 static void
110 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
111 {
112 if (!ctx->emitted_atest) {
113 bi_instruction ins = {
114 .type = BI_ATEST
115 };
116
117 bi_emit(ctx, ins);
118 bi_schedule_barrier(ctx);
119 ctx->emitted_atest = true;
120 }
121
122 bi_instruction blend = {
123 .type = BI_BLEND,
124 .blend_location = nir_intrinsic_base(instr),
125 .src = {
126 bir_src_index(&instr->src[0])
127 },
128 .swizzle = {
129 { 0, 1, 2, 3 }
130 }
131 };
132
133 bi_emit(ctx, blend);
134 bi_schedule_barrier(ctx);
135 }
136
137 static void
138 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
139 {
140 bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
141 address.dest = bi_make_temp(ctx);
142 address.dest_type = nir_type_uint64;
143 address.writemask = (1 << 8) - 1;
144
145 bi_instruction st = {
146 .type = BI_STORE_VAR,
147 .src = {
148 address.dest,
149 bir_src_index(&instr->src[0])
150 },
151 .swizzle = {
152 { 0, 1, 2, 3 }
153 }
154 };
155
156 bi_emit(ctx, address);
157 bi_emit(ctx, st);
158 }
159
160 static void
161 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
162 {
163 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
164 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
165 bi_emit(ctx, ld);
166 }
167
168 static void
169 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
170 {
171
172 switch (instr->intrinsic) {
173 case nir_intrinsic_load_barycentric_pixel:
174 /* stub */
175 break;
176 case nir_intrinsic_load_interpolated_input:
177 case nir_intrinsic_load_input:
178 if (ctx->stage == MESA_SHADER_FRAGMENT)
179 bi_emit_ld_vary(ctx, instr);
180 else if (ctx->stage == MESA_SHADER_VERTEX)
181 bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
182 else {
183 unreachable("Unsupported shader stage");
184 }
185 break;
186
187 case nir_intrinsic_store_output:
188 if (ctx->stage == MESA_SHADER_FRAGMENT)
189 bi_emit_frag_out(ctx, instr);
190 else if (ctx->stage == MESA_SHADER_VERTEX)
191 bi_emit_st_vary(ctx, instr);
192 else
193 unreachable("Unsupported shader stage");
194 break;
195
196 case nir_intrinsic_load_uniform:
197 bi_emit_ld_uniform(ctx, instr);
198 break;
199
200 default:
201 /* todo */
202 break;
203 }
204 }
205
206 static void
207 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
208 {
209 /* Make sure we've been lowered */
210 assert(instr->def.num_components == 1);
211
212 bi_instruction move = {
213 .type = BI_MOV,
214 .dest = bir_ssa_index(&instr->def),
215 .dest_type = instr->def.bit_size | nir_type_uint,
216 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
217 .src = {
218 BIR_INDEX_CONSTANT
219 },
220 .constant = {
221 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
222 }
223 };
224
225 bi_emit(ctx, move);
226 }
227
228 static enum bi_class
229 bi_class_for_nir_alu(nir_op op)
230 {
231 switch (op) {
232 case nir_op_iadd:
233 case nir_op_fadd:
234 case nir_op_fsub:
235 return BI_ADD;
236
237 case nir_op_i2i8:
238 case nir_op_i2i16:
239 case nir_op_i2i32:
240 case nir_op_i2i64:
241 case nir_op_u2u8:
242 case nir_op_u2u16:
243 case nir_op_u2u32:
244 case nir_op_u2u64:
245 case nir_op_f2i16:
246 case nir_op_f2i32:
247 case nir_op_f2i64:
248 case nir_op_f2u16:
249 case nir_op_f2u32:
250 case nir_op_f2u64:
251 case nir_op_i2f16:
252 case nir_op_i2f32:
253 case nir_op_i2f64:
254 case nir_op_u2f16:
255 case nir_op_u2f32:
256 case nir_op_u2f64:
257 return BI_CONVERT;
258
259 case nir_op_fmul:
260 return BI_FMA;
261
262 case nir_op_imin:
263 case nir_op_imax:
264 case nir_op_umin:
265 case nir_op_umax:
266 case nir_op_fmin:
267 case nir_op_fmax:
268 return BI_MINMAX;
269
270 case nir_op_fsat:
271 case nir_op_fneg:
272 case nir_op_fabs:
273 case nir_op_mov:
274 return BI_MOV;
275
276 case nir_op_frcp:
277 case nir_op_frsq:
278 case nir_op_fsin:
279 case nir_op_fcos:
280 return BI_SPECIAL;
281
282 default:
283 unreachable("Unknown ALU op");
284 }
285 }
286
287 static void
288 emit_alu(bi_context *ctx, nir_alu_instr *instr)
289 {
290 /* Assume it's something we can handle normally */
291 bi_instruction alu = {
292 .type = bi_class_for_nir_alu(instr->op),
293 .dest = bir_dest_index(&instr->dest.dest),
294 .dest_type = nir_op_infos[instr->op].output_type
295 | nir_dest_bit_size(instr->dest.dest),
296 };
297
298 /* TODO: Implement lowering of special functions for older Bifrost */
299 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
300
301 if (instr->dest.dest.is_ssa) {
302 /* Construct a writemask */
303 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
304 unsigned comps = instr->dest.dest.ssa.num_components;
305 assert(comps == 1);
306 unsigned bits = bits_per_comp * comps;
307 unsigned bytes = MAX2(bits / 8, 1);
308 alu.writemask = (1 << bytes) - 1;
309 } else {
310 unsigned comp_mask = instr->dest.write_mask;
311
312 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
313 comp_mask);
314 }
315
316 /* We inline constants as we go. This tracks how many constants have
317 * been inlined, since we're limited to 64-bits of constants per
318 * instruction */
319
320 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
321 unsigned constants_left = (64 / dest_bits);
322 unsigned constant_shift = 0;
323
324 /* Copy sources */
325
326 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
327 assert(num_inputs <= ARRAY_SIZE(alu.src));
328
329 for (unsigned i = 0; i < num_inputs; ++i) {
330 unsigned bits = nir_src_bit_size(instr->src[i].src);
331 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
332 | bits;
333
334 /* Try to inline a constant */
335 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
336 alu.constant.u64 |=
337 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
338
339 alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
340 --constants_left;
341 constant_shift += dest_bits;
342 continue;
343 }
344
345 alu.src[i] = bir_src_index(&instr->src[i].src);
346
347 /* We assert scalarization above */
348 alu.swizzle[i][0] = instr->src[i].swizzle[0];
349 }
350
351 /* Op-specific fixup */
352 switch (instr->op) {
353 case nir_op_fmul:
354 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
355 break;
356 case nir_op_fsat:
357 alu.outmod = BIFROST_SAT; /* MOV */
358 break;
359 case nir_op_fneg:
360 alu.src_neg[0] = true; /* MOV */
361 break;
362 case nir_op_fabs:
363 alu.src_abs[0] = true; /* MOV */
364 break;
365 case nir_op_fsub:
366 alu.src_neg[1] = true; /* ADD */
367 break;
368 case nir_op_fmax:
369 case nir_op_imax:
370 case nir_op_umax:
371 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
372 break;
373 case nir_op_frcp:
374 alu.op.special = BI_SPECIAL_FRCP;
375 break;
376 case nir_op_frsq:
377 alu.op.special = BI_SPECIAL_FRSQ;
378 break;
379 case nir_op_fsin:
380 alu.op.special = BI_SPECIAL_FSIN;
381 break;
382 case nir_op_fcos:
383 alu.op.special = BI_SPECIAL_FCOS;
384 break;
385 default:
386 break;
387 }
388
389 bi_emit(ctx, alu);
390 }
391
392 static void
393 emit_instr(bi_context *ctx, struct nir_instr *instr)
394 {
395 switch (instr->type) {
396 case nir_instr_type_load_const:
397 emit_load_const(ctx, nir_instr_as_load_const(instr));
398 break;
399
400 case nir_instr_type_intrinsic:
401 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
402 break;
403
404 case nir_instr_type_alu:
405 emit_alu(ctx, nir_instr_as_alu(instr));
406 break;
407
408 #if 0
409 case nir_instr_type_tex:
410 emit_tex(ctx, nir_instr_as_tex(instr));
411 break;
412 #endif
413
414 case nir_instr_type_jump:
415 emit_jump(ctx, nir_instr_as_jump(instr));
416 break;
417
418 case nir_instr_type_ssa_undef:
419 /* Spurious */
420 break;
421
422 default:
423 //unreachable("Unhandled instruction type");
424 break;
425 }
426 }
427
428
429
430 static bi_block *
431 create_empty_block(bi_context *ctx)
432 {
433 bi_block *blk = rzalloc(ctx, bi_block);
434
435 blk->predecessors = _mesa_set_create(blk,
436 _mesa_hash_pointer,
437 _mesa_key_pointer_equal);
438
439 blk->name = ctx->block_name_count++;
440
441 return blk;
442 }
443
444 static void
445 bi_block_add_successor(bi_block *block, bi_block *successor)
446 {
447 assert(block);
448 assert(successor);
449
450 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); ++i) {
451 if (block->successors[i]) {
452 if (block->successors[i] == successor)
453 return;
454 else
455 continue;
456 }
457
458 block->successors[i] = successor;
459 _mesa_set_add(successor->predecessors, block);
460 return;
461 }
462
463 unreachable("Too many successors");
464 }
465
466 static void
467 bi_schedule_barrier(bi_context *ctx)
468 {
469 bi_block *temp = ctx->after_block;
470 ctx->after_block = create_empty_block(ctx);
471 list_addtail(&ctx->after_block->link, &ctx->blocks);
472 list_inithead(&ctx->after_block->instructions);
473 bi_block_add_successor(ctx->current_block, ctx->after_block);
474 ctx->current_block = ctx->after_block;
475 ctx->after_block = temp;
476 }
477
478 static bi_block *
479 emit_block(bi_context *ctx, nir_block *block)
480 {
481 if (ctx->after_block) {
482 ctx->current_block = ctx->after_block;
483 ctx->after_block = NULL;
484 } else {
485 ctx->current_block = create_empty_block(ctx);
486 }
487
488 list_addtail(&ctx->current_block->link, &ctx->blocks);
489 list_inithead(&ctx->current_block->instructions);
490
491 nir_foreach_instr(instr, block) {
492 emit_instr(ctx, instr);
493 ++ctx->instruction_count;
494 }
495
496 return ctx->current_block;
497 }
498
499 /* Emits an unconditional branch to the end of the current block, returning a
500 * pointer so the user can fill in details */
501
502 static bi_instruction *
503 bi_emit_branch(bi_context *ctx)
504 {
505 bi_instruction branch = {
506 .type = BI_BRANCH,
507 .branch = {
508 .cond = BI_COND_ALWAYS
509 }
510 };
511
512 return bi_emit(ctx, branch);
513 }
514
515 /* Sets a condition for a branch by examing the NIR condition. If we're
516 * familiar with the condition, we unwrap it to fold it into the branch
517 * instruction. Otherwise, we consume the condition directly. We
518 * generally use 1-bit booleans which allows us to use small types for
519 * the conditions.
520 */
521
522 static void
523 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
524 {
525 /* TODO: Try to unwrap instead of always bailing */
526 branch->src[0] = bir_src_index(cond);
527 branch->src[1] = BIR_INDEX_ZERO;
528 branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
529 branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
530 }
531
532 static void
533 emit_if(bi_context *ctx, nir_if *nif)
534 {
535 bi_block *before_block = ctx->current_block;
536
537 /* Speculatively emit the branch, but we can't fill it in until later */
538 bi_instruction *then_branch = bi_emit_branch(ctx);
539 bi_set_branch_cond(then_branch, &nif->condition, true);
540
541 /* Emit the two subblocks. */
542 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
543 bi_block *end_then_block = ctx->current_block;
544
545 /* Emit a jump from the end of the then block to the end of the else */
546 bi_instruction *then_exit = bi_emit_branch(ctx);
547
548 /* Emit second block, and check if it's empty */
549
550 int count_in = ctx->instruction_count;
551 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
552 bi_block *end_else_block = ctx->current_block;
553 ctx->after_block = create_empty_block(ctx);
554
555 /* Now that we have the subblocks emitted, fix up the branches */
556
557 assert(then_block);
558 assert(else_block);
559
560 if (ctx->instruction_count == count_in) {
561 /* The else block is empty, so don't emit an exit jump */
562 bi_remove_instruction(then_exit);
563 then_branch->branch.target = ctx->after_block;
564 } else {
565 then_branch->branch.target = else_block;
566 then_exit->branch.target = ctx->after_block;
567 bi_block_add_successor(end_then_block, then_exit->branch.target);
568 }
569
570 /* Wire up the successors */
571
572 bi_block_add_successor(before_block, then_branch->branch.target); /* then_branch */
573
574 bi_block_add_successor(before_block, then_block); /* fallthrough */
575 bi_block_add_successor(end_else_block, ctx->after_block); /* fallthrough */
576 }
577
578 static void
579 emit_loop(bi_context *ctx, nir_loop *nloop)
580 {
581 /* Remember where we are */
582 bi_block *start_block = ctx->current_block;
583
584 bi_block *saved_break = ctx->break_block;
585 bi_block *saved_continue = ctx->continue_block;
586
587 ctx->continue_block = create_empty_block(ctx);
588 ctx->break_block = create_empty_block(ctx);
589 ctx->after_block = ctx->continue_block;
590
591 /* Emit the body itself */
592 emit_cf_list(ctx, &nloop->body);
593
594 /* Branch back to loop back */
595 bi_instruction *br_back = bi_emit_branch(ctx);
596 br_back->branch.target = ctx->continue_block;
597 bi_block_add_successor(start_block, ctx->continue_block);
598 bi_block_add_successor(ctx->current_block, ctx->continue_block);
599
600 ctx->after_block = ctx->break_block;
601
602 /* Pop off */
603 ctx->break_block = saved_break;
604 ctx->continue_block = saved_continue;
605 ++ctx->loop_count;
606 }
607
608 static bi_block *
609 emit_cf_list(bi_context *ctx, struct exec_list *list)
610 {
611 bi_block *start_block = NULL;
612
613 foreach_list_typed(nir_cf_node, node, node, list) {
614 switch (node->type) {
615 case nir_cf_node_block: {
616 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
617
618 if (!start_block)
619 start_block = block;
620
621 break;
622 }
623
624 case nir_cf_node_if:
625 emit_if(ctx, nir_cf_node_as_if(node));
626 break;
627
628 case nir_cf_node_loop:
629 emit_loop(ctx, nir_cf_node_as_loop(node));
630 break;
631
632 default:
633 unreachable("Unknown control flow");
634 }
635 }
636
637 return start_block;
638 }
639
640 static int
641 glsl_type_size(const struct glsl_type *type, bool bindless)
642 {
643 return glsl_count_attribute_slots(type, false);
644 }
645
646 static void
647 bi_optimize_nir(nir_shader *nir)
648 {
649 bool progress;
650 unsigned lower_flrp = 16 | 32 | 64;
651
652 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
653 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
654
655 nir_lower_tex_options lower_tex_options = {
656 .lower_txs_lod = true,
657 .lower_txp = ~0,
658 .lower_tex_without_implicit_lod = true,
659 .lower_txd = true,
660 };
661
662 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
663 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
664 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
665
666 do {
667 progress = false;
668
669 NIR_PASS(progress, nir, nir_lower_var_copies);
670 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
671
672 NIR_PASS(progress, nir, nir_copy_prop);
673 NIR_PASS(progress, nir, nir_opt_remove_phis);
674 NIR_PASS(progress, nir, nir_opt_dce);
675 NIR_PASS(progress, nir, nir_opt_dead_cf);
676 NIR_PASS(progress, nir, nir_opt_cse);
677 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
678 NIR_PASS(progress, nir, nir_opt_algebraic);
679 NIR_PASS(progress, nir, nir_opt_constant_folding);
680
681 if (lower_flrp != 0) {
682 bool lower_flrp_progress = false;
683 NIR_PASS(lower_flrp_progress,
684 nir,
685 nir_lower_flrp,
686 lower_flrp,
687 false /* always_precise */,
688 nir->options->lower_ffma);
689 if (lower_flrp_progress) {
690 NIR_PASS(progress, nir,
691 nir_opt_constant_folding);
692 progress = true;
693 }
694
695 /* Nothing should rematerialize any flrps, so we only
696 * need to do this lowering once.
697 */
698 lower_flrp = 0;
699 }
700
701 NIR_PASS(progress, nir, nir_opt_undef);
702 NIR_PASS(progress, nir, nir_opt_loop_unroll,
703 nir_var_shader_in |
704 nir_var_shader_out |
705 nir_var_function_temp);
706 } while (progress);
707
708 NIR_PASS(progress, nir, nir_opt_algebraic_late);
709 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
710 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
711
712 /* Take us out of SSA */
713 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
714 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
715
716 /* We're a primary scalar architecture but there's enough vector that
717 * we use a vector IR so let's not also deal with scalar hacks on top
718 * of the vector hacks */
719
720 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
721 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
722 NIR_PASS(progress, nir, nir_opt_dce);
723 }
724
725 void
726 bifrost_compile_shader_nir(nir_shader *nir, bifrost_program *program, unsigned product_id)
727 {
728 bi_context *ctx = rzalloc(NULL, bi_context);
729 ctx->nir = nir;
730 ctx->stage = nir->info.stage;
731 ctx->quirks = bifrost_get_quirks(product_id);
732 list_inithead(&ctx->blocks);
733
734 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
735 * (so we don't accidentally duplicate the epilogue since mesa/st has
736 * messed with our I/O quite a bit already) */
737
738 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
739
740 if (ctx->stage == MESA_SHADER_VERTEX) {
741 NIR_PASS_V(nir, nir_lower_viewport_transform);
742 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
743 }
744
745 NIR_PASS_V(nir, nir_split_var_copies);
746 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
747 NIR_PASS_V(nir, nir_lower_var_copies);
748 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
749 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
750 NIR_PASS_V(nir, nir_lower_ssbo);
751
752 bi_optimize_nir(nir);
753 nir_print_shader(nir, stdout);
754
755 nir_foreach_function(func, nir) {
756 if (!func->impl)
757 continue;
758
759 ctx->impl = func->impl;
760 emit_cf_list(ctx, &func->impl->body);
761 break; /* TODO: Multi-function shaders */
762 }
763
764 bi_print_shader(ctx, stdout);
765 bi_schedule(ctx);
766
767 ralloc_free(ctx);
768 }