src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "util/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .src_types = { nir_type_uint32 },
  78                 .constant = { .u64 = nir_intrinsic_base(instr) },
  79         };
  80
  81         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  82
  83         if (info->has_dest)
  84                 load.dest = bir_dest_index(&instr->dest);
  85
  86         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  87                 load.dest_type = nir_intrinsic_type(instr);
  88
  89         nir_src *offset = nir_get_io_offset_src(instr);
  90
  91         if (nir_src_is_const(*offset))
  92                 load.constant.u64 += nir_src_as_uint(*offset);
  93         else
  94                 load.src[0] = bir_src_index(offset);
  95
  96         return load;
  97 }
  98
  99 static void
 100 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 101 {
 102         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 103         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 104         ins.load_vary.reuse = false; /* TODO */
 105         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 106         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 107
 108         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 109                 /* Zero it out for direct */
 110                 ins.src[1] = BIR_INDEX_ZERO;
 111         } else {
 112                 /* R61 contains sample mask stuff, TODO RA XXX */
 113                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 114         }
 115
 116         bi_emit(ctx, ins);
 117 }
 118
 119 static void
 120 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 121 {
 122         if (!ctx->emitted_atest) {
 123                 bi_instruction ins = {
 124                         .type = BI_ATEST,
 125                         .src = {
 126                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 127                                 bir_src_index(&instr->src[0])
 128                         },
 129                         .src_types = {
 130                                 nir_type_uint32,
 131                                 nir_type_float32
 132                         },
 133                         .swizzle = {
 134                                 { 0 },
 135                                 { 3, 0 } /* swizzle out the alpha */
 136                         },
 137                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 138                         .dest_type = nir_type_uint32,
 139                         .writemask = 0xF
 140                 };
 141
 142                 bi_emit(ctx, ins);
 143                 bi_schedule_barrier(ctx);
 144                 ctx->emitted_atest = true;
 145         }
 146
 147         bi_instruction blend = {
 148                 .type = BI_BLEND,
 149                 .blend_location = nir_intrinsic_base(instr),
 150                 .src = {
 151                         bir_src_index(&instr->src[0]),
 152                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 153                 },
 154                 .src_types = {
 155                         nir_type_float32,
 156                         nir_type_uint32
 157                 },
 158                 .swizzle = {
 159                         { 0, 1, 2, 3 },
 160                         { 0 }
 161                 },
 162                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 163                 .dest_type = nir_type_uint32,
 164                 .writemask = 0xF
 165         };
 166
 167         bi_emit(ctx, blend);
 168         bi_schedule_barrier(ctx);
 169 }
 170
 171 static bi_instruction
 172 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
 173 {
 174         bi_instruction ld = bi_load(T, instr);
 175         ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
 176         ld.src[2] = BIR_INDEX_REGISTER | 62;
 177         ld.src[3] = 0;
 178         ld.src_types[1] = nir_type_uint32;
 179         ld.src_types[2] = nir_type_uint32;
 180         ld.src_types[3] = nir_intrinsic_type(instr);
 181         return ld;
 182 }
 183
 184 static void
 185 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 186 {
 187         bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
 188         address.dest = bi_make_temp(ctx);
 189         address.dest_type = nir_type_uint32;
 190         address.writemask = (1 << 12) - 1;
 191
 192         bi_instruction st = {
 193                 .type = BI_STORE_VAR,
 194                 .src = {
 195                         bir_src_index(&instr->src[0]),
 196                         address.dest, address.dest, address.dest,
 197                 },
 198                 .src_types = {
 199                         nir_type_uint32,
 200                         nir_type_uint32, nir_type_uint32, nir_type_uint32,
 201                 },
 202                 .swizzle = {
 203                         { 0, 1, 2, 3 },
 204                         { 0 }, { 1 }, { 2}
 205                 },
 206                 .store_channels = 4, /* TODO: WRITEMASK */
 207         };
 208
 209         bi_emit(ctx, address);
 210         bi_emit(ctx, st);
 211 }
 212
 213 static void
 214 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 215 {
 216         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 217         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 218
 219         /* TODO: Indirect access, since we need to multiply by the element
 220          * size. I believe we can get this lowering automatically via
 221          * nir_lower_io (as mul instructions) with the proper options, but this
 222          * is TODO */
 223         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 224         ld.constant.u64 += ctx->sysvals.sysval_count;
 225         ld.constant.u64 *= 16;
 226
 227         bi_emit(ctx, ld);
 228 }
 229
 230 static void
 231 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 232                 unsigned nr_components, unsigned offset)
 233 {
 234         nir_dest nir_dest;
 235
 236         /* Figure out which uniform this is */
 237         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 238         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 239
 240         /* Sysvals are prefix uniforms */
 241         unsigned uniform = ((uintptr_t) val) - 1;
 242
 243         /* Emit the read itself -- this is never indirect */
 244
 245         bi_instruction load = {
 246                 .type = BI_LOAD_UNIFORM,
 247                 .writemask = (1 << (nr_components * 4)) - 1,
 248                 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
 249                 .src_types = { nir_type_uint32, nir_type_uint32 },
 250                 .constant = { (uniform * 16) + offset },
 251                 .dest = bir_dest_index(&nir_dest),
 252                 .dest_type = nir_type_uint32, /* TODO */
 253         };
 254
 255         bi_emit(ctx, load);
 256 }
 257
 258 static void
 259 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 260 {
 261
 262         switch (instr->intrinsic) {
 263         case nir_intrinsic_load_barycentric_pixel:
 264                 /* stub */
 265                 break;
 266         case nir_intrinsic_load_interpolated_input:
 267         case nir_intrinsic_load_input:
 268                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 269                         bi_emit_ld_vary(ctx, instr);
 270                 else if (ctx->stage == MESA_SHADER_VERTEX)
 271                         bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
 272                 else {
 273                         unreachable("Unsupported shader stage");
 274                 }
 275                 break;
 276
 277         case nir_intrinsic_store_output:
 278                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 279                         bi_emit_frag_out(ctx, instr);
 280                 else if (ctx->stage == MESA_SHADER_VERTEX)
 281                         bi_emit_st_vary(ctx, instr);
 282                 else
 283                         unreachable("Unsupported shader stage");
 284                 break;
 285
 286         case nir_intrinsic_load_uniform:
 287                 bi_emit_ld_uniform(ctx, instr);
 288                 break;
 289
 290         case nir_intrinsic_load_ssbo_address:
 291                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 292                 break;
 293
 294         case nir_intrinsic_get_buffer_size:
 295                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 296                 break;
 297
 298         case nir_intrinsic_load_viewport_scale:
 299         case nir_intrinsic_load_viewport_offset:
 300         case nir_intrinsic_load_num_work_groups:
 301         case nir_intrinsic_load_sampler_lod_parameters_pan:
 302                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 303                 break;
 304
 305         default:
 306                 /* todo */
 307                 break;
 308         }
 309 }
 310
 311 static void
 312 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 313 {
 314         /* Make sure we've been lowered */
 315         assert(instr->def.num_components == 1);
 316
 317         bi_instruction move = {
 318                 .type = BI_MOV,
 319                 .dest = bir_ssa_index(&instr->def),
 320                 .dest_type = instr->def.bit_size | nir_type_uint,
 321                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 322                 .src = {
 323                         BIR_INDEX_CONSTANT
 324                 },
 325                 .src_types = {
 326                         instr->def.bit_size | nir_type_uint,
 327                 },
 328                 .constant = {
 329                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 330                 }
 331         };
 332
 333         bi_emit(ctx, move);
 334 }
 335
 336 #define BI_CASE_CMP(op) \
 337         case op##8: \
 338         case op##16: \
 339         case op##32: \
 340
 341 static enum bi_class
 342 bi_class_for_nir_alu(nir_op op)
 343 {
 344         switch (op) {
 345         case nir_op_iadd:
 346         case nir_op_fadd:
 347         case nir_op_fsub:
 348                 return BI_ADD;
 349         case nir_op_isub:
 350                 return BI_ISUB;
 351
 352         BI_CASE_CMP(nir_op_flt)
 353         BI_CASE_CMP(nir_op_fge)
 354         BI_CASE_CMP(nir_op_feq)
 355         BI_CASE_CMP(nir_op_fne)
 356         BI_CASE_CMP(nir_op_ilt)
 357         BI_CASE_CMP(nir_op_ige)
 358         BI_CASE_CMP(nir_op_ieq)
 359         BI_CASE_CMP(nir_op_ine)
 360                 return BI_CMP;
 361
 362         case nir_op_b8csel:
 363         case nir_op_b16csel:
 364         case nir_op_b32csel:
 365                 return BI_CSEL;
 366
 367         case nir_op_i2i8:
 368         case nir_op_i2i16:
 369         case nir_op_i2i32:
 370         case nir_op_i2i64:
 371         case nir_op_u2u8:
 372         case nir_op_u2u16:
 373         case nir_op_u2u32:
 374         case nir_op_u2u64:
 375         case nir_op_f2i16:
 376         case nir_op_f2i32:
 377         case nir_op_f2i64:
 378         case nir_op_f2u16:
 379         case nir_op_f2u32:
 380         case nir_op_f2u64:
 381         case nir_op_i2f16:
 382         case nir_op_i2f32:
 383         case nir_op_i2f64:
 384         case nir_op_u2f16:
 385         case nir_op_u2f32:
 386         case nir_op_u2f64:
 387         case nir_op_f2f16:
 388         case nir_op_f2f32:
 389         case nir_op_f2f64:
 390         case nir_op_f2fmp:
 391                 return BI_CONVERT;
 392
 393         case nir_op_vec2:
 394         case nir_op_vec3:
 395         case nir_op_vec4:
 396                 return BI_COMBINE;
 397
 398         case nir_op_vec8:
 399         case nir_op_vec16:
 400                 unreachable("should've been lowered");
 401
 402         case nir_op_ffma:
 403         case nir_op_fmul:
 404                 return BI_FMA;
 405
 406         case nir_op_imin:
 407         case nir_op_imax:
 408         case nir_op_umin:
 409         case nir_op_umax:
 410         case nir_op_fmin:
 411         case nir_op_fmax:
 412                 return BI_MINMAX;
 413
 414         case nir_op_fsat:
 415         case nir_op_fneg:
 416         case nir_op_fabs:
 417                 return BI_FMOV;
 418         case nir_op_mov:
 419                 return BI_MOV;
 420
 421         case nir_op_fround_even:
 422         case nir_op_fceil:
 423         case nir_op_ffloor:
 424         case nir_op_ftrunc:
 425                 return BI_ROUND;
 426
 427         case nir_op_frcp:
 428         case nir_op_frsq:
 429                 return BI_SPECIAL;
 430
 431         default:
 432                 unreachable("Unknown ALU op");
 433         }
 434 }
 435
 436 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
 437  * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
 438  * optimizations). Otherwise it will bail (when used for primary code
 439  * generation). */
 440
 441 static enum bi_cond
 442 bi_cond_for_nir(nir_op op, bool soft)
 443 {
 444         switch (op) {
 445         BI_CASE_CMP(nir_op_flt)
 446         BI_CASE_CMP(nir_op_ilt)
 447                 return BI_COND_LT;
 448
 449         BI_CASE_CMP(nir_op_fge)
 450         BI_CASE_CMP(nir_op_ige)
 451                 return BI_COND_GE;
 452
 453         BI_CASE_CMP(nir_op_feq)
 454         BI_CASE_CMP(nir_op_ieq)
 455                 return BI_COND_EQ;
 456
 457         BI_CASE_CMP(nir_op_fne)
 458         BI_CASE_CMP(nir_op_ine)
 459                 return BI_COND_NE;
 460         default:
 461                 if (soft)
 462                         return BI_COND_ALWAYS;
 463                 else
 464                         unreachable("Invalid compare");
 465         }
 466 }
 467
 468 static void
 469 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
 470                 unsigned *constants_left, unsigned *constant_shift)
 471 {
 472         unsigned bits = nir_src_bit_size(instr->src[i].src);
 473         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 474
 475         alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
 476                 | bits;
 477
 478         /* Try to inline a constant */
 479         if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
 480                 alu->constant.u64 |=
 481                         (nir_src_as_uint(instr->src[i].src)) << *constant_shift;
 482
 483                 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
 484                 --(*constants_left);
 485                 (*constant_shift) += dest_bits;
 486                 return;
 487         }
 488
 489         alu->src[to] = bir_src_index(&instr->src[i].src);
 490
 491         /* We assert scalarization above */
 492         alu->swizzle[to][0] = instr->src[i].swizzle[0];
 493 }
 494
 495 static void
 496 bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
 497                 unsigned *constants_left, unsigned *constant_shift)
 498 {
 499         /* Bail for vector weirdness */
 500         if (cond.swizzle[0] != 0)
 501                 return;
 502
 503         if (!cond.src.is_ssa)
 504                 return;
 505
 506         nir_ssa_def *def = cond.src.ssa;
 507         nir_instr *parent = def->parent_instr;
 508
 509         if (parent->type != nir_instr_type_alu)
 510                 return;
 511
 512         nir_alu_instr *alu = nir_instr_as_alu(parent);
 513
 514         /* Try to match a condition */
 515         enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
 516
 517         if (bcond == BI_COND_ALWAYS)
 518                 return;
 519
 520         /* We found one, let's fuse it in */
 521         csel->csel_cond = bcond;
 522         bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift);
 523         bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift);
 524 }
 525
 526 static void
 527 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 528 {
 529         /* Assume it's something we can handle normally */
 530         bi_instruction alu = {
 531                 .type = bi_class_for_nir_alu(instr->op),
 532                 .dest = bir_dest_index(&instr->dest.dest),
 533                 .dest_type = nir_op_infos[instr->op].output_type
 534                         | nir_dest_bit_size(instr->dest.dest),
 535         };
 536
 537         /* TODO: Implement lowering of special functions for older Bifrost */
 538         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 539
 540         if (instr->dest.dest.is_ssa) {
 541                 /* Construct a writemask */
 542                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 543                 unsigned comps = instr->dest.dest.ssa.num_components;
 544
 545                 if (alu.type != BI_COMBINE)
 546                         assert(comps == 1);
 547
 548                 unsigned bits = bits_per_comp * comps;
 549                 unsigned bytes = bits / 8;
 550                 alu.writemask = (1 << bytes) - 1;
 551         } else {
 552                 unsigned comp_mask = instr->dest.write_mask;
 553
 554                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 555                                 comp_mask);
 556         }
 557
 558         /* We inline constants as we go. This tracks how many constants have
 559          * been inlined, since we're limited to 64-bits of constants per
 560          * instruction */
 561
 562         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 563         unsigned constants_left = (64 / dest_bits);
 564         unsigned constant_shift = 0;
 565
 566         if (alu.type == BI_COMBINE)
 567                 constants_left = 0;
 568
 569         /* Copy sources */
 570
 571         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 572         assert(num_inputs <= ARRAY_SIZE(alu.src));
 573
 574         for (unsigned i = 0; i < num_inputs; ++i) {
 575                 unsigned f = 0;
 576
 577                 if (i && alu.type == BI_CSEL)
 578                         f++;
 579
 580                 bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift);
 581         }
 582
 583         /* Op-specific fixup */
 584         switch (instr->op) {
 585         case nir_op_fmul:
 586                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 587                 alu.src_types[2] = alu.src_types[1];
 588                 break;
 589         case nir_op_fsat:
 590                 alu.outmod = BIFROST_SAT; /* FMOV */
 591                 break;
 592         case nir_op_fneg:
 593                 alu.src_neg[0] = true; /* FMOV */
 594                 break;
 595         case nir_op_fabs:
 596                 alu.src_abs[0] = true; /* FMOV */
 597                 break;
 598         case nir_op_fsub:
 599                 alu.src_neg[1] = true; /* FADD */
 600                 break;
 601         case nir_op_fmax:
 602         case nir_op_imax:
 603         case nir_op_umax:
 604                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 605                 break;
 606         case nir_op_frcp:
 607                 alu.op.special = BI_SPECIAL_FRCP;
 608                 break;
 609         case nir_op_frsq:
 610                 alu.op.special = BI_SPECIAL_FRSQ;
 611                 break;
 612         BI_CASE_CMP(nir_op_flt)
 613         BI_CASE_CMP(nir_op_ilt)
 614         BI_CASE_CMP(nir_op_fge)
 615         BI_CASE_CMP(nir_op_ige)
 616         BI_CASE_CMP(nir_op_feq)
 617         BI_CASE_CMP(nir_op_ieq)
 618         BI_CASE_CMP(nir_op_fne)
 619         BI_CASE_CMP(nir_op_ine)
 620                 alu.op.compare = bi_cond_for_nir(instr->op, false);
 621                 break;
 622         case nir_op_fround_even:
 623                 alu.op.round = BI_ROUND_MODE;
 624                 alu.roundmode = BIFROST_RTE;
 625                 break;
 626         case nir_op_fceil:
 627                 alu.op.round = BI_ROUND_MODE;
 628                 alu.roundmode = BIFROST_RTP;
 629                 break;
 630         case nir_op_ffloor:
 631                 alu.op.round = BI_ROUND_MODE;
 632                 alu.roundmode = BIFROST_RTN;
 633                 break;
 634         case nir_op_ftrunc:
 635                 alu.op.round = BI_ROUND_MODE;
 636                 alu.roundmode = BIFROST_RTZ;
 637                 break;
 638         default:
 639                 break;
 640         }
 641
 642         if (alu.type == BI_CSEL) {
 643                 /* Default to csel3 */
 644                 alu.csel_cond = BI_COND_NE;
 645                 alu.src[1] = BIR_INDEX_ZERO;
 646                 alu.src_types[1] = alu.src_types[0];
 647
 648                 bi_fuse_csel_cond(&alu, instr->src[0],
 649                                 &constants_left, &constant_shift);
 650         }
 651
 652         bi_emit(ctx, alu);
 653 }
 654
 655 static void
 656 emit_instr(bi_context *ctx, struct nir_instr *instr)
 657 {
 658         switch (instr->type) {
 659         case nir_instr_type_load_const:
 660                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 661                 break;
 662
 663         case nir_instr_type_intrinsic:
 664                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 665                 break;
 666
 667         case nir_instr_type_alu:
 668                 emit_alu(ctx, nir_instr_as_alu(instr));
 669                 break;
 670
 671 #if 0
 672         case nir_instr_type_tex:
 673                 emit_tex(ctx, nir_instr_as_tex(instr));
 674                 break;
 675 #endif
 676
 677         case nir_instr_type_jump:
 678                 emit_jump(ctx, nir_instr_as_jump(instr));
 679                 break;
 680
 681         case nir_instr_type_ssa_undef:
 682                 /* Spurious */
 683                 break;
 684
 685         default:
 686                 //unreachable("Unhandled instruction type");
 687                 break;
 688         }
 689 }
 690
 691
 692
 693 static bi_block *
 694 create_empty_block(bi_context *ctx)
 695 {
 696         bi_block *blk = rzalloc(ctx, bi_block);
 697
 698         blk->base.predecessors = _mesa_set_create(blk,
 699                         _mesa_hash_pointer,
 700                         _mesa_key_pointer_equal);
 701
 702         blk->base.name = ctx->block_name_count++;
 703
 704         return blk;
 705 }
 706
 707 static void
 708 bi_schedule_barrier(bi_context *ctx)
 709 {
 710         bi_block *temp = ctx->after_block;
 711         ctx->after_block = create_empty_block(ctx);
 712         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 713         list_inithead(&ctx->after_block->base.instructions);
 714         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 715         ctx->current_block = ctx->after_block;
 716         ctx->after_block = temp;
 717 }
 718
 719 static bi_block *
 720 emit_block(bi_context *ctx, nir_block *block)
 721 {
 722         if (ctx->after_block) {
 723                 ctx->current_block = ctx->after_block;
 724                 ctx->after_block = NULL;
 725         } else {
 726                 ctx->current_block = create_empty_block(ctx);
 727         }
 728
 729         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 730         list_inithead(&ctx->current_block->base.instructions);
 731
 732         nir_foreach_instr(instr, block) {
 733                 emit_instr(ctx, instr);
 734                 ++ctx->instruction_count;
 735         }
 736
 737         return ctx->current_block;
 738 }
 739
 740 /* Emits an unconditional branch to the end of the current block, returning a
 741  * pointer so the user can fill in details */
 742
 743 static bi_instruction *
 744 bi_emit_branch(bi_context *ctx)
 745 {
 746         bi_instruction branch = {
 747                 .type = BI_BRANCH,
 748                 .branch = {
 749                         .cond = BI_COND_ALWAYS
 750                 }
 751         };
 752
 753         return bi_emit(ctx, branch);
 754 }
 755
 756 /* Sets a condition for a branch by examing the NIR condition. If we're
 757  * familiar with the condition, we unwrap it to fold it into the branch
 758  * instruction. Otherwise, we consume the condition directly. We
 759  * generally use 1-bit booleans which allows us to use small types for
 760  * the conditions.
 761  */
 762
 763 static void
 764 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 765 {
 766         /* TODO: Try to unwrap instead of always bailing */
 767         branch->src[0] = bir_src_index(cond);
 768         branch->src[1] = BIR_INDEX_ZERO;
 769         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 770         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 771 }
 772
 773 static void
 774 emit_if(bi_context *ctx, nir_if *nif)
 775 {
 776         bi_block *before_block = ctx->current_block;
 777
 778         /* Speculatively emit the branch, but we can't fill it in until later */
 779         bi_instruction *then_branch = bi_emit_branch(ctx);
 780         bi_set_branch_cond(then_branch, &nif->condition, true);
 781
 782         /* Emit the two subblocks. */
 783         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 784         bi_block *end_then_block = ctx->current_block;
 785
 786         /* Emit a jump from the end of the then block to the end of the else */
 787         bi_instruction *then_exit = bi_emit_branch(ctx);
 788
 789         /* Emit second block, and check if it's empty */
 790
 791         int count_in = ctx->instruction_count;
 792         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 793         bi_block *end_else_block = ctx->current_block;
 794         ctx->after_block = create_empty_block(ctx);
 795
 796         /* Now that we have the subblocks emitted, fix up the branches */
 797
 798         assert(then_block);
 799         assert(else_block);
 800
 801         if (ctx->instruction_count == count_in) {
 802                 /* The else block is empty, so don't emit an exit jump */
 803                 bi_remove_instruction(then_exit);
 804                 then_branch->branch.target = ctx->after_block;
 805         } else {
 806                 then_branch->branch.target = else_block;
 807                 then_exit->branch.target = ctx->after_block;
 808                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 809         }
 810
 811         /* Wire up the successors */
 812
 813         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 814
 815         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 816         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 817 }
 818
 819 static void
 820 emit_loop(bi_context *ctx, nir_loop *nloop)
 821 {
 822         /* Remember where we are */
 823         bi_block *start_block = ctx->current_block;
 824
 825         bi_block *saved_break = ctx->break_block;
 826         bi_block *saved_continue = ctx->continue_block;
 827
 828         ctx->continue_block = create_empty_block(ctx);
 829         ctx->break_block = create_empty_block(ctx);
 830         ctx->after_block = ctx->continue_block;
 831
 832         /* Emit the body itself */
 833         emit_cf_list(ctx, &nloop->body);
 834
 835         /* Branch back to loop back */
 836         bi_instruction *br_back = bi_emit_branch(ctx);
 837         br_back->branch.target = ctx->continue_block;
 838         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 839         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 840
 841         ctx->after_block = ctx->break_block;
 842
 843         /* Pop off */
 844         ctx->break_block = saved_break;
 845         ctx->continue_block = saved_continue;
 846         ++ctx->loop_count;
 847 }
 848
 849 static bi_block *
 850 emit_cf_list(bi_context *ctx, struct exec_list *list)
 851 {
 852         bi_block *start_block = NULL;
 853
 854         foreach_list_typed(nir_cf_node, node, node, list) {
 855                 switch (node->type) {
 856                 case nir_cf_node_block: {
 857                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 858
 859                         if (!start_block)
 860                                 start_block = block;
 861
 862                         break;
 863                 }
 864
 865                 case nir_cf_node_if:
 866                         emit_if(ctx, nir_cf_node_as_if(node));
 867                         break;
 868
 869                 case nir_cf_node_loop:
 870                         emit_loop(ctx, nir_cf_node_as_loop(node));
 871                         break;
 872
 873                 default:
 874                         unreachable("Unknown control flow");
 875                 }
 876         }
 877
 878         return start_block;
 879 }
 880
 881 static int
 882 glsl_type_size(const struct glsl_type *type, bool bindless)
 883 {
 884         return glsl_count_attribute_slots(type, false);
 885 }
 886
 887 static void
 888 bi_optimize_nir(nir_shader *nir)
 889 {
 890         bool progress;
 891         unsigned lower_flrp = 16 | 32 | 64;
 892
 893         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 894         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 895
 896         nir_lower_tex_options lower_tex_options = {
 897                 .lower_txs_lod = true,
 898                 .lower_txp = ~0,
 899                 .lower_tex_without_implicit_lod = true,
 900                 .lower_txd = true,
 901         };
 902
 903         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 904         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 905         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 906
 907         do {
 908                 progress = false;
 909
 910                 NIR_PASS(progress, nir, nir_lower_var_copies);
 911                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 912
 913                 NIR_PASS(progress, nir, nir_copy_prop);
 914                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 915                 NIR_PASS(progress, nir, nir_opt_dce);
 916                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 917                 NIR_PASS(progress, nir, nir_opt_cse);
 918                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 919                 NIR_PASS(progress, nir, nir_opt_algebraic);
 920                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 921
 922                 if (lower_flrp != 0) {
 923                         bool lower_flrp_progress = false;
 924                         NIR_PASS(lower_flrp_progress,
 925                                  nir,
 926                                  nir_lower_flrp,
 927                                  lower_flrp,
 928                                  false /* always_precise */,
 929                                  nir->options->lower_ffma);
 930                         if (lower_flrp_progress) {
 931                                 NIR_PASS(progress, nir,
 932                                          nir_opt_constant_folding);
 933                                 progress = true;
 934                         }
 935
 936                         /* Nothing should rematerialize any flrps, so we only
 937                          * need to do this lowering once.
 938                          */
 939                         lower_flrp = 0;
 940                 }
 941
 942                 NIR_PASS(progress, nir, nir_opt_undef);
 943                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 944                          nir_var_shader_in |
 945                          nir_var_shader_out |
 946                          nir_var_function_temp);
 947         } while (progress);
 948
 949         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 950         NIR_PASS(progress, nir, nir_lower_bool_to_int32);
 951         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 952         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 953         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 954
 955         /* Take us out of SSA */
 956         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 957         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 958         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 959 }
 960
 961 void
 962 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 963 {
 964         bi_context *ctx = rzalloc(NULL, bi_context);
 965         ctx->nir = nir;
 966         ctx->stage = nir->info.stage;
 967         ctx->quirks = bifrost_get_quirks(product_id);
 968         list_inithead(&ctx->blocks);
 969
 970         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 971          * (so we don't accidentally duplicate the epilogue since mesa/st has
 972          * messed with our I/O quite a bit already) */
 973
 974         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 975
 976         if (ctx->stage == MESA_SHADER_VERTEX) {
 977                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 978                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 979         }
 980
 981         NIR_PASS_V(nir, nir_split_var_copies);
 982         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 983         NIR_PASS_V(nir, nir_lower_var_copies);
 984         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 985         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 986         NIR_PASS_V(nir, nir_lower_ssbo);
 987
 988         bi_optimize_nir(nir);
 989         nir_print_shader(nir, stdout);
 990
 991         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 992         program->sysval_count = ctx->sysvals.sysval_count;
 993         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 994
 995         nir_foreach_function(func, nir) {
 996                 if (!func->impl)
 997                         continue;
 998
 999                 ctx->impl = func->impl;
1000                 emit_cf_list(ctx, &func->impl->body);
1001                 break; /* TODO: Multi-function shaders */
1002         }
1003
1004         bi_foreach_block(ctx, _block) {
1005                 bi_block *block = (bi_block *) _block;
1006                 bi_lower_combine(ctx, block);
1007         }
1008
1009         bool progress = false;
1010
1011         do {
1012                 progress = false;
1013
1014                 bi_foreach_block(ctx, _block) {
1015                         bi_block *block = (bi_block *) _block;
1016                         progress |= bi_opt_dead_code_eliminate(ctx, block);
1017                 }
1018         } while(progress);
1019
1020         bi_print_shader(ctx, stdout);
1021         bi_schedule(ctx);
1022         bi_register_allocate(ctx);
1023         bi_print_shader(ctx, stdout);
1024         bi_pack(ctx, &program->compiled);
1025         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1026
1027         ralloc_free(ctx);
1028 }