2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
32 #include "panfrost/util/pan_ir.h"
34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
35 * ADD with two completely different opcodes, and opcodes can be varying
36 * length in some cases. Then we have different opcodes for int vs float
37 * and then sometimes even for different typesizes. Further, virtually
38 * every op has a number of flags which depend on the op. In constrast
39 * to Midgard where you have a strict ALU/LDST/TEX division and within
40 * ALU you have strict int/float and that's it... here it's a *lot* more
41 * involved. As such, we use something much higher level for our IR,
42 * encoding "classes" of operations, letting the opcode details get
43 * sorted out at emit time.
45 * Please keep this list alphabetized. Please use a dictionary if you
46 * don't know how to do that.
75 BI_SPECIAL
, /* _FAST on supported GPUs */
83 /* Properties of a class... */
84 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
86 /* abs/neg/outmod valid for a float op */
87 #define BI_MODS (1 << 0)
89 /* Accepts a bi_cond */
90 #define BI_CONDITIONAL (1 << 1)
92 /* Accepts a bifrost_roundmode */
93 #define BI_ROUNDMODE (1 << 2)
95 /* Can be scheduled to FMA */
96 #define BI_SCHED_FMA (1 << 3)
98 /* Can be scheduled to ADD */
99 #define BI_SCHED_ADD (1 << 4)
101 /* Most ALU ops can do either, actually */
102 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
104 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
105 * nopped out. Used for _FAST operations. */
106 #define BI_SCHED_SLOW (1 << 5)
108 /* Swizzling allowed for the 8/16-bit source */
109 #define BI_SWIZZLABLE (1 << 6)
111 /* For scheduling purposes this is a high latency instruction and must be at
112 * the end of a clause. Implies ADD */
113 #define BI_SCHED_HI_LATENCY (1 << 7)
115 /* Intrinsic is vectorized and acts with `vector_channels` components */
116 #define BI_VECTOR (1 << 8)
118 /* Use a data register for src0/dest respectively, bypassing the usual
119 * register accessor. Mutually exclusive. */
120 #define BI_DATA_REG_SRC (1 << 9)
121 #define BI_DATA_REG_DEST (1 << 10)
123 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
124 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
126 /* It can't get any worse than csel4... can it? */
127 #define BIR_SRC_COUNT 4
130 struct bi_load_vary
{
131 enum bifrost_interp_mode interp_mode
;
136 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
137 * the target. We forward declare bi_block since this is mildly circular (not
138 * strictly, but this order of the file makes more sense I think)
140 * We define our own enum of conditions since the conditions in the hardware
141 * packed in crazy ways that would make manipulation unweildly (meaning changes
142 * based on port swapping, etc), so we defer dealing with that until emit time.
143 * Likewise, we expose NIR types instead of the crazy branch types, although
144 * the restrictions do eventually apply of course. */
158 /* Opcodes within a class */
180 /* fp32 log2() with low precision, suitable for GL or half_log2() in
181 * CL. In the first argument, takes x. Letting u be such that x =
182 * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
183 * log2(u) / (u - 1). */
185 BI_TABLE_LOG2_U_OVER_U_1_LOW
,
189 /* Takes two fp32 arguments and returns x + frexp(y). Used in
190 * low-precision log2 argument reduction on newer models. */
192 BI_REDUCE_ADD_FREXPM
,
203 /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
204 * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
205 * the second, it takes x itself. */
218 bool rshift
; /* false for lshift */
222 /* Constant indices. Indirect would need to be in src[..] like normal,
223 * we can reserve some sentinels there for that for future. */
224 unsigned texture_index
, sampler_index
;
228 struct list_head link
; /* Must be first */
231 /* Indices, see pan_ssa_index etc. Note zero is special cased
232 * to "no argument" */
234 unsigned src
[BIR_SRC_COUNT
];
236 /* 32-bit word offset for destination, added to the register number in
237 * RA when lowering combines */
238 unsigned dest_offset
;
240 /* If one of the sources has BIR_INDEX_CONSTANT */
248 /* Floating-point modifiers, type/class permitting. If not
249 * allowed for the type/class, these are ignored. */
250 enum bifrost_outmod outmod
;
251 bool src_abs
[BIR_SRC_COUNT
];
252 bool src_neg
[BIR_SRC_COUNT
];
254 /* Round mode (requires BI_ROUNDMODE) */
255 enum bifrost_roundmode roundmode
;
257 /* Destination type. Usually the type of the instruction
258 * itself, but if sources and destination have different
259 * types, the type of the destination wins (so f2i would be
260 * int). Zero if there is no destination. Bitsize included */
261 nir_alu_type dest_type
;
263 /* Source types if required by the class */
264 nir_alu_type src_types
[BIR_SRC_COUNT
];
266 /* If the source type is 8-bit or 16-bit such that SIMD is possible,
267 * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
268 * sense. On non-SIMD instructions, it can be used for component
269 * selection, so we don't have to special case extraction. */
270 uint8_t swizzle
[BIR_SRC_COUNT
][NIR_MAX_VEC_COMPONENTS
];
272 /* For VECTOR ops, how many channels are written? */
273 unsigned vector_channels
;
275 /* The comparison op. BI_COND_ALWAYS may not be valid. */
278 /* A class-specific op from which the actual opcode can be derived
279 * (along with the above information) */
282 enum bi_minmax_op minmax
;
283 enum bi_bitwise_op bitwise
;
284 enum bi_special_op special
;
285 enum bi_reduce_op reduce
;
286 enum bi_table_op table
;
287 enum bi_frexp_op frexp
;
288 enum bi_tex_op texture
;
289 enum bi_imath_op imath
;
290 enum bi_imul_op imul
;
292 /* For FMA/ADD, should we add a biased exponent? */
296 /* Union for class-specific information */
298 enum bifrost_minmax_mode minmax
;
299 struct bi_load_vary load_vary
;
300 struct bi_block
*branch_target
;
302 /* For BLEND -- the location 0-7 */
303 unsigned blend_location
;
305 struct bi_bitwise bitwise
;
306 struct bi_texture texture
;
310 /* Represents the assignment of ports for a given bi_bundle */
313 /* Register to assign to each port */
316 /* Read ports can be disabled */
319 /* Should we write FMA? what about ADD? If only a single port is
320 * enabled it is in port 2, else ADD/FMA is 2/3 respectively */
321 bool write_fma
, write_add
;
323 /* Should we read with port 3? */
326 /* Packed uniform/constant */
327 uint8_t uniform_constant
;
329 /* Whether writes are actually for the last instruction */
330 bool first_instruction
;
333 /* A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
334 * leave it NULL; the emitter will fill in a nop. Instructions reference
335 * registers via ports which are assigned per bundle.
347 struct list_head link
;
349 /* Link back up for branch calculations */
350 struct bi_block
*block
;
352 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
353 * can be 8 bundles. */
355 unsigned bundle_count
;
356 bi_bundle bundles
[8];
358 /* For scoreboarding -- the clause ID (this is not globally unique!)
359 * and its dependencies in terms of other clauses, computed during
360 * scheduling and used when emitting code. Dependencies expressed as a
361 * bitfield matching the hardware, except shifted by a clause (the
362 * shift back to the ISA's off-by-one encoding is worked out when
363 * emitting clauses) */
364 unsigned scoreboard_id
;
365 uint8_t dependencies
;
367 /* Back-to-back corresponds directly to the back-to-back bit. Branch
368 * conditional corresponds to the branch conditional bit except that in
369 * the emitted code it's always set if back-to-bit is, whereas we use
370 * the actual value (without back-to-back so to speak) internally */
372 bool branch_conditional
;
374 /* Assigned data register */
375 unsigned data_register
;
377 /* Corresponds to the usual bit but shifted by a clause */
378 bool data_register_write_barrier
;
380 /* Constants read by this clause. ISA limit. Must satisfy:
382 * constant_count + bundle_count <= 13
384 * Also implicitly constant_count <= bundle_count since a bundle only
385 * reads a single constant.
387 uint64_t constants
[8];
388 unsigned constant_count
;
390 /* Branches encode a constant offset relative to the program counter
391 * with some magic flags. By convention, if there is a branch, its
392 * constant will be last. Set this flag to indicate this is required.
394 bool branch_constant
;
396 /* What type of high latency instruction is here, basically */
397 unsigned clause_type
;
400 typedef struct bi_block
{
401 pan_block base
; /* must be first */
403 /* If true, uses clauses; if false, uses instructions */
405 struct list_head clauses
; /* list of bi_clause */
410 gl_shader_stage stage
;
411 struct list_head blocks
; /* list of bi_block */
412 struct panfrost_sysvals sysvals
;
415 /* During NIR->BIR */
416 nir_function_impl
*impl
;
417 bi_block
*current_block
;
418 bi_block
*after_block
;
419 bi_block
*break_block
;
420 bi_block
*continue_block
;
422 nir_alu_type
*blend_types
;
424 /* For creating temporaries */
427 /* Analysis results */
430 /* Stats for shader-db */
431 unsigned instruction_count
;
435 static inline bi_instruction
*
436 bi_emit(bi_context
*ctx
, bi_instruction ins
)
438 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
439 memcpy(u
, &ins
, sizeof(ins
));
440 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
444 static inline bi_instruction
*
445 bi_emit_before(bi_context
*ctx
, bi_instruction
*tag
, bi_instruction ins
)
447 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
448 memcpy(u
, &ins
, sizeof(ins
));
449 list_addtail(&u
->link
, &tag
->link
);
454 bi_remove_instruction(bi_instruction
*ins
)
456 list_del(&ins
->link
);
459 /* If high bits are set, instead of SSA/registers, we have specials indexed by
460 * the low bits if necessary.
462 * Fixed register: do not allocate register, do not collect $200.
463 * Uniform: access a uniform register given by low bits.
464 * Constant: access the specified constant (specifies a bit offset / shift)
465 * Zero: special cased to avoid wasting a constant
466 * Passthrough: a bifrost_packed_src to passthrough T/T0/T1
469 #define BIR_INDEX_REGISTER (1 << 31)
470 #define BIR_INDEX_UNIFORM (1 << 30)
471 #define BIR_INDEX_CONSTANT (1 << 29)
472 #define BIR_INDEX_ZERO (1 << 28)
473 #define BIR_INDEX_PASS (1 << 27)
475 /* Keep me synced please so we can check src & BIR_SPECIAL */
477 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
478 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
480 static inline unsigned
481 bi_max_temp(bi_context
*ctx
)
483 unsigned alloc
= MAX2(ctx
->impl
->reg_alloc
, ctx
->impl
->ssa_alloc
);
484 return ((alloc
+ 2 + ctx
->temp_alloc
) << 1);
487 static inline unsigned
488 bi_make_temp(bi_context
*ctx
)
490 return (ctx
->impl
->ssa_alloc
+ 1 + ctx
->temp_alloc
++) << 1;
493 static inline unsigned
494 bi_make_temp_reg(bi_context
*ctx
)
496 return ((ctx
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | PAN_IS_REG
;
499 /* Iterators for Bifrost IR */
501 #define bi_foreach_block(ctx, v) \
502 list_for_each_entry(pan_block, v, &ctx->blocks, link)
504 #define bi_foreach_block_from(ctx, from, v) \
505 list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
507 #define bi_foreach_block_from_rev(ctx, from, v) \
508 list_for_each_entry_from_rev(pan_block, v, from, &ctx->blocks, link)
510 #define bi_foreach_instr_in_block(block, v) \
511 list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
513 #define bi_foreach_instr_in_block_rev(block, v) \
514 list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
516 #define bi_foreach_instr_in_block_safe(block, v) \
517 list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
519 #define bi_foreach_instr_in_block_safe_rev(block, v) \
520 list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
522 #define bi_foreach_instr_in_block_from(block, v, from) \
523 list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
525 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
526 list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
528 #define bi_foreach_clause_in_block(block, v) \
529 list_for_each_entry(bi_clause, v, &(block)->clauses, link)
531 #define bi_foreach_clause_in_block_from(block, v, from) \
532 list_for_each_entry_from(bi_clause, v, from, &(block)->clauses, link)
534 #define bi_foreach_clause_in_block_from_rev(block, v, from) \
535 list_for_each_entry_from_rev(bi_clause, v, from, &(block)->clauses, link)
537 #define bi_foreach_instr_global(ctx, v) \
538 bi_foreach_block(ctx, v_block) \
539 bi_foreach_instr_in_block((bi_block *) v_block, v)
541 #define bi_foreach_instr_global_safe(ctx, v) \
542 bi_foreach_block(ctx, v_block) \
543 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
545 /* Based on set_foreach, expanded with automatic type casts */
547 #define bi_foreach_predecessor(blk, v) \
548 struct set_entry *_entry_##v; \
550 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
551 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
552 _entry_##v != NULL; \
553 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
554 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
556 #define bi_foreach_src(ins, v) \
557 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
559 static inline bi_instruction
*
560 bi_prev_op(bi_instruction
*ins
)
562 return list_last_entry(&(ins
->link
), bi_instruction
, link
);
565 static inline bi_instruction
*
566 bi_next_op(bi_instruction
*ins
)
568 return list_first_entry(&(ins
->link
), bi_instruction
, link
);
571 static inline pan_block
*
572 pan_next_block(pan_block
*block
)
574 return list_first_entry(&(block
->link
), pan_block
, link
);
577 /* Special functions */
579 void bi_emit_fexp2(bi_context
*ctx
, nir_alu_instr
*instr
);
580 void bi_emit_flog2(bi_context
*ctx
, nir_alu_instr
*instr
);
582 /* BIR manipulation */
584 bool bi_has_outmod(bi_instruction
*ins
);
585 bool bi_has_source_mods(bi_instruction
*ins
);
586 bool bi_is_src_swizzled(bi_instruction
*ins
, unsigned s
);
587 bool bi_has_arg(bi_instruction
*ins
, unsigned arg
);
588 uint16_t bi_from_bytemask(uint16_t bytemask
, unsigned bytes
);
589 unsigned bi_get_component_count(bi_instruction
*ins
, signed s
);
590 uint16_t bi_bytemask_of_read_components(bi_instruction
*ins
, unsigned node
);
591 uint64_t bi_get_immediate(bi_instruction
*ins
, unsigned index
);
592 bool bi_writes_component(bi_instruction
*ins
, unsigned comp
);
593 unsigned bi_writemask(bi_instruction
*ins
);
597 void bi_lower_combine(bi_context
*ctx
, bi_block
*block
);
598 bool bi_opt_dead_code_eliminate(bi_context
*ctx
, bi_block
*block
);
599 void bi_schedule(bi_context
*ctx
);
600 void bi_register_allocate(bi_context
*ctx
);
604 void bi_compute_liveness(bi_context
*ctx
);
605 void bi_liveness_ins_update(uint16_t *live
, bi_instruction
*ins
, unsigned max
);
606 void bi_invalidate_liveness(bi_context
*ctx
);
607 bool bi_is_live_after(bi_context
*ctx
, bi_block
*block
, bi_instruction
*start
, int src
);
611 bool bi_can_insert_bundle(bi_clause
*clause
, bool constant
);
612 unsigned bi_clause_quadwords(bi_clause
*clause
);
613 signed bi_block_offset(bi_context
*ctx
, bi_clause
*start
, bi_block
*target
);
617 void bi_pack(bi_context
*ctx
, struct util_dynarray
*emission
);