src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_COMBINE,
  57         BI_CONVERT,
  58         BI_CSEL,
  59         BI_DISCARD,
  60         BI_FMA,
  61         BI_FMOV,
  62         BI_FREXP,
  63         BI_IMATH,
  64         BI_LOAD,
  65         BI_LOAD_UNIFORM,
  66         BI_LOAD_ATTR,
  67         BI_LOAD_VAR,
  68         BI_LOAD_VAR_ADDRESS,
  69         BI_MINMAX,
  70         BI_MOV,
  71         BI_REDUCE_FMA,
  72         BI_SELECT,
  73         BI_SHIFT,
  74         BI_STORE,
  75         BI_STORE_VAR,
  76         BI_SPECIAL, /* _FAST on supported GPUs */
  77         BI_TABLE,
  78         BI_TEX,
  79         BI_ROUND,
  80         BI_NUM_CLASSES
  81 };
  82
  83 /* Properties of a class... */
  84 extern unsigned bi_class_props[BI_NUM_CLASSES];
  85
  86 /* abs/neg/outmod valid for a float op */
  87 #define BI_MODS (1 << 0)
  88
  89 /* Accepts a bi_cond */
  90 #define BI_CONDITIONAL (1 << 1)
  91
  92 /* Accepts a bifrost_roundmode */
  93 #define BI_ROUNDMODE (1 << 2)
  94
  95 /* Can be scheduled to FMA */
  96 #define BI_SCHED_FMA (1 << 3)
  97
  98 /* Can be scheduled to ADD */
  99 #define BI_SCHED_ADD (1 << 4)
 100
 101 /* Most ALU ops can do either, actually */
 102 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 103
 104 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 105  * nopped out. Used for _FAST operations. */
 106 #define BI_SCHED_SLOW (1 << 5)
 107
 108 /* Swizzling allowed for the 8/16-bit source */
 109 #define BI_SWIZZLABLE (1 << 6)
 110
 111 /* For scheduling purposes this is a high latency instruction and must be at
 112  * the end of a clause. Implies ADD */
 113 #define BI_SCHED_HI_LATENCY (1 << 7)
 114
 115 /* Intrinsic is vectorized and acts with `vector_channels` components */
 116 #define BI_VECTOR (1 << 8)
 117
 118 /* Use a data register for src0/dest respectively, bypassing the usual
 119  * register accessor. Mutually exclusive. */
 120 #define BI_DATA_REG_SRC (1 << 9)
 121 #define BI_DATA_REG_DEST (1 << 10)
 122
 123 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
 124 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
 125
 126 /* It can't get any worse than csel4... can it? */
 127 #define BIR_SRC_COUNT 4
 128
 129 /* BI_LD_VARY */
 130 struct bi_load_vary {
 131         enum bifrost_interp_mode interp_mode;
 132         bool reuse;
 133         bool flat;
 134 };
 135
 136 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 137  * the target. We forward declare bi_block since this is mildly circular (not
 138  * strictly, but this order of the file makes more sense I think)
 139  *
 140  * We define our own enum of conditions since the conditions in the hardware
 141  * packed in crazy ways that would make manipulation unweildly (meaning changes
 142  * based on port swapping, etc), so we defer dealing with that until emit time.
 143  * Likewise, we expose NIR types instead of the crazy branch types, although
 144  * the restrictions do eventually apply of course. */
 145
 146 struct bi_block;
 147
 148 enum bi_cond {
 149         BI_COND_ALWAYS,
 150         BI_COND_LT,
 151         BI_COND_LE,
 152         BI_COND_GE,
 153         BI_COND_GT,
 154         BI_COND_EQ,
 155         BI_COND_NE,
 156 };
 157
 158 /* Opcodes within a class */
 159 enum bi_minmax_op {
 160         BI_MINMAX_MIN,
 161         BI_MINMAX_MAX
 162 };
 163
 164 enum bi_bitwise_op {
 165         BI_BITWISE_AND,
 166         BI_BITWISE_OR,
 167         BI_BITWISE_XOR
 168 };
 169
 170 enum bi_imath_op {
 171         BI_IMATH_ADD,
 172         BI_IMATH_SUB,
 173 };
 174
 175 enum bi_table_op {
 176         /* fp32 log2() with low precision, suitable for GL or half_log2() in
 177          * CL. In the first argument, takes x. Letting u be such that x =
 178          * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
 179          * log2(u) / (u - 1). */
 180
 181         BI_TABLE_LOG2_U_OVER_U_1_LOW,
 182 };
 183
 184 enum bi_reduce_op {
 185         /* Takes two fp32 arguments and returns x + frexp(y). Used in
 186          * low-precision log2 argument reduction on newer models. */
 187
 188         BI_REDUCE_ADD_FREXPM,
 189 };
 190
 191 enum bi_frexp_op {
 192         BI_FREXPE_LOG,
 193 };
 194
 195 enum bi_special_op {
 196         BI_SPECIAL_FRCP,
 197         BI_SPECIAL_FRSQ,
 198
 199         /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
 200          * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
 201          * the second, it takes x itself. */
 202         BI_SPECIAL_EXP2_LOW,
 203 };
 204
 205 enum bi_tex_op {
 206         BI_TEX_NORMAL,
 207         BI_TEX_COMPACT,
 208         BI_TEX_DUAL
 209 };
 210
 211 struct bi_bitwise {
 212         bool src_invert[2];
 213         bool rshift; /* false for lshift */
 214 };
 215
 216 struct bi_texture {
 217         /* Constant indices. Indirect would need to be in src[..] like normal,
 218          * we can reserve some sentinels there for that for future. */
 219         unsigned texture_index, sampler_index;
 220 };
 221
 222 typedef struct {
 223         struct list_head link; /* Must be first */
 224         enum bi_class type;
 225
 226         /* Indices, see pan_ssa_index etc. Note zero is special cased
 227          * to "no argument" */
 228         unsigned dest;
 229         unsigned src[BIR_SRC_COUNT];
 230
 231         /* 32-bit word offset for destination, added to the register number in
 232          * RA when lowering combines */
 233         unsigned dest_offset;
 234
 235         /* If one of the sources has BIR_INDEX_CONSTANT */
 236         union {
 237                 uint64_t u64;
 238                 uint32_t u32;
 239                 uint16_t u16[2];
 240                 uint8_t u8[4];
 241         } constant;
 242
 243         /* Floating-point modifiers, type/class permitting. If not
 244          * allowed for the type/class, these are ignored. */
 245         enum bifrost_outmod outmod;
 246         bool src_abs[BIR_SRC_COUNT];
 247         bool src_neg[BIR_SRC_COUNT];
 248
 249         /* Round mode (requires BI_ROUNDMODE) */
 250         enum bifrost_roundmode roundmode;
 251
 252         /* Destination type. Usually the type of the instruction
 253          * itself, but if sources and destination have different
 254          * types, the type of the destination wins (so f2i would be
 255          * int). Zero if there is no destination. Bitsize included */
 256         nir_alu_type dest_type;
 257
 258         /* Source types if required by the class */
 259         nir_alu_type src_types[BIR_SRC_COUNT];
 260
 261         /* If the source type is 8-bit or 16-bit such that SIMD is possible,
 262          * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
 263          * sense. On non-SIMD instructions, it can be used for component
 264          * selection, so we don't have to special case extraction. */
 265         uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
 266
 267         /* For VECTOR ops, how many channels are written? */
 268         unsigned vector_channels;
 269
 270         /* The comparison op. BI_COND_ALWAYS may not be valid. */
 271         enum bi_cond cond;
 272
 273         /* A class-specific op from which the actual opcode can be derived
 274          * (along with the above information) */
 275
 276         union {
 277                 enum bi_minmax_op minmax;
 278                 enum bi_bitwise_op bitwise;
 279                 enum bi_special_op special;
 280                 enum bi_reduce_op reduce;
 281                 enum bi_table_op table;
 282                 enum bi_frexp_op frexp;
 283                 enum bi_tex_op texture;
 284                 enum bi_imath_op imath;
 285
 286                 /* For FMA/ADD, should we add a biased exponent? */
 287                 bool mscale;
 288         } op;
 289
 290         /* Union for class-specific information */
 291         union {
 292                 enum bifrost_minmax_mode minmax;
 293                 struct bi_load_vary load_vary;
 294                 struct bi_block *branch_target;
 295
 296                 /* For BLEND -- the location 0-7 */
 297                 unsigned blend_location;
 298
 299                 struct bi_bitwise bitwise;
 300                 struct bi_texture texture;
 301         };
 302 } bi_instruction;
 303
 304 /* Represents the assignment of ports for a given bi_bundle */
 305
 306 typedef struct {
 307         /* Register to assign to each port */
 308         unsigned port[4];
 309
 310         /* Read ports can be disabled */
 311         bool enabled[2];
 312
 313         /* Should we write FMA? what about ADD? If only a single port is
 314          * enabled it is in port 2, else ADD/FMA is 2/3 respectively */
 315         bool write_fma, write_add;
 316
 317         /* Should we read with port 3? */
 318         bool read_port3;
 319
 320         /* Packed uniform/constant */
 321         uint8_t uniform_constant;
 322
 323         /* Whether writes are actually for the last instruction */
 324         bool first_instruction;
 325 } bi_registers;
 326
 327 /* A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 328  * leave it NULL; the emitter will fill in a nop. Instructions reference
 329  * registers via ports which are assigned per bundle.
 330  */
 331
 332 typedef struct {
 333         bi_registers regs;
 334         bi_instruction *fma;
 335         bi_instruction *add;
 336 } bi_bundle;
 337
 338 typedef struct {
 339         struct list_head link;
 340
 341         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 342          * can be 8 bundles. */
 343
 344         unsigned bundle_count;
 345         bi_bundle bundles[8];
 346
 347         /* For scoreboarding -- the clause ID (this is not globally unique!)
 348          * and its dependencies in terms of other clauses, computed during
 349          * scheduling and used when emitting code. Dependencies expressed as a
 350          * bitfield matching the hardware, except shifted by a clause (the
 351          * shift back to the ISA's off-by-one encoding is worked out when
 352          * emitting clauses) */
 353         unsigned scoreboard_id;
 354         uint8_t dependencies;
 355
 356         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 357          * conditional corresponds to the branch conditional bit except that in
 358          * the emitted code it's always set if back-to-bit is, whereas we use
 359          * the actual value (without back-to-back so to speak) internally */
 360         bool back_to_back;
 361         bool branch_conditional;
 362
 363         /* Assigned data register */
 364         unsigned data_register;
 365
 366         /* Corresponds to the usual bit but shifted by a clause */
 367         bool data_register_write_barrier;
 368
 369         /* Constants read by this clause. ISA limit. Must satisfy:
 370          *
 371          *      constant_count + bundle_count <= 13
 372          *
 373          * Also implicitly constant_count <= bundle_count since a bundle only
 374          * reads a single constant.
 375          */
 376         uint64_t constants[8];
 377         unsigned constant_count;
 378
 379         /* What type of high latency instruction is here, basically */
 380         unsigned clause_type;
 381 } bi_clause;
 382
 383 typedef struct bi_block {
 384         pan_block base; /* must be first */
 385
 386         /* If true, uses clauses; if false, uses instructions */
 387         bool scheduled;
 388         struct list_head clauses; /* list of bi_clause */
 389 } bi_block;
 390
 391 typedef struct {
 392        nir_shader *nir;
 393        gl_shader_stage stage;
 394        struct list_head blocks; /* list of bi_block */
 395        struct panfrost_sysvals sysvals;
 396        uint32_t quirks;
 397
 398        /* During NIR->BIR */
 399        nir_function_impl *impl;
 400        bi_block *current_block;
 401        unsigned block_name_count;
 402        bi_block *after_block;
 403        bi_block *break_block;
 404        bi_block *continue_block;
 405        bool emitted_atest;
 406        nir_alu_type *blend_types;
 407
 408        /* For creating temporaries */
 409        unsigned temp_alloc;
 410
 411        /* Analysis results */
 412        bool has_liveness;
 413
 414        /* Stats for shader-db */
 415        unsigned instruction_count;
 416        unsigned loop_count;
 417 } bi_context;
 418
 419 static inline bi_instruction *
 420 bi_emit(bi_context *ctx, bi_instruction ins)
 421 {
 422         bi_instruction *u = rzalloc(ctx, bi_instruction);
 423         memcpy(u, &ins, sizeof(ins));
 424         list_addtail(&u->link, &ctx->current_block->base.instructions);
 425         return u;
 426 }
 427
 428 static inline bi_instruction *
 429 bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
 430 {
 431         bi_instruction *u = rzalloc(ctx, bi_instruction);
 432         memcpy(u, &ins, sizeof(ins));
 433         list_addtail(&u->link, &tag->link);
 434         return u;
 435 }
 436
 437 static inline void
 438 bi_remove_instruction(bi_instruction *ins)
 439 {
 440         list_del(&ins->link);
 441 }
 442
 443 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 444  * the low bits if necessary.
 445  *
 446  *  Fixed register: do not allocate register, do not collect $200.
 447  *  Uniform: access a uniform register given by low bits.
 448  *  Constant: access the specified constant (specifies a bit offset / shift)
 449  *  Zero: special cased to avoid wasting a constant
 450  *  Passthrough: a bifrost_packed_src to passthrough T/T0/T1
 451  */
 452
 453 #define BIR_INDEX_REGISTER (1 << 31)
 454 #define BIR_INDEX_UNIFORM  (1 << 30)
 455 #define BIR_INDEX_CONSTANT (1 << 29)
 456 #define BIR_INDEX_ZERO     (1 << 28)
 457 #define BIR_INDEX_PASS     (1 << 27)
 458
 459 /* Keep me synced please so we can check src & BIR_SPECIAL */
 460
 461 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 462         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
 463
 464 static inline unsigned
 465 bi_max_temp(bi_context *ctx)
 466 {
 467         unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
 468         return ((alloc + 2 + ctx->temp_alloc) << 1);
 469 }
 470
 471 static inline unsigned
 472 bi_make_temp(bi_context *ctx)
 473 {
 474         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 475 }
 476
 477 static inline unsigned
 478 bi_make_temp_reg(bi_context *ctx)
 479 {
 480         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 481 }
 482
 483 /* Iterators for Bifrost IR */
 484
 485 #define bi_foreach_block(ctx, v) \
 486         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 487
 488 #define bi_foreach_block_from(ctx, from, v) \
 489         list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
 490
 491 #define bi_foreach_instr_in_block(block, v) \
 492         list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
 493
 494 #define bi_foreach_instr_in_block_rev(block, v) \
 495         list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
 496
 497 #define bi_foreach_instr_in_block_safe(block, v) \
 498         list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
 499
 500 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 501         list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
 502
 503 #define bi_foreach_instr_in_block_from(block, v, from) \
 504         list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
 505
 506 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 507         list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
 508
 509 #define bi_foreach_clause_in_block(block, v) \
 510         list_for_each_entry(bi_clause, v, &(block)->clauses, link)
 511
 512 #define bi_foreach_instr_global(ctx, v) \
 513         bi_foreach_block(ctx, v_block) \
 514                 bi_foreach_instr_in_block((bi_block *) v_block, v)
 515
 516 #define bi_foreach_instr_global_safe(ctx, v) \
 517         bi_foreach_block(ctx, v_block) \
 518                 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
 519
 520 /* Based on set_foreach, expanded with automatic type casts */
 521
 522 #define bi_foreach_predecessor(blk, v) \
 523         struct set_entry *_entry_##v; \
 524         bi_block *v; \
 525         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 526                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 527                 _entry_##v != NULL; \
 528                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 529                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 530
 531 #define bi_foreach_src(ins, v) \
 532         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 533
 534 static inline bi_instruction *
 535 bi_prev_op(bi_instruction *ins)
 536 {
 537         return list_last_entry(&(ins->link), bi_instruction, link);
 538 }
 539
 540 static inline bi_instruction *
 541 bi_next_op(bi_instruction *ins)
 542 {
 543         return list_first_entry(&(ins->link), bi_instruction, link);
 544 }
 545
 546 static inline pan_block *
 547 pan_next_block(pan_block *block)
 548 {
 549         return list_first_entry(&(block->link), pan_block, link);
 550 }
 551
 552 /* Special functions */
 553
 554 void bi_emit_fexp2(bi_context *ctx, nir_alu_instr *instr);
 555 void bi_emit_flog2(bi_context *ctx, nir_alu_instr *instr);
 556
 557 /* BIR manipulation */
 558
 559 bool bi_has_outmod(bi_instruction *ins);
 560 bool bi_has_source_mods(bi_instruction *ins);
 561 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 562 bool bi_has_arg(bi_instruction *ins, unsigned arg);
 563 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
 564 unsigned bi_get_component_count(bi_instruction *ins, signed s);
 565 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
 566 uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
 567 bool bi_writes_component(bi_instruction *ins, unsigned comp);
 568 unsigned bi_writemask(bi_instruction *ins);
 569
 570 /* BIR passes */
 571
 572 void bi_lower_combine(bi_context *ctx, bi_block *block);
 573 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
 574 void bi_schedule(bi_context *ctx);
 575 void bi_register_allocate(bi_context *ctx);
 576
 577 /* Liveness */
 578
 579 void bi_compute_liveness(bi_context *ctx);
 580 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
 581 void bi_invalidate_liveness(bi_context *ctx);
 582 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
 583
 584 /* Layout */
 585
 586 bool bi_can_insert_bundle(bi_clause *clause, bool constant);
 587
 588 /* Code emit */
 589
 590 void bi_pack(bi_context *ctx, struct util_dynarray *emission);
 591
 592 #endif