2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
32 #include "panfrost/util/pan_ir.h"
34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
35 * ADD with two completely different opcodes, and opcodes can be varying
36 * length in some cases. Then we have different opcodes for int vs float
37 * and then sometimes even for different typesizes. Further, virtually
38 * every op has a number of flags which depend on the op. In constrast
39 * to Midgard where you have a strict ALU/LDST/TEX division and within
40 * ALU you have strict int/float and that's it... here it's a *lot* more
41 * involved. As such, we use something much higher level for our IR,
42 * encoding "classes" of operations, letting the opcode details get
43 * sorted out at emit time.
45 * Please keep this list alphabetized. Please use a dictionary if you
46 * don't know how to do that.
72 BI_SPECIAL
, /* _FAST, _TABLE on supported GPUs */
79 /* Properties of a class... */
80 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
82 /* abs/neg/outmod valid for a float op */
83 #define BI_MODS (1 << 0)
85 /* Generic enough that little class-specific information is required. In other
86 * words, it acts as a "normal" ALU op, even if the encoding ends up being
87 * irregular enough to warrant a separate class */
88 #define BI_GENERIC (1 << 1)
90 /* Accepts a bifrost_roundmode */
91 #define BI_ROUNDMODE (1 << 2)
93 /* Can be scheduled to FMA */
94 #define BI_SCHED_FMA (1 << 3)
96 /* Can be scheduled to ADD */
97 #define BI_SCHED_ADD (1 << 4)
99 /* Most ALU ops can do either, actually */
100 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
102 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
103 * nopped out. Used for _FAST operations. */
104 #define BI_SCHED_SLOW (1 << 5)
106 /* Swizzling allowed for the 8/16-bit source */
107 #define BI_SWIZZLABLE (1 << 6)
109 /* For scheduling purposes this is a high latency instruction and must be at
110 * the end of a clause. Implies ADD */
111 #define BI_SCHED_HI_LATENCY ((1 << 7) | BI_SCHED_ADD)
113 /* Intrinsic is vectorized and should read 4 components regardless of writemask */
114 #define BI_VECTOR (1 << 8)
116 /* Use a data register for src0/dest respectively, bypassing the usual
117 * register accessor. Mutually exclusive. */
118 #define BI_DATA_REG_SRC (1 << 9)
119 #define BI_DATA_REG_DEST (1 << 10)
121 /* It can't get any worse than csel4... can it? */
122 #define BIR_SRC_COUNT 4
125 struct bi_load_vary
{
126 enum bifrost_interp_mode interp_mode
;
131 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
132 * the target. We forward declare bi_block since this is mildly circular (not
133 * strictly, but this order of the file makes more sense I think)
135 * We define our own enum of conditions since the conditions in the hardware
136 * packed in crazy ways that would make manipulation unweildly (meaning changes
137 * based on port swapping, etc), so we defer dealing with that until emit time.
138 * Likewise, we expose NIR types instead of the crazy branch types, although
139 * the restrictions do eventually apply of course. */
154 /* Types are specified in src_types and must be compatible (either both
155 * int, or both float, 16/32, and same size or 32/16 if float. Types
156 * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
159 struct bi_block
*target
;
162 /* Opcodes within a class */
175 BI_ROUND_MODE
, /* use round mode */
176 BI_ROUND_ROUND
/* i.e.: fround() */
191 struct list_head link
; /* Must be first */
194 /* Indices, see bir_ssa_index etc. Note zero is special cased
195 * to "no argument" */
197 unsigned src
[BIR_SRC_COUNT
];
199 /* If one of the sources has BIR_INDEX_CONSTANT */
207 /* Floating-point modifiers, type/class permitting. If not
208 * allowed for the type/class, these are ignored. */
209 enum bifrost_outmod outmod
;
210 bool src_abs
[BIR_SRC_COUNT
];
211 bool src_neg
[BIR_SRC_COUNT
];
213 /* Round mode (requires BI_ROUNDMODE) */
214 enum bifrost_roundmode roundmode
;
216 /* Writemask (bit for each affected byte). This is quite restricted --
217 * ALU ops can only write to a single channel (exception: <32 in which
218 * you can write to 32/N contiguous aligned channels). Load/store can
219 * only write to all channels at once, in a sense. But it's still
220 * better to use this generic form than have synthetic ops flying
221 * about, since we're not essentially vector for RA purposes. */
224 /* Destination type. Usually the type of the instruction
225 * itself, but if sources and destination have different
226 * types, the type of the destination wins (so f2i would be
227 * int). Zero if there is no destination. Bitsize included */
228 nir_alu_type dest_type
;
230 /* Source types if required by the class */
231 nir_alu_type src_types
[BIR_SRC_COUNT
];
233 /* If the source type is 8-bit or 16-bit such that SIMD is possible,
234 * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
235 * sense. On non-SIMD instructions, it can be used for component
236 * selection, so we don't have to special case extraction. */
237 uint8_t swizzle
[BIR_SRC_COUNT
][NIR_MAX_VEC_COMPONENTS
];
239 /* A class-specific op from which the actual opcode can be derived
240 * (along with the above information) */
243 enum bi_minmax_op minmax
;
244 enum bi_bitwise_op bitwise
;
245 enum bi_round_op round
;
246 enum bi_special_op special
;
247 enum bi_cond compare
;
250 /* Union for class-specific information */
252 enum bifrost_minmax_mode minmax
;
253 struct bi_load_vary load_vary
;
254 struct bi_branch branch
;
256 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
257 * sense here but you can always just use a move for that */
258 enum bi_cond csel_cond
;
260 /* For BLEND -- the location 0-7 */
261 unsigned blend_location
;
265 /* Scheduling takes place in two steps. Step 1 groups instructions within a
266 * block into distinct clauses (bi_clause). Step 2 schedules instructions
267 * within a clause into FMA/ADD pairs (bi_bundle).
269 * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
270 * leave it NULL; the emitter will fill in a nop.
279 struct list_head link
;
281 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
282 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
283 * so a clause can have up to 16 bi_instructions. Whether bundles or
284 * instructions are used depends on where in scheduling we are. */
286 unsigned instruction_count
;
287 unsigned bundle_count
;
290 bi_instruction
*instructions
[16];
291 bi_bundle bundles
[8];
294 /* For scoreboarding -- the clause ID (this is not globally unique!)
295 * and its dependencies in terms of other clauses, computed during
296 * scheduling and used when emitting code. Dependencies expressed as a
297 * bitfield matching the hardware, except shifted by a clause (the
298 * shift back to the ISA's off-by-one encoding is worked out when
299 * emitting clauses) */
300 unsigned scoreboard_id
;
301 uint8_t dependencies
;
303 /* Back-to-back corresponds directly to the back-to-back bit. Branch
304 * conditional corresponds to the branch conditional bit except that in
305 * the emitted code it's always set if back-to-bit is, whereas we use
306 * the actual value (without back-to-back so to speak) internally */
308 bool branch_conditional
;
310 /* Assigned data register */
311 unsigned data_register
;
313 /* Corresponds to the usual bit but shifted by a clause */
314 bool data_register_write_barrier
;
316 /* Constants read by this clause. ISA limit. */
317 uint64_t constants
[8];
318 unsigned constant_count
;
320 /* What type of high latency instruction is here, basically */
321 unsigned clause_type
;
324 typedef struct bi_block
{
325 pan_block base
; /* must be first */
327 /* If true, uses clauses; if false, uses instructions */
329 struct list_head clauses
; /* list of bi_clause */
334 gl_shader_stage stage
;
335 struct list_head blocks
; /* list of bi_block */
336 struct panfrost_sysvals sysvals
;
339 /* During NIR->BIR */
340 nir_function_impl
*impl
;
341 bi_block
*current_block
;
342 unsigned block_name_count
;
343 bi_block
*after_block
;
344 bi_block
*break_block
;
345 bi_block
*continue_block
;
348 /* For creating temporaries */
351 /* Analysis results */
354 /* Stats for shader-db */
355 unsigned instruction_count
;
359 static inline bi_instruction
*
360 bi_emit(bi_context
*ctx
, bi_instruction ins
)
362 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
363 memcpy(u
, &ins
, sizeof(ins
));
364 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
369 bi_remove_instruction(bi_instruction
*ins
)
371 list_del(&ins
->link
);
374 /* So we can distinguish between SSA/reg/sentinel quickly */
375 #define BIR_NO_ARG (0)
376 #define BIR_IS_REG (1)
378 /* If high bits are set, instead of SSA/registers, we have specials indexed by
379 * the low bits if necessary.
381 * Fixed register: do not allocate register, do not collect $200.
382 * Uniform: access a uniform register given by low bits.
383 * Constant: access the specified constant
384 * Zero: special cased to avoid wasting a constant
385 * Passthrough: a bifrost_packed_src to passthrough T/T0/T1
388 #define BIR_INDEX_REGISTER (1 << 31)
389 #define BIR_INDEX_UNIFORM (1 << 30)
390 #define BIR_INDEX_CONSTANT (1 << 29)
391 #define BIR_INDEX_ZERO (1 << 28)
392 #define BIR_INDEX_PASS (1 << 27)
394 /* Keep me synced please so we can check src & BIR_SPECIAL */
396 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
397 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
399 static inline unsigned
400 bi_max_temp(bi_context
*ctx
)
402 unsigned alloc
= MAX2(ctx
->impl
->reg_alloc
, ctx
->impl
->ssa_alloc
);
403 return ((alloc
+ 2 + ctx
->temp_alloc
) << 1);
406 static inline unsigned
407 bi_make_temp(bi_context
*ctx
)
409 return (ctx
->impl
->ssa_alloc
+ 1 + ctx
->temp_alloc
++) << 1;
412 static inline unsigned
413 bi_make_temp_reg(bi_context
*ctx
)
415 return ((ctx
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | BIR_IS_REG
;
418 static inline unsigned
419 bir_ssa_index(nir_ssa_def
*ssa
)
421 /* Off-by-one ensures BIR_NO_ARG is skipped */
422 return ((ssa
->index
+ 1) << 1) | 0;
425 static inline unsigned
426 bir_src_index(nir_src
*src
)
429 return bir_ssa_index(src
->ssa
);
431 assert(!src
->reg
.indirect
);
432 return (src
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
436 static inline unsigned
437 bir_dest_index(nir_dest
*dst
)
440 return bir_ssa_index(&dst
->ssa
);
442 assert(!dst
->reg
.indirect
);
443 return (dst
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
447 /* Iterators for Bifrost IR */
449 #define bi_foreach_block(ctx, v) \
450 list_for_each_entry(pan_block, v, &ctx->blocks, link)
452 #define bi_foreach_block_from(ctx, from, v) \
453 list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
455 #define bi_foreach_instr_in_block(block, v) \
456 list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
458 #define bi_foreach_instr_in_block_rev(block, v) \
459 list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
461 #define bi_foreach_instr_in_block_safe(block, v) \
462 list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
464 #define bi_foreach_instr_in_block_safe_rev(block, v) \
465 list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
467 #define bi_foreach_instr_in_block_from(block, v, from) \
468 list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
470 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
471 list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
473 #define bi_foreach_clause_in_block(block, v) \
474 list_for_each_entry(bi_clause, v, &(block)->clauses, link)
476 #define bi_foreach_instr_global(ctx, v) \
477 bi_foreach_block(ctx, v_block) \
478 bi_foreach_instr_in_block((bi_block *) v_block, v)
480 #define bi_foreach_instr_global_safe(ctx, v) \
481 bi_foreach_block(ctx, v_block) \
482 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
484 /* Based on set_foreach, expanded with automatic type casts */
486 #define bi_foreach_predecessor(blk, v) \
487 struct set_entry *_entry_##v; \
489 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
490 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
491 _entry_##v != NULL; \
492 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
493 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
495 #define bi_foreach_src(ins, v) \
496 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
498 static inline bi_instruction
*
499 bi_prev_op(bi_instruction
*ins
)
501 return list_last_entry(&(ins
->link
), bi_instruction
, link
);
504 static inline bi_instruction
*
505 bi_next_op(bi_instruction
*ins
)
507 return list_first_entry(&(ins
->link
), bi_instruction
, link
);
510 static inline pan_block
*
511 pan_next_block(pan_block
*block
)
513 return list_first_entry(&(block
->link
), pan_block
, link
);
516 /* BIR manipulation */
518 bool bi_has_outmod(bi_instruction
*ins
);
519 bool bi_has_source_mods(bi_instruction
*ins
);
520 bool bi_is_src_swizzled(bi_instruction
*ins
, unsigned s
);
521 bool bi_has_arg(bi_instruction
*ins
, unsigned arg
);
522 uint16_t bi_from_bytemask(uint16_t bytemask
, unsigned bytes
);
523 unsigned bi_get_component_count(bi_instruction
*ins
);
524 uint16_t bi_bytemask_of_read_components(bi_instruction
*ins
, unsigned node
);
528 bool bi_opt_dead_code_eliminate(bi_context
*ctx
, bi_block
*block
);
529 void bi_schedule(bi_context
*ctx
);
530 void bi_register_allocate(bi_context
*ctx
);
534 void bi_compute_liveness(bi_context
*ctx
);
535 void bi_liveness_ins_update(uint16_t *live
, bi_instruction
*ins
, unsigned max
);
536 void bi_invalidate_liveness(bi_context
*ctx
);
537 bool bi_is_live_after(bi_context
*ctx
, bi_block
*block
, bi_instruction
*start
, int src
);
541 void bi_pack(bi_context
*ctx
, struct util_dynarray
*emission
);