2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
33 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
34 * ADD with two completely different opcodes, and opcodes can be varying
35 * length in some cases. Then we have different opcodes for int vs float
36 * and then sometimes even for different typesizes. Further, virtually
37 * every op has a number of flags which depend on the op. In constrast
38 * to Midgard where you have a strict ALU/LDST/TEX division and within
39 * ALU you have strict int/float and that's it... here it's a *lot* more
40 * involved. As such, we use something much higher level for our IR,
41 * encoding "classes" of operations, letting the opcode details get
42 * sorted out at emit time.
44 * Please keep this list alphabetized. Please use a dictionary if you
45 * don't know how to do that.
71 BI_SPECIAL
, /* _FAST, _TABLE on supported GPUs */
78 /* Properties of a class... */
79 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
81 /* abs/neg/outmod valid for a float op */
82 #define BI_MODS (1 << 0)
84 /* Generic enough that little class-specific information is required. In other
85 * words, it acts as a "normal" ALU op, even if the encoding ends up being
86 * irregular enough to warrant a separate class */
87 #define BI_GENERIC (1 << 1)
89 /* Accepts a bifrost_roundmode */
90 #define BI_ROUNDMODE (1 << 2)
92 /* Can be scheduled to FMA */
93 #define BI_SCHED_FMA (1 << 3)
95 /* Can be scheduled to ADD */
96 #define BI_SCHED_ADD (1 << 4)
98 /* Most ALU ops can do either, actually */
99 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
101 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
102 * nopped out. Used for _FAST operations. */
103 #define BI_SCHED_SLOW (1 << 5)
105 /* Swizzling allowed for the 8/16-bit source */
106 #define BI_SWIZZLABLE (1 << 6)
108 /* It can't get any worse than csel4... can it? */
109 #define BIR_SRC_COUNT 4
111 /* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
113 /* Note: no indirects here */
116 /* Only for BI_LD_ATTR. But number of vector channels */
121 struct bi_load_vary
{
122 /* All parameters used here. Indirect location specified in
123 * src1 and ignoring location, if present. */
126 enum bifrost_interp_mode interp_mode
;
131 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
132 * the target. We forward declare bi_block since this is mildly circular (not
133 * strictly, but this order of the file makes more sense I think)
135 * We define our own enum of conditions since the conditions in the hardware
136 * packed in crazy ways that would make manipulation unweildly (meaning changes
137 * based on port swapping, etc), so we defer dealing with that until emit time.
138 * Likewise, we expose NIR types instead of the crazy branch types, although
139 * the restrictions do eventually apply of course. */
154 /* Types are specified in src_types and must be compatible (either both
155 * int, or both float, 16/32, and same size or 32/16 if float. Types
156 * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
159 struct bi_block
*target
;
162 /* Opcodes within a class */
175 BI_ROUND_MODE
, /* use round mode */
176 BI_ROUND_ROUND
/* i.e.: fround() */
180 struct list_head link
; /* Must be first */
183 /* Indices, see bir_ssa_index etc. Note zero is special cased
184 * to "no argument" */
186 unsigned src
[BIR_SRC_COUNT
];
188 /* If one of the sources has BIR_INDEX_CONSTANT... Also, for
189 * BI_EXTRACT, the component index is stored here. */
197 /* Floating-point modifiers, type/class permitting. If not
198 * allowed for the type/class, these are ignored. */
199 enum bifrost_outmod outmod
;
200 bool src_abs
[BIR_SRC_COUNT
];
201 bool src_neg
[BIR_SRC_COUNT
];
203 /* Round mode (requires BI_ROUNDMODE) */
204 enum bifrost_roundmode roundmode
;
206 /* Destination type. Usually the type of the instruction
207 * itself, but if sources and destination have different
208 * types, the type of the destination wins (so f2i would be
209 * int). Zero if there is no destination. Bitsize included */
210 nir_alu_type dest_type
;
212 /* Source types if required by the class */
213 nir_alu_type src_types
[BIR_SRC_COUNT
];
215 /* If the source type is 8-bit or 16-bit such that SIMD is possible, and
216 * the class has BI_SWIZZLABLE, this is a swizzle for the input. Swizzles
217 * in practice only occur with one-source arguments (conversions,
218 * dedicated swizzle ops) and as component selection on two-sources
219 * where it is unambiguous which is which. Bounds are 32/type_size. */
222 /* A class-specific op from which the actual opcode can be derived
223 * (along with the above information) */
226 enum bi_minmax_op minmax
;
227 enum bi_bitwise_op bitwise
;
228 enum bi_round_op round
;
231 /* Union for class-specific information */
233 enum bifrost_minmax_mode minmax
;
235 struct bi_load_vary load_vary
;
236 struct bi_branch branch
;
240 /* Scheduling takes place in two steps. Step 1 groups instructions within a
241 * block into distinct clauses (bi_clause). Step 2 schedules instructions
242 * within a clause into FMA/ADD pairs (bi_bundle).
244 * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
245 * leave it NULL; the emitter will fill in a nop.
254 struct list_head link
;
256 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
257 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
258 * so a clause can have up to 16 bi_instructions. Whether bundles or
259 * instructions are used depends on where in scheduling we are. */
261 unsigned instruction_count
;
262 unsigned bundle_count
;
265 bi_instruction
*instructions
[16];
266 bi_bundle bundles
[8];
269 /* For scoreboarding -- the clause ID (this is not globally unique!)
270 * and its dependencies in terms of other clauses, computed during
271 * scheduling and used when emitting code. Dependencies expressed as a
272 * bitfield matching the hardware, except shifted by a clause (the
273 * shift back to the ISA's off-by-one encoding is worked out when
274 * emitting clauses) */
275 unsigned scoreboard_id
;
276 uint8_t dependencies
;
278 /* Back-to-back corresponds directly to the back-to-back bit. Branch
279 * conditional corresponds to the branch conditional bit except that in
280 * the emitted code it's always set if back-to-bit is, whereas we use
281 * the actual value (without back-to-back so to speak) internally */
283 bool branch_conditional
;
285 /* Corresponds to the usual bit but shifted by a clause */
286 bool data_register_write_barrier
;
288 /* Constants read by this clause. ISA limit. */
289 uint64_t constants
[8];
290 unsigned constant_count
;
293 typedef struct bi_block
{
294 struct list_head link
; /* must be first */
295 unsigned name
; /* Just for pretty-printing */
297 /* If true, uses clauses; if false, uses instructions */
301 struct list_head instructions
; /* pre-schedule, list of bi_instructions */
302 struct list_head clauses
; /* list of bi_clause */
305 /* Control flow graph */
306 struct set
*predecessors
;
307 struct bi_block
*successors
[2];
312 struct list_head blocks
; /* list of bi_block */
315 /* So we can distinguish between SSA/reg/sentinel quickly */
316 #define BIR_NO_ARG (0)
317 #define BIR_IS_REG (1)
319 /* If high bits are set, instead of SSA/registers, we have specials indexed by
320 * the low bits if necessary.
322 * Fixed register: do not allocate register, do not collect $200.
323 * Uniform: access a uniform register given by low bits.
324 * Constant: access the specified constant
325 * Zero: special cased to avoid wasting a constant
328 #define BIR_INDEX_REGISTER (1 << 31)
329 #define BIR_INDEX_UNIFORM (1 << 30)
330 #define BIR_INDEX_CONSTANT (1 << 29)
331 #define BIR_INDEX_ZERO (1 << 28)
333 /* Keep me synced please so we can check src & BIR_SPECIAL */
335 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
336 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
338 static inline unsigned
339 bir_ssa_index(nir_ssa_def
*ssa
)
341 /* Off-by-one ensures BIR_NO_ARG is skipped */
342 return ((ssa
->index
+ 1) << 1) | 0;
345 static inline unsigned
346 bir_src_index(nir_src
*src
)
349 return bir_ssa_index(src
->ssa
);
351 assert(!src
->reg
.indirect
);
352 return (src
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
356 static inline unsigned
357 bir_dest_index(nir_dest
*dst
)
360 return bir_ssa_index(&dst
->ssa
);
362 assert(!dst
->reg
.indirect
);
363 return (dst
->reg
.reg
->index
<< 1) | BIR_IS_REG
;