2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
33 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
34 * ADD with two completely different opcodes, and opcodes can be varying
35 * length in some cases. Then we have different opcodes for int vs float
36 * and then sometimes even for different typesizes. Further, virtually
37 * every op has a number of flags which depend on the op. In constrast
38 * to Midgard where you have a strict ALU/LDST/TEX division and within
39 * ALU you have strict int/float and that's it... here it's a *lot* more
40 * involved. As such, we use something much higher level for our IR,
41 * encoding "classes" of operations, letting the opcode details get
42 * sorted out at emit time.
44 * Please keep this list alphabetized. Please use a dictionary if you
45 * don't know how to do that.
71 BI_SPECIAL
, /* _FAST, _TABLE on supported GPUs */
78 /* Properties of a class... */
79 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
81 /* abs/neg/outmod valid for a float op */
82 #define BI_MODS (1 << 0)
84 /* Generic enough that little class-specific information is required. In other
85 * words, it acts as a "normal" ALU op, even if the encoding ends up being
86 * irregular enough to warrant a separate class */
87 #define BI_GENERIC (1 << 1)
89 /* Accepts a bifrost_roundmode */
90 #define BI_ROUNDMODE (1 << 2)
92 /* Can be scheduled to FMA */
93 #define BI_SCHED_FMA (1 << 3)
95 /* Can be scheduled to ADD */
96 #define BI_SCHED_ADD (1 << 4)
98 /* Most ALU ops can do either, actually */
99 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
101 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
102 * nopped out. Used for _FAST operations. */
103 #define BI_SCHED_SLOW (1 << 5)
105 /* Swizzling allowed for the 8/16-bit source */
106 #define BI_SWIZZLABLE (1 << 6)
108 /* For scheduling purposes this is a high latency instruction and must be at
109 * the end of a clause. Implies ADD */
110 #define BI_SCHED_HI_LATENCY ((1 << 7) | BI_SCHED_ADD)
112 /* It can't get any worse than csel4... can it? */
113 #define BIR_SRC_COUNT 4
115 /* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
117 /* Note: no indirects here */
120 /* Only for BI_LD_ATTR. But number of vector channels */
125 struct bi_load_vary
{
126 /* All parameters used here. Indirect location specified in
127 * src1 and ignoring location, if present. */
130 enum bifrost_interp_mode interp_mode
;
135 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
136 * the target. We forward declare bi_block since this is mildly circular (not
137 * strictly, but this order of the file makes more sense I think)
139 * We define our own enum of conditions since the conditions in the hardware
140 * packed in crazy ways that would make manipulation unweildly (meaning changes
141 * based on port swapping, etc), so we defer dealing with that until emit time.
142 * Likewise, we expose NIR types instead of the crazy branch types, although
143 * the restrictions do eventually apply of course. */
158 /* Types are specified in src_types and must be compatible (either both
159 * int, or both float, 16/32, and same size or 32/16 if float. Types
160 * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
163 struct bi_block
*target
;
166 /* Opcodes within a class */
179 BI_ROUND_MODE
, /* use round mode */
180 BI_ROUND_ROUND
/* i.e.: fround() */
184 struct list_head link
; /* Must be first */
187 /* Indices, see bir_ssa_index etc. Note zero is special cased
188 * to "no argument" */
190 unsigned src
[BIR_SRC_COUNT
];
192 /* If one of the sources has BIR_INDEX_CONSTANT... Also, for
193 * BI_EXTRACT, the component index is stored here. */
201 /* Floating-point modifiers, type/class permitting. If not
202 * allowed for the type/class, these are ignored. */
203 enum bifrost_outmod outmod
;
204 bool src_abs
[BIR_SRC_COUNT
];
205 bool src_neg
[BIR_SRC_COUNT
];
207 /* Round mode (requires BI_ROUNDMODE) */
208 enum bifrost_roundmode roundmode
;
210 /* Destination type. Usually the type of the instruction
211 * itself, but if sources and destination have different
212 * types, the type of the destination wins (so f2i would be
213 * int). Zero if there is no destination. Bitsize included */
214 nir_alu_type dest_type
;
216 /* Source types if required by the class */
217 nir_alu_type src_types
[BIR_SRC_COUNT
];
219 /* If the source type is 8-bit or 16-bit such that SIMD is possible, and
220 * the class has BI_SWIZZLABLE, this is a swizzle for the input. Swizzles
221 * in practice only occur with one-source arguments (conversions,
222 * dedicated swizzle ops) and as component selection on two-sources
223 * where it is unambiguous which is which. Bounds are 32/type_size. */
226 /* A class-specific op from which the actual opcode can be derived
227 * (along with the above information) */
230 enum bi_minmax_op minmax
;
231 enum bi_bitwise_op bitwise
;
232 enum bi_round_op round
;
235 /* Union for class-specific information */
237 enum bifrost_minmax_mode minmax
;
239 struct bi_load_vary load_vary
;
240 struct bi_branch branch
;
242 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
243 * sense here but you can always just use a move for that */
244 enum bi_cond csel_cond
;
248 /* Scheduling takes place in two steps. Step 1 groups instructions within a
249 * block into distinct clauses (bi_clause). Step 2 schedules instructions
250 * within a clause into FMA/ADD pairs (bi_bundle).
252 * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
253 * leave it NULL; the emitter will fill in a nop.
262 struct list_head link
;
264 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
265 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
266 * so a clause can have up to 16 bi_instructions. Whether bundles or
267 * instructions are used depends on where in scheduling we are. */
269 unsigned instruction_count
;
270 unsigned bundle_count
;
273 bi_instruction
*instructions
[16];
274 bi_bundle bundles
[8];
277 /* For scoreboarding -- the clause ID (this is not globally unique!)
278 * and its dependencies in terms of other clauses, computed during
279 * scheduling and used when emitting code. Dependencies expressed as a
280 * bitfield matching the hardware, except shifted by a clause (the
281 * shift back to the ISA's off-by-one encoding is worked out when
282 * emitting clauses) */
283 unsigned scoreboard_id
;
284 uint8_t dependencies
;
286 /* Back-to-back corresponds directly to the back-to-back bit. Branch
287 * conditional corresponds to the branch conditional bit except that in
288 * the emitted code it's always set if back-to-bit is, whereas we use
289 * the actual value (without back-to-back so to speak) internally */
291 bool branch_conditional
;
293 /* Corresponds to the usual bit but shifted by a clause */
294 bool data_register_write_barrier
;
296 /* Constants read by this clause. ISA limit. */
297 uint64_t constants
[8];
298 unsigned constant_count
;
301 typedef struct bi_block
{
302 struct list_head link
; /* must be first */
303 unsigned name
; /* Just for pretty-printing */
305 /* If true, uses clauses; if false, uses instructions */
309 struct list_head instructions
; /* pre-schedule, list of bi_instructions */
310 struct list_head clauses
; /* list of bi_clause */
313 /* Control flow graph */
314 struct set
*predecessors
;
315 struct bi_block
*successors
[2];
320 struct list_head blocks
; /* list of bi_block */
324 /* So we can distinguish between SSA/reg/sentinel quickly */
325 #define BIR_NO_ARG (0)
326 #define BIR_IS_REG (1)
328 /* If high bits are set, instead of SSA/registers, we have specials indexed by
329 * the low bits if necessary.
331 * Fixed register: do not allocate register, do not collect $200.
332 * Uniform: access a uniform register given by low bits.
333 * Constant: access the specified constant
334 * Zero: special cased to avoid wasting a constant
337 #define BIR_INDEX_REGISTER (1 << 31)
338 #define BIR_INDEX_UNIFORM (1 << 30)
339 #define BIR_INDEX_CONSTANT (1 << 29)
340 #define BIR_INDEX_ZERO (1 << 28)
342 /* Keep me synced please so we can check src & BIR_SPECIAL */
344 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
345 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
347 static inline unsigned
348 bir_ssa_index(nir_ssa_def
*ssa
)
350 /* Off-by-one ensures BIR_NO_ARG is skipped */
351 return ((ssa
->index
+ 1) << 1) | 0;
354 static inline unsigned
355 bir_src_index(nir_src
*src
)
358 return bir_ssa_index(src
->ssa
);
360 assert(!src
->reg
.indirect
);
361 return (src
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
365 static inline unsigned
366 bir_dest_index(nir_dest
*dst
)
369 return bir_ssa_index(&dst
->ssa
);
371 assert(!dst
->reg
.indirect
);
372 return (dst
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
376 /* Iterators for Bifrost IR */
378 #define bi_foreach_block(ctx, v) \
379 list_for_each_entry(bi_block, v, &ctx->blocks, link)
381 #define bi_foreach_block_from(ctx, from, v) \
382 list_for_each_entry_from(bi_block, v, from, &ctx->blocks, link)
384 #define bi_foreach_instr_in_block(block, v) \
385 list_for_each_entry(bi_instruction, v, &block->instructions, link)
387 #define bi_foreach_instr_in_block_rev(block, v) \
388 list_for_each_entry_rev(bi_instruction, v, &block->instructions, link)
390 #define bi_foreach_instr_in_block_safe(block, v) \
391 list_for_each_entry_safe(bi_instruction, v, &block->instructions, link)
393 #define bi_foreach_instr_in_block_safe_rev(block, v) \
394 list_for_each_entry_safe_rev(bi_instruction, v, &block->instructions, link)
396 #define bi_foreach_instr_in_block_from(block, v, from) \
397 list_for_each_entry_from(bi_instruction, v, from, &block->instructions, link)
399 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
400 list_for_each_entry_from_rev(bi_instruction, v, from, &block->instructions, link)
402 #define bi_foreach_clause_in_block(block, v) \
403 list_for_each_entry(bi_clause, v, &block->clauses, link)
405 #define bi_foreach_instr_global(ctx, v) \
406 bi_foreach_block(ctx, v_block) \
407 bi_foreach_instr_in_block(v_block, v)
409 #define bi_foreach_instr_global_safe(ctx, v) \
410 bi_foreach_block(ctx, v_block) \
411 bi_foreach_instr_in_block_safe(v_block, v)
413 #define bi_foreach_successor(blk, v) \
416 for (_v = &blk->successors[0], \
418 v != NULL && _v < &blk->successors[2]; \
421 /* Based on set_foreach, expanded with automatic type casts */
423 #define bi_foreach_predecessor(blk, v) \
424 struct set_entry *_entry_##v; \
426 for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
427 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
428 _entry_##v != NULL; \
429 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
430 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
432 #define bi_foreach_src(ins, v) \
433 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)