src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_CONVERT,
  57         BI_CSEL,
  58         BI_DISCARD,
  59         BI_EXTRACT,
  60         BI_FMA,
  61         BI_FREXP,
  62         BI_LOAD,
  63         BI_LOAD_UNIFORM,
  64         BI_LOAD_ATTR,
  65         BI_LOAD_VAR,
  66         BI_LOAD_VAR_ADDRESS,
  67         BI_MAKE_VEC,
  68         BI_MINMAX,
  69         BI_MOV,
  70         BI_SHIFT,
  71         BI_STORE,
  72         BI_STORE_VAR,
  73         BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
  74         BI_SWIZZLE,
  75         BI_TEX,
  76         BI_ROUND,
  77         BI_NUM_CLASSES
  78 };
  79
  80 /* Properties of a class... */
  81 extern unsigned bi_class_props[BI_NUM_CLASSES];
  82
  83 /* abs/neg/outmod valid for a float op */
  84 #define BI_MODS (1 << 0)
  85
  86 /* Generic enough that little class-specific information is required. In other
  87  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  88  * irregular enough to warrant a separate class */
  89 #define BI_GENERIC (1 << 1)
  90
  91 /* Accepts a bifrost_roundmode */
  92 #define BI_ROUNDMODE (1 << 2)
  93
  94 /* Can be scheduled to FMA */
  95 #define BI_SCHED_FMA (1 << 3)
  96
  97 /* Can be scheduled to ADD */
  98 #define BI_SCHED_ADD (1 << 4)
  99
 100 /* Most ALU ops can do either, actually */
 101 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 102
 103 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 104  * nopped out. Used for _FAST operations. */
 105 #define BI_SCHED_SLOW (1 << 5)
 106
 107 /* Swizzling allowed for the 8/16-bit source */
 108 #define BI_SWIZZLABLE (1 << 6)
 109
 110 /* For scheduling purposes this is a high latency instruction and must be at
 111  * the end of a clause. Implies ADD */
 112 #define BI_SCHED_HI_LATENCY ((1 << 7) | BI_SCHED_ADD)
 113
 114 /* It can't get any worse than csel4... can it? */
 115 #define BIR_SRC_COUNT 4
 116
 117 /* Class-specific data for BI_LOAD, BI_LD_ATTR, BI_LD_VAR_ADDR */
 118 struct bi_load {
 119         /* Note: LD_ATTR does not support indirects */
 120         unsigned location;
 121
 122         /* Number of vector channels */
 123         unsigned channels;
 124 };
 125
 126 /* BI_LD_VARY */
 127 struct bi_load_vary {
 128         /* All parameters used here. Indirect location specified in
 129          * src1 and ignoring location, if present. */
 130         struct bi_load load;
 131
 132         enum bifrost_interp_mode interp_mode;
 133         bool reuse;
 134         bool flat;
 135 };
 136
 137 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 138  * the target. We forward declare bi_block since this is mildly circular (not
 139  * strictly, but this order of the file makes more sense I think)
 140  *
 141  * We define our own enum of conditions since the conditions in the hardware
 142  * packed in crazy ways that would make manipulation unweildly (meaning changes
 143  * based on port swapping, etc), so we defer dealing with that until emit time.
 144  * Likewise, we expose NIR types instead of the crazy branch types, although
 145  * the restrictions do eventually apply of course. */
 146
 147 struct bi_block;
 148
 149 enum bi_cond {
 150         BI_COND_ALWAYS,
 151         BI_COND_LT,
 152         BI_COND_LE,
 153         BI_COND_GE,
 154         BI_COND_GT,
 155         BI_COND_EQ,
 156         BI_COND_NE,
 157 };
 158
 159 struct bi_branch {
 160         /* Types are specified in src_types and must be compatible (either both
 161          * int, or both float, 16/32, and same size or 32/16 if float. Types
 162          * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
 163
 164         enum bi_cond cond;
 165         struct bi_block *target;
 166 };
 167
 168 /* Opcodes within a class */
 169 enum bi_minmax_op {
 170         BI_MINMAX_MIN,
 171         BI_MINMAX_MAX
 172 };
 173
 174 enum bi_bitwise_op {
 175         BI_BITWISE_AND,
 176         BI_BITWISE_OR,
 177         BI_BITWISE_XOR
 178 };
 179
 180 enum bi_round_op {
 181         BI_ROUND_MODE, /* use round mode */
 182         BI_ROUND_ROUND /* i.e.: fround() */
 183 };
 184
 185 typedef struct {
 186         struct list_head link; /* Must be first */
 187         enum bi_class type;
 188
 189         /* Indices, see bir_ssa_index etc. Note zero is special cased
 190          * to "no argument" */
 191         unsigned dest;
 192         unsigned src[BIR_SRC_COUNT];
 193
 194         /* If one of the sources has BIR_INDEX_CONSTANT... Also, for
 195          * BI_EXTRACT, the component index is stored here. */
 196         union {
 197                 uint64_t u64;
 198                 uint32_t u32;
 199                 uint16_t u16[2];
 200                 uint8_t u8[4];
 201         } constant;
 202
 203         /* Floating-point modifiers, type/class permitting. If not
 204          * allowed for the type/class, these are ignored. */
 205         enum bifrost_outmod outmod;
 206         bool src_abs[BIR_SRC_COUNT];
 207         bool src_neg[BIR_SRC_COUNT];
 208
 209         /* Round mode (requires BI_ROUNDMODE) */
 210         enum bifrost_roundmode roundmode;
 211
 212         /* Destination type. Usually the type of the instruction
 213          * itself, but if sources and destination have different
 214          * types, the type of the destination wins (so f2i would be
 215          * int). Zero if there is no destination. Bitsize included */
 216         nir_alu_type dest_type;
 217
 218         /* Source types if required by the class */
 219         nir_alu_type src_types[BIR_SRC_COUNT];
 220
 221         /* If the source type is 8-bit or 16-bit such that SIMD is possible, and
 222          * the class has BI_SWIZZLABLE, this is a swizzle for the input. Swizzles
 223          * in practice only occur with one-source arguments (conversions,
 224          * dedicated swizzle ops) and as component selection on two-sources
 225          * where it is unambiguous which is which. Bounds are 32/type_size. */
 226         unsigned swizzle[4];
 227
 228         /* A class-specific op from which the actual opcode can be derived
 229          * (along with the above information) */
 230
 231         union {
 232                 enum bi_minmax_op minmax;
 233                 enum bi_bitwise_op bitwise;
 234                 enum bi_round_op round;
 235         } op;
 236
 237         /* Union for class-specific information */
 238         union {
 239                 enum bifrost_minmax_mode minmax;
 240                 struct bi_load load;
 241                 struct bi_load_vary load_vary;
 242                 struct bi_branch branch;
 243
 244                 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
 245                  * sense here but you can always just use a move for that */
 246                 enum bi_cond csel_cond;
 247
 248                 /* For BLEND -- the location 0-7 */
 249                 unsigned blend_location;
 250         };
 251 } bi_instruction;
 252
 253 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 254  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 255  * within a clause into FMA/ADD pairs (bi_bundle).
 256  *
 257  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 258  * leave it NULL; the emitter will fill in a nop.
 259  */
 260
 261 typedef struct {
 262         bi_instruction *fma;
 263         bi_instruction *add;
 264 } bi_bundle;
 265
 266 typedef struct {
 267         struct list_head link;
 268
 269         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 270          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 271          * so a clause can have up to 16 bi_instructions. Whether bundles or
 272          * instructions are used depends on where in scheduling we are. */
 273
 274         unsigned instruction_count;
 275         unsigned bundle_count;
 276
 277         union {
 278                 bi_instruction *instructions[16];
 279                 bi_bundle bundles[8];
 280         };
 281
 282         /* For scoreboarding -- the clause ID (this is not globally unique!)
 283          * and its dependencies in terms of other clauses, computed during
 284          * scheduling and used when emitting code. Dependencies expressed as a
 285          * bitfield matching the hardware, except shifted by a clause (the
 286          * shift back to the ISA's off-by-one encoding is worked out when
 287          * emitting clauses) */
 288         unsigned scoreboard_id;
 289         uint8_t dependencies;
 290
 291         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 292          * conditional corresponds to the branch conditional bit except that in
 293          * the emitted code it's always set if back-to-bit is, whereas we use
 294          * the actual value (without back-to-back so to speak) internally */
 295         bool back_to_back;
 296         bool branch_conditional;
 297
 298         /* Corresponds to the usual bit but shifted by a clause */
 299         bool data_register_write_barrier;
 300
 301         /* Constants read by this clause. ISA limit. */
 302         uint64_t constants[8];
 303         unsigned constant_count;
 304 } bi_clause;
 305
 306 typedef struct bi_block {
 307         struct list_head link; /* must be first */
 308         unsigned name; /* Just for pretty-printing */
 309
 310         /* If true, uses clauses; if false, uses instructions */
 311         bool scheduled;
 312         struct list_head instructions; /* pre-schedule, list of bi_instructions */
 313         struct list_head clauses; /* list of bi_clause */
 314
 315         /* Control flow graph */
 316         struct set *predecessors;
 317         struct bi_block *successors[2];
 318 } bi_block;
 319
 320 typedef struct {
 321        nir_shader *nir;
 322        gl_shader_stage stage;
 323        struct list_head blocks; /* list of bi_block */
 324        uint32_t quirks;
 325
 326        /* During NIR->BIR */
 327        nir_function_impl *impl;
 328        bi_block *current_block;
 329        unsigned block_name_count;
 330        bi_block *after_block;
 331        bi_block *break_block;
 332        bi_block *continue_block;
 333        bool emitted_atest;
 334
 335        /* For creating temporaries */
 336        unsigned temp_alloc;
 337
 338        /* Stats for shader-db */
 339        unsigned instruction_count;
 340        unsigned loop_count;
 341 } bi_context;
 342
 343 static inline bi_instruction *
 344 bi_emit(bi_context *ctx, bi_instruction ins)
 345 {
 346         bi_instruction *u = rzalloc(ctx, bi_instruction);
 347         memcpy(u, &ins, sizeof(ins));
 348         list_addtail(&u->link, &ctx->current_block->instructions);
 349         return u;
 350 }
 351
 352 static inline void
 353 bi_remove_instruction(bi_instruction *ins)
 354 {
 355         list_del(&ins->link);
 356 }
 357
 358 /* So we can distinguish between SSA/reg/sentinel quickly */
 359 #define BIR_NO_ARG (0)
 360 #define BIR_IS_REG (1)
 361
 362 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 363  * the low bits if necessary.
 364  *
 365  *  Fixed register: do not allocate register, do not collect $200.
 366  *  Uniform: access a uniform register given by low bits.
 367  *  Constant: access the specified constant
 368  *  Zero: special cased to avoid wasting a constant
 369  */
 370
 371 #define BIR_INDEX_REGISTER (1 << 31)
 372 #define BIR_INDEX_UNIFORM  (1 << 30)
 373 #define BIR_INDEX_CONSTANT (1 << 29)
 374 #define BIR_INDEX_ZERO     (1 << 28)
 375
 376 /* Keep me synced please so we can check src & BIR_SPECIAL */
 377
 378 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 379         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
 380
 381 static inline unsigned
 382 bi_make_temp(bi_context *ctx)
 383 {
 384         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 385 }
 386
 387 static inline unsigned
 388 bi_make_temp_reg(bi_context *ctx)
 389 {
 390         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG;
 391 }
 392
 393 static inline unsigned
 394 bir_ssa_index(nir_ssa_def *ssa)
 395 {
 396         /* Off-by-one ensures BIR_NO_ARG is skipped */
 397         return ((ssa->index + 1) << 1) | 0;
 398 }
 399
 400 static inline unsigned
 401 bir_src_index(nir_src *src)
 402 {
 403         if (src->is_ssa)
 404                 return bir_ssa_index(src->ssa);
 405         else {
 406                 assert(!src->reg.indirect);
 407                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 408         }
 409 }
 410
 411 static inline unsigned
 412 bir_dest_index(nir_dest *dst)
 413 {
 414         if (dst->is_ssa)
 415                 return bir_ssa_index(&dst->ssa);
 416         else {
 417                 assert(!dst->reg.indirect);
 418                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 419         }
 420 }
 421
 422 /* Iterators for Bifrost IR */
 423
 424 #define bi_foreach_block(ctx, v) \
 425         list_for_each_entry(bi_block, v, &ctx->blocks, link)
 426
 427 #define bi_foreach_block_from(ctx, from, v) \
 428         list_for_each_entry_from(bi_block, v, from, &ctx->blocks, link)
 429
 430 #define bi_foreach_instr_in_block(block, v) \
 431         list_for_each_entry(bi_instruction, v, &block->instructions, link)
 432
 433 #define bi_foreach_instr_in_block_rev(block, v) \
 434         list_for_each_entry_rev(bi_instruction, v, &block->instructions, link)
 435
 436 #define bi_foreach_instr_in_block_safe(block, v) \
 437         list_for_each_entry_safe(bi_instruction, v, &block->instructions, link)
 438
 439 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 440         list_for_each_entry_safe_rev(bi_instruction, v, &block->instructions, link)
 441
 442 #define bi_foreach_instr_in_block_from(block, v, from) \
 443         list_for_each_entry_from(bi_instruction, v, from, &block->instructions, link)
 444
 445 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 446         list_for_each_entry_from_rev(bi_instruction, v, from, &block->instructions, link)
 447
 448 #define bi_foreach_clause_in_block(block, v) \
 449         list_for_each_entry(bi_clause, v, &block->clauses, link)
 450
 451 #define bi_foreach_instr_global(ctx, v) \
 452         bi_foreach_block(ctx, v_block) \
 453                 bi_foreach_instr_in_block(v_block, v)
 454
 455 #define bi_foreach_instr_global_safe(ctx, v) \
 456         bi_foreach_block(ctx, v_block) \
 457                 bi_foreach_instr_in_block_safe(v_block, v)
 458
 459 #define bi_foreach_successor(blk, v) \
 460         bi_block *v; \
 461         bi_block **_v; \
 462         for (_v = &blk->successors[0], \
 463                 v = *_v; \
 464                 v != NULL && _v < &blk->successors[2]; \
 465                 _v++, v = *_v) \
 466
 467 /* Based on set_foreach, expanded with automatic type casts */
 468
 469 #define bi_foreach_predecessor(blk, v) \
 470         struct set_entry *_entry_##v; \
 471         bi_block *v; \
 472         for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
 473                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 474                 _entry_##v != NULL; \
 475                 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
 476                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 477
 478 #define bi_foreach_src(ins, v) \
 479         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 480
 481 /* BIR manipulation */
 482
 483 bool bi_has_outmod(bi_instruction *ins);
 484 bool bi_has_source_mods(bi_instruction *ins);
 485 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 486
 487 /* BIR passes */
 488
 489 void bi_schedule(bi_context *ctx);
 490
 491 #endif