src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_COMBINE,
  57         BI_CONVERT,
  58         BI_CSEL,
  59         BI_DISCARD,
  60         BI_FMA,
  61         BI_FMOV,
  62         BI_FREXP,
  63         BI_ISUB,
  64         BI_LOAD,
  65         BI_LOAD_UNIFORM,
  66         BI_LOAD_ATTR,
  67         BI_LOAD_VAR,
  68         BI_LOAD_VAR_ADDRESS,
  69         BI_MINMAX,
  70         BI_MOV,
  71         BI_SHIFT,
  72         BI_STORE,
  73         BI_STORE_VAR,
  74         BI_SPECIAL, /* _FAST on supported GPUs */
  75         BI_SWIZZLE,
  76         BI_TABLE,
  77         BI_TEX,
  78         BI_ROUND,
  79         BI_NUM_CLASSES
  80 };
  81
  82 /* Properties of a class... */
  83 extern unsigned bi_class_props[BI_NUM_CLASSES];
  84
  85 /* abs/neg/outmod valid for a float op */
  86 #define BI_MODS (1 << 0)
  87
  88 /* Generic enough that little class-specific information is required. In other
  89  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  90  * irregular enough to warrant a separate class */
  91 #define BI_GENERIC (1 << 1)
  92
  93 /* Accepts a bifrost_roundmode */
  94 #define BI_ROUNDMODE (1 << 2)
  95
  96 /* Can be scheduled to FMA */
  97 #define BI_SCHED_FMA (1 << 3)
  98
  99 /* Can be scheduled to ADD */
 100 #define BI_SCHED_ADD (1 << 4)
 101
 102 /* Most ALU ops can do either, actually */
 103 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 104
 105 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 106  * nopped out. Used for _FAST operations. */
 107 #define BI_SCHED_SLOW (1 << 5)
 108
 109 /* Swizzling allowed for the 8/16-bit source */
 110 #define BI_SWIZZLABLE (1 << 6)
 111
 112 /* For scheduling purposes this is a high latency instruction and must be at
 113  * the end of a clause. Implies ADD */
 114 #define BI_SCHED_HI_LATENCY (1 << 7)
 115
 116 /* Intrinsic is vectorized and should read 4 components in the first source
 117  * regardless of writemask */
 118 #define BI_VECTOR (1 << 8)
 119
 120 /* Use a data register for src0/dest respectively, bypassing the usual
 121  * register accessor. Mutually exclusive. */
 122 #define BI_DATA_REG_SRC (1 << 9)
 123 #define BI_DATA_REG_DEST (1 << 10)
 124
 125 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
 126 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
 127
 128 /* It can't get any worse than csel4... can it? */
 129 #define BIR_SRC_COUNT 4
 130
 131 /* BI_LD_VARY */
 132 struct bi_load_vary {
 133         enum bifrost_interp_mode interp_mode;
 134         bool reuse;
 135         bool flat;
 136 };
 137
 138 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 139  * the target. We forward declare bi_block since this is mildly circular (not
 140  * strictly, but this order of the file makes more sense I think)
 141  *
 142  * We define our own enum of conditions since the conditions in the hardware
 143  * packed in crazy ways that would make manipulation unweildly (meaning changes
 144  * based on port swapping, etc), so we defer dealing with that until emit time.
 145  * Likewise, we expose NIR types instead of the crazy branch types, although
 146  * the restrictions do eventually apply of course. */
 147
 148 struct bi_block;
 149
 150 enum bi_cond {
 151         BI_COND_ALWAYS,
 152         BI_COND_LT,
 153         BI_COND_LE,
 154         BI_COND_GE,
 155         BI_COND_GT,
 156         BI_COND_EQ,
 157         BI_COND_NE,
 158 };
 159
 160 struct bi_branch {
 161         /* Types are specified in src_types and must be compatible (either both
 162          * int, or both float, 16/32, and same size or 32/16 if float. Types
 163          * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
 164
 165         enum bi_cond cond;
 166         struct bi_block *target;
 167 };
 168
 169 /* Opcodes within a class */
 170 enum bi_minmax_op {
 171         BI_MINMAX_MIN,
 172         BI_MINMAX_MAX
 173 };
 174
 175 enum bi_bitwise_op {
 176         BI_BITWISE_AND,
 177         BI_BITWISE_OR,
 178         BI_BITWISE_XOR
 179 };
 180
 181 enum bi_round_op {
 182         BI_ROUND_MODE, /* use round mode */
 183         BI_ROUND_ROUND /* i.e.: fround() */
 184 };
 185
 186 enum bi_table_op {
 187         /* fp32 log2() with low precision, suitable for GL or half_log2() in
 188          * CL. In the first argument, takes x. Letting u be such that x =
 189          * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
 190          * log2(u) / (u - 1). */
 191
 192         BI_TABLE_LOG2_U_OVER_U_1_LOW,
 193 };
 194
 195 enum bi_special_op {
 196         BI_SPECIAL_FRCP,
 197         BI_SPECIAL_FRSQ,
 198 };
 199
 200 typedef struct {
 201         struct list_head link; /* Must be first */
 202         enum bi_class type;
 203
 204         /* Indices, see bir_ssa_index etc. Note zero is special cased
 205          * to "no argument" */
 206         unsigned dest;
 207         unsigned src[BIR_SRC_COUNT];
 208
 209         /* If one of the sources has BIR_INDEX_CONSTANT */
 210         union {
 211                 uint64_t u64;
 212                 uint32_t u32;
 213                 uint16_t u16[2];
 214                 uint8_t u8[4];
 215         } constant;
 216
 217         /* Floating-point modifiers, type/class permitting. If not
 218          * allowed for the type/class, these are ignored. */
 219         enum bifrost_outmod outmod;
 220         bool src_abs[BIR_SRC_COUNT];
 221         bool src_neg[BIR_SRC_COUNT];
 222
 223         /* Round mode (requires BI_ROUNDMODE) */
 224         enum bifrost_roundmode roundmode;
 225
 226         /* Writemask (bit for each affected byte). This is quite restricted --
 227          * ALU ops can only write to a single channel (exception: <32 in which
 228          * you can write to 32/N contiguous aligned channels). Load/store can
 229          * only write to all channels at once, in a sense. But it's still
 230          * better to use this generic form than have synthetic ops flying
 231          * about, since we're not essentially vector for RA purposes. */
 232         uint16_t writemask;
 233
 234         /* Destination type. Usually the type of the instruction
 235          * itself, but if sources and destination have different
 236          * types, the type of the destination wins (so f2i would be
 237          * int). Zero if there is no destination. Bitsize included */
 238         nir_alu_type dest_type;
 239
 240         /* Source types if required by the class */
 241         nir_alu_type src_types[BIR_SRC_COUNT];
 242
 243         /* If the source type is 8-bit or 16-bit such that SIMD is possible,
 244          * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
 245          * sense. On non-SIMD instructions, it can be used for component
 246          * selection, so we don't have to special case extraction. */
 247         uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
 248
 249         /* A class-specific op from which the actual opcode can be derived
 250          * (along with the above information) */
 251
 252         union {
 253                 enum bi_minmax_op minmax;
 254                 enum bi_bitwise_op bitwise;
 255                 enum bi_round_op round;
 256                 enum bi_special_op special;
 257                 enum bi_table_op table;
 258                 enum bi_cond compare;
 259         } op;
 260
 261         /* Union for class-specific information */
 262         union {
 263                 enum bifrost_minmax_mode minmax;
 264                 struct bi_load_vary load_vary;
 265                 struct bi_branch branch;
 266
 267                 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
 268                  * sense here but you can always just use a move for that */
 269                 enum bi_cond csel_cond;
 270
 271                 /* For BLEND -- the location 0-7 */
 272                 unsigned blend_location;
 273
 274                 /* For STORE, STORE_VAR -- channel count */
 275                 unsigned store_channels;
 276         };
 277 } bi_instruction;
 278
 279 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 280  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 281  * within a clause into FMA/ADD pairs (bi_bundle).
 282  *
 283  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 284  * leave it NULL; the emitter will fill in a nop.
 285  */
 286
 287 typedef struct {
 288         bi_instruction *fma;
 289         bi_instruction *add;
 290 } bi_bundle;
 291
 292 typedef struct {
 293         struct list_head link;
 294
 295         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 296          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 297          * so a clause can have up to 16 bi_instructions. Whether bundles or
 298          * instructions are used depends on where in scheduling we are. */
 299
 300         unsigned instruction_count;
 301         unsigned bundle_count;
 302
 303         union {
 304                 bi_instruction *instructions[16];
 305                 bi_bundle bundles[8];
 306         };
 307
 308         /* For scoreboarding -- the clause ID (this is not globally unique!)
 309          * and its dependencies in terms of other clauses, computed during
 310          * scheduling and used when emitting code. Dependencies expressed as a
 311          * bitfield matching the hardware, except shifted by a clause (the
 312          * shift back to the ISA's off-by-one encoding is worked out when
 313          * emitting clauses) */
 314         unsigned scoreboard_id;
 315         uint8_t dependencies;
 316
 317         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 318          * conditional corresponds to the branch conditional bit except that in
 319          * the emitted code it's always set if back-to-bit is, whereas we use
 320          * the actual value (without back-to-back so to speak) internally */
 321         bool back_to_back;
 322         bool branch_conditional;
 323
 324         /* Assigned data register */
 325         unsigned data_register;
 326
 327         /* Corresponds to the usual bit but shifted by a clause */
 328         bool data_register_write_barrier;
 329
 330         /* Constants read by this clause. ISA limit. */
 331         uint64_t constants[8];
 332         unsigned constant_count;
 333
 334         /* What type of high latency instruction is here, basically */
 335         unsigned clause_type;
 336 } bi_clause;
 337
 338 typedef struct bi_block {
 339         pan_block base; /* must be first */
 340
 341         /* If true, uses clauses; if false, uses instructions */
 342         bool scheduled;
 343         struct list_head clauses; /* list of bi_clause */
 344 } bi_block;
 345
 346 typedef struct {
 347        nir_shader *nir;
 348        gl_shader_stage stage;
 349        struct list_head blocks; /* list of bi_block */
 350        struct panfrost_sysvals sysvals;
 351        uint32_t quirks;
 352
 353        /* During NIR->BIR */
 354        nir_function_impl *impl;
 355        bi_block *current_block;
 356        unsigned block_name_count;
 357        bi_block *after_block;
 358        bi_block *break_block;
 359        bi_block *continue_block;
 360        bool emitted_atest;
 361
 362        /* For creating temporaries */
 363        unsigned temp_alloc;
 364
 365        /* Analysis results */
 366        bool has_liveness;
 367
 368        /* Stats for shader-db */
 369        unsigned instruction_count;
 370        unsigned loop_count;
 371 } bi_context;
 372
 373 static inline bi_instruction *
 374 bi_emit(bi_context *ctx, bi_instruction ins)
 375 {
 376         bi_instruction *u = rzalloc(ctx, bi_instruction);
 377         memcpy(u, &ins, sizeof(ins));
 378         list_addtail(&u->link, &ctx->current_block->base.instructions);
 379         return u;
 380 }
 381
 382 static inline bi_instruction *
 383 bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
 384 {
 385         bi_instruction *u = rzalloc(ctx, bi_instruction);
 386         memcpy(u, &ins, sizeof(ins));
 387         list_addtail(&u->link, &tag->link);
 388         return u;
 389 }
 390
 391 static inline void
 392 bi_remove_instruction(bi_instruction *ins)
 393 {
 394         list_del(&ins->link);
 395 }
 396
 397 /* So we can distinguish between SSA/reg/sentinel quickly */
 398 #define BIR_NO_ARG (0)
 399 #define BIR_IS_REG (1)
 400
 401 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 402  * the low bits if necessary.
 403  *
 404  *  Fixed register: do not allocate register, do not collect $200.
 405  *  Uniform: access a uniform register given by low bits.
 406  *  Constant: access the specified constant (specifies a bit offset / shift)
 407  *  Zero: special cased to avoid wasting a constant
 408  *  Passthrough: a bifrost_packed_src to passthrough T/T0/T1
 409  */
 410
 411 #define BIR_INDEX_REGISTER (1 << 31)
 412 #define BIR_INDEX_UNIFORM  (1 << 30)
 413 #define BIR_INDEX_CONSTANT (1 << 29)
 414 #define BIR_INDEX_ZERO     (1 << 28)
 415 #define BIR_INDEX_PASS     (1 << 27)
 416
 417 /* Keep me synced please so we can check src & BIR_SPECIAL */
 418
 419 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 420         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
 421
 422 static inline unsigned
 423 bi_max_temp(bi_context *ctx)
 424 {
 425         unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
 426         return ((alloc + 2 + ctx->temp_alloc) << 1);
 427 }
 428
 429 static inline unsigned
 430 bi_make_temp(bi_context *ctx)
 431 {
 432         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 433 }
 434
 435 static inline unsigned
 436 bi_make_temp_reg(bi_context *ctx)
 437 {
 438         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG;
 439 }
 440
 441 static inline unsigned
 442 bir_ssa_index(nir_ssa_def *ssa)
 443 {
 444         /* Off-by-one ensures BIR_NO_ARG is skipped */
 445         return ((ssa->index + 1) << 1) | 0;
 446 }
 447
 448 static inline unsigned
 449 bir_src_index(nir_src *src)
 450 {
 451         if (src->is_ssa)
 452                 return bir_ssa_index(src->ssa);
 453         else {
 454                 assert(!src->reg.indirect);
 455                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 456         }
 457 }
 458
 459 static inline unsigned
 460 bir_dest_index(nir_dest *dst)
 461 {
 462         if (dst->is_ssa)
 463                 return bir_ssa_index(&dst->ssa);
 464         else {
 465                 assert(!dst->reg.indirect);
 466                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 467         }
 468 }
 469
 470 /* Iterators for Bifrost IR */
 471
 472 #define bi_foreach_block(ctx, v) \
 473         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 474
 475 #define bi_foreach_block_from(ctx, from, v) \
 476         list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
 477
 478 #define bi_foreach_instr_in_block(block, v) \
 479         list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
 480
 481 #define bi_foreach_instr_in_block_rev(block, v) \
 482         list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
 483
 484 #define bi_foreach_instr_in_block_safe(block, v) \
 485         list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
 486
 487 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 488         list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
 489
 490 #define bi_foreach_instr_in_block_from(block, v, from) \
 491         list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
 492
 493 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 494         list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
 495
 496 #define bi_foreach_clause_in_block(block, v) \
 497         list_for_each_entry(bi_clause, v, &(block)->clauses, link)
 498
 499 #define bi_foreach_instr_global(ctx, v) \
 500         bi_foreach_block(ctx, v_block) \
 501                 bi_foreach_instr_in_block((bi_block *) v_block, v)
 502
 503 #define bi_foreach_instr_global_safe(ctx, v) \
 504         bi_foreach_block(ctx, v_block) \
 505                 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
 506
 507 /* Based on set_foreach, expanded with automatic type casts */
 508
 509 #define bi_foreach_predecessor(blk, v) \
 510         struct set_entry *_entry_##v; \
 511         bi_block *v; \
 512         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 513                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 514                 _entry_##v != NULL; \
 515                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 516                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 517
 518 #define bi_foreach_src(ins, v) \
 519         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 520
 521 static inline bi_instruction *
 522 bi_prev_op(bi_instruction *ins)
 523 {
 524         return list_last_entry(&(ins->link), bi_instruction, link);
 525 }
 526
 527 static inline bi_instruction *
 528 bi_next_op(bi_instruction *ins)
 529 {
 530         return list_first_entry(&(ins->link), bi_instruction, link);
 531 }
 532
 533 static inline pan_block *
 534 pan_next_block(pan_block *block)
 535 {
 536         return list_first_entry(&(block->link), pan_block, link);
 537 }
 538
 539 /* BIR manipulation */
 540
 541 bool bi_has_outmod(bi_instruction *ins);
 542 bool bi_has_source_mods(bi_instruction *ins);
 543 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 544 bool bi_has_arg(bi_instruction *ins, unsigned arg);
 545 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
 546 unsigned bi_get_component_count(bi_instruction *ins, unsigned s);
 547 unsigned bi_load32_components(bi_instruction *ins);
 548 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
 549 uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
 550 bool bi_writes_component(bi_instruction *ins, unsigned comp);
 551
 552 /* BIR passes */
 553
 554 void bi_lower_combine(bi_context *ctx, bi_block *block);
 555 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
 556 void bi_schedule(bi_context *ctx);
 557 void bi_register_allocate(bi_context *ctx);
 558
 559 /* Liveness */
 560
 561 void bi_compute_liveness(bi_context *ctx);
 562 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
 563 void bi_invalidate_liveness(bi_context *ctx);
 564 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
 565
 566 /* Code emit */
 567
 568 void bi_pack(bi_context *ctx, struct util_dynarray *emission);
 569
 570 #endif