src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32
  33 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  34  * ADD with two completely different opcodes, and opcodes can be varying
  35  * length in some cases. Then we have different opcodes for int vs float
  36  * and then sometimes even for different typesizes. Further, virtually
  37  * every op has a number of flags which depend on the op. In constrast
  38  * to Midgard where you have a strict ALU/LDST/TEX division and within
  39  * ALU you have strict int/float and that's it... here it's a *lot* more
  40  * involved. As such, we use something much higher level for our IR,
  41  * encoding "classes" of operations, letting the opcode details get
  42  * sorted out at emit time.
  43  *
  44  * Please keep this list alphabetized. Please use a dictionary if you
  45  * don't know how to do that.
  46  */
  47
  48 enum bi_class {
  49         BI_ADD,
  50         BI_ATEST,
  51         BI_BRANCH,
  52         BI_CMP,
  53         BI_BLEND,
  54         BI_BITWISE,
  55         BI_CONVERT,
  56         BI_CSEL,
  57         BI_DISCARD,
  58         BI_FMA,
  59         BI_FREXP,
  60         BI_LOAD,
  61         BI_LOAD_ATTR,
  62         BI_LOAD_VAR,
  63         BI_LOAD_VAR_ADDRESS,
  64         BI_MINMAX,
  65         BI_MOV,
  66         BI_SHIFT,
  67         BI_STORE,
  68         BI_STORE_VAR,
  69         BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
  70         BI_TEX,
  71         BI_ROUND,
  72         BI_NUM_CLASSES
  73 };
  74
  75 /* Properties of a class... */
  76 extern unsigned bi_class_props[BI_NUM_CLASSES];
  77
  78 /* abs/neg/outmod valid for a float op */
  79 #define BI_MODS (1 << 0)
  80
  81 /* Generic enough that little class-specific information is required. In other
  82  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  83  * irregular enough to warrant a separate class */
  84 #define BI_GENERIC (1 << 1)
  85
  86 /* Accepts a bifrost_roundmode */
  87 #define BI_ROUNDMODE (1 << 2)
  88
  89 /* Can be scheduled to FMA */
  90 #define BI_SCHED_FMA (1 << 3)
  91
  92 /* Can be scheduled to ADD */
  93 #define BI_SCHED_ADD (1 << 4)
  94
  95 /* Most ALU ops can do either, actually */
  96 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
  97
  98 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
  99  * nopped out. Used for _FAST operations. */
 100 #define BI_SCHED_SLOW (1 << 5)
 101
 102 /* It can't get any worse than csel4... can it? */
 103 #define BIR_SRC_COUNT 4
 104
 105 /* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
 106 struct bi_load {
 107         /* Note: no indirects here */
 108         unsigned location;
 109
 110         /* Only for BI_LD_ATTR. But number of vector channels */
 111         unsigned channels;
 112 };
 113
 114 /* BI_LD_VARY */
 115 struct bi_load_vary {
 116         /* All parameters used here. Indirect location specified in
 117          * src1 and ignoring location, if present. */
 118         struct bi_load load;
 119
 120         enum bifrost_interp_mode interp_mode;
 121         bool reuse;
 122         bool flat;
 123 };
 124
 125 /* Opcodes within a class */
 126 enum bi_minmax_op {
 127         BI_MINMAX_MIN,
 128         BI_MINMAX_MAX
 129 };
 130
 131 enum bi_bitwise_op {
 132         BI_BITWISE_AND,
 133         BI_BITWISE_OR,
 134         BI_BITWISE_XOR
 135 };
 136
 137 enum bi_round_op {
 138         BI_ROUND_MODE, /* use round mode */
 139         BI_ROUND_ROUND /* i.e.: fround() */
 140 };
 141
 142 typedef struct {
 143         struct list_head link; /* Must be first */
 144         enum bi_class type;
 145
 146         /* Indices, see bir_ssa_index etc. Note zero is special cased
 147          * to "no argument" */
 148         unsigned dest;
 149         unsigned src[BIR_SRC_COUNT];
 150
 151         /* If one of the sources has BIR_INDEX_CONSTANT... */
 152         union {
 153                 uint64_t u64;
 154                 uint32_t u32;
 155                 uint16_t u16[2];
 156                 uint8_t u8[4];
 157         } constant;
 158
 159         /* Floating-point modifiers, type/class permitting. If not
 160          * allowed for the type/class, these are ignored. */
 161         enum bifrost_outmod outmod;
 162         bool src_abs[BIR_SRC_COUNT];
 163         bool src_neg[BIR_SRC_COUNT];
 164
 165         /* Round mode (requires BI_ROUNDMODE) */
 166         enum bifrost_roundmode roundmode;
 167
 168         /* Destination type. Usually the type of the instruction
 169          * itself, but if sources and destination have different
 170          * types, the type of the destination wins (so f2i would be
 171          * int). Zero if there is no destination. Bitsize included */
 172         nir_alu_type dest_type;
 173
 174         /* A class-specific op from which the actual opcode can be derived
 175          * (along with the above information) */
 176
 177         union {
 178                 enum bi_minmax_op minmax;
 179                 enum bi_bitwise_op bitwise;
 180                 enum bi_round_op round;
 181         } op;
 182
 183         /* Union for class-specific information */
 184         union {
 185                 enum bifrost_minmax_mode minmax;
 186                 struct bi_load load;
 187                 struct bi_load_vary load_vary;
 188         };
 189 } bi_instruction;
 190
 191 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 192  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 193  * within a clause into FMA/ADD pairs (bi_bundle).
 194  *
 195  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 196  * leave it NULL; the emitter will fill in a nop.
 197  */
 198
 199 typedef struct {
 200         bi_instruction *fma;
 201         bi_instruction *add;
 202 } bi_bundle;
 203
 204 typedef struct {
 205         struct list_head link;
 206
 207         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 208          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 209          * so a clause can have up to 16 bi_instructions. Whether bundles or
 210          * instructions are used depends on where in scheduling we are. */
 211
 212         unsigned instruction_count;
 213         unsigned bundle_count;
 214
 215         union {
 216                 bi_instruction *instructions[16];
 217                 bi_bundle bundles[8];
 218         };
 219
 220         /* For scoreboarding -- the clause ID (this is not globally unique!)
 221          * and its dependencies in terms of other clauses, computed during
 222          * scheduling and used when emitting code. Dependencies expressed as a
 223          * bitfield matching the hardware, except shifted by a clause (the
 224          * shift back to the ISA's off-by-one encoding is worked out when
 225          * emitting clauses) */
 226         unsigned scoreboard_id;
 227         uint8_t dependencies;
 228
 229         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 230          * conditional corresponds to the branch conditional bit except that in
 231          * the emitted code it's always set if back-to-bit is, whereas we use
 232          * the actual value (without back-to-back so to speak) internally */
 233         bool back_to_back;
 234         bool branch_conditional;
 235
 236         /* Corresponds to the usual bit but shifted by a clause */
 237         bool data_register_write_barrier;
 238 } bi_clause;
 239
 240 typedef struct bi_block {
 241         struct list_head link; /* must be first */
 242         unsigned name; /* Just for pretty-printing */
 243
 244         /* If true, uses clauses; if false, uses instructions */
 245         bool scheduled;
 246
 247         union {
 248                 struct list_head instructions; /* pre-schedule, list of bi_instructions */
 249                 struct list_head clauses; /* list of bi_clause */
 250         };
 251 } bi_block;
 252
 253 typedef struct {
 254        nir_shader *nir;
 255        struct list_head blocks; /* list of bi_block */
 256 } bi_context;
 257
 258 /* So we can distinguish between SSA/reg/sentinel quickly */
 259 #define BIR_NO_ARG (0)
 260 #define BIR_IS_REG (1)
 261
 262 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 263  * the low bits if necessary.
 264  *
 265  *  Fixed register: do not allocate register, do not collect $200.
 266  *  Uniform: access a uniform register given by low bits.
 267  *  Constant: access the specified constant
 268  *  Zero: special cased to avoid wasting a constant
 269  */
 270
 271 #define BIR_INDEX_REGISTER (1 << 31)
 272 #define BIR_INDEX_UNIFORM  (1 << 30)
 273 #define BIR_INDEX_CONSTANT (1 << 29)
 274 #define BIR_INDEX_ZERO     (1 << 28)
 275
 276 /* Keep me synced please so we can check src & BIR_SPECIAL */
 277
 278 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 279         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
 280
 281 static inline unsigned
 282 bir_ssa_index(nir_ssa_def *ssa)
 283 {
 284         /* Off-by-one ensures BIR_NO_ARG is skipped */
 285         return ((ssa->index + 1) << 1) | 0;
 286 }
 287
 288 static inline unsigned
 289 bir_src_index(nir_src *src)
 290 {
 291         if (src->is_ssa)
 292                 return bir_ssa_index(src->ssa);
 293         else {
 294                 assert(!src->reg.indirect);
 295                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 296         }
 297 }
 298
 299 static inline unsigned
 300 bir_dest_index(nir_dest *dst)
 301 {
 302         if (dst->is_ssa)
 303                 return bir_ssa_index(&dst->ssa);
 304         else {
 305                 assert(!dst->reg.indirect);
 306                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 307         }
 308 }
 309
 310 #endif