src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32
  33 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  34  * ADD with two completely different opcodes, and opcodes can be varying
  35  * length in some cases. Then we have different opcodes for int vs float
  36  * and then sometimes even for different typesizes. Further, virtually
  37  * every op has a number of flags which depend on the op. In constrast
  38  * to Midgard where you have a strict ALU/LDST/TEX division and within
  39  * ALU you have strict int/float and that's it... here it's a *lot* more
  40  * involved. As such, we use something much higher level for our IR,
  41  * encoding "classes" of operations, letting the opcode details get
  42  * sorted out at emit time.
  43  *
  44  * Please keep this list alphabetized. Please use a dictionary if you
  45  * don't know how to do that.
  46  */
  47
  48 enum bi_class {
  49         BI_ADD,
  50         BI_ATEST,
  51         BI_BRANCH,
  52         BI_CMP,
  53         BI_BLEND,
  54         BI_BITWISE,
  55         BI_CONVERT,
  56         BI_CSEL,
  57         BI_DISCARD,
  58         BI_EXTRACT,
  59         BI_FMA,
  60         BI_FREXP,
  61         BI_LOAD,
  62         BI_LOAD_ATTR,
  63         BI_LOAD_VAR,
  64         BI_LOAD_VAR_ADDRESS,
  65         BI_MAKE_VEC,
  66         BI_MINMAX,
  67         BI_MOV,
  68         BI_SHIFT,
  69         BI_STORE,
  70         BI_STORE_VAR,
  71         BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
  72         BI_SWIZZLE,
  73         BI_TEX,
  74         BI_ROUND,
  75         BI_NUM_CLASSES
  76 };
  77
  78 /* Properties of a class... */
  79 extern unsigned bi_class_props[BI_NUM_CLASSES];
  80
  81 /* abs/neg/outmod valid for a float op */
  82 #define BI_MODS (1 << 0)
  83
  84 /* Generic enough that little class-specific information is required. In other
  85  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  86  * irregular enough to warrant a separate class */
  87 #define BI_GENERIC (1 << 1)
  88
  89 /* Accepts a bifrost_roundmode */
  90 #define BI_ROUNDMODE (1 << 2)
  91
  92 /* Can be scheduled to FMA */
  93 #define BI_SCHED_FMA (1 << 3)
  94
  95 /* Can be scheduled to ADD */
  96 #define BI_SCHED_ADD (1 << 4)
  97
  98 /* Most ALU ops can do either, actually */
  99 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 100
 101 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 102  * nopped out. Used for _FAST operations. */
 103 #define BI_SCHED_SLOW (1 << 5)
 104
 105 /* Swizzling allowed for the 8/16-bit source */
 106 #define BI_SWIZZLABLE (1 << 6)
 107
 108 /* It can't get any worse than csel4... can it? */
 109 #define BIR_SRC_COUNT 4
 110
 111 /* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
 112 struct bi_load {
 113         /* Note: no indirects here */
 114         unsigned location;
 115
 116         /* Only for BI_LD_ATTR. But number of vector channels */
 117         unsigned channels;
 118 };
 119
 120 /* BI_LD_VARY */
 121 struct bi_load_vary {
 122         /* All parameters used here. Indirect location specified in
 123          * src1 and ignoring location, if present. */
 124         struct bi_load load;
 125
 126         enum bifrost_interp_mode interp_mode;
 127         bool reuse;
 128         bool flat;
 129 };
 130
 131 /* Opcodes within a class */
 132 enum bi_minmax_op {
 133         BI_MINMAX_MIN,
 134         BI_MINMAX_MAX
 135 };
 136
 137 enum bi_bitwise_op {
 138         BI_BITWISE_AND,
 139         BI_BITWISE_OR,
 140         BI_BITWISE_XOR
 141 };
 142
 143 enum bi_round_op {
 144         BI_ROUND_MODE, /* use round mode */
 145         BI_ROUND_ROUND /* i.e.: fround() */
 146 };
 147
 148 typedef struct {
 149         struct list_head link; /* Must be first */
 150         enum bi_class type;
 151
 152         /* Indices, see bir_ssa_index etc. Note zero is special cased
 153          * to "no argument" */
 154         unsigned dest;
 155         unsigned src[BIR_SRC_COUNT];
 156
 157         /* If one of the sources has BIR_INDEX_CONSTANT... Also, for
 158          * BI_EXTRACT, the component index is stored here. */
 159         union {
 160                 uint64_t u64;
 161                 uint32_t u32;
 162                 uint16_t u16[2];
 163                 uint8_t u8[4];
 164         } constant;
 165
 166         /* Floating-point modifiers, type/class permitting. If not
 167          * allowed for the type/class, these are ignored. */
 168         enum bifrost_outmod outmod;
 169         bool src_abs[BIR_SRC_COUNT];
 170         bool src_neg[BIR_SRC_COUNT];
 171
 172         /* Round mode (requires BI_ROUNDMODE) */
 173         enum bifrost_roundmode roundmode;
 174
 175         /* Destination type. Usually the type of the instruction
 176          * itself, but if sources and destination have different
 177          * types, the type of the destination wins (so f2i would be
 178          * int). Zero if there is no destination. Bitsize included */
 179         nir_alu_type dest_type;
 180
 181         /* Source types if required by the class */
 182         nir_alu_type src_types[BIR_SRC_COUNT];
 183
 184         /* If the source type is 8-bit or 16-bit such that SIMD is possible, and
 185          * the class has BI_SWIZZLABLE, this is a swizzle for the input. Swizzles
 186          * in practice only occur with one-source arguments (conversions,
 187          * dedicated swizzle ops) and as component selection on two-sources
 188          * where it is unambiguous which is which. Bounds are 32/type_size. */
 189         unsigned swizzle[4];
 190
 191         /* A class-specific op from which the actual opcode can be derived
 192          * (along with the above information) */
 193
 194         union {
 195                 enum bi_minmax_op minmax;
 196                 enum bi_bitwise_op bitwise;
 197                 enum bi_round_op round;
 198         } op;
 199
 200         /* Union for class-specific information */
 201         union {
 202                 enum bifrost_minmax_mode minmax;
 203                 struct bi_load load;
 204                 struct bi_load_vary load_vary;
 205         };
 206 } bi_instruction;
 207
 208 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 209  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 210  * within a clause into FMA/ADD pairs (bi_bundle).
 211  *
 212  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 213  * leave it NULL; the emitter will fill in a nop.
 214  */
 215
 216 typedef struct {
 217         bi_instruction *fma;
 218         bi_instruction *add;
 219 } bi_bundle;
 220
 221 typedef struct {
 222         struct list_head link;
 223
 224         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 225          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 226          * so a clause can have up to 16 bi_instructions. Whether bundles or
 227          * instructions are used depends on where in scheduling we are. */
 228
 229         unsigned instruction_count;
 230         unsigned bundle_count;
 231
 232         union {
 233                 bi_instruction *instructions[16];
 234                 bi_bundle bundles[8];
 235         };
 236
 237         /* For scoreboarding -- the clause ID (this is not globally unique!)
 238          * and its dependencies in terms of other clauses, computed during
 239          * scheduling and used when emitting code. Dependencies expressed as a
 240          * bitfield matching the hardware, except shifted by a clause (the
 241          * shift back to the ISA's off-by-one encoding is worked out when
 242          * emitting clauses) */
 243         unsigned scoreboard_id;
 244         uint8_t dependencies;
 245
 246         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 247          * conditional corresponds to the branch conditional bit except that in
 248          * the emitted code it's always set if back-to-bit is, whereas we use
 249          * the actual value (without back-to-back so to speak) internally */
 250         bool back_to_back;
 251         bool branch_conditional;
 252
 253         /* Corresponds to the usual bit but shifted by a clause */
 254         bool data_register_write_barrier;
 255 } bi_clause;
 256
 257 typedef struct bi_block {
 258         struct list_head link; /* must be first */
 259         unsigned name; /* Just for pretty-printing */
 260
 261         /* If true, uses clauses; if false, uses instructions */
 262         bool scheduled;
 263
 264         union {
 265                 struct list_head instructions; /* pre-schedule, list of bi_instructions */
 266                 struct list_head clauses; /* list of bi_clause */
 267         };
 268 } bi_block;
 269
 270 typedef struct {
 271        nir_shader *nir;
 272        struct list_head blocks; /* list of bi_block */
 273 } bi_context;
 274
 275 /* So we can distinguish between SSA/reg/sentinel quickly */
 276 #define BIR_NO_ARG (0)
 277 #define BIR_IS_REG (1)
 278
 279 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 280  * the low bits if necessary.
 281  *
 282  *  Fixed register: do not allocate register, do not collect $200.
 283  *  Uniform: access a uniform register given by low bits.
 284  *  Constant: access the specified constant
 285  *  Zero: special cased to avoid wasting a constant
 286  */
 287
 288 #define BIR_INDEX_REGISTER (1 << 31)
 289 #define BIR_INDEX_UNIFORM  (1 << 30)
 290 #define BIR_INDEX_CONSTANT (1 << 29)
 291 #define BIR_INDEX_ZERO     (1 << 28)
 292
 293 /* Keep me synced please so we can check src & BIR_SPECIAL */
 294
 295 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 296         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
 297
 298 static inline unsigned
 299 bir_ssa_index(nir_ssa_def *ssa)
 300 {
 301         /* Off-by-one ensures BIR_NO_ARG is skipped */
 302         return ((ssa->index + 1) << 1) | 0;
 303 }
 304
 305 static inline unsigned
 306 bir_src_index(nir_src *src)
 307 {
 308         if (src->is_ssa)
 309                 return bir_ssa_index(src->ssa);
 310         else {
 311                 assert(!src->reg.indirect);
 312                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 313         }
 314 }
 315
 316 static inline unsigned
 317 bir_dest_index(nir_dest *dst)
 318 {
 319         if (dst->is_ssa)
 320                 return bir_ssa_index(&dst->ssa);
 321         else {
 322                 assert(!dst->reg.indirect);
 323                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 324         }
 325 }
 326
 327 #endif