src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_COMBINE,
  57         BI_CONVERT,
  58         BI_CSEL,
  59         BI_DISCARD,
  60         BI_FMA,
  61         BI_FMOV,
  62         BI_FREXP,
  63         BI_ISUB,
  64         BI_LOAD,
  65         BI_LOAD_UNIFORM,
  66         BI_LOAD_ATTR,
  67         BI_LOAD_VAR,
  68         BI_LOAD_VAR_ADDRESS,
  69         BI_MINMAX,
  70         BI_MOV,
  71         BI_REDUCE_FMA,
  72         BI_SHIFT,
  73         BI_STORE,
  74         BI_STORE_VAR,
  75         BI_SPECIAL, /* _FAST on supported GPUs */
  76         BI_SWIZZLE,
  77         BI_TABLE,
  78         BI_TEX,
  79         BI_ROUND,
  80         BI_NUM_CLASSES
  81 };
  82
  83 /* Properties of a class... */
  84 extern unsigned bi_class_props[BI_NUM_CLASSES];
  85
  86 /* abs/neg/outmod valid for a float op */
  87 #define BI_MODS (1 << 0)
  88
  89 /* Generic enough that little class-specific information is required. In other
  90  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  91  * irregular enough to warrant a separate class */
  92 #define BI_GENERIC (1 << 1)
  93
  94 /* Accepts a bifrost_roundmode */
  95 #define BI_ROUNDMODE (1 << 2)
  96
  97 /* Can be scheduled to FMA */
  98 #define BI_SCHED_FMA (1 << 3)
  99
 100 /* Can be scheduled to ADD */
 101 #define BI_SCHED_ADD (1 << 4)
 102
 103 /* Most ALU ops can do either, actually */
 104 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 105
 106 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 107  * nopped out. Used for _FAST operations. */
 108 #define BI_SCHED_SLOW (1 << 5)
 109
 110 /* Swizzling allowed for the 8/16-bit source */
 111 #define BI_SWIZZLABLE (1 << 6)
 112
 113 /* For scheduling purposes this is a high latency instruction and must be at
 114  * the end of a clause. Implies ADD */
 115 #define BI_SCHED_HI_LATENCY (1 << 7)
 116
 117 /* Intrinsic is vectorized and should read 4 components in the first source
 118  * regardless of writemask */
 119 #define BI_VECTOR (1 << 8)
 120
 121 /* Use a data register for src0/dest respectively, bypassing the usual
 122  * register accessor. Mutually exclusive. */
 123 #define BI_DATA_REG_SRC (1 << 9)
 124 #define BI_DATA_REG_DEST (1 << 10)
 125
 126 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
 127 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
 128
 129 /* It can't get any worse than csel4... can it? */
 130 #define BIR_SRC_COUNT 4
 131
 132 /* BI_LD_VARY */
 133 struct bi_load_vary {
 134         enum bifrost_interp_mode interp_mode;
 135         bool reuse;
 136         bool flat;
 137 };
 138
 139 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 140  * the target. We forward declare bi_block since this is mildly circular (not
 141  * strictly, but this order of the file makes more sense I think)
 142  *
 143  * We define our own enum of conditions since the conditions in the hardware
 144  * packed in crazy ways that would make manipulation unweildly (meaning changes
 145  * based on port swapping, etc), so we defer dealing with that until emit time.
 146  * Likewise, we expose NIR types instead of the crazy branch types, although
 147  * the restrictions do eventually apply of course. */
 148
 149 struct bi_block;
 150
 151 enum bi_cond {
 152         BI_COND_ALWAYS,
 153         BI_COND_LT,
 154         BI_COND_LE,
 155         BI_COND_GE,
 156         BI_COND_GT,
 157         BI_COND_EQ,
 158         BI_COND_NE,
 159 };
 160
 161 struct bi_branch {
 162         /* Types are specified in src_types and must be compatible (either both
 163          * int, or both float, 16/32, and same size or 32/16 if float. Types
 164          * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
 165
 166         enum bi_cond cond;
 167         struct bi_block *target;
 168 };
 169
 170 /* Opcodes within a class */
 171 enum bi_minmax_op {
 172         BI_MINMAX_MIN,
 173         BI_MINMAX_MAX
 174 };
 175
 176 enum bi_bitwise_op {
 177         BI_BITWISE_AND,
 178         BI_BITWISE_OR,
 179         BI_BITWISE_XOR
 180 };
 181
 182 enum bi_round_op {
 183         BI_ROUND_MODE, /* use round mode */
 184         BI_ROUND_ROUND /* i.e.: fround() */
 185 };
 186
 187 enum bi_table_op {
 188         /* fp32 log2() with low precision, suitable for GL or half_log2() in
 189          * CL. In the first argument, takes x. Letting u be such that x =
 190          * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
 191          * log2(u) / (u - 1). */
 192
 193         BI_TABLE_LOG2_U_OVER_U_1_LOW,
 194 };
 195
 196 enum bi_reduce_op {
 197         /* Takes two fp32 arguments and returns x + frexp(y). Used in
 198          * low-precision log2 argument reduction on newer models. */
 199
 200         BI_REDUCE_ADD_FREXPM,
 201 };
 202
 203 enum bi_frexp_op {
 204         BI_FREXPE_LOG,
 205 };
 206
 207 enum bi_special_op {
 208         BI_SPECIAL_FRCP,
 209         BI_SPECIAL_FRSQ,
 210
 211         /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
 212          * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
 213          * the second, it takes x itself. */
 214         BI_SPECIAL_EXP2_LOW,
 215 };
 216
 217 typedef struct {
 218         struct list_head link; /* Must be first */
 219         enum bi_class type;
 220
 221         /* Indices, see bir_ssa_index etc. Note zero is special cased
 222          * to "no argument" */
 223         unsigned dest;
 224         unsigned src[BIR_SRC_COUNT];
 225
 226         /* If one of the sources has BIR_INDEX_CONSTANT */
 227         union {
 228                 uint64_t u64;
 229                 uint32_t u32;
 230                 uint16_t u16[2];
 231                 uint8_t u8[4];
 232         } constant;
 233
 234         /* Floating-point modifiers, type/class permitting. If not
 235          * allowed for the type/class, these are ignored. */
 236         enum bifrost_outmod outmod;
 237         bool src_abs[BIR_SRC_COUNT];
 238         bool src_neg[BIR_SRC_COUNT];
 239
 240         /* Round mode (requires BI_ROUNDMODE) */
 241         enum bifrost_roundmode roundmode;
 242
 243         /* Writemask (bit for each affected byte). This is quite restricted --
 244          * ALU ops can only write to a single channel (exception: <32 in which
 245          * you can write to 32/N contiguous aligned channels). Load/store can
 246          * only write to all channels at once, in a sense. But it's still
 247          * better to use this generic form than have synthetic ops flying
 248          * about, since we're not essentially vector for RA purposes. */
 249         uint16_t writemask;
 250
 251         /* Destination type. Usually the type of the instruction
 252          * itself, but if sources and destination have different
 253          * types, the type of the destination wins (so f2i would be
 254          * int). Zero if there is no destination. Bitsize included */
 255         nir_alu_type dest_type;
 256
 257         /* Source types if required by the class */
 258         nir_alu_type src_types[BIR_SRC_COUNT];
 259
 260         /* If the source type is 8-bit or 16-bit such that SIMD is possible,
 261          * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
 262          * sense. On non-SIMD instructions, it can be used for component
 263          * selection, so we don't have to special case extraction. */
 264         uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
 265
 266         /* A class-specific op from which the actual opcode can be derived
 267          * (along with the above information) */
 268
 269         union {
 270                 enum bi_minmax_op minmax;
 271                 enum bi_bitwise_op bitwise;
 272                 enum bi_round_op round;
 273                 enum bi_special_op special;
 274                 enum bi_reduce_op reduce;
 275                 enum bi_table_op table;
 276                 enum bi_frexp_op frexp;
 277                 enum bi_cond compare;
 278         } op;
 279
 280         /* Union for class-specific information */
 281         union {
 282                 enum bifrost_minmax_mode minmax;
 283                 struct bi_load_vary load_vary;
 284                 struct bi_branch branch;
 285
 286                 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
 287                  * sense here but you can always just use a move for that */
 288                 enum bi_cond csel_cond;
 289
 290                 /* For BLEND -- the location 0-7 */
 291                 unsigned blend_location;
 292
 293                 /* For STORE, STORE_VAR -- channel count */
 294                 unsigned store_channels;
 295         };
 296 } bi_instruction;
 297
 298 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 299  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 300  * within a clause into FMA/ADD pairs (bi_bundle).
 301  *
 302  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 303  * leave it NULL; the emitter will fill in a nop.
 304  */
 305
 306 typedef struct {
 307         bi_instruction *fma;
 308         bi_instruction *add;
 309 } bi_bundle;
 310
 311 typedef struct {
 312         struct list_head link;
 313
 314         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 315          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 316          * so a clause can have up to 16 bi_instructions. Whether bundles or
 317          * instructions are used depends on where in scheduling we are. */
 318
 319         unsigned instruction_count;
 320         unsigned bundle_count;
 321
 322         union {
 323                 bi_instruction *instructions[16];
 324                 bi_bundle bundles[8];
 325         };
 326
 327         /* For scoreboarding -- the clause ID (this is not globally unique!)
 328          * and its dependencies in terms of other clauses, computed during
 329          * scheduling and used when emitting code. Dependencies expressed as a
 330          * bitfield matching the hardware, except shifted by a clause (the
 331          * shift back to the ISA's off-by-one encoding is worked out when
 332          * emitting clauses) */
 333         unsigned scoreboard_id;
 334         uint8_t dependencies;
 335
 336         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 337          * conditional corresponds to the branch conditional bit except that in
 338          * the emitted code it's always set if back-to-bit is, whereas we use
 339          * the actual value (without back-to-back so to speak) internally */
 340         bool back_to_back;
 341         bool branch_conditional;
 342
 343         /* Assigned data register */
 344         unsigned data_register;
 345
 346         /* Corresponds to the usual bit but shifted by a clause */
 347         bool data_register_write_barrier;
 348
 349         /* Constants read by this clause. ISA limit. */
 350         uint64_t constants[8];
 351         unsigned constant_count;
 352
 353         /* What type of high latency instruction is here, basically */
 354         unsigned clause_type;
 355 } bi_clause;
 356
 357 typedef struct bi_block {
 358         pan_block base; /* must be first */
 359
 360         /* If true, uses clauses; if false, uses instructions */
 361         bool scheduled;
 362         struct list_head clauses; /* list of bi_clause */
 363 } bi_block;
 364
 365 typedef struct {
 366        nir_shader *nir;
 367        gl_shader_stage stage;
 368        struct list_head blocks; /* list of bi_block */
 369        struct panfrost_sysvals sysvals;
 370        uint32_t quirks;
 371
 372        /* During NIR->BIR */
 373        nir_function_impl *impl;
 374        bi_block *current_block;
 375        unsigned block_name_count;
 376        bi_block *after_block;
 377        bi_block *break_block;
 378        bi_block *continue_block;
 379        bool emitted_atest;
 380
 381        /* For creating temporaries */
 382        unsigned temp_alloc;
 383
 384        /* Analysis results */
 385        bool has_liveness;
 386
 387        /* Stats for shader-db */
 388        unsigned instruction_count;
 389        unsigned loop_count;
 390 } bi_context;
 391
 392 static inline bi_instruction *
 393 bi_emit(bi_context *ctx, bi_instruction ins)
 394 {
 395         bi_instruction *u = rzalloc(ctx, bi_instruction);
 396         memcpy(u, &ins, sizeof(ins));
 397         list_addtail(&u->link, &ctx->current_block->base.instructions);
 398         return u;
 399 }
 400
 401 static inline bi_instruction *
 402 bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
 403 {
 404         bi_instruction *u = rzalloc(ctx, bi_instruction);
 405         memcpy(u, &ins, sizeof(ins));
 406         list_addtail(&u->link, &tag->link);
 407         return u;
 408 }
 409
 410 static inline void
 411 bi_remove_instruction(bi_instruction *ins)
 412 {
 413         list_del(&ins->link);
 414 }
 415
 416 /* So we can distinguish between SSA/reg/sentinel quickly */
 417 #define BIR_NO_ARG (0)
 418 #define BIR_IS_REG (1)
 419
 420 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 421  * the low bits if necessary.
 422  *
 423  *  Fixed register: do not allocate register, do not collect $200.
 424  *  Uniform: access a uniform register given by low bits.
 425  *  Constant: access the specified constant (specifies a bit offset / shift)
 426  *  Zero: special cased to avoid wasting a constant
 427  *  Passthrough: a bifrost_packed_src to passthrough T/T0/T1
 428  */
 429
 430 #define BIR_INDEX_REGISTER (1 << 31)
 431 #define BIR_INDEX_UNIFORM  (1 << 30)
 432 #define BIR_INDEX_CONSTANT (1 << 29)
 433 #define BIR_INDEX_ZERO     (1 << 28)
 434 #define BIR_INDEX_PASS     (1 << 27)
 435
 436 /* Keep me synced please so we can check src & BIR_SPECIAL */
 437
 438 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 439         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
 440
 441 static inline unsigned
 442 bi_max_temp(bi_context *ctx)
 443 {
 444         unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
 445         return ((alloc + 2 + ctx->temp_alloc) << 1);
 446 }
 447
 448 static inline unsigned
 449 bi_make_temp(bi_context *ctx)
 450 {
 451         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 452 }
 453
 454 static inline unsigned
 455 bi_make_temp_reg(bi_context *ctx)
 456 {
 457         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG;
 458 }
 459
 460 static inline unsigned
 461 bir_ssa_index(nir_ssa_def *ssa)
 462 {
 463         /* Off-by-one ensures BIR_NO_ARG is skipped */
 464         return ((ssa->index + 1) << 1) | 0;
 465 }
 466
 467 static inline unsigned
 468 bir_src_index(nir_src *src)
 469 {
 470         if (src->is_ssa)
 471                 return bir_ssa_index(src->ssa);
 472         else {
 473                 assert(!src->reg.indirect);
 474                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 475         }
 476 }
 477
 478 static inline unsigned
 479 bir_dest_index(nir_dest *dst)
 480 {
 481         if (dst->is_ssa)
 482                 return bir_ssa_index(&dst->ssa);
 483         else {
 484                 assert(!dst->reg.indirect);
 485                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 486         }
 487 }
 488
 489 /* Iterators for Bifrost IR */
 490
 491 #define bi_foreach_block(ctx, v) \
 492         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 493
 494 #define bi_foreach_block_from(ctx, from, v) \
 495         list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
 496
 497 #define bi_foreach_instr_in_block(block, v) \
 498         list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
 499
 500 #define bi_foreach_instr_in_block_rev(block, v) \
 501         list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
 502
 503 #define bi_foreach_instr_in_block_safe(block, v) \
 504         list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
 505
 506 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 507         list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
 508
 509 #define bi_foreach_instr_in_block_from(block, v, from) \
 510         list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
 511
 512 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 513         list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
 514
 515 #define bi_foreach_clause_in_block(block, v) \
 516         list_for_each_entry(bi_clause, v, &(block)->clauses, link)
 517
 518 #define bi_foreach_instr_global(ctx, v) \
 519         bi_foreach_block(ctx, v_block) \
 520                 bi_foreach_instr_in_block((bi_block *) v_block, v)
 521
 522 #define bi_foreach_instr_global_safe(ctx, v) \
 523         bi_foreach_block(ctx, v_block) \
 524                 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
 525
 526 /* Based on set_foreach, expanded with automatic type casts */
 527
 528 #define bi_foreach_predecessor(blk, v) \
 529         struct set_entry *_entry_##v; \
 530         bi_block *v; \
 531         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 532                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 533                 _entry_##v != NULL; \
 534                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 535                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 536
 537 #define bi_foreach_src(ins, v) \
 538         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 539
 540 static inline bi_instruction *
 541 bi_prev_op(bi_instruction *ins)
 542 {
 543         return list_last_entry(&(ins->link), bi_instruction, link);
 544 }
 545
 546 static inline bi_instruction *
 547 bi_next_op(bi_instruction *ins)
 548 {
 549         return list_first_entry(&(ins->link), bi_instruction, link);
 550 }
 551
 552 static inline pan_block *
 553 pan_next_block(pan_block *block)
 554 {
 555         return list_first_entry(&(block->link), pan_block, link);
 556 }
 557
 558 /* BIR manipulation */
 559
 560 bool bi_has_outmod(bi_instruction *ins);
 561 bool bi_has_source_mods(bi_instruction *ins);
 562 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 563 bool bi_has_arg(bi_instruction *ins, unsigned arg);
 564 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
 565 unsigned bi_get_component_count(bi_instruction *ins, unsigned s);
 566 unsigned bi_load32_components(bi_instruction *ins);
 567 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
 568 uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
 569 bool bi_writes_component(bi_instruction *ins, unsigned comp);
 570
 571 /* BIR passes */
 572
 573 void bi_lower_combine(bi_context *ctx, bi_block *block);
 574 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
 575 void bi_schedule(bi_context *ctx);
 576 void bi_register_allocate(bi_context *ctx);
 577
 578 /* Liveness */
 579
 580 void bi_compute_liveness(bi_context *ctx);
 581 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
 582 void bi_invalidate_liveness(bi_context *ctx);
 583 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
 584
 585 /* Code emit */
 586
 587 void bi_pack(bi_context *ctx, struct util_dynarray *emission);
 588
 589 #endif