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7169df85108859f0518af2ece1d0283f90f18900
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "disassemble.h"
35 #include "bi_print_common.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 static unsigned get_reg0(struct bifrost_regs regs)
56 {
57 if (regs.ctrl == 0)
58 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
59
60 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
61 }
62
63 static unsigned get_reg1(struct bifrost_regs regs)
64 {
65 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
66 }
67
68 // this represents the decoded version of the ctrl register field.
69 struct bifrost_reg_ctrl {
70 bool read_reg0;
71 bool read_reg1;
72 bool read_reg3;
73 enum bifrost_reg_write_unit fma_write_unit;
74 enum bifrost_reg_write_unit add_write_unit;
75 bool clause_start;
76 };
77
78 enum fma_src_type {
79 FMA_ONE_SRC,
80 FMA_TWO_SRC,
81 FMA_FADD,
82 FMA_FMINMAX,
83 FMA_FADD16,
84 FMA_FMINMAX16,
85 FMA_FCMP,
86 FMA_FCMP16,
87 FMA_THREE_SRC,
88 FMA_SHIFT,
89 FMA_FMA,
90 FMA_FMA16,
91 FMA_CSEL4,
92 FMA_FMA_MSCALE,
93 FMA_SHIFT_ADD64,
94 };
95
96 struct fma_op_info {
97 bool extended;
98 unsigned op;
99 char name[30];
100 enum fma_src_type src_type;
101 };
102
103 enum add_src_type {
104 ADD_ONE_SRC,
105 ADD_TWO_SRC,
106 ADD_FADD,
107 ADD_FMINMAX,
108 ADD_FADD16,
109 ADD_FMINMAX16,
110 ADD_THREE_SRC,
111 ADD_SHIFT,
112 ADD_FADDMscale,
113 ADD_FCMP,
114 ADD_FCMP16,
115 ADD_TEX_COMPACT, // texture instruction with embedded sampler
116 ADD_TEX, // texture instruction with sampler/etc. in uniform port
117 ADD_VARYING_INTERP,
118 ADD_BLENDING,
119 ADD_LOAD_ATTR,
120 ADD_VARYING_ADDRESS,
121 ADD_BRANCH,
122 };
123
124 struct add_op_info {
125 unsigned op;
126 char name[30];
127 enum add_src_type src_type;
128 bool has_data_reg;
129 };
130
131 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
132 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
133 struct bifrost_regs next_regs, uint64_t *consts,
134 unsigned data_reg, unsigned offset, bool verbose);
135 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
136
137 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
138 {
139 fprintf(fp, "id(%du) ", header.scoreboard_index);
140
141 if (header.clause_type != 0) {
142 const char *name = bi_clause_type_name(header.clause_type);
143
144 if (name[0] == '?')
145 fprintf(fp, "unk%u ", header.clause_type);
146 else
147 fprintf(fp, "%s ", name);
148 }
149
150 if (header.scoreboard_deps != 0) {
151 fprintf(fp, "next-wait(");
152 bool first = true;
153 for (unsigned i = 0; i < 8; i++) {
154 if (header.scoreboard_deps & (1 << i)) {
155 if (!first) {
156 fprintf(fp, ", ");
157 }
158 fprintf(fp, "%d", i);
159 first = false;
160 }
161 }
162 fprintf(fp, ") ");
163 }
164
165 if (header.datareg_writebarrier)
166 fprintf(fp, "data-reg-barrier ");
167
168 if (!header.no_end_of_shader)
169 fprintf(fp, "eos ");
170
171 if (!header.back_to_back) {
172 fprintf(fp, "nbb ");
173 if (header.branch_cond)
174 fprintf(fp, "branch-cond ");
175 else
176 fprintf(fp, "branch-uncond ");
177 }
178
179 if (header.elide_writes)
180 fprintf(fp, "we ");
181
182 if (header.suppress_inf)
183 fprintf(fp, "suppress-inf ");
184 if (header.suppress_nan)
185 fprintf(fp, "suppress-nan ");
186
187 if (header.unk0)
188 fprintf(fp, "unk0 ");
189 if (header.unk1)
190 fprintf(fp, "unk1 ");
191 if (header.unk2)
192 fprintf(fp, "unk2 ");
193 if (header.unk3)
194 fprintf(fp, "unk3 ");
195 if (header.unk4)
196 fprintf(fp, "unk4 ");
197
198 fprintf(fp, "\n");
199
200 if (verbose) {
201 fprintf(fp, "# clause type %d, next clause type %d\n",
202 header.clause_type, header.next_clause_type);
203 }
204 }
205
206 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
207 {
208 struct bifrost_reg_ctrl decoded = {};
209 unsigned ctrl;
210 if (regs.ctrl == 0) {
211 ctrl = regs.reg1 >> 2;
212 decoded.read_reg0 = !(regs.reg1 & 0x2);
213 decoded.read_reg1 = false;
214 } else {
215 ctrl = regs.ctrl;
216 decoded.read_reg0 = decoded.read_reg1 = true;
217 }
218 switch (ctrl) {
219 case 1:
220 decoded.fma_write_unit = REG_WRITE_TWO;
221 break;
222 case 2:
223 case 3:
224 decoded.fma_write_unit = REG_WRITE_TWO;
225 decoded.read_reg3 = true;
226 break;
227 case 4:
228 decoded.read_reg3 = true;
229 break;
230 case 5:
231 decoded.add_write_unit = REG_WRITE_TWO;
232 break;
233 case 6:
234 decoded.add_write_unit = REG_WRITE_TWO;
235 decoded.read_reg3 = true;
236 break;
237 case 8:
238 decoded.clause_start = true;
239 break;
240 case 9:
241 decoded.fma_write_unit = REG_WRITE_TWO;
242 decoded.clause_start = true;
243 break;
244 case 11:
245 break;
246 case 12:
247 decoded.read_reg3 = true;
248 decoded.clause_start = true;
249 break;
250 case 13:
251 decoded.add_write_unit = REG_WRITE_TWO;
252 decoded.clause_start = true;
253 break;
254
255 case 7:
256 case 15:
257 decoded.fma_write_unit = REG_WRITE_THREE;
258 decoded.add_write_unit = REG_WRITE_TWO;
259 break;
260 default:
261 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
262 }
263
264 return decoded;
265 }
266
267 // Pass in the add_write_unit or fma_write_unit, and this returns which register
268 // the ADD/FMA units are writing to
269 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
270 {
271 switch (unit) {
272 case REG_WRITE_TWO:
273 return regs.reg2;
274 case REG_WRITE_THREE:
275 return regs.reg3;
276 default: /* REG_WRITE_NONE */
277 assert(0);
278 return 0;
279 }
280 }
281
282 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
283 {
284 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
285 fprintf(fp, "# ");
286 if (ctrl.read_reg0)
287 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
288 if (ctrl.read_reg1)
289 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
290
291 if (ctrl.fma_write_unit == REG_WRITE_TWO)
292 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
293 else if (ctrl.add_write_unit == REG_WRITE_TWO)
294 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
295
296 if (ctrl.fma_write_unit == REG_WRITE_THREE)
297 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
298 else if (ctrl.add_write_unit == REG_WRITE_THREE)
299 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
300 else if (ctrl.read_reg3)
301 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
302
303 if (srcs.uniform_const) {
304 if (srcs.uniform_const & 0x80) {
305 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
306 }
307 }
308
309 fprintf(fp, "\n");
310 }
311 static void dump_const_imm(FILE *fp, uint32_t imm)
312 {
313 union {
314 float f;
315 uint32_t i;
316 } fi;
317 fi.i = imm;
318 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
319 }
320
321 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
322 {
323 unsigned low_bits = srcs.uniform_const & 0xf;
324 uint64_t imm;
325 switch (srcs.uniform_const >> 4) {
326 case 4:
327 imm = consts[0];
328 break;
329 case 5:
330 imm = consts[1];
331 break;
332 case 6:
333 imm = consts[2];
334 break;
335 case 7:
336 imm = consts[3];
337 break;
338 case 2:
339 imm = consts[4];
340 break;
341 case 3:
342 imm = consts[5];
343 break;
344 default:
345 assert(0);
346 break;
347 }
348 return imm | low_bits;
349 }
350
351 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
352 {
353 if (srcs.uniform_const & 0x80) {
354 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
355 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
356 } else if (srcs.uniform_const >= 0x20) {
357 uint64_t imm = get_const(consts, srcs);
358 if (high32)
359 dump_const_imm(fp, imm >> 32);
360 else
361 dump_const_imm(fp, imm);
362 } else {
363 switch (srcs.uniform_const) {
364 case 0:
365 fprintf(fp, "0");
366 break;
367 case 5:
368 fprintf(fp, "atest-data");
369 break;
370 case 6:
371 fprintf(fp, "sample-ptr");
372 break;
373 case 8:
374 case 9:
375 case 10:
376 case 11:
377 case 12:
378 case 13:
379 case 14:
380 case 15:
381 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
382 break;
383 default:
384 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
385 break;
386 }
387
388 if (high32)
389 fprintf(fp, ".y");
390 else
391 fprintf(fp, ".x");
392 }
393 }
394
395 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
396 {
397 switch (src) {
398 case 0:
399 fprintf(fp, "R%d", get_reg0(srcs));
400 break;
401 case 1:
402 fprintf(fp, "R%d", get_reg1(srcs));
403 break;
404 case 2:
405 fprintf(fp, "R%d", srcs.reg3);
406 break;
407 case 3:
408 if (isFMA)
409 fprintf(fp, "0");
410 else
411 fprintf(fp, "T"); // i.e. the output of FMA this cycle
412 break;
413 case 4:
414 dump_uniform_const_src(fp, srcs, consts, false);
415 break;
416 case 5:
417 dump_uniform_const_src(fp, srcs, consts, true);
418 break;
419 case 6:
420 fprintf(fp, "T0");
421 break;
422 case 7:
423 fprintf(fp, "T1");
424 break;
425 }
426 }
427
428 static const struct fma_op_info FMAOpInfos[] = {
429 { false, 0x00000, "FMA.f32", FMA_FMA },
430 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
431 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
432 { false, 0x48000, "FCMP.GL", FMA_FCMP },
433 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
434 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
435 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
436 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
437 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
438 { false, 0x58000, "ADD.f32", FMA_FADD },
439 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
440 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
441 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
442 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
443 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
444 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
445 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
446 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
447 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
448 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
449 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
450 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
451 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
452 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
453 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
454 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
455 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
456 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
457 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
458 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
459 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
460 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
461 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
462 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
463 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
464 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
465 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
466 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
467 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
468 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
469 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
470 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
471 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
472 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
473 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
474 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
475 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
476 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
477 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
478 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
479 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
480 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
481 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
482 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
483
484 /* TODO: Combine to bifrost_fma_f2i_i2f16 */
485 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
486 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
487 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
488 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
489 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
490 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
491 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
492 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
493 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
494 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
495 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
496 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
497 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
498 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
499 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
500 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
501
502 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
503 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
504 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
505 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
506
507 /* TODO: cleanup to use bifrost_fma_int16_to_32 */
508 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
509 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
510 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
511 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
512 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
513 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
514 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
515 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
516
517 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
518 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
519
520 { true, 0x0032c, "NOP", FMA_ONE_SRC },
521 { true, 0x0032d, "MOV", FMA_ONE_SRC },
522 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
523 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
524 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
525 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
526 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
527 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
528 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
529 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
530 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
531 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
532 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
533 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
534 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
535 { true, 0x00ec2, "ROUND.v2f16", FMA_ONE_SRC },
536 { true, 0x00ec5, "ROUND.f32", FMA_ONE_SRC },
537 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
538 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
539 { true, 0x01802, "ROUNDEVEN.v2f16", FMA_ONE_SRC },
540 { true, 0x01805, "ROUNDEVEN.f32", FMA_ONE_SRC },
541 { true, 0x01842, "CEIL.v2f16", FMA_ONE_SRC },
542 { true, 0x01845, "CEIL.f32", FMA_ONE_SRC },
543 { true, 0x01882, "FLOOR.v2f16", FMA_ONE_SRC },
544 { true, 0x01885, "FLOOR.f32", FMA_ONE_SRC },
545 { true, 0x018c2, "TRUNC.v2f16", FMA_ONE_SRC },
546 { true, 0x018c5, "TRUNC.f32", FMA_ONE_SRC },
547 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
548 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
549 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
550 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
551 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
552 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
553 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
554 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
555 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
556 { true, 0x01e80, "ADD_FREXPM.f32", FMA_TWO_SRC },
557 { true, 0x02000, "SWZ.XXXX.v4i8", FMA_ONE_SRC },
558 { true, 0x03e00, "SWZ.ZZZZ.v4i8", FMA_ONE_SRC },
559 { true, 0x00800, "IMAD", FMA_THREE_SRC },
560 { true, 0x07818, "MUL.i32", FMA_TWO_SRC },
561 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
562 };
563
564 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
565 {
566 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
567 unsigned opCmp = ~0;
568
569 if (FMAOpInfos[i].extended != extended)
570 continue;
571
572 if (extended)
573 op &= ~0xe0000;
574
575 switch (FMAOpInfos[i].src_type) {
576 case FMA_ONE_SRC:
577 opCmp = op;
578 break;
579 case FMA_TWO_SRC:
580 opCmp = op & ~0x7;
581 break;
582 case FMA_FCMP:
583 case FMA_FCMP16:
584 opCmp = op & ~0x1fff;
585 break;
586 case FMA_THREE_SRC:
587 case FMA_SHIFT_ADD64:
588 opCmp = op & ~0x3f;
589 break;
590 case FMA_FADD:
591 case FMA_FMINMAX:
592 case FMA_FADD16:
593 case FMA_FMINMAX16:
594 opCmp = op & ~0x3fff;
595 break;
596 case FMA_FMA:
597 case FMA_FMA16:
598 opCmp = op & ~0x3ffff;
599 break;
600 case FMA_CSEL4:
601 case FMA_SHIFT:
602 opCmp = op & ~0xfff;
603 break;
604 case FMA_FMA_MSCALE:
605 opCmp = op & ~0x7fff;
606 break;
607 default:
608 opCmp = ~0;
609 break;
610 }
611 if (FMAOpInfos[i].op == opCmp)
612 return FMAOpInfos[i];
613 }
614
615 struct fma_op_info info;
616 snprintf(info.name, sizeof(info.name), "op%04x", op);
617 info.extended = extended;
618 info.op = op;
619 info.src_type = FMA_THREE_SRC;
620 return info;
621 }
622
623 static void dump_fcmp(FILE *fp, unsigned op)
624 {
625 switch (op) {
626 case 0:
627 fprintf(fp, ".OEQ");
628 break;
629 case 1:
630 fprintf(fp, ".OGT");
631 break;
632 case 2:
633 fprintf(fp, ".OGE");
634 break;
635 case 3:
636 fprintf(fp, ".UNE");
637 break;
638 case 4:
639 fprintf(fp, ".OLT");
640 break;
641 case 5:
642 fprintf(fp, ".OLE");
643 break;
644 default:
645 fprintf(fp, ".unk%d", op);
646 break;
647 }
648 }
649
650 static void dump_16swizzle(FILE *fp, unsigned swiz)
651 {
652 if (swiz == 2)
653 return;
654 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
655 }
656
657 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
658 {
659 switch (ctrl) {
660 case 3:
661 case 4:
662 case 6:
663 fprintf(fp, ".x");
664 break;
665 case 5:
666 case 7:
667 fprintf(fp, ".y");
668 break;
669 case 0:
670 case 1:
671 case 2:
672 break;
673 default:
674 fprintf(fp, ".unk");
675 break;
676 }
677 }
678
679 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
680 {
681 switch (ctrl) {
682 case 1:
683 case 3:
684 fprintf(fp, ".x");
685 break;
686 case 2:
687 case 4:
688 case 5:
689 fprintf(fp, ".y");
690 break;
691 case 0:
692 case 6:
693 case 7:
694 break;
695 default:
696 fprintf(fp, ".unk");
697 break;
698 }
699 }
700
701 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
702 {
703 if (verbose) {
704 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
705 }
706 struct bifrost_fma_inst FMA;
707 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
708 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
709
710 fprintf(fp, "%s", info.name);
711 if (info.src_type == FMA_FADD ||
712 info.src_type == FMA_FMINMAX ||
713 info.src_type == FMA_FMA ||
714 info.src_type == FMA_FADD16 ||
715 info.src_type == FMA_FMINMAX16 ||
716 info.src_type == FMA_FMA16) {
717 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 12, 14)));
718 switch (info.src_type) {
719 case FMA_FADD:
720 case FMA_FMA:
721 case FMA_FADD16:
722 case FMA_FMA16:
723 fprintf(fp, "%s", bi_round_mode_name(bits(FMA.op, 10, 12)));
724 break;
725 case FMA_FMINMAX:
726 case FMA_FMINMAX16:
727 fprintf(fp, "%s", bi_minmax_mode_name(bits(FMA.op, 10, 12)));
728 break;
729 default:
730 assert(0);
731 }
732 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
733 dump_fcmp(fp, bits(FMA.op, 10, 13));
734 if (info.src_type == FMA_FCMP)
735 fprintf(fp, ".f32");
736 else
737 fprintf(fp, ".v2f16");
738 } else if (info.src_type == FMA_FMA_MSCALE) {
739 if (FMA.op & (1 << 11)) {
740 switch ((FMA.op >> 9) & 0x3) {
741 case 0:
742 /* This mode seems to do a few things:
743 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
744 * since generating a nan would poison the result of
745 * 1/infinity and 1/0.
746 * - Fiddles with which nan is returned in nan * nan,
747 * presumably to make sure that the same exact nan is
748 * returned for 1/nan.
749 */
750 fprintf(fp, ".rcp_mode");
751 break;
752 case 3:
753 /* Similar to the above, but src0 always wins when multiplying
754 * 0 by infinity.
755 */
756 fprintf(fp, ".sqrt_mode");
757 break;
758 default:
759 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
760 }
761 } else {
762 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 9, 11)));
763 }
764 } else if (info.src_type == FMA_SHIFT) {
765 struct bifrost_shift_fma shift;
766 memcpy(&shift, &FMA, sizeof(shift));
767
768 if (shift.half == 0x7)
769 fprintf(fp, ".v2i16");
770 else if (shift.half == 0)
771 fprintf(fp, ".i32");
772 else if (shift.half == 0x4)
773 fprintf(fp, ".v4i8");
774 else
775 fprintf(fp, ".unk%u", shift.half);
776
777 if (!shift.unk)
778 fprintf(fp, ".no_unk");
779
780 if (shift.invert_1)
781 fprintf(fp, ".invert_1");
782
783 if (shift.invert_2)
784 fprintf(fp, ".invert_2");
785 }
786
787 fprintf(fp, " ");
788
789 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
790 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
791 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
792 } else {
793 fprintf(fp, "T0, ");
794 }
795
796 switch (info.src_type) {
797 case FMA_ONE_SRC:
798 dump_src(fp, FMA.src0, regs, consts, true);
799 break;
800 case FMA_TWO_SRC:
801 dump_src(fp, FMA.src0, regs, consts, true);
802 fprintf(fp, ", ");
803 dump_src(fp, FMA.op & 0x7, regs, consts, true);
804 break;
805 case FMA_FADD:
806 case FMA_FMINMAX:
807 if (FMA.op & 0x10)
808 fprintf(fp, "-");
809 if (FMA.op & 0x200)
810 fprintf(fp, "abs(");
811 dump_src(fp, FMA.src0, regs, consts, true);
812 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
813 if (FMA.op & 0x200)
814 fprintf(fp, ")");
815 fprintf(fp, ", ");
816 if (FMA.op & 0x20)
817 fprintf(fp, "-");
818 if (FMA.op & 0x8)
819 fprintf(fp, "abs(");
820 dump_src(fp, FMA.op & 0x7, regs, consts, true);
821 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
822 if (FMA.op & 0x8)
823 fprintf(fp, ")");
824 break;
825 case FMA_FADD16:
826 case FMA_FMINMAX16: {
827 bool abs1 = FMA.op & 0x8;
828 bool abs2 = (FMA.op & 0x7) < FMA.src0;
829 if (FMA.op & 0x10)
830 fprintf(fp, "-");
831 if (abs1 || abs2)
832 fprintf(fp, "abs(");
833 dump_src(fp, FMA.src0, regs, consts, true);
834 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
835 if (abs1 || abs2)
836 fprintf(fp, ")");
837 fprintf(fp, ", ");
838 if (FMA.op & 0x20)
839 fprintf(fp, "-");
840 if (abs1 && abs2)
841 fprintf(fp, "abs(");
842 dump_src(fp, FMA.op & 0x7, regs, consts, true);
843 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
844 if (abs1 && abs2)
845 fprintf(fp, ")");
846 break;
847 }
848 case FMA_FCMP:
849 if (FMA.op & 0x200)
850 fprintf(fp, "abs(");
851 dump_src(fp, FMA.src0, regs, consts, true);
852 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
853 if (FMA.op & 0x200)
854 fprintf(fp, ")");
855 fprintf(fp, ", ");
856 if (FMA.op & 0x20)
857 fprintf(fp, "-");
858 if (FMA.op & 0x8)
859 fprintf(fp, "abs(");
860 dump_src(fp, FMA.op & 0x7, regs, consts, true);
861 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
862 if (FMA.op & 0x8)
863 fprintf(fp, ")");
864 break;
865 case FMA_FCMP16:
866 dump_src(fp, FMA.src0, regs, consts, true);
867 // Note: this is kinda a guess, I haven't seen the blob set this to
868 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
869 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
870 fprintf(fp, ", ");
871 dump_src(fp, FMA.op & 0x7, regs, consts, true);
872 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
873 break;
874 case FMA_SHIFT_ADD64:
875 dump_src(fp, FMA.src0, regs, consts, true);
876 fprintf(fp, ", ");
877 dump_src(fp, FMA.op & 0x7, regs, consts, true);
878 fprintf(fp, ", ");
879 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
880 break;
881 case FMA_THREE_SRC:
882 dump_src(fp, FMA.src0, regs, consts, true);
883 fprintf(fp, ", ");
884 dump_src(fp, FMA.op & 0x7, regs, consts, true);
885 fprintf(fp, ", ");
886 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
887 break;
888 case FMA_SHIFT: {
889 struct bifrost_shift_fma shift;
890 memcpy(&shift, &FMA, sizeof(shift));
891
892 dump_src(fp, shift.src0, regs, consts, true);
893 fprintf(fp, ", ");
894 dump_src(fp, shift.src1, regs, consts, true);
895 fprintf(fp, ", ");
896 dump_src(fp, shift.src2, regs, consts, true);
897 break;
898 }
899 case FMA_FMA:
900 if (FMA.op & (1 << 14))
901 fprintf(fp, "-");
902 if (FMA.op & (1 << 9))
903 fprintf(fp, "abs(");
904 dump_src(fp, FMA.src0, regs, consts, true);
905 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
906 if (FMA.op & (1 << 9))
907 fprintf(fp, ")");
908 fprintf(fp, ", ");
909 if (FMA.op & (1 << 16))
910 fprintf(fp, "abs(");
911 dump_src(fp, FMA.op & 0x7, regs, consts, true);
912 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
913 if (FMA.op & (1 << 16))
914 fprintf(fp, ")");
915 fprintf(fp, ", ");
916 if (FMA.op & (1 << 15))
917 fprintf(fp, "-");
918 if (FMA.op & (1 << 17))
919 fprintf(fp, "abs(");
920 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
921 if (FMA.op & (1 << 17))
922 fprintf(fp, ")");
923 break;
924 case FMA_FMA16:
925 if (FMA.op & (1 << 14))
926 fprintf(fp, "-");
927 dump_src(fp, FMA.src0, regs, consts, true);
928 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
929 fprintf(fp, ", ");
930 dump_src(fp, FMA.op & 0x7, regs, consts, true);
931 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
932 fprintf(fp, ", ");
933 if (FMA.op & (1 << 15))
934 fprintf(fp, "-");
935 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
936 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
937 break;
938 case FMA_CSEL4: {
939 struct bifrost_csel4 csel;
940 memcpy(&csel, &FMA, sizeof(csel));
941 fprintf(fp, ".%s ", bi_csel_cond_name(csel.cond));
942
943 dump_src(fp, csel.src0, regs, consts, true);
944 fprintf(fp, ", ");
945 dump_src(fp, csel.src1, regs, consts, true);
946 fprintf(fp, ", ");
947 dump_src(fp, csel.src2, regs, consts, true);
948 fprintf(fp, ", ");
949 dump_src(fp, csel.src3, regs, consts, true);
950 break;
951 }
952 case FMA_FMA_MSCALE:
953 if (FMA.op & (1 << 12))
954 fprintf(fp, "abs(");
955 dump_src(fp, FMA.src0, regs, consts, true);
956 if (FMA.op & (1 << 12))
957 fprintf(fp, ")");
958 fprintf(fp, ", ");
959 if (FMA.op & (1 << 13))
960 fprintf(fp, "-");
961 dump_src(fp, FMA.op & 0x7, regs, consts, true);
962 fprintf(fp, ", ");
963 if (FMA.op & (1 << 14))
964 fprintf(fp, "-");
965 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
966 fprintf(fp, ", ");
967 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
968 break;
969 }
970 fprintf(fp, "\n");
971 }
972
973 static const struct add_op_info add_op_infos[] = {
974 { 0x00000, "MAX.f32", ADD_FMINMAX },
975 { 0x02000, "MIN.f32", ADD_FMINMAX },
976 { 0x04000, "ADD.f32", ADD_FADD },
977 { 0x06000, "FCMP.GL", ADD_FCMP },
978 { 0x07000, "FCMP.D3D", ADD_FCMP },
979 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
980 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
981 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
982 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
983 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
984 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
985 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
986 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
987 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
988 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
989 { 0x07909, "B1_TO_F16", ADD_ONE_SRC },
990 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
991 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
992 { 0x07971, "B1_TO_F32", ADD_ONE_SRC },
993 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
994 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
995 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
996 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
997 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
998 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
999 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
1000 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
1001 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
1002 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
1003 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
1004 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
1005 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1006 { 0x07b2c, "NOP", ADD_ONE_SRC },
1007 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1008 { 0x07b2d, "MOV", ADD_ONE_SRC },
1009 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1010 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1011 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1012 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1013 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1014 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1015 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1016 { 0x07bd4, "IABS.i32", ADD_ONE_SRC },
1017 { 0x07d42, "CEIL.v2f16", ADD_ONE_SRC },
1018 { 0x07d45, "CEIL.f32", ADD_ONE_SRC },
1019 { 0x07d82, "FLOOR.v2f16", ADD_ONE_SRC },
1020 { 0x07d85, "FLOOR.f32", ADD_ONE_SRC },
1021 { 0x07dc2, "TRUNC.v2f16", ADD_ONE_SRC },
1022 { 0x07dc5, "TRUNC.f32", ADD_ONE_SRC },
1023 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1024 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
1025 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1026 { 0x0b000, "TEXC", ADD_TEX_COMPACT, true },
1027 { 0x0b400, "TEXC.vtx", ADD_TEX_COMPACT, true },
1028 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1029 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1030 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1031 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1032 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1033 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1034 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1035 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1036 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1037 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1038 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1039 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1040 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1041 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1042 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1043 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1044 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1045 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1046 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1047 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1048 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1049 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1050 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1051 { 0x0cc68, "FLOG2_U.f32", ADD_ONE_SRC },
1052 { 0x0cd58, "FEXP2_FAST.f32", ADD_ONE_SRC },
1053 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1054 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1055 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1056 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1057 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1058 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1059 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1060 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1061 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1062 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1063 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1064 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1065 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1066 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1067 { 0x0d000, "BRANCH", ADD_BRANCH },
1068 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1069 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1070 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1071 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1072 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1073 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1074 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1075 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1076 { 0x0e840, "CSEL.64", ADD_THREE_SRC }, // u2u32(src2) ? src0 : src1
1077 { 0x0e940, "CSEL.8", ADD_THREE_SRC }, // (src2 != 0) ? src0 : src1
1078 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1079 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1080 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1081 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1082 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1083 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1084 { 0x0f690, "UCMP.8.GT", ADD_TWO_SRC },
1085 { 0x0f698, "UCMP.8.GE", ADD_TWO_SRC },
1086 { 0x0f6a8, "ICMP.8.NE", ADD_TWO_SRC },
1087 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1088 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1089 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1090 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1091 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1092 { 0x0f700, "ICMP.64.GT.PT1", ADD_TWO_SRC },
1093 { 0x0f708, "ICMP.64.GE.PT1", ADD_TWO_SRC },
1094 { 0x0f710, "UCMP.64.GT.PT1", ADD_TWO_SRC },
1095 { 0x0f718, "UCMP.64.GE.PT1", ADD_TWO_SRC },
1096 { 0x0f720, "ICMP.64.EQ.PT1", ADD_TWO_SRC },
1097 { 0x0f728, "ICMP.64.NE.PT1", ADD_TWO_SRC },
1098 { 0x0f7c0, "ICMP.64.PT2", ADD_THREE_SRC }, // src3 = result of PT1
1099 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1100 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1101 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1102 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1103 { 0x16000, "FCMP.GL", ADD_FCMP16 },
1104 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1105 { 0x17880, "ADD.v4i8", ADD_TWO_SRC },
1106 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1107 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1108 { 0x17a80, "SUB.v4i8", ADD_TWO_SRC },
1109 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1110 { 0x17b00, "SUB.v2i16", ADD_TWO_SRC },
1111 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1112 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1113 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1114 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1115 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1116 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, false },
1117 { 0x19100, "DISCARD.FEQ.f16", ADD_TWO_SRC, false },
1118 { 0x19108, "DISCARD.FNE.f16", ADD_TWO_SRC, false },
1119 { 0x19110, "DISCARD.FLE.f16", ADD_TWO_SRC, false },
1120 { 0x19118, "DISCARD.FLT.f16", ADD_TWO_SRC, false },
1121 { 0x19180, "DISCARD.FEQ.f32", ADD_TWO_SRC, false },
1122 { 0x19188, "DISCARD.FNE.f32", ADD_TWO_SRC, false },
1123 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, false },
1124 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, false },
1125 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1126 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1127 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1128 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1129 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1130 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1131 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1132 { 0x1952c, "BLEND", ADD_BLENDING, true },
1133 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1134 { 0x1ae20, "TEX.vtx", ADD_TEX, true },
1135 { 0x1ae60, "TEX", ADD_TEX, true },
1136 { 0x1b000, "TEXC.f16", ADD_TEX_COMPACT, true },
1137 { 0x1b400, "TEXC.vtx.f16", ADD_TEX_COMPACT, true },
1138 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
1139 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
1140 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
1141 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT },
1142 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT },
1143 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT },
1144 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT },
1145 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1146 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1147 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1148 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1149 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1150 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1151 };
1152
1153 static struct add_op_info find_add_op_info(unsigned op)
1154 {
1155 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1156 unsigned opCmp = ~0;
1157 switch (add_op_infos[i].src_type) {
1158 case ADD_ONE_SRC:
1159 case ADD_BLENDING:
1160 opCmp = op;
1161 break;
1162 case ADD_TWO_SRC:
1163 opCmp = op & ~0x7;
1164 break;
1165 case ADD_THREE_SRC:
1166 opCmp = op & ~0x3f;
1167 break;
1168 case ADD_SHIFT:
1169 opCmp = op & ~0x3ff;
1170 break;
1171 case ADD_TEX:
1172 opCmp = op & ~0xf;
1173 break;
1174 case ADD_FADD:
1175 case ADD_FMINMAX:
1176 case ADD_FADD16:
1177 opCmp = op & ~0x1fff;
1178 break;
1179 case ADD_FMINMAX16:
1180 case ADD_FADDMscale:
1181 opCmp = op & ~0xfff;
1182 break;
1183 case ADD_FCMP:
1184 case ADD_FCMP16:
1185 opCmp = op & ~0x7ff;
1186 break;
1187 case ADD_TEX_COMPACT:
1188 opCmp = op & ~0x3ff;
1189 break;
1190 case ADD_VARYING_INTERP:
1191 opCmp = op & ~0x7ff;
1192 break;
1193 case ADD_VARYING_ADDRESS:
1194 opCmp = op & ~0xfff;
1195 break;
1196 case ADD_LOAD_ATTR:
1197 case ADD_BRANCH:
1198 opCmp = op & ~0xfff;
1199 break;
1200 default:
1201 opCmp = ~0;
1202 break;
1203 }
1204 if (add_op_infos[i].op == opCmp)
1205 return add_op_infos[i];
1206 }
1207
1208 struct add_op_info info;
1209 snprintf(info.name, sizeof(info.name), "op%04x", op);
1210 info.op = op;
1211 info.src_type = ADD_TWO_SRC;
1212 info.has_data_reg = true;
1213 return info;
1214 }
1215
1216 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1217 struct bifrost_regs next_regs, uint64_t *consts,
1218 unsigned data_reg, unsigned offset, bool verbose)
1219 {
1220 if (verbose) {
1221 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1222 }
1223 struct bifrost_add_inst ADD;
1224 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1225 struct add_op_info info = find_add_op_info(ADD.op);
1226
1227 fprintf(fp, "%s", info.name);
1228
1229 // float16 seems like it doesn't support output modifiers
1230 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1231 // output modifiers
1232 fprintf(fp, "%s", bi_output_mod_name(bits(ADD.op, 8, 10)));
1233 if (info.src_type == ADD_FADD)
1234 fprintf(fp, "%s", bi_round_mode_name(bits(ADD.op, 10, 12)));
1235 else
1236 fprintf(fp, "%s", bi_minmax_mode_name(bits(ADD.op, 10, 12)));
1237 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1238 dump_fcmp(fp, bits(ADD.op, 3, 6));
1239 if (info.src_type == ADD_FCMP)
1240 fprintf(fp, ".f32");
1241 else
1242 fprintf(fp, ".v2f16");
1243 } else if (info.src_type == ADD_FADDMscale) {
1244 switch ((ADD.op >> 6) & 0x7) {
1245 case 0:
1246 break;
1247 // causes GPU hangs on G71
1248 case 1:
1249 fprintf(fp, ".invalid");
1250 break;
1251 // Same as usual outmod value.
1252 case 2:
1253 fprintf(fp, ".clamp_0_1");
1254 break;
1255 // If src0 is infinite or NaN, flush it to zero so that the other
1256 // source is passed through unmodified.
1257 case 3:
1258 fprintf(fp, ".flush_src0_inf_nan");
1259 break;
1260 // Vice versa.
1261 case 4:
1262 fprintf(fp, ".flush_src1_inf_nan");
1263 break;
1264 // Every other case seems to behave the same as the above?
1265 default:
1266 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1267 break;
1268 }
1269 } else if (info.src_type == ADD_VARYING_INTERP) {
1270 if (ADD.op & 0x200)
1271 fprintf(fp, ".reuse");
1272 if (ADD.op & 0x400)
1273 fprintf(fp, ".flat");
1274 fprintf(fp, "%s", bi_interp_mode_name((ADD.op >> 7) & 0x3));
1275 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1276 } else if (info.src_type == ADD_BRANCH) {
1277 enum bifrost_branch_code branchCode = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1278 if (branchCode == BR_ALWAYS) {
1279 // unconditional branch
1280 } else {
1281 enum bifrost_branch_cond cond = (enum bifrost_branch_cond) ((ADD.op >> 6) & 0x7);
1282 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1283 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1284 // See the comment in branch_bit_size
1285 if (size == BR_SIZE_16YX0)
1286 portSwapped = true;
1287 if (size == BR_SIZE_16YX1)
1288 portSwapped = false;
1289 // These sizes are only for floating point comparisons, so the
1290 // non-floating-point comparisons are reused to encode the flipped
1291 // versions.
1292 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1293 portSwapped = false;
1294 // There's only one argument, so we reuse the extra argument to
1295 // encode this.
1296 if (size == BR_SIZE_ZERO)
1297 portSwapped = !(ADD.op & 1);
1298
1299 switch (cond) {
1300 case BR_COND_LT:
1301 if (portSwapped)
1302 fprintf(fp, ".LT.u");
1303 else
1304 fprintf(fp, ".LT.i");
1305 break;
1306 case BR_COND_LE:
1307 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1308 fprintf(fp, ".UNE.f");
1309 } else {
1310 if (portSwapped)
1311 fprintf(fp, ".LE.u");
1312 else
1313 fprintf(fp, ".LE.i");
1314 }
1315 break;
1316 case BR_COND_GT:
1317 if (portSwapped)
1318 fprintf(fp, ".GT.u");
1319 else
1320 fprintf(fp, ".GT.i");
1321 break;
1322 case BR_COND_GE:
1323 if (portSwapped)
1324 fprintf(fp, ".GE.u");
1325 else
1326 fprintf(fp, ".GE.i");
1327 break;
1328 case BR_COND_EQ:
1329 if (portSwapped)
1330 fprintf(fp, ".NE.i");
1331 else
1332 fprintf(fp, ".EQ.i");
1333 break;
1334 case BR_COND_OEQ:
1335 if (portSwapped)
1336 fprintf(fp, ".UNE.f");
1337 else
1338 fprintf(fp, ".OEQ.f");
1339 break;
1340 case BR_COND_OGT:
1341 if (portSwapped)
1342 fprintf(fp, ".OGT.unk.f");
1343 else
1344 fprintf(fp, ".OGT.f");
1345 break;
1346 case BR_COND_OLT:
1347 if (portSwapped)
1348 fprintf(fp, ".OLT.unk.f");
1349 else
1350 fprintf(fp, ".OLT.f");
1351 break;
1352 }
1353 switch (size) {
1354 case BR_SIZE_32:
1355 case BR_SIZE_32_AND_16X:
1356 case BR_SIZE_32_AND_16Y:
1357 fprintf(fp, "32");
1358 break;
1359 case BR_SIZE_16XX:
1360 case BR_SIZE_16YY:
1361 case BR_SIZE_16YX0:
1362 case BR_SIZE_16YX1:
1363 fprintf(fp, "16");
1364 break;
1365 case BR_SIZE_ZERO: {
1366 unsigned ctrl = (ADD.op >> 1) & 0x3;
1367 if (ctrl == 0)
1368 fprintf(fp, "32.Z");
1369 else
1370 fprintf(fp, "16.Z");
1371 break;
1372 }
1373 }
1374 }
1375 } else if (info.src_type == ADD_SHIFT) {
1376 struct bifrost_shift_add shift;
1377 memcpy(&shift, &ADD, sizeof(ADD));
1378
1379 if (shift.invert_1)
1380 fprintf(fp, ".invert_1");
1381
1382 if (shift.invert_2)
1383 fprintf(fp, ".invert_2");
1384
1385 if (shift.zero)
1386 fprintf(fp, ".unk%u", shift.zero);
1387 } else if (info.src_type == ADD_VARYING_ADDRESS) {
1388 struct bifrost_ld_var_addr ld;
1389 memcpy(&ld, &ADD, sizeof(ADD));
1390 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1391 } else if (info.src_type == ADD_LOAD_ATTR) {
1392 struct bifrost_ld_attr ld;
1393 memcpy(&ld, &ADD, sizeof(ADD));
1394
1395 if (ld.channels)
1396 fprintf(fp, ".v%d%s", ld.channels + 1, bi_ldst_type_name(ld.type));
1397 else
1398 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1399 }
1400
1401 fprintf(fp, " ");
1402
1403 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1404 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1405 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1406 } else {
1407 fprintf(fp, "T1, ");
1408 }
1409
1410 switch (info.src_type) {
1411 case ADD_BLENDING:
1412 // Note: in this case, regs.uniform_const == location | 0x8
1413 // This probably means we can't load uniforms or immediates in the
1414 // same instruction. This re-uses the encoding that normally means
1415 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1416 // 0x8 or'd in indicates this is happening.
1417 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1418 // fallthrough
1419 case ADD_ONE_SRC:
1420 dump_src(fp, ADD.src0, regs, consts, false);
1421 break;
1422 case ADD_TEX:
1423 case ADD_TEX_COMPACT: {
1424 int tex_index;
1425 int sampler_index;
1426 bool dualTex = false;
1427
1428 fprintf(fp, "coords <");
1429 dump_src(fp, ADD.src0, regs, consts, false);
1430 fprintf(fp, ", ");
1431 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1432 fprintf(fp, ">, ");
1433
1434 if (info.src_type == ADD_TEX_COMPACT) {
1435 tex_index = (ADD.op >> 3) & 0x7;
1436 sampler_index = (ADD.op >> 7) & 0x7;
1437 bool compute_lod = (ADD.op & 0x40);
1438 if (!compute_lod)
1439 fprintf(fp, "vtx lod 0 ");
1440 } else {
1441 uint64_t constVal = get_const(consts, regs);
1442 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1443 struct bifrost_tex_ctrl ctrl;
1444 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1445
1446 /* Dual-tex triggered for adjacent texturing
1447 * instructions with the same coordinates to different
1448 * textures/samplers. Observed for the compact
1449 * (2D/normal) case. */
1450
1451 if ((ctrl.result_type & 7) == 1) {
1452 bool f32 = ctrl.result_type & 8;
1453
1454 struct bifrost_dual_tex_ctrl dualCtrl;
1455 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1456 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d %s",
1457 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1458 dualCtrl.tex_index1, dualCtrl.sampler_index1,
1459 f32 ? "f32" : "f16");
1460 if (dualCtrl.unk0 != 3)
1461 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1462 dualTex = true;
1463 } else {
1464 if (ctrl.no_merge_index) {
1465 tex_index = ctrl.tex_index;
1466 sampler_index = ctrl.sampler_index;
1467 } else {
1468 tex_index = sampler_index = ctrl.tex_index;
1469 unsigned unk = ctrl.sampler_index >> 2;
1470 if (unk != 3)
1471 fprintf(fp, "unk:%d ", unk);
1472 if (ctrl.sampler_index & 1)
1473 tex_index = -1;
1474 if (ctrl.sampler_index & 2)
1475 sampler_index = -1;
1476 }
1477
1478 if (ctrl.unk0 != 3)
1479 fprintf(fp, "unk0:%d ", ctrl.unk0);
1480 if (ctrl.unk1)
1481 fprintf(fp, "unk1 ");
1482 if (ctrl.unk2 != 0xf)
1483 fprintf(fp, "unk2:%x ", ctrl.unk2);
1484
1485 switch (ctrl.result_type) {
1486 case 0x4:
1487 fprintf(fp, "f32 ");
1488 break;
1489 case 0xe:
1490 fprintf(fp, "i32 ");
1491 break;
1492 case 0xf:
1493 fprintf(fp, "u32 ");
1494 break;
1495 default:
1496 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1497 }
1498
1499 switch (ctrl.tex_type) {
1500 case 0:
1501 fprintf(fp, "cube ");
1502 break;
1503 case 1:
1504 fprintf(fp, "buffer ");
1505 break;
1506 case 2:
1507 fprintf(fp, "2D ");
1508 break;
1509 case 3:
1510 fprintf(fp, "3D ");
1511 break;
1512 }
1513
1514 if (ctrl.is_shadow)
1515 fprintf(fp, "shadow ");
1516 if (ctrl.is_array)
1517 fprintf(fp, "array ");
1518
1519 if (!ctrl.filter) {
1520 if (ctrl.calc_gradients) {
1521 int comp = (controlBits >> 20) & 0x3;
1522 fprintf(fp, "txg comp:%d ", comp);
1523 } else {
1524 fprintf(fp, "txf ");
1525 }
1526 } else {
1527 if (!ctrl.not_supply_lod) {
1528 if (ctrl.compute_lod)
1529 fprintf(fp, "lod_bias ");
1530 else
1531 fprintf(fp, "lod ");
1532 }
1533
1534 if (!ctrl.calc_gradients)
1535 fprintf(fp, "grad ");
1536 }
1537
1538 if (ctrl.texel_offset)
1539 fprintf(fp, "offset ");
1540 }
1541 }
1542
1543 if (!dualTex) {
1544 if (tex_index == -1)
1545 fprintf(fp, "tex:indirect ");
1546 else
1547 fprintf(fp, "tex:%d ", tex_index);
1548
1549 if (sampler_index == -1)
1550 fprintf(fp, "samp:indirect ");
1551 else
1552 fprintf(fp, "samp:%d ", sampler_index);
1553 }
1554 break;
1555 }
1556 case ADD_VARYING_INTERP: {
1557 unsigned addr = ADD.op & 0x1f;
1558 if (addr < 0b10100) {
1559 // direct addr
1560 fprintf(fp, "%d", addr);
1561 } else if (addr < 0b11000) {
1562 if (addr == 20)
1563 fprintf(fp, "pointcoord");
1564 else if (addr == 22)
1565 fprintf(fp, "fragw");
1566 else if (addr == 23)
1567 fprintf(fp, "fragz");
1568 else
1569 fprintf(fp, "unk%d", addr);
1570 } else {
1571 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1572 }
1573 fprintf(fp, ", ");
1574 dump_src(fp, ADD.src0, regs, consts, false);
1575 break;
1576 }
1577 case ADD_VARYING_ADDRESS: {
1578 dump_src(fp, ADD.src0, regs, consts, false);
1579 fprintf(fp, ", ");
1580 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1581 fprintf(fp, ", ");
1582 unsigned location = (ADD.op >> 3) & 0x1f;
1583 if (location < 16) {
1584 fprintf(fp, "location:%d", location);
1585 } else if (location == 20) {
1586 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1587 } else if (location == 21) {
1588 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1589 } else {
1590 fprintf(fp, "location:%d(unk)", location);
1591 }
1592 break;
1593 }
1594 case ADD_LOAD_ATTR:
1595 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0x1f);
1596 /* fallthrough */
1597 case ADD_TWO_SRC:
1598 dump_src(fp, ADD.src0, regs, consts, false);
1599 fprintf(fp, ", ");
1600 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1601 break;
1602 case ADD_THREE_SRC:
1603 dump_src(fp, ADD.src0, regs, consts, false);
1604 fprintf(fp, ", ");
1605 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1606 fprintf(fp, ", ");
1607 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1608 break;
1609 case ADD_SHIFT: {
1610 struct bifrost_shift_add shift;
1611 memcpy(&shift, &ADD, sizeof(ADD));
1612 dump_src(fp, shift.src0, regs, consts, false);
1613 fprintf(fp, ", ");
1614 dump_src(fp, shift.src1, regs, consts, false);
1615 fprintf(fp, ", ");
1616 dump_src(fp, shift.src2, regs, consts, false);
1617 break;
1618 }
1619 case ADD_FADD:
1620 case ADD_FMINMAX:
1621 if (ADD.op & 0x10)
1622 fprintf(fp, "-");
1623 if (ADD.op & 0x1000)
1624 fprintf(fp, "abs(");
1625 dump_src(fp, ADD.src0, regs, consts, false);
1626 switch ((ADD.op >> 6) & 0x3) {
1627 case 3:
1628 fprintf(fp, ".x");
1629 break;
1630 default:
1631 break;
1632 }
1633 if (ADD.op & 0x1000)
1634 fprintf(fp, ")");
1635 fprintf(fp, ", ");
1636 if (ADD.op & 0x20)
1637 fprintf(fp, "-");
1638 if (ADD.op & 0x8)
1639 fprintf(fp, "abs(");
1640 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1641 switch ((ADD.op >> 6) & 0x3) {
1642 case 1:
1643 case 3:
1644 fprintf(fp, ".x");
1645 break;
1646 case 2:
1647 fprintf(fp, ".y");
1648 break;
1649 case 0:
1650 break;
1651 default:
1652 fprintf(fp, ".unk");
1653 break;
1654 }
1655 if (ADD.op & 0x8)
1656 fprintf(fp, ")");
1657 break;
1658 case ADD_FADD16:
1659 if (ADD.op & 0x10)
1660 fprintf(fp, "-");
1661 if (ADD.op & 0x1000)
1662 fprintf(fp, "abs(");
1663 dump_src(fp, ADD.src0, regs, consts, false);
1664 if (ADD.op & 0x1000)
1665 fprintf(fp, ")");
1666 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1667 fprintf(fp, ", ");
1668 if (ADD.op & 0x20)
1669 fprintf(fp, "-");
1670 if (ADD.op & 0x8)
1671 fprintf(fp, "abs(");
1672 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1673 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1674 if (ADD.op & 0x8)
1675 fprintf(fp, ")");
1676 break;
1677 case ADD_FMINMAX16: {
1678 bool abs1 = ADD.op & 0x8;
1679 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1680 if (ADD.op & 0x10)
1681 fprintf(fp, "-");
1682 if (abs1 || abs2)
1683 fprintf(fp, "abs(");
1684 dump_src(fp, ADD.src0, regs, consts, false);
1685 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1686 if (abs1 || abs2)
1687 fprintf(fp, ")");
1688 fprintf(fp, ", ");
1689 if (ADD.op & 0x20)
1690 fprintf(fp, "-");
1691 if (abs1 && abs2)
1692 fprintf(fp, "abs(");
1693 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1694 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1695 if (abs1 && abs2)
1696 fprintf(fp, ")");
1697 fprintf(fp, "/* %X */\n", (ADD.op >> 10) & 0x3); /* mode */
1698 break;
1699 }
1700 case ADD_FADDMscale: {
1701 if (ADD.op & 0x400)
1702 fprintf(fp, "-");
1703 if (ADD.op & 0x200)
1704 fprintf(fp, "abs(");
1705 dump_src(fp, ADD.src0, regs, consts, false);
1706 if (ADD.op & 0x200)
1707 fprintf(fp, ")");
1708
1709 fprintf(fp, ", ");
1710
1711 if (ADD.op & 0x800)
1712 fprintf(fp, "-");
1713 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1714
1715 fprintf(fp, ", ");
1716
1717 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1718 break;
1719 }
1720 case ADD_FCMP:
1721 if (ADD.op & 0x400) {
1722 fprintf(fp, "-");
1723 }
1724 if (ADD.op & 0x100) {
1725 fprintf(fp, "abs(");
1726 }
1727 dump_src(fp, ADD.src0, regs, consts, false);
1728 switch ((ADD.op >> 6) & 0x3) {
1729 case 3:
1730 fprintf(fp, ".x");
1731 break;
1732 default:
1733 break;
1734 }
1735 if (ADD.op & 0x100) {
1736 fprintf(fp, ")");
1737 }
1738 fprintf(fp, ", ");
1739 if (ADD.op & 0x200) {
1740 fprintf(fp, "abs(");
1741 }
1742 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1743 switch ((ADD.op >> 6) & 0x3) {
1744 case 1:
1745 case 3:
1746 fprintf(fp, ".x");
1747 break;
1748 case 2:
1749 fprintf(fp, ".y");
1750 break;
1751 case 0:
1752 break;
1753 default:
1754 fprintf(fp, ".unk");
1755 break;
1756 }
1757 if (ADD.op & 0x200) {
1758 fprintf(fp, ")");
1759 }
1760 break;
1761 case ADD_FCMP16:
1762 dump_src(fp, ADD.src0, regs, consts, false);
1763 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1764 fprintf(fp, ", ");
1765 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1766 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1767 break;
1768 case ADD_BRANCH: {
1769 enum bifrost_branch_code code = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1770 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1771 if (code != BR_ALWAYS) {
1772 dump_src(fp, ADD.src0, regs, consts, false);
1773 switch (size) {
1774 case BR_SIZE_16XX:
1775 fprintf(fp, ".x");
1776 break;
1777 case BR_SIZE_16YY:
1778 case BR_SIZE_16YX0:
1779 case BR_SIZE_16YX1:
1780 fprintf(fp, ".y");
1781 break;
1782 case BR_SIZE_ZERO: {
1783 unsigned ctrl = (ADD.op >> 1) & 0x3;
1784 switch (ctrl) {
1785 case 1:
1786 fprintf(fp, ".y");
1787 break;
1788 case 2:
1789 fprintf(fp, ".x");
1790 break;
1791 default:
1792 break;
1793 }
1794 }
1795 default:
1796 break;
1797 }
1798 fprintf(fp, ", ");
1799 }
1800 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1801 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1802 switch (size) {
1803 case BR_SIZE_16XX:
1804 case BR_SIZE_16YX0:
1805 case BR_SIZE_16YX1:
1806 case BR_SIZE_32_AND_16X:
1807 fprintf(fp, ".x");
1808 break;
1809 case BR_SIZE_16YY:
1810 case BR_SIZE_32_AND_16Y:
1811 fprintf(fp, ".y");
1812 break;
1813 default:
1814 break;
1815 }
1816 fprintf(fp, ", ");
1817 }
1818 // I haven't had the chance to test if this actually specifies the
1819 // branch offset, since I couldn't get it to produce values other
1820 // than 5 (uniform/const high), but these three bits are always
1821 // consistent across branch instructions, so it makes sense...
1822 int offsetSrc = (ADD.op >> 3) & 0x7;
1823 if (offsetSrc == 4 || offsetSrc == 5) {
1824 // If the offset is known/constant, we can decode it
1825 uint32_t raw_offset;
1826 if (offsetSrc == 4)
1827 raw_offset = get_const(consts, regs);
1828 else
1829 raw_offset = get_const(consts, regs) >> 32;
1830 // The high 4 bits are flags, while the rest is the
1831 // twos-complement offset in bytes (here we convert to
1832 // clauses).
1833 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1834
1835 // If high4 is the high 4 bits of the last 64-bit constant,
1836 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1837 // offset itself is the last constant. Not sure if this is
1838 // actually used, or just garbage in unused bits, but in any
1839 // case, we can just ignore it here since it's redundant. Note
1840 // that if there is any padding, this will be 4 since the
1841 // padding counts as the last constant.
1842 unsigned flags = raw_offset >> 28;
1843 (void) flags;
1844
1845 // Note: the offset is in bytes, relative to the beginning of the
1846 // current clause, so a zero offset would be a loop back to the
1847 // same clause (annoyingly different from Midgard).
1848 fprintf(fp, "clause_%d", offset + branch_offset);
1849 } else {
1850 dump_src(fp, offsetSrc, regs, consts, false);
1851 }
1852 }
1853 }
1854 if (info.has_data_reg) {
1855 fprintf(fp, ", R%d", data_reg);
1856 }
1857 fprintf(fp, "\n");
1858 }
1859
1860 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1861 struct bifrost_regs next_regs, uint64_t *consts,
1862 unsigned data_reg, unsigned offset, bool verbose)
1863 {
1864 struct bifrost_regs regs;
1865 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1866
1867 if (verbose) {
1868 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1869 dump_regs(fp, regs);
1870 }
1871 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1872 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1873 }
1874
1875 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1876 {
1877 // State for a decoded clause
1878 struct bifrost_alu_inst instrs[8] = {};
1879 uint64_t consts[6] = {};
1880 unsigned num_instrs = 0;
1881 unsigned num_consts = 0;
1882 uint64_t header_bits = 0;
1883 bool stopbit = false;
1884
1885 unsigned i;
1886 for (i = 0; ; i++, words += 4) {
1887 if (verbose) {
1888 fprintf(fp, "# ");
1889 for (int j = 0; j < 4; j++)
1890 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1891 fprintf(fp, "\n");
1892 }
1893 unsigned tag = bits(words[0], 0, 8);
1894
1895 // speculatively decode some things that are common between many formats, so we can share some code
1896 struct bifrost_alu_inst main_instr = {};
1897 // 20 bits
1898 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1899 // 23 bits
1900 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1901 // 35 bits
1902 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1903
1904 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1905 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1906
1907 bool stop = tag & 0x40;
1908
1909 if (verbose) {
1910 fprintf(fp, "# tag: 0x%02x\n", tag);
1911 }
1912 if (tag & 0x80) {
1913 unsigned idx = stop ? 5 : 2;
1914 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
1915 instrs[idx + 1] = main_instr;
1916 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
1917 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
1918 consts[0] = bits(words[3], 17, 32) << 4;
1919 } else {
1920 bool done = false;
1921 switch ((tag >> 3) & 0x7) {
1922 case 0x0:
1923 switch (tag & 0x7) {
1924 case 0x3:
1925 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
1926 instrs[1] = main_instr;
1927 num_instrs = 2;
1928 done = stop;
1929 break;
1930 case 0x4:
1931 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1932 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1933 consts[0] = const0;
1934 num_instrs = 3;
1935 num_consts = 1;
1936 done = stop;
1937 break;
1938 case 0x1:
1939 case 0x5:
1940 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1941 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1942 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1943 instrs[3] = main_instr;
1944 if ((tag & 0x7) == 0x5) {
1945 num_instrs = 4;
1946 done = stop;
1947 }
1948 break;
1949 case 0x6:
1950 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1951 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1952 consts[0] = const0;
1953 num_instrs = 6;
1954 num_consts = 1;
1955 done = stop;
1956 break;
1957 case 0x7:
1958 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1959 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1960 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1961 instrs[6] = main_instr;
1962 num_instrs = 7;
1963 done = stop;
1964 break;
1965 default:
1966 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
1967 }
1968 break;
1969 case 0x2:
1970 case 0x3: {
1971 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
1972 main_instr.add_bits |= (tag & 0x7) << 17;
1973 instrs[idx] = main_instr;
1974 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
1975 num_consts = 1;
1976 num_instrs = idx + 1;
1977 done = stop;
1978 break;
1979 }
1980 case 0x4: {
1981 unsigned idx = stop ? 4 : 1;
1982 main_instr.add_bits |= (tag & 0x7) << 17;
1983 instrs[idx] = main_instr;
1984 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
1985 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
1986 break;
1987 }
1988 case 0x1:
1989 // only constants can come after this
1990 num_instrs = 1;
1991 done = stop;
1992 /* fallthrough */
1993 case 0x5:
1994 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
1995 main_instr.add_bits |= (tag & 0x7) << 17;
1996 instrs[0] = main_instr;
1997 break;
1998 case 0x6:
1999 case 0x7: {
2000 unsigned pos = tag & 0xf;
2001 // note that `pos' encodes both the total number of
2002 // instructions and the position in the constant stream,
2003 // presumably because decoded constants and instructions
2004 // share a buffer in the decoder, but we only care about
2005 // the position in the constant stream; the total number of
2006 // instructions is redundant.
2007 unsigned const_idx = 0;
2008 switch (pos) {
2009 case 0:
2010 case 1:
2011 case 2:
2012 case 6:
2013 const_idx = 0;
2014 break;
2015 case 3:
2016 case 4:
2017 case 7:
2018 case 9:
2019 const_idx = 1;
2020 break;
2021 case 5:
2022 case 0xa:
2023 const_idx = 2;
2024 break;
2025 case 8:
2026 case 0xb:
2027 case 0xc:
2028 const_idx = 3;
2029 break;
2030 case 0xd:
2031 const_idx = 4;
2032 break;
2033 case 0xe:
2034 const_idx = 5;
2035 break;
2036 default:
2037 fprintf(fp, "# unknown pos 0x%x\n", pos);
2038 break;
2039 }
2040
2041 if (num_consts < const_idx + 2)
2042 num_consts = const_idx + 2;
2043
2044 consts[const_idx] = const0;
2045 consts[const_idx + 1] = const1;
2046 done = stop;
2047 break;
2048 }
2049 default:
2050 break;
2051 }
2052
2053 if (done)
2054 break;
2055 }
2056 }
2057
2058 *size = i + 1;
2059
2060 if (verbose) {
2061 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
2062 }
2063
2064 struct bifrost_header header;
2065 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2066 dump_header(fp, header, verbose);
2067 if (!header.no_end_of_shader)
2068 stopbit = true;
2069
2070 fprintf(fp, "{\n");
2071 for (i = 0; i < num_instrs; i++) {
2072 struct bifrost_regs next_regs;
2073 if (i + 1 == num_instrs) {
2074 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2075 sizeof(next_regs));
2076 } else {
2077 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2078 sizeof(next_regs));
2079 }
2080
2081 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2082 }
2083 fprintf(fp, "}\n");
2084
2085 if (verbose) {
2086 for (unsigned i = 0; i < num_consts; i++) {
2087 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2088 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2089 }
2090 }
2091 return stopbit;
2092 }
2093
2094 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2095 {
2096 uint32_t *words = (uint32_t *) code;
2097 uint32_t *words_end = words + (size / 4);
2098 // used for displaying branch targets
2099 unsigned offset = 0;
2100 while (words != words_end) {
2101 // we don't know what the program-end bit is quite yet, so for now just
2102 // assume that an all-0 quadword is padding
2103 uint32_t zero[4] = {};
2104 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2105 break;
2106 fprintf(fp, "clause_%d:\n", offset);
2107 unsigned size;
2108 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2109 break;
2110 }
2111 words += size * 4;
2112 offset += size;
2113 }
2114 }
2115