projects / mesa.git / blob
? search:


e90b7ca973fd6b3d71858bd9cd1e201328b8e311
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "disassemble.h"
35 #include "bi_print.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 static unsigned get_reg0(struct bifrost_regs regs)
56 {
57 if (regs.ctrl == 0)
58 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
59
60 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
61 }
62
63 static unsigned get_reg1(struct bifrost_regs regs)
64 {
65 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
66 }
67
68 // this represents the decoded version of the ctrl register field.
69 struct bifrost_reg_ctrl {
70 bool read_reg0;
71 bool read_reg1;
72 bool read_reg3;
73 enum bifrost_reg_write_unit fma_write_unit;
74 enum bifrost_reg_write_unit add_write_unit;
75 bool clause_start;
76 };
77
78 enum fma_src_type {
79 FMA_ONE_SRC,
80 FMA_TWO_SRC,
81 FMA_FADD,
82 FMA_FMINMAX,
83 FMA_FADD16,
84 FMA_FMINMAX16,
85 FMA_FCMP,
86 FMA_FCMP16,
87 FMA_THREE_SRC,
88 FMA_SHIFT,
89 FMA_FMA,
90 FMA_FMA16,
91 FMA_CSEL4,
92 FMA_FMA_MSCALE,
93 FMA_SHIFT_ADD64,
94 };
95
96 struct fma_op_info {
97 bool extended;
98 unsigned op;
99 char name[30];
100 enum fma_src_type src_type;
101 };
102
103 enum add_src_type {
104 ADD_ONE_SRC,
105 ADD_TWO_SRC,
106 ADD_FADD,
107 ADD_FMINMAX,
108 ADD_FADD16,
109 ADD_FMINMAX16,
110 ADD_THREE_SRC,
111 ADD_SHIFT,
112 ADD_FADDMscale,
113 ADD_FCMP,
114 ADD_FCMP16,
115 ADD_TEX_COMPACT, // texture instruction with embedded sampler
116 ADD_TEX, // texture instruction with sampler/etc. in uniform port
117 ADD_VARYING_INTERP,
118 ADD_BLENDING,
119 ADD_LOAD_ATTR,
120 ADD_VARYING_ADDRESS,
121 ADD_BRANCH,
122 };
123
124 struct add_op_info {
125 unsigned op;
126 char name[30];
127 enum add_src_type src_type;
128 bool has_data_reg;
129 };
130
131 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
132 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
133 struct bifrost_regs next_regs, uint64_t *consts,
134 unsigned data_reg, unsigned offset, bool verbose);
135 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
136
137 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
138 {
139 fprintf(fp, "id(%du) ", header.scoreboard_index);
140
141 if (header.clause_type != 0) {
142 const char *name = bi_clause_type_name(header.clause_type);
143
144 if (name[0] == '?')
145 fprintf(fp, "unk%u ", header.clause_type);
146 else
147 fprintf(fp, "%s ", name);
148 }
149
150 if (header.scoreboard_deps != 0) {
151 fprintf(fp, "next-wait(");
152 bool first = true;
153 for (unsigned i = 0; i < 8; i++) {
154 if (header.scoreboard_deps & (1 << i)) {
155 if (!first) {
156 fprintf(fp, ", ");
157 }
158 fprintf(fp, "%d", i);
159 first = false;
160 }
161 }
162 fprintf(fp, ") ");
163 }
164
165 if (header.datareg_writebarrier)
166 fprintf(fp, "data-reg-barrier ");
167
168 if (!header.no_end_of_shader)
169 fprintf(fp, "eos ");
170
171 if (!header.back_to_back) {
172 fprintf(fp, "nbb ");
173 if (header.branch_cond)
174 fprintf(fp, "branch-cond ");
175 else
176 fprintf(fp, "branch-uncond ");
177 }
178
179 if (header.elide_writes)
180 fprintf(fp, "we ");
181
182 if (header.suppress_inf)
183 fprintf(fp, "suppress-inf ");
184 if (header.suppress_nan)
185 fprintf(fp, "suppress-nan ");
186
187 if (header.unk0)
188 fprintf(fp, "unk0 ");
189 if (header.unk1)
190 fprintf(fp, "unk1 ");
191 if (header.unk2)
192 fprintf(fp, "unk2 ");
193 if (header.unk3)
194 fprintf(fp, "unk3 ");
195 if (header.unk4)
196 fprintf(fp, "unk4 ");
197
198 fprintf(fp, "\n");
199
200 if (verbose) {
201 fprintf(fp, "# clause type %d, next clause type %d\n",
202 header.clause_type, header.next_clause_type);
203 }
204 }
205
206 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
207 {
208 struct bifrost_reg_ctrl decoded = {};
209 unsigned ctrl;
210 if (regs.ctrl == 0) {
211 ctrl = regs.reg1 >> 2;
212 decoded.read_reg0 = !(regs.reg1 & 0x2);
213 decoded.read_reg1 = false;
214 } else {
215 ctrl = regs.ctrl;
216 decoded.read_reg0 = decoded.read_reg1 = true;
217 }
218 switch (ctrl) {
219 case 1:
220 decoded.fma_write_unit = REG_WRITE_TWO;
221 break;
222 case 2:
223 case 3:
224 decoded.fma_write_unit = REG_WRITE_TWO;
225 decoded.read_reg3 = true;
226 break;
227 case 4:
228 decoded.read_reg3 = true;
229 break;
230 case 5:
231 decoded.add_write_unit = REG_WRITE_TWO;
232 break;
233 case 6:
234 decoded.add_write_unit = REG_WRITE_TWO;
235 decoded.read_reg3 = true;
236 break;
237 case 8:
238 decoded.clause_start = true;
239 break;
240 case 9:
241 decoded.fma_write_unit = REG_WRITE_TWO;
242 decoded.clause_start = true;
243 break;
244 case 11:
245 break;
246 case 12:
247 decoded.read_reg3 = true;
248 decoded.clause_start = true;
249 break;
250 case 13:
251 decoded.add_write_unit = REG_WRITE_TWO;
252 decoded.clause_start = true;
253 break;
254
255 case 7:
256 case 15:
257 decoded.fma_write_unit = REG_WRITE_THREE;
258 decoded.add_write_unit = REG_WRITE_TWO;
259 break;
260 default:
261 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
262 }
263
264 return decoded;
265 }
266
267 // Pass in the add_write_unit or fma_write_unit, and this returns which register
268 // the ADD/FMA units are writing to
269 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
270 {
271 switch (unit) {
272 case REG_WRITE_TWO:
273 return regs.reg2;
274 case REG_WRITE_THREE:
275 return regs.reg3;
276 default: /* REG_WRITE_NONE */
277 assert(0);
278 return 0;
279 }
280 }
281
282 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
283 {
284 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
285 fprintf(fp, "# ");
286 if (ctrl.read_reg0)
287 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
288 if (ctrl.read_reg1)
289 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
290
291 if (ctrl.fma_write_unit == REG_WRITE_TWO)
292 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
293 else if (ctrl.add_write_unit == REG_WRITE_TWO)
294 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
295
296 if (ctrl.fma_write_unit == REG_WRITE_THREE)
297 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
298 else if (ctrl.add_write_unit == REG_WRITE_THREE)
299 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
300 else if (ctrl.read_reg3)
301 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
302
303 if (srcs.uniform_const) {
304 if (srcs.uniform_const & 0x80) {
305 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
306 }
307 }
308
309 fprintf(fp, "\n");
310 }
311 static void dump_const_imm(FILE *fp, uint32_t imm)
312 {
313 union {
314 float f;
315 uint32_t i;
316 } fi;
317 fi.i = imm;
318 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
319 }
320
321 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
322 {
323 unsigned low_bits = srcs.uniform_const & 0xf;
324 uint64_t imm;
325 switch (srcs.uniform_const >> 4) {
326 case 4:
327 imm = consts[0];
328 break;
329 case 5:
330 imm = consts[1];
331 break;
332 case 6:
333 imm = consts[2];
334 break;
335 case 7:
336 imm = consts[3];
337 break;
338 case 2:
339 imm = consts[4];
340 break;
341 case 3:
342 imm = consts[5];
343 break;
344 default:
345 assert(0);
346 break;
347 }
348 return imm | low_bits;
349 }
350
351 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
352 {
353 if (srcs.uniform_const & 0x80) {
354 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
355 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
356 } else if (srcs.uniform_const >= 0x20) {
357 uint64_t imm = get_const(consts, srcs);
358 if (high32)
359 dump_const_imm(fp, imm >> 32);
360 else
361 dump_const_imm(fp, imm);
362 } else {
363 switch (srcs.uniform_const) {
364 case 0:
365 fprintf(fp, "0");
366 break;
367 case 5:
368 fprintf(fp, "atest-data");
369 break;
370 case 6:
371 fprintf(fp, "sample-ptr");
372 break;
373 case 8:
374 case 9:
375 case 10:
376 case 11:
377 case 12:
378 case 13:
379 case 14:
380 case 15:
381 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
382 break;
383 default:
384 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
385 break;
386 }
387
388 if (high32)
389 fprintf(fp, ".y");
390 else
391 fprintf(fp, ".x");
392 }
393 }
394
395 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
396 {
397 switch (src) {
398 case 0:
399 fprintf(fp, "R%d", get_reg0(srcs));
400 break;
401 case 1:
402 fprintf(fp, "R%d", get_reg1(srcs));
403 break;
404 case 2:
405 fprintf(fp, "R%d", srcs.reg3);
406 break;
407 case 3:
408 if (isFMA)
409 fprintf(fp, "0");
410 else
411 fprintf(fp, "T"); // i.e. the output of FMA this cycle
412 break;
413 case 4:
414 dump_uniform_const_src(fp, srcs, consts, false);
415 break;
416 case 5:
417 dump_uniform_const_src(fp, srcs, consts, true);
418 break;
419 case 6:
420 fprintf(fp, "T0");
421 break;
422 case 7:
423 fprintf(fp, "T1");
424 break;
425 }
426 }
427
428 static const struct fma_op_info FMAOpInfos[] = {
429 { false, 0x00000, "FMA.f32", FMA_FMA },
430 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
431 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
432 { false, 0x48000, "FCMP.GL", FMA_FCMP },
433 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
434 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
435 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
436 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
437 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
438 { false, 0x58000, "ADD.f32", FMA_FADD },
439 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
440 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
441 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
442 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
443 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
444 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
445 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
446 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
447 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
448 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
449 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
450 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
451 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
452 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
453 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
454 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
455 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
456 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
457 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
458 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
459 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
460 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
461 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
462 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
463 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
464 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
465 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
466 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
467 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
468 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
469 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
470 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
471 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
472 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
473 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
474 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
475 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
476 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
477 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
478 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
479 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
480 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
481 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
482 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
483
484 /* TODO: Combine to bifrost_fma_f2i_i2f16 */
485 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
486 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
487 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
488 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
489 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
490 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
491 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
492 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
493 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
494 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
495 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
496 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
497 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
498 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
499 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
500 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
501
502 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
503 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
504 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
505 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
506
507 /* TODO: cleanup to use bifrost_fma_int16_to_32 */
508 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
509 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
510 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
511 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
512 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
513 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
514 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
515 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
516
517 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
518 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
519
520 { true, 0x0032c, "NOP", FMA_ONE_SRC },
521 { true, 0x0032d, "MOV", FMA_ONE_SRC },
522 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
523 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
524 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
525 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
526 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
527 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
528 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
529 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
530 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
531 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
532 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
533 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
534 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
535 { true, 0x00ec2, "ROUND.v2f16", FMA_ONE_SRC },
536 { true, 0x00ec5, "ROUND.f32", FMA_ONE_SRC },
537 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
538 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
539 { true, 0x01802, "ROUNDEVEN.v2f16", FMA_ONE_SRC },
540 { true, 0x01805, "ROUNDEVEN.f32", FMA_ONE_SRC },
541 { true, 0x01842, "CEIL.v2f16", FMA_ONE_SRC },
542 { true, 0x01845, "CEIL.f32", FMA_ONE_SRC },
543 { true, 0x01882, "FLOOR.v2f16", FMA_ONE_SRC },
544 { true, 0x01885, "FLOOR.f32", FMA_ONE_SRC },
545 { true, 0x018c2, "TRUNC.v2f16", FMA_ONE_SRC },
546 { true, 0x018c5, "TRUNC.f32", FMA_ONE_SRC },
547 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
548 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
549 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
550 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
551 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
552 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
553 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
554 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
555 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
556 { true, 0x01e80, "ADD_FREXPM.f32", FMA_TWO_SRC },
557 { true, 0x02000, "SWZ.XXXX.v4i8", FMA_ONE_SRC },
558 { true, 0x03e00, "SWZ.ZZZZ.v4i8", FMA_ONE_SRC },
559 { true, 0x00800, "IMAD", FMA_THREE_SRC },
560 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
561 };
562
563 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
564 {
565 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
566 unsigned opCmp = ~0;
567
568 if (FMAOpInfos[i].extended != extended)
569 continue;
570
571 if (extended)
572 op &= ~0xe0000;
573
574 switch (FMAOpInfos[i].src_type) {
575 case FMA_ONE_SRC:
576 opCmp = op;
577 break;
578 case FMA_TWO_SRC:
579 opCmp = op & ~0x7;
580 break;
581 case FMA_FCMP:
582 case FMA_FCMP16:
583 opCmp = op & ~0x1fff;
584 break;
585 case FMA_THREE_SRC:
586 case FMA_SHIFT_ADD64:
587 opCmp = op & ~0x3f;
588 break;
589 case FMA_FADD:
590 case FMA_FMINMAX:
591 case FMA_FADD16:
592 case FMA_FMINMAX16:
593 opCmp = op & ~0x3fff;
594 break;
595 case FMA_FMA:
596 case FMA_FMA16:
597 opCmp = op & ~0x3ffff;
598 break;
599 case FMA_CSEL4:
600 case FMA_SHIFT:
601 opCmp = op & ~0xfff;
602 break;
603 case FMA_FMA_MSCALE:
604 opCmp = op & ~0x7fff;
605 break;
606 default:
607 opCmp = ~0;
608 break;
609 }
610 if (FMAOpInfos[i].op == opCmp)
611 return FMAOpInfos[i];
612 }
613
614 struct fma_op_info info;
615 snprintf(info.name, sizeof(info.name), "op%04x", op);
616 info.extended = extended;
617 info.op = op;
618 info.src_type = FMA_THREE_SRC;
619 return info;
620 }
621
622 static void dump_fcmp(FILE *fp, unsigned op)
623 {
624 switch (op) {
625 case 0:
626 fprintf(fp, ".OEQ");
627 break;
628 case 1:
629 fprintf(fp, ".OGT");
630 break;
631 case 2:
632 fprintf(fp, ".OGE");
633 break;
634 case 3:
635 fprintf(fp, ".UNE");
636 break;
637 case 4:
638 fprintf(fp, ".OLT");
639 break;
640 case 5:
641 fprintf(fp, ".OLE");
642 break;
643 default:
644 fprintf(fp, ".unk%d", op);
645 break;
646 }
647 }
648
649 static void dump_16swizzle(FILE *fp, unsigned swiz)
650 {
651 if (swiz == 2)
652 return;
653 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
654 }
655
656 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
657 {
658 switch (ctrl) {
659 case 3:
660 case 4:
661 case 6:
662 fprintf(fp, ".x");
663 break;
664 case 5:
665 case 7:
666 fprintf(fp, ".y");
667 break;
668 case 0:
669 case 1:
670 case 2:
671 break;
672 default:
673 fprintf(fp, ".unk");
674 break;
675 }
676 }
677
678 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
679 {
680 switch (ctrl) {
681 case 1:
682 case 3:
683 fprintf(fp, ".x");
684 break;
685 case 2:
686 case 4:
687 case 5:
688 fprintf(fp, ".y");
689 break;
690 case 0:
691 case 6:
692 case 7:
693 break;
694 default:
695 fprintf(fp, ".unk");
696 break;
697 }
698 }
699
700 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
701 {
702 if (verbose) {
703 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
704 }
705 struct bifrost_fma_inst FMA;
706 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
707 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
708
709 fprintf(fp, "%s", info.name);
710 if (info.src_type == FMA_FADD ||
711 info.src_type == FMA_FMINMAX ||
712 info.src_type == FMA_FMA ||
713 info.src_type == FMA_FADD16 ||
714 info.src_type == FMA_FMINMAX16 ||
715 info.src_type == FMA_FMA16) {
716 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 12, 14)));
717 switch (info.src_type) {
718 case FMA_FADD:
719 case FMA_FMA:
720 case FMA_FADD16:
721 case FMA_FMA16:
722 fprintf(fp, "%s", bi_round_mode_name(bits(FMA.op, 10, 12)));
723 break;
724 case FMA_FMINMAX:
725 case FMA_FMINMAX16:
726 fprintf(fp, "%s", bi_minmax_mode_name(bits(FMA.op, 10, 12)));
727 break;
728 default:
729 assert(0);
730 }
731 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
732 dump_fcmp(fp, bits(FMA.op, 10, 13));
733 if (info.src_type == FMA_FCMP)
734 fprintf(fp, ".f32");
735 else
736 fprintf(fp, ".v2f16");
737 } else if (info.src_type == FMA_FMA_MSCALE) {
738 if (FMA.op & (1 << 11)) {
739 switch ((FMA.op >> 9) & 0x3) {
740 case 0:
741 /* This mode seems to do a few things:
742 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
743 * since generating a nan would poison the result of
744 * 1/infinity and 1/0.
745 * - Fiddles with which nan is returned in nan * nan,
746 * presumably to make sure that the same exact nan is
747 * returned for 1/nan.
748 */
749 fprintf(fp, ".rcp_mode");
750 break;
751 case 3:
752 /* Similar to the above, but src0 always wins when multiplying
753 * 0 by infinity.
754 */
755 fprintf(fp, ".sqrt_mode");
756 break;
757 default:
758 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
759 }
760 } else {
761 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 9, 11)));
762 }
763 } else if (info.src_type == FMA_SHIFT) {
764 struct bifrost_shift_fma shift;
765 memcpy(&shift, &FMA, sizeof(shift));
766
767 if (shift.half == 0x7)
768 fprintf(fp, ".v2i16");
769 else if (shift.half == 0)
770 fprintf(fp, ".i32");
771 else if (shift.half == 0x4)
772 fprintf(fp, ".v4i8");
773 else
774 fprintf(fp, ".unk%u", shift.half);
775
776 if (!shift.unk)
777 fprintf(fp, ".no_unk");
778
779 if (shift.invert_1)
780 fprintf(fp, ".invert_1");
781
782 if (shift.invert_2)
783 fprintf(fp, ".invert_2");
784 }
785
786 fprintf(fp, " ");
787
788 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
789 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
790 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
791 } else {
792 fprintf(fp, "T0, ");
793 }
794
795 switch (info.src_type) {
796 case FMA_ONE_SRC:
797 dump_src(fp, FMA.src0, regs, consts, true);
798 break;
799 case FMA_TWO_SRC:
800 dump_src(fp, FMA.src0, regs, consts, true);
801 fprintf(fp, ", ");
802 dump_src(fp, FMA.op & 0x7, regs, consts, true);
803 break;
804 case FMA_FADD:
805 case FMA_FMINMAX:
806 if (FMA.op & 0x10)
807 fprintf(fp, "-");
808 if (FMA.op & 0x200)
809 fprintf(fp, "abs(");
810 dump_src(fp, FMA.src0, regs, consts, true);
811 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
812 if (FMA.op & 0x200)
813 fprintf(fp, ")");
814 fprintf(fp, ", ");
815 if (FMA.op & 0x20)
816 fprintf(fp, "-");
817 if (FMA.op & 0x8)
818 fprintf(fp, "abs(");
819 dump_src(fp, FMA.op & 0x7, regs, consts, true);
820 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
821 if (FMA.op & 0x8)
822 fprintf(fp, ")");
823 break;
824 case FMA_FADD16:
825 case FMA_FMINMAX16: {
826 bool abs1 = FMA.op & 0x8;
827 bool abs2 = (FMA.op & 0x7) < FMA.src0;
828 if (FMA.op & 0x10)
829 fprintf(fp, "-");
830 if (abs1 || abs2)
831 fprintf(fp, "abs(");
832 dump_src(fp, FMA.src0, regs, consts, true);
833 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
834 if (abs1 || abs2)
835 fprintf(fp, ")");
836 fprintf(fp, ", ");
837 if (FMA.op & 0x20)
838 fprintf(fp, "-");
839 if (abs1 && abs2)
840 fprintf(fp, "abs(");
841 dump_src(fp, FMA.op & 0x7, regs, consts, true);
842 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
843 if (abs1 && abs2)
844 fprintf(fp, ")");
845 break;
846 }
847 case FMA_FCMP:
848 if (FMA.op & 0x200)
849 fprintf(fp, "abs(");
850 dump_src(fp, FMA.src0, regs, consts, true);
851 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
852 if (FMA.op & 0x200)
853 fprintf(fp, ")");
854 fprintf(fp, ", ");
855 if (FMA.op & 0x20)
856 fprintf(fp, "-");
857 if (FMA.op & 0x8)
858 fprintf(fp, "abs(");
859 dump_src(fp, FMA.op & 0x7, regs, consts, true);
860 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
861 if (FMA.op & 0x8)
862 fprintf(fp, ")");
863 break;
864 case FMA_FCMP16:
865 dump_src(fp, FMA.src0, regs, consts, true);
866 // Note: this is kinda a guess, I haven't seen the blob set this to
867 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
868 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
869 fprintf(fp, ", ");
870 dump_src(fp, FMA.op & 0x7, regs, consts, true);
871 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
872 break;
873 case FMA_SHIFT_ADD64:
874 dump_src(fp, FMA.src0, regs, consts, true);
875 fprintf(fp, ", ");
876 dump_src(fp, FMA.op & 0x7, regs, consts, true);
877 fprintf(fp, ", ");
878 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
879 break;
880 case FMA_THREE_SRC:
881 dump_src(fp, FMA.src0, regs, consts, true);
882 fprintf(fp, ", ");
883 dump_src(fp, FMA.op & 0x7, regs, consts, true);
884 fprintf(fp, ", ");
885 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
886 break;
887 case FMA_SHIFT: {
888 struct bifrost_shift_fma shift;
889 memcpy(&shift, &FMA, sizeof(shift));
890
891 dump_src(fp, shift.src0, regs, consts, true);
892 fprintf(fp, ", ");
893 dump_src(fp, shift.src1, regs, consts, true);
894 fprintf(fp, ", ");
895 dump_src(fp, shift.src2, regs, consts, true);
896 break;
897 }
898 case FMA_FMA:
899 if (FMA.op & (1 << 14))
900 fprintf(fp, "-");
901 if (FMA.op & (1 << 9))
902 fprintf(fp, "abs(");
903 dump_src(fp, FMA.src0, regs, consts, true);
904 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
905 if (FMA.op & (1 << 9))
906 fprintf(fp, ")");
907 fprintf(fp, ", ");
908 if (FMA.op & (1 << 16))
909 fprintf(fp, "abs(");
910 dump_src(fp, FMA.op & 0x7, regs, consts, true);
911 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
912 if (FMA.op & (1 << 16))
913 fprintf(fp, ")");
914 fprintf(fp, ", ");
915 if (FMA.op & (1 << 15))
916 fprintf(fp, "-");
917 if (FMA.op & (1 << 17))
918 fprintf(fp, "abs(");
919 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
920 if (FMA.op & (1 << 17))
921 fprintf(fp, ")");
922 break;
923 case FMA_FMA16:
924 if (FMA.op & (1 << 14))
925 fprintf(fp, "-");
926 dump_src(fp, FMA.src0, regs, consts, true);
927 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
928 fprintf(fp, ", ");
929 dump_src(fp, FMA.op & 0x7, regs, consts, true);
930 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
931 fprintf(fp, ", ");
932 if (FMA.op & (1 << 15))
933 fprintf(fp, "-");
934 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
935 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
936 break;
937 case FMA_CSEL4: {
938 struct bifrost_csel4 csel;
939 memcpy(&csel, &FMA, sizeof(csel));
940 fprintf(fp, ".%s ", bi_csel_cond_name(csel.cond));
941
942 dump_src(fp, csel.src0, regs, consts, true);
943 fprintf(fp, ", ");
944 dump_src(fp, csel.src1, regs, consts, true);
945 fprintf(fp, ", ");
946 dump_src(fp, csel.src2, regs, consts, true);
947 fprintf(fp, ", ");
948 dump_src(fp, csel.src3, regs, consts, true);
949 break;
950 }
951 case FMA_FMA_MSCALE:
952 if (FMA.op & (1 << 12))
953 fprintf(fp, "abs(");
954 dump_src(fp, FMA.src0, regs, consts, true);
955 if (FMA.op & (1 << 12))
956 fprintf(fp, ")");
957 fprintf(fp, ", ");
958 if (FMA.op & (1 << 13))
959 fprintf(fp, "-");
960 dump_src(fp, FMA.op & 0x7, regs, consts, true);
961 fprintf(fp, ", ");
962 if (FMA.op & (1 << 14))
963 fprintf(fp, "-");
964 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
965 fprintf(fp, ", ");
966 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
967 break;
968 }
969 fprintf(fp, "\n");
970 }
971
972 static const struct add_op_info add_op_infos[] = {
973 { 0x00000, "MAX.f32", ADD_FMINMAX },
974 { 0x02000, "MIN.f32", ADD_FMINMAX },
975 { 0x04000, "ADD.f32", ADD_FADD },
976 { 0x06000, "FCMP.GL", ADD_FCMP },
977 { 0x07000, "FCMP.D3D", ADD_FCMP },
978 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
979 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
980 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
981 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
982 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
983 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
984 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
985 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
986 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
987 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
988 { 0x07909, "B1_TO_F16", ADD_ONE_SRC },
989 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
990 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
991 { 0x07971, "B1_TO_F32", ADD_ONE_SRC },
992 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
993 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
994 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
995 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
996 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
997 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
998 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
999 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
1000 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
1001 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
1002 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
1003 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
1004 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1005 { 0x07b2c, "NOP", ADD_ONE_SRC },
1006 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1007 { 0x07b2d, "MOV", ADD_ONE_SRC },
1008 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1009 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1010 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1011 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1012 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1013 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1014 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1015 { 0x07d42, "CEIL.v2f16", ADD_ONE_SRC },
1016 { 0x07d45, "CEIL.f32", ADD_ONE_SRC },
1017 { 0x07d82, "FLOOR.v2f16", ADD_ONE_SRC },
1018 { 0x07d85, "FLOOR.f32", ADD_ONE_SRC },
1019 { 0x07dc2, "TRUNC.v2f16", ADD_ONE_SRC },
1020 { 0x07dc5, "TRUNC.f32", ADD_ONE_SRC },
1021 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1022 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
1023 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1024 { 0x0b000, "TEXC", ADD_TEX_COMPACT, true },
1025 { 0x0b400, "TEXC.vtx", ADD_TEX_COMPACT, true },
1026 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1027 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1028 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1029 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1030 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1031 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1032 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1033 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1034 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1035 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1036 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1037 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1038 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1039 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1040 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1041 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1042 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1043 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1044 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1045 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1046 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1047 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1048 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1049 { 0x0cc68, "FLOG2_U.f32", ADD_ONE_SRC },
1050 { 0x0cd58, "FEXP2_FAST.f32", ADD_ONE_SRC },
1051 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1052 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1053 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1054 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1055 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1056 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1057 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1058 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1059 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1060 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1061 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1062 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1063 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1064 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1065 { 0x0d000, "BRANCH", ADD_BRANCH },
1066 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1067 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1068 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1069 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1070 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1071 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1072 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1073 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1074 { 0x0e840, "CSEL.64", ADD_THREE_SRC }, // u2u32(src2) ? src0 : src1
1075 { 0x0e940, "CSEL.8", ADD_THREE_SRC }, // (src2 != 0) ? src0 : src1
1076 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1077 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1078 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1079 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1080 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1081 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1082 { 0x0f690, "UCMP.8.GT", ADD_TWO_SRC },
1083 { 0x0f698, "UCMP.8.GE", ADD_TWO_SRC },
1084 { 0x0f6a8, "ICMP.8.NE", ADD_TWO_SRC },
1085 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1086 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1087 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1088 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1089 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1090 { 0x0f700, "ICMP.64.GT.PT1", ADD_TWO_SRC },
1091 { 0x0f708, "ICMP.64.GE.PT1", ADD_TWO_SRC },
1092 { 0x0f710, "UCMP.64.GT.PT1", ADD_TWO_SRC },
1093 { 0x0f718, "UCMP.64.GE.PT1", ADD_TWO_SRC },
1094 { 0x0f720, "ICMP.64.EQ.PT1", ADD_TWO_SRC },
1095 { 0x0f728, "ICMP.64.NE.PT1", ADD_TWO_SRC },
1096 { 0x0f7c0, "ICMP.64.PT2", ADD_THREE_SRC }, // src3 = result of PT1
1097 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1098 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1099 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1100 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1101 { 0x16000, "FCMP.GL", ADD_FCMP16 },
1102 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1103 { 0x17880, "ADD.v4i8", ADD_TWO_SRC },
1104 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1105 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1106 { 0x17a80, "SUB.v4i8", ADD_TWO_SRC },
1107 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1108 { 0x17b00, "SUB.v2i16", ADD_TWO_SRC },
1109 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1110 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1111 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1112 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1113 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1114 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, false },
1115 { 0x19100, "DISCARD.FEQ.f16", ADD_TWO_SRC, false },
1116 { 0x19108, "DISCARD.FNE.f16", ADD_TWO_SRC, false },
1117 { 0x19110, "DISCARD.FLE.f16", ADD_TWO_SRC, false },
1118 { 0x19118, "DISCARD.FLT.f16", ADD_TWO_SRC, false },
1119 { 0x19180, "DISCARD.FEQ.f32", ADD_TWO_SRC, false },
1120 { 0x19188, "DISCARD.FNE.f32", ADD_TWO_SRC, false },
1121 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, false },
1122 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, false },
1123 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1124 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1125 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1126 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1127 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1128 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1129 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1130 { 0x1952c, "BLEND", ADD_BLENDING, true },
1131 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1132 { 0x1ae20, "TEX.vtx", ADD_TEX, true },
1133 { 0x1ae60, "TEX", ADD_TEX, true },
1134 { 0x1b000, "TEXC.f16", ADD_TEX_COMPACT, true },
1135 { 0x1b400, "TEXC.vtx.f16", ADD_TEX_COMPACT, true },
1136 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
1137 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
1138 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
1139 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT },
1140 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT },
1141 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT },
1142 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT },
1143 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1144 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1145 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1146 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1147 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1148 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1149 };
1150
1151 static struct add_op_info find_add_op_info(unsigned op)
1152 {
1153 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1154 unsigned opCmp = ~0;
1155 switch (add_op_infos[i].src_type) {
1156 case ADD_ONE_SRC:
1157 case ADD_BLENDING:
1158 opCmp = op;
1159 break;
1160 case ADD_TWO_SRC:
1161 opCmp = op & ~0x7;
1162 break;
1163 case ADD_THREE_SRC:
1164 opCmp = op & ~0x3f;
1165 break;
1166 case ADD_SHIFT:
1167 opCmp = op & ~0x3ff;
1168 break;
1169 case ADD_TEX:
1170 opCmp = op & ~0xf;
1171 break;
1172 case ADD_FADD:
1173 case ADD_FMINMAX:
1174 case ADD_FADD16:
1175 opCmp = op & ~0x1fff;
1176 break;
1177 case ADD_FMINMAX16:
1178 case ADD_FADDMscale:
1179 opCmp = op & ~0xfff;
1180 break;
1181 case ADD_FCMP:
1182 case ADD_FCMP16:
1183 opCmp = op & ~0x7ff;
1184 break;
1185 case ADD_TEX_COMPACT:
1186 opCmp = op & ~0x3ff;
1187 break;
1188 case ADD_VARYING_INTERP:
1189 opCmp = op & ~0x7ff;
1190 break;
1191 case ADD_VARYING_ADDRESS:
1192 opCmp = op & ~0xfff;
1193 break;
1194 case ADD_LOAD_ATTR:
1195 case ADD_BRANCH:
1196 opCmp = op & ~0xfff;
1197 break;
1198 default:
1199 opCmp = ~0;
1200 break;
1201 }
1202 if (add_op_infos[i].op == opCmp)
1203 return add_op_infos[i];
1204 }
1205
1206 struct add_op_info info;
1207 snprintf(info.name, sizeof(info.name), "op%04x", op);
1208 info.op = op;
1209 info.src_type = ADD_TWO_SRC;
1210 info.has_data_reg = true;
1211 return info;
1212 }
1213
1214 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1215 struct bifrost_regs next_regs, uint64_t *consts,
1216 unsigned data_reg, unsigned offset, bool verbose)
1217 {
1218 if (verbose) {
1219 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1220 }
1221 struct bifrost_add_inst ADD;
1222 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1223 struct add_op_info info = find_add_op_info(ADD.op);
1224
1225 fprintf(fp, "%s", info.name);
1226
1227 // float16 seems like it doesn't support output modifiers
1228 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1229 // output modifiers
1230 fprintf(fp, "%s", bi_output_mod_name(bits(ADD.op, 8, 10)));
1231 if (info.src_type == ADD_FADD)
1232 fprintf(fp, "%s", bi_round_mode_name(bits(ADD.op, 10, 12)));
1233 else
1234 fprintf(fp, "%s", bi_minmax_mode_name(bits(ADD.op, 10, 12)));
1235 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1236 dump_fcmp(fp, bits(ADD.op, 3, 6));
1237 if (info.src_type == ADD_FCMP)
1238 fprintf(fp, ".f32");
1239 else
1240 fprintf(fp, ".v2f16");
1241 } else if (info.src_type == ADD_FADDMscale) {
1242 switch ((ADD.op >> 6) & 0x7) {
1243 case 0:
1244 break;
1245 // causes GPU hangs on G71
1246 case 1:
1247 fprintf(fp, ".invalid");
1248 break;
1249 // Same as usual outmod value.
1250 case 2:
1251 fprintf(fp, ".clamp_0_1");
1252 break;
1253 // If src0 is infinite or NaN, flush it to zero so that the other
1254 // source is passed through unmodified.
1255 case 3:
1256 fprintf(fp, ".flush_src0_inf_nan");
1257 break;
1258 // Vice versa.
1259 case 4:
1260 fprintf(fp, ".flush_src1_inf_nan");
1261 break;
1262 // Every other case seems to behave the same as the above?
1263 default:
1264 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1265 break;
1266 }
1267 } else if (info.src_type == ADD_VARYING_INTERP) {
1268 if (ADD.op & 0x200)
1269 fprintf(fp, ".reuse");
1270 if (ADD.op & 0x400)
1271 fprintf(fp, ".flat");
1272 fprintf(fp, "%s", bi_interp_mode_name((ADD.op >> 7) & 0x3));
1273 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1274 } else if (info.src_type == ADD_BRANCH) {
1275 enum bifrost_branch_code branchCode = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1276 if (branchCode == BR_ALWAYS) {
1277 // unconditional branch
1278 } else {
1279 enum bifrost_branch_cond cond = (enum bifrost_branch_cond) ((ADD.op >> 6) & 0x7);
1280 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1281 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1282 // See the comment in branch_bit_size
1283 if (size == BR_SIZE_16YX0)
1284 portSwapped = true;
1285 if (size == BR_SIZE_16YX1)
1286 portSwapped = false;
1287 // These sizes are only for floating point comparisons, so the
1288 // non-floating-point comparisons are reused to encode the flipped
1289 // versions.
1290 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1291 portSwapped = false;
1292 // There's only one argument, so we reuse the extra argument to
1293 // encode this.
1294 if (size == BR_SIZE_ZERO)
1295 portSwapped = !(ADD.op & 1);
1296
1297 switch (cond) {
1298 case BR_COND_LT:
1299 if (portSwapped)
1300 fprintf(fp, ".LT.u");
1301 else
1302 fprintf(fp, ".LT.i");
1303 break;
1304 case BR_COND_LE:
1305 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1306 fprintf(fp, ".UNE.f");
1307 } else {
1308 if (portSwapped)
1309 fprintf(fp, ".LE.u");
1310 else
1311 fprintf(fp, ".LE.i");
1312 }
1313 break;
1314 case BR_COND_GT:
1315 if (portSwapped)
1316 fprintf(fp, ".GT.u");
1317 else
1318 fprintf(fp, ".GT.i");
1319 break;
1320 case BR_COND_GE:
1321 if (portSwapped)
1322 fprintf(fp, ".GE.u");
1323 else
1324 fprintf(fp, ".GE.i");
1325 break;
1326 case BR_COND_EQ:
1327 if (portSwapped)
1328 fprintf(fp, ".NE.i");
1329 else
1330 fprintf(fp, ".EQ.i");
1331 break;
1332 case BR_COND_OEQ:
1333 if (portSwapped)
1334 fprintf(fp, ".UNE.f");
1335 else
1336 fprintf(fp, ".OEQ.f");
1337 break;
1338 case BR_COND_OGT:
1339 if (portSwapped)
1340 fprintf(fp, ".OGT.unk.f");
1341 else
1342 fprintf(fp, ".OGT.f");
1343 break;
1344 case BR_COND_OLT:
1345 if (portSwapped)
1346 fprintf(fp, ".OLT.unk.f");
1347 else
1348 fprintf(fp, ".OLT.f");
1349 break;
1350 }
1351 switch (size) {
1352 case BR_SIZE_32:
1353 case BR_SIZE_32_AND_16X:
1354 case BR_SIZE_32_AND_16Y:
1355 fprintf(fp, "32");
1356 break;
1357 case BR_SIZE_16XX:
1358 case BR_SIZE_16YY:
1359 case BR_SIZE_16YX0:
1360 case BR_SIZE_16YX1:
1361 fprintf(fp, "16");
1362 break;
1363 case BR_SIZE_ZERO: {
1364 unsigned ctrl = (ADD.op >> 1) & 0x3;
1365 if (ctrl == 0)
1366 fprintf(fp, "32.Z");
1367 else
1368 fprintf(fp, "16.Z");
1369 break;
1370 }
1371 }
1372 }
1373 } else if (info.src_type == ADD_SHIFT) {
1374 struct bifrost_shift_add shift;
1375 memcpy(&shift, &ADD, sizeof(ADD));
1376
1377 if (shift.invert_1)
1378 fprintf(fp, ".invert_1");
1379
1380 if (shift.invert_2)
1381 fprintf(fp, ".invert_2");
1382
1383 if (shift.zero)
1384 fprintf(fp, ".unk%u", shift.zero);
1385 } else if (info.src_type == ADD_VARYING_ADDRESS) {
1386 struct bifrost_ld_var_addr ld;
1387 memcpy(&ld, &ADD, sizeof(ADD));
1388 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1389 } else if (info.src_type == ADD_LOAD_ATTR) {
1390 struct bifrost_ld_attr ld;
1391 memcpy(&ld, &ADD, sizeof(ADD));
1392
1393 if (ld.channels)
1394 fprintf(fp, ".v%d%s", ld.channels + 1, bi_ldst_type_name(ld.type));
1395 else
1396 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1397 }
1398
1399 fprintf(fp, " ");
1400
1401 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1402 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1403 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1404 } else {
1405 fprintf(fp, "T1, ");
1406 }
1407
1408 switch (info.src_type) {
1409 case ADD_BLENDING:
1410 // Note: in this case, regs.uniform_const == location | 0x8
1411 // This probably means we can't load uniforms or immediates in the
1412 // same instruction. This re-uses the encoding that normally means
1413 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1414 // 0x8 or'd in indicates this is happening.
1415 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1416 // fallthrough
1417 case ADD_ONE_SRC:
1418 dump_src(fp, ADD.src0, regs, consts, false);
1419 break;
1420 case ADD_TEX:
1421 case ADD_TEX_COMPACT: {
1422 int tex_index;
1423 int sampler_index;
1424 bool dualTex = false;
1425
1426 fprintf(fp, "coords <");
1427 dump_src(fp, ADD.src0, regs, consts, false);
1428 fprintf(fp, ", ");
1429 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1430 fprintf(fp, ">, ");
1431
1432 if (info.src_type == ADD_TEX_COMPACT) {
1433 tex_index = (ADD.op >> 3) & 0x7;
1434 sampler_index = (ADD.op >> 7) & 0x7;
1435 bool compute_lod = (ADD.op & 0x40);
1436 if (!compute_lod)
1437 fprintf(fp, "vtx lod 0 ");
1438 } else {
1439 uint64_t constVal = get_const(consts, regs);
1440 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1441 struct bifrost_tex_ctrl ctrl;
1442 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1443
1444 /* Dual-tex triggered for adjacent texturing
1445 * instructions with the same coordinates to different
1446 * textures/samplers. Observed for the compact
1447 * (2D/normal) case. */
1448
1449 if ((ctrl.result_type & 7) == 1) {
1450 bool f32 = ctrl.result_type & 8;
1451
1452 struct bifrost_dual_tex_ctrl dualCtrl;
1453 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1454 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d %s",
1455 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1456 dualCtrl.tex_index1, dualCtrl.sampler_index1,
1457 f32 ? "f32" : "f16");
1458 if (dualCtrl.unk0 != 3)
1459 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1460 dualTex = true;
1461 } else {
1462 if (ctrl.no_merge_index) {
1463 tex_index = ctrl.tex_index;
1464 sampler_index = ctrl.sampler_index;
1465 } else {
1466 tex_index = sampler_index = ctrl.tex_index;
1467 unsigned unk = ctrl.sampler_index >> 2;
1468 if (unk != 3)
1469 fprintf(fp, "unk:%d ", unk);
1470 if (ctrl.sampler_index & 1)
1471 tex_index = -1;
1472 if (ctrl.sampler_index & 2)
1473 sampler_index = -1;
1474 }
1475
1476 if (ctrl.unk0 != 3)
1477 fprintf(fp, "unk0:%d ", ctrl.unk0);
1478 if (ctrl.unk1)
1479 fprintf(fp, "unk1 ");
1480 if (ctrl.unk2 != 0xf)
1481 fprintf(fp, "unk2:%x ", ctrl.unk2);
1482
1483 switch (ctrl.result_type) {
1484 case 0x4:
1485 fprintf(fp, "f32 ");
1486 break;
1487 case 0xe:
1488 fprintf(fp, "i32 ");
1489 break;
1490 case 0xf:
1491 fprintf(fp, "u32 ");
1492 break;
1493 default:
1494 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1495 }
1496
1497 switch (ctrl.tex_type) {
1498 case 0:
1499 fprintf(fp, "cube ");
1500 break;
1501 case 1:
1502 fprintf(fp, "buffer ");
1503 break;
1504 case 2:
1505 fprintf(fp, "2D ");
1506 break;
1507 case 3:
1508 fprintf(fp, "3D ");
1509 break;
1510 }
1511
1512 if (ctrl.is_shadow)
1513 fprintf(fp, "shadow ");
1514 if (ctrl.is_array)
1515 fprintf(fp, "array ");
1516
1517 if (!ctrl.filter) {
1518 if (ctrl.calc_gradients) {
1519 int comp = (controlBits >> 20) & 0x3;
1520 fprintf(fp, "txg comp:%d ", comp);
1521 } else {
1522 fprintf(fp, "txf ");
1523 }
1524 } else {
1525 if (!ctrl.not_supply_lod) {
1526 if (ctrl.compute_lod)
1527 fprintf(fp, "lod_bias ");
1528 else
1529 fprintf(fp, "lod ");
1530 }
1531
1532 if (!ctrl.calc_gradients)
1533 fprintf(fp, "grad ");
1534 }
1535
1536 if (ctrl.texel_offset)
1537 fprintf(fp, "offset ");
1538 }
1539 }
1540
1541 if (!dualTex) {
1542 if (tex_index == -1)
1543 fprintf(fp, "tex:indirect ");
1544 else
1545 fprintf(fp, "tex:%d ", tex_index);
1546
1547 if (sampler_index == -1)
1548 fprintf(fp, "samp:indirect ");
1549 else
1550 fprintf(fp, "samp:%d ", sampler_index);
1551 }
1552 break;
1553 }
1554 case ADD_VARYING_INTERP: {
1555 unsigned addr = ADD.op & 0x1f;
1556 if (addr < 0b10100) {
1557 // direct addr
1558 fprintf(fp, "%d", addr);
1559 } else if (addr < 0b11000) {
1560 if (addr == 22)
1561 fprintf(fp, "fragw");
1562 else if (addr == 23)
1563 fprintf(fp, "fragz");
1564 else
1565 fprintf(fp, "unk%d", addr);
1566 } else {
1567 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1568 }
1569 fprintf(fp, ", ");
1570 dump_src(fp, ADD.src0, regs, consts, false);
1571 break;
1572 }
1573 case ADD_VARYING_ADDRESS: {
1574 dump_src(fp, ADD.src0, regs, consts, false);
1575 fprintf(fp, ", ");
1576 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1577 fprintf(fp, ", ");
1578 unsigned location = (ADD.op >> 3) & 0x1f;
1579 if (location < 16) {
1580 fprintf(fp, "location:%d", location);
1581 } else if (location == 20) {
1582 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1583 } else if (location == 21) {
1584 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1585 } else {
1586 fprintf(fp, "location:%d(unk)", location);
1587 }
1588 break;
1589 }
1590 case ADD_LOAD_ATTR:
1591 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0x1f);
1592 case ADD_TWO_SRC:
1593 dump_src(fp, ADD.src0, regs, consts, false);
1594 fprintf(fp, ", ");
1595 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1596 break;
1597 case ADD_THREE_SRC:
1598 dump_src(fp, ADD.src0, regs, consts, false);
1599 fprintf(fp, ", ");
1600 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1601 fprintf(fp, ", ");
1602 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1603 break;
1604 case ADD_SHIFT: {
1605 struct bifrost_shift_add shift;
1606 memcpy(&shift, &ADD, sizeof(ADD));
1607 dump_src(fp, shift.src0, regs, consts, false);
1608 fprintf(fp, ", ");
1609 dump_src(fp, shift.src1, regs, consts, false);
1610 fprintf(fp, ", ");
1611 dump_src(fp, shift.src2, regs, consts, false);
1612 break;
1613 }
1614 case ADD_FADD:
1615 case ADD_FMINMAX:
1616 if (ADD.op & 0x10)
1617 fprintf(fp, "-");
1618 if (ADD.op & 0x1000)
1619 fprintf(fp, "abs(");
1620 dump_src(fp, ADD.src0, regs, consts, false);
1621 switch ((ADD.op >> 6) & 0x3) {
1622 case 3:
1623 fprintf(fp, ".x");
1624 break;
1625 default:
1626 break;
1627 }
1628 if (ADD.op & 0x1000)
1629 fprintf(fp, ")");
1630 fprintf(fp, ", ");
1631 if (ADD.op & 0x20)
1632 fprintf(fp, "-");
1633 if (ADD.op & 0x8)
1634 fprintf(fp, "abs(");
1635 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1636 switch ((ADD.op >> 6) & 0x3) {
1637 case 1:
1638 case 3:
1639 fprintf(fp, ".x");
1640 break;
1641 case 2:
1642 fprintf(fp, ".y");
1643 break;
1644 case 0:
1645 break;
1646 default:
1647 fprintf(fp, ".unk");
1648 break;
1649 }
1650 if (ADD.op & 0x8)
1651 fprintf(fp, ")");
1652 break;
1653 case ADD_FADD16:
1654 if (ADD.op & 0x10)
1655 fprintf(fp, "-");
1656 if (ADD.op & 0x1000)
1657 fprintf(fp, "abs(");
1658 dump_src(fp, ADD.src0, regs, consts, false);
1659 if (ADD.op & 0x1000)
1660 fprintf(fp, ")");
1661 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1662 fprintf(fp, ", ");
1663 if (ADD.op & 0x20)
1664 fprintf(fp, "-");
1665 if (ADD.op & 0x8)
1666 fprintf(fp, "abs(");
1667 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1668 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1669 if (ADD.op & 0x8)
1670 fprintf(fp, ")");
1671 break;
1672 case ADD_FMINMAX16: {
1673 bool abs1 = ADD.op & 0x8;
1674 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1675 if (ADD.op & 0x10)
1676 fprintf(fp, "-");
1677 if (abs1 || abs2)
1678 fprintf(fp, "abs(");
1679 dump_src(fp, ADD.src0, regs, consts, false);
1680 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1681 if (abs1 || abs2)
1682 fprintf(fp, ")");
1683 fprintf(fp, ", ");
1684 if (ADD.op & 0x20)
1685 fprintf(fp, "-");
1686 if (abs1 && abs2)
1687 fprintf(fp, "abs(");
1688 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1689 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1690 if (abs1 && abs2)
1691 fprintf(fp, ")");
1692 fprintf(fp, "/* %X */\n", (ADD.op >> 10) & 0x3); /* mode */
1693 break;
1694 }
1695 case ADD_FADDMscale: {
1696 if (ADD.op & 0x400)
1697 fprintf(fp, "-");
1698 if (ADD.op & 0x200)
1699 fprintf(fp, "abs(");
1700 dump_src(fp, ADD.src0, regs, consts, false);
1701 if (ADD.op & 0x200)
1702 fprintf(fp, ")");
1703
1704 fprintf(fp, ", ");
1705
1706 if (ADD.op & 0x800)
1707 fprintf(fp, "-");
1708 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1709
1710 fprintf(fp, ", ");
1711
1712 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1713 break;
1714 }
1715 case ADD_FCMP:
1716 if (ADD.op & 0x400) {
1717 fprintf(fp, "-");
1718 }
1719 if (ADD.op & 0x100) {
1720 fprintf(fp, "abs(");
1721 }
1722 dump_src(fp, ADD.src0, regs, consts, false);
1723 switch ((ADD.op >> 6) & 0x3) {
1724 case 3:
1725 fprintf(fp, ".x");
1726 break;
1727 default:
1728 break;
1729 }
1730 if (ADD.op & 0x100) {
1731 fprintf(fp, ")");
1732 }
1733 fprintf(fp, ", ");
1734 if (ADD.op & 0x200) {
1735 fprintf(fp, "abs(");
1736 }
1737 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1738 switch ((ADD.op >> 6) & 0x3) {
1739 case 1:
1740 case 3:
1741 fprintf(fp, ".x");
1742 break;
1743 case 2:
1744 fprintf(fp, ".y");
1745 break;
1746 case 0:
1747 break;
1748 default:
1749 fprintf(fp, ".unk");
1750 break;
1751 }
1752 if (ADD.op & 0x200) {
1753 fprintf(fp, ")");
1754 }
1755 break;
1756 case ADD_FCMP16:
1757 dump_src(fp, ADD.src0, regs, consts, false);
1758 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1759 fprintf(fp, ", ");
1760 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1761 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1762 break;
1763 case ADD_BRANCH: {
1764 enum bifrost_branch_code code = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1765 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1766 if (code != BR_ALWAYS) {
1767 dump_src(fp, ADD.src0, regs, consts, false);
1768 switch (size) {
1769 case BR_SIZE_16XX:
1770 fprintf(fp, ".x");
1771 break;
1772 case BR_SIZE_16YY:
1773 case BR_SIZE_16YX0:
1774 case BR_SIZE_16YX1:
1775 fprintf(fp, ".y");
1776 break;
1777 case BR_SIZE_ZERO: {
1778 unsigned ctrl = (ADD.op >> 1) & 0x3;
1779 switch (ctrl) {
1780 case 1:
1781 fprintf(fp, ".y");
1782 break;
1783 case 2:
1784 fprintf(fp, ".x");
1785 break;
1786 default:
1787 break;
1788 }
1789 }
1790 default:
1791 break;
1792 }
1793 fprintf(fp, ", ");
1794 }
1795 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1796 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1797 switch (size) {
1798 case BR_SIZE_16XX:
1799 case BR_SIZE_16YX0:
1800 case BR_SIZE_16YX1:
1801 case BR_SIZE_32_AND_16X:
1802 fprintf(fp, ".x");
1803 break;
1804 case BR_SIZE_16YY:
1805 case BR_SIZE_32_AND_16Y:
1806 fprintf(fp, ".y");
1807 break;
1808 default:
1809 break;
1810 }
1811 fprintf(fp, ", ");
1812 }
1813 // I haven't had the chance to test if this actually specifies the
1814 // branch offset, since I couldn't get it to produce values other
1815 // than 5 (uniform/const high), but these three bits are always
1816 // consistent across branch instructions, so it makes sense...
1817 int offsetSrc = (ADD.op >> 3) & 0x7;
1818 if (offsetSrc == 4 || offsetSrc == 5) {
1819 // If the offset is known/constant, we can decode it
1820 uint32_t raw_offset;
1821 if (offsetSrc == 4)
1822 raw_offset = get_const(consts, regs);
1823 else
1824 raw_offset = get_const(consts, regs) >> 32;
1825 // The high 4 bits are flags, while the rest is the
1826 // twos-complement offset in bytes (here we convert to
1827 // clauses).
1828 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1829
1830 // If high4 is the high 4 bits of the last 64-bit constant,
1831 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1832 // offset itself is the last constant. Not sure if this is
1833 // actually used, or just garbage in unused bits, but in any
1834 // case, we can just ignore it here since it's redundant. Note
1835 // that if there is any padding, this will be 4 since the
1836 // padding counts as the last constant.
1837 unsigned flags = raw_offset >> 28;
1838 (void) flags;
1839
1840 // Note: the offset is in bytes, relative to the beginning of the
1841 // current clause, so a zero offset would be a loop back to the
1842 // same clause (annoyingly different from Midgard).
1843 fprintf(fp, "clause_%d", offset + branch_offset);
1844 } else {
1845 dump_src(fp, offsetSrc, regs, consts, false);
1846 }
1847 }
1848 }
1849 if (info.has_data_reg) {
1850 fprintf(fp, ", R%d", data_reg);
1851 }
1852 fprintf(fp, "\n");
1853 }
1854
1855 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1856 struct bifrost_regs next_regs, uint64_t *consts,
1857 unsigned data_reg, unsigned offset, bool verbose)
1858 {
1859 struct bifrost_regs regs;
1860 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1861
1862 if (verbose) {
1863 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1864 dump_regs(fp, regs);
1865 }
1866 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1867 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1868 }
1869
1870 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1871 {
1872 // State for a decoded clause
1873 struct bifrost_alu_inst instrs[8] = {};
1874 uint64_t consts[6] = {};
1875 unsigned num_instrs = 0;
1876 unsigned num_consts = 0;
1877 uint64_t header_bits = 0;
1878 bool stopbit = false;
1879
1880 unsigned i;
1881 for (i = 0; ; i++, words += 4) {
1882 if (verbose) {
1883 fprintf(fp, "# ");
1884 for (int j = 0; j < 4; j++)
1885 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1886 fprintf(fp, "\n");
1887 }
1888 unsigned tag = bits(words[0], 0, 8);
1889
1890 // speculatively decode some things that are common between many formats, so we can share some code
1891 struct bifrost_alu_inst main_instr = {};
1892 // 20 bits
1893 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1894 // 23 bits
1895 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1896 // 35 bits
1897 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1898
1899 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1900 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1901
1902 bool stop = tag & 0x40;
1903
1904 if (verbose) {
1905 fprintf(fp, "# tag: 0x%02x\n", tag);
1906 }
1907 if (tag & 0x80) {
1908 unsigned idx = stop ? 5 : 2;
1909 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
1910 instrs[idx + 1] = main_instr;
1911 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
1912 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
1913 consts[0] = bits(words[3], 17, 32) << 4;
1914 } else {
1915 bool done = false;
1916 switch ((tag >> 3) & 0x7) {
1917 case 0x0:
1918 switch (tag & 0x7) {
1919 case 0x3:
1920 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
1921 instrs[1] = main_instr;
1922 num_instrs = 2;
1923 done = stop;
1924 break;
1925 case 0x4:
1926 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1927 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1928 consts[0] = const0;
1929 num_instrs = 3;
1930 num_consts = 1;
1931 done = stop;
1932 break;
1933 case 0x1:
1934 case 0x5:
1935 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1936 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1937 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1938 instrs[3] = main_instr;
1939 if ((tag & 0x7) == 0x5) {
1940 num_instrs = 4;
1941 done = stop;
1942 }
1943 break;
1944 case 0x6:
1945 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1946 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1947 consts[0] = const0;
1948 num_instrs = 6;
1949 num_consts = 1;
1950 done = stop;
1951 break;
1952 case 0x7:
1953 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1954 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1955 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1956 instrs[6] = main_instr;
1957 num_instrs = 7;
1958 done = stop;
1959 break;
1960 default:
1961 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
1962 }
1963 break;
1964 case 0x2:
1965 case 0x3: {
1966 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
1967 main_instr.add_bits |= (tag & 0x7) << 17;
1968 instrs[idx] = main_instr;
1969 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
1970 num_consts = 1;
1971 num_instrs = idx + 1;
1972 done = stop;
1973 break;
1974 }
1975 case 0x4: {
1976 unsigned idx = stop ? 4 : 1;
1977 main_instr.add_bits |= (tag & 0x7) << 17;
1978 instrs[idx] = main_instr;
1979 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
1980 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
1981 break;
1982 }
1983 case 0x1:
1984 // only constants can come after this
1985 num_instrs = 1;
1986 done = stop;
1987 case 0x5:
1988 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
1989 main_instr.add_bits |= (tag & 0x7) << 17;
1990 instrs[0] = main_instr;
1991 break;
1992 case 0x6:
1993 case 0x7: {
1994 unsigned pos = tag & 0xf;
1995 // note that `pos' encodes both the total number of
1996 // instructions and the position in the constant stream,
1997 // presumably because decoded constants and instructions
1998 // share a buffer in the decoder, but we only care about
1999 // the position in the constant stream; the total number of
2000 // instructions is redundant.
2001 unsigned const_idx = 0;
2002 switch (pos) {
2003 case 0:
2004 case 1:
2005 case 2:
2006 case 6:
2007 const_idx = 0;
2008 break;
2009 case 3:
2010 case 4:
2011 case 7:
2012 case 9:
2013 const_idx = 1;
2014 break;
2015 case 5:
2016 case 0xa:
2017 const_idx = 2;
2018 break;
2019 case 8:
2020 case 0xb:
2021 case 0xc:
2022 const_idx = 3;
2023 break;
2024 case 0xd:
2025 const_idx = 4;
2026 break;
2027 case 0xe:
2028 const_idx = 5;
2029 break;
2030 default:
2031 fprintf(fp, "# unknown pos 0x%x\n", pos);
2032 break;
2033 }
2034
2035 if (num_consts < const_idx + 2)
2036 num_consts = const_idx + 2;
2037
2038 consts[const_idx] = const0;
2039 consts[const_idx + 1] = const1;
2040 done = stop;
2041 break;
2042 }
2043 default:
2044 break;
2045 }
2046
2047 if (done)
2048 break;
2049 }
2050 }
2051
2052 *size = i + 1;
2053
2054 if (verbose) {
2055 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
2056 }
2057
2058 struct bifrost_header header;
2059 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2060 dump_header(fp, header, verbose);
2061 if (!header.no_end_of_shader)
2062 stopbit = true;
2063
2064 fprintf(fp, "{\n");
2065 for (i = 0; i < num_instrs; i++) {
2066 struct bifrost_regs next_regs;
2067 if (i + 1 == num_instrs) {
2068 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2069 sizeof(next_regs));
2070 } else {
2071 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2072 sizeof(next_regs));
2073 }
2074
2075 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2076 }
2077 fprintf(fp, "}\n");
2078
2079 if (verbose) {
2080 for (unsigned i = 0; i < num_consts; i++) {
2081 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2082 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2083 }
2084 }
2085 return stopbit;
2086 }
2087
2088 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2089 {
2090 uint32_t *words = (uint32_t *) code;
2091 uint32_t *words_end = words + (size / 4);
2092 // used for displaying branch targets
2093 unsigned offset = 0;
2094 while (words != words_end) {
2095 // we don't know what the program-end bit is quite yet, so for now just
2096 // assume that an all-0 quadword is padding
2097 uint32_t zero[4] = {};
2098 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2099 break;
2100 fprintf(fp, "clause_%d:\n", offset);
2101 unsigned size;
2102 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2103 break;
2104 }
2105 words += size * 4;
2106 offset += size;
2107 }
2108 }
2109