2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
39 typedef uint64_t mali_ptr
;
41 /* Applies to tiler_gl_enables */
43 #define MALI_OCCLUSION_QUERY (1 << 3)
44 #define MALI_OCCLUSION_PRECISE (1 << 4)
46 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
47 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
48 * disagree about how to do viewport flipping, so the blob actually sets this
49 * for GL_CW but then has a negative viewport stride */
51 #define MALI_FRONT_CCW_TOP (1 << 5)
53 #define MALI_CULL_FACE_FRONT (1 << 6)
54 #define MALI_CULL_FACE_BACK (1 << 7)
56 /* Flags apply to unknown2_3? */
58 #define MALI_HAS_MSAA (1 << 0)
60 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
62 #define MALI_PER_SAMPLE (1 << 2)
63 #define MALI_CAN_DISCARD (1 << 5)
65 /* Applies on SFBD systems, specifying that programmable blending is in use */
66 #define MALI_HAS_BLEND_SHADER (1 << 6)
68 /* func is mali_func */
69 #define MALI_DEPTH_FUNC(func) (func << 8)
70 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
71 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
73 #define MALI_DEPTH_WRITEMASK (1 << 11)
75 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
76 #define MALI_DEPTH_CLIP_FAR (1 << 13)
78 /* Next flags to unknown2_4 */
79 #define MALI_STENCIL_TEST (1 << 0)
81 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
83 #define MALI_NO_DITHER (1 << 9)
84 #define MALI_DEPTH_RANGE_A (1 << 12)
85 #define MALI_DEPTH_RANGE_B (1 << 13)
86 #define MALI_NO_MSAA (1 << 14)
88 #define MALI_MASK_R (1 << 0)
89 #define MALI_MASK_G (1 << 1)
90 #define MALI_MASK_B (1 << 2)
91 #define MALI_MASK_A (1 << 3)
93 enum mali_nondominant_mode
{
94 MALI_BLEND_NON_MIRROR
= 0,
95 MALI_BLEND_NON_ZERO
= 1
98 enum mali_dominant_blend
{
99 MALI_BLEND_DOM_SOURCE
= 0,
100 MALI_BLEND_DOM_DESTINATION
= 1
103 enum mali_dominant_factor
{
104 MALI_DOMINANT_UNK0
= 0,
105 MALI_DOMINANT_ZERO
= 1,
106 MALI_DOMINANT_SRC_COLOR
= 2,
107 MALI_DOMINANT_DST_COLOR
= 3,
108 MALI_DOMINANT_UNK4
= 4,
109 MALI_DOMINANT_SRC_ALPHA
= 5,
110 MALI_DOMINANT_DST_ALPHA
= 6,
111 MALI_DOMINANT_CONSTANT
= 7,
114 enum mali_blend_modifier
{
115 MALI_BLEND_MOD_UNK0
= 0,
116 MALI_BLEND_MOD_NORMAL
= 1,
117 MALI_BLEND_MOD_SOURCE_ONE
= 2,
118 MALI_BLEND_MOD_DEST_ONE
= 3,
121 struct mali_blend_mode
{
122 enum mali_blend_modifier clip_modifier
: 2;
123 unsigned unused_0
: 1;
124 unsigned negate_source
: 1;
126 enum mali_dominant_blend dominant
: 1;
128 enum mali_nondominant_mode nondominant_mode
: 1;
130 unsigned unused_1
: 1;
132 unsigned negate_dest
: 1;
134 enum mali_dominant_factor dominant_factor
: 3;
135 unsigned complement_dominant
: 1;
136 } __attribute__((packed
));
138 struct mali_blend_equation
{
139 /* Of type mali_blend_mode */
140 unsigned rgb_mode
: 12;
141 unsigned alpha_mode
: 12;
145 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
147 unsigned color_mask
: 4;
148 } __attribute__((packed
));
150 /* Used with channel swizzling */
152 MALI_CHANNEL_RED
= 0,
153 MALI_CHANNEL_GREEN
= 1,
154 MALI_CHANNEL_BLUE
= 2,
155 MALI_CHANNEL_ALPHA
= 3,
156 MALI_CHANNEL_ZERO
= 4,
157 MALI_CHANNEL_ONE
= 5,
158 MALI_CHANNEL_RESERVED_0
= 6,
159 MALI_CHANNEL_RESERVED_1
= 7,
162 /* Compressed per-pixel formats. Each of these formats expands to one to four
163 * floating-point or integer numbers, as defined by the OpenGL specification.
164 * There are various places in OpenGL where the user can specify a compressed
165 * format in memory, which all use the same 8-bit enum in the various
166 * descriptors, although different hardware units support different formats.
169 /* The top 3 bits specify how the bits of each component are interpreted. */
172 #define MALI_FORMAT_COMPRESSED (0 << 5)
174 /* e.g. R11F_G11F_B10F */
175 #define MALI_FORMAT_SPECIAL (2 << 5)
177 /* signed normalized, e.g. RGBA8_SNORM */
178 #define MALI_FORMAT_SNORM (3 << 5)
181 #define MALI_FORMAT_UINT (4 << 5)
183 /* e.g. RGBA8 and RGBA32F */
184 #define MALI_FORMAT_UNORM (5 << 5)
186 /* e.g. RGBA8I and RGBA16F */
187 #define MALI_FORMAT_SINT (6 << 5)
189 /* These formats seem to largely duplicate the others. They're used at least
190 * for Bifrost framebuffer output.
192 #define MALI_FORMAT_SPECIAL2 (7 << 5)
193 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
195 /* If the high 3 bits are 3 to 6 these two bits say how many components
198 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
199 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
201 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
202 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
206 #define MALI_CHANNEL_4 2
208 #define MALI_CHANNEL_8 3
210 #define MALI_CHANNEL_16 4
212 #define MALI_CHANNEL_32 5
214 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
215 * MALI_FORMAT_UNORM, it means a 32-bit float.
217 #define MALI_CHANNEL_FLOAT 7
218 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
221 /* Not all formats are in fact available, need to query dynamically to
222 * check. Factory settings for Juno enables only ETC2 and ASTC, no
227 MALI_ETC2_RGB8
= MALI_FORMAT_COMPRESSED
| 0x1,
228 MALI_ETC2_R11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x2,
229 MALI_ETC2_RGBA8
= MALI_FORMAT_COMPRESSED
| 0x3,
230 MALI_ETC2_RG11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x4,
232 MALI_NXR
= MALI_FORMAT_COMPRESSED
| 0x6, /* Nokia eXtended Range */
233 MALI_BC1_UNORM
= MALI_FORMAT_COMPRESSED
| 0x7, /* DXT1 */
234 MALI_BC2_UNORM
= MALI_FORMAT_COMPRESSED
| 0x8, /* DXT3 */
235 MALI_BC3_UNORM
= MALI_FORMAT_COMPRESSED
| 0x9, /* DXT5 */
236 MALI_BC4_UNORM
= MALI_FORMAT_COMPRESSED
| 0xA, /* RGTC1_UNORM */
237 MALI_BC4_SNORM
= MALI_FORMAT_COMPRESSED
| 0xB, /* RGTC1_SNORM */
238 MALI_BC5_UNORM
= MALI_FORMAT_COMPRESSED
| 0xC, /* RGTC2_UNORM */
239 MALI_BC5_SNORM
= MALI_FORMAT_COMPRESSED
| 0xD, /* RGTC2_SNORM */
240 MALI_BC6H_UF16
= MALI_FORMAT_COMPRESSED
| 0xE,
241 MALI_BC6H_SF16
= MALI_FORMAT_COMPRESSED
| 0xF,
242 MALI_BC7_UNORM
= MALI_FORMAT_COMPRESSED
| 0x10,
243 MALI_ETC2_R11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x11, /* EAC_SNORM */
244 MALI_ETC2_RG11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x12, /* EAC_SNORM */
245 MALI_ETC2_RGB8A1
= MALI_FORMAT_COMPRESSED
| 0x13,
246 MALI_ASTC_3D_LDR
= MALI_FORMAT_COMPRESSED
| 0x14,
247 MALI_ASTC_3D_HDR
= MALI_FORMAT_COMPRESSED
| 0x15,
248 MALI_ASTC_2D_LDR
= MALI_FORMAT_COMPRESSED
| 0x16,
249 MALI_ASTC_2D_HDR
= MALI_FORMAT_COMPRESSED
| 0x17,
251 MALI_RGB565
= MALI_FORMAT_SPECIAL
| 0x0,
252 MALI_RGB5_X1_UNORM
= MALI_FORMAT_SPECIAL
| 0x1,
253 MALI_RGB5_A1_UNORM
= MALI_FORMAT_SPECIAL
| 0x2,
254 MALI_RGB10_A2_UNORM
= MALI_FORMAT_SPECIAL
| 0x3,
255 MALI_RGB10_A2_SNORM
= MALI_FORMAT_SPECIAL
| 0x5,
256 MALI_RGB10_A2UI
= MALI_FORMAT_SPECIAL
| 0x7,
257 MALI_RGB10_A2I
= MALI_FORMAT_SPECIAL
| 0x9,
259 MALI_RGB332_UNORM
= MALI_FORMAT_SPECIAL
| 0xb,
260 MALI_RGB233_UNORM
= MALI_FORMAT_SPECIAL
| 0xc,
262 MALI_Z24X8_UNORM
= MALI_FORMAT_SPECIAL
| 0xd,
263 MALI_R32_FIXED
= MALI_FORMAT_SPECIAL
| 0x11,
264 MALI_RG32_FIXED
= MALI_FORMAT_SPECIAL
| 0x12,
265 MALI_RGB32_FIXED
= MALI_FORMAT_SPECIAL
| 0x13,
266 MALI_RGBA32_FIXED
= MALI_FORMAT_SPECIAL
| 0x14,
267 MALI_R11F_G11F_B10F
= MALI_FORMAT_SPECIAL
| 0x19,
268 MALI_R9F_G9F_B9F_E5F
= MALI_FORMAT_SPECIAL
| 0x1b,
269 /* Only used for varyings, to indicate the transformed gl_Position */
270 MALI_VARYING_POS
= MALI_FORMAT_SPECIAL
| 0x1e,
271 /* Only used for varyings, to indicate that the write should be
274 MALI_VARYING_DISCARD
= MALI_FORMAT_SPECIAL
| 0x1f,
276 MALI_R8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
277 MALI_R16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
278 MALI_R32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
279 MALI_RG8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
280 MALI_RG16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
281 MALI_RG32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
282 MALI_RGB8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
283 MALI_RGB16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
284 MALI_RGB32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
285 MALI_RGBA8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
286 MALI_RGBA16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
287 MALI_RGBA32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
289 MALI_R8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
290 MALI_R16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
291 MALI_R32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
292 MALI_RG8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
293 MALI_RG16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
294 MALI_RG32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
295 MALI_RGB8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
296 MALI_RGB16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
297 MALI_RGB32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
298 MALI_RGBA8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
299 MALI_RGBA16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
300 MALI_RGBA32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
302 MALI_R8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
303 MALI_R16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
304 MALI_R32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
305 MALI_R32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
306 MALI_RG8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
307 MALI_RG16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
308 MALI_RG32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
309 MALI_RG32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
310 MALI_RGB8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
311 MALI_RGB16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
312 MALI_RGB32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
313 MALI_RGB32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
314 MALI_RGBA4_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_4
,
315 MALI_RGBA8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
316 MALI_RGBA16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
317 MALI_RGBA32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
318 MALI_RGBA32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
320 MALI_R8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
321 MALI_R16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
322 MALI_R32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
323 MALI_R16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
324 MALI_RG8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
325 MALI_RG16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
326 MALI_RG32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
327 MALI_RG16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
328 MALI_RGB8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
329 MALI_RGB16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
330 MALI_RGB32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
331 MALI_RGB16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
332 MALI_RGBA8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
333 MALI_RGBA16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
334 MALI_RGBA32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
335 MALI_RGBA16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
337 MALI_RGBA4
= MALI_FORMAT_SPECIAL2
| 0x8,
338 MALI_RGBA8_2
= MALI_FORMAT_SPECIAL2
| 0xd,
339 MALI_RGB10_A2_2
= MALI_FORMAT_SPECIAL2
| 0xe,
343 /* Applies to midgard1.flags_lo */
345 /* Should be set when the fragment shader updates the depth value. */
346 #define MALI_WRITES_Z (1 << 4)
348 /* Should the hardware perform early-Z testing? Set if the shader does not use
349 * discard, alpha-to-coverage, shader depth writes, and if the shader has no
350 * side effects (writes to global memory or images) unless early-z testing is
351 * forced in the shader.
354 #define MALI_EARLY_Z (1 << 6)
356 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
357 * fragment shader that uses texturing or derivative functions */
359 #define MALI_HELPER_INVOCATIONS (1 << 7)
361 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
362 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
363 * it might read depth/stencil in particular, also set MALI_READS_ZS */
365 #define MALI_READS_ZS (1 << 8)
367 /* The shader might write to global memory (via OpenCL, SSBOs, or images).
368 * Reading is okay, as are ordinary writes to the tilebuffer/varyings. Setting
369 * incurs a performance penalty. On a fragment shader, this bit implies there
370 * are side effects, hence it interacts with early-z. */
371 #define MALI_WRITES_GLOBAL (1 << 9)
373 #define MALI_READS_TILEBUFFER (1 << 10)
375 /* Applies to midgard1.flags_hi */
377 /* Should be set when the fragment shader updates the stencil value. */
378 #define MALI_WRITES_S (1 << 2)
380 /* Mode to suppress generation of Infinity and NaN values by clamping inf
381 * (-inf) to MAX_FLOAT (-MIN_FLOAT) and flushing NaN to 0.0
383 * Compare suppress_inf/suppress_nan flags on the Bifrost clause header for the
384 * same functionality.
386 * This is not conformant on GLES3 or OpenCL, but is optional on GLES2, where
387 * it works around app bugs (e.g. in glmark2-es2 -bterrain with FP16).
389 #define MALI_SUPPRESS_INF_NAN (1 << 3)
391 /* Flags for bifrost1.unk1 */
393 /* Shader uses less than 32 registers, partitioned as [R0, R15] U [R48, R63],
394 * allowing for full thread count. If clear, the full [R0, R63] register set is
395 * available at half thread count */
396 #define MALI_BIFROST_FULL_THREAD (1 << 9)
398 /* Enable early-z testing (presumably). This flag may not be set if the shader:
402 * - Writes gl_FragDepth
404 * This differs from Midgard which sets the MALI_EARLY_Z flag even with
405 * blending, although I've begun to suspect that flag does not in fact enable
407 #define MALI_BIFROST_EARLY_Z (1 << 15)
409 /* First clause type is ATEST */
410 #define MALI_BIFROST_FIRST_ATEST (1 << 26)
412 /* The raw Midgard blend payload can either be an equation or a shader
413 * address, depending on the context */
415 union midgard_blend
{
419 struct mali_blend_equation equation
;
424 /* We need to load the tilebuffer to blend (i.e. the destination factor is not
427 #define MALI_BLEND_LOAD_TIB (0x1)
429 /* A blend shader is used to blend this render target */
430 #define MALI_BLEND_MRT_SHADER (0x2)
432 /* On MRT Midgard systems (using an MFBD), each render target gets its own
433 * blend descriptor */
435 #define MALI_BLEND_SRGB (0x400)
437 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
438 #define MALI_BLEND_NO_DITHER (0x800)
440 struct midgard_blend_rt
{
441 /* Flags base value of 0x200 to enable the render target.
442 * OR with 0x1 for blending (anything other than REPLACE).
443 * OR with 0x2 for programmable blending
444 * OR with MALI_BLEND_SRGB for implicit sRGB
448 union midgard_blend blend
;
449 } __attribute__((packed
));
451 /* On Bifrost systems (all MRT), each render target gets one of these
454 enum bifrost_shader_type
{
455 BIFROST_BLEND_F16
= 0,
456 BIFROST_BLEND_F32
= 1,
457 BIFROST_BLEND_I32
= 2,
458 BIFROST_BLEND_U32
= 3,
459 BIFROST_BLEND_I16
= 4,
460 BIFROST_BLEND_U16
= 5,
463 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
465 struct bifrost_blend_rt
{
466 /* This is likely an analogue of the flags on
467 * midgard_blend_rt */
469 u16 flags
; // = 0x200
471 /* Single-channel blend constants are encoded in a sort of
472 * fixed-point. Basically, the float is mapped to a byte, becoming
473 * a high byte, and then the lower-byte is added for precision.
474 * For the original float f:
476 * f = (constant_hi / 255) + (constant_lo / 65535)
478 * constant_hi = int(f / 255)
479 * constant_lo = 65535*f - (65535/255) * constant_hi
483 struct mali_blend_equation equation
;
487 * - 0x3 when this slot is unused (everything else is 0 except the index)
488 * - 0x11 when this is the fourth slot (and it's used)
489 * - 0 when there is a blend shader
493 /* increments from 0 to 3 */
498 /* So far, I've only seen:
499 * - R001 for 1-component formats
500 * - RG01 for 2-component formats
501 * - RGB1 for 3-component formats
502 * - RGBA for 4-component formats
505 enum mali_format format
: 8;
507 /* Type of the shader output variable. Note, this can
508 * be different from the format.
509 * enum bifrost_shader_type
516 /* Only the low 32 bits of the blend shader are stored, the
517 * high 32 bits are implicitly the same as the original shader.
518 * According to the kernel driver, the program counter for
519 * shaders is actually only 24 bits, so shaders cannot cross
520 * the 2^24-byte boundary, and neither can the blend shader.
521 * The blob handles this by allocating a 2^24 byte pool for
522 * shaders, and making sure that any blend shaders are stored
523 * in the same pool as the original shader. The kernel will
524 * make sure this allocation is aligned to 2^24 bytes.
528 } __attribute__((packed
));
530 /* Descriptor for the shader. Following this is at least one, up to four blend
531 * descriptors for each active render target */
533 struct mali_shader_meta
{
542 u32 uniform_buffer_count
: 4;
543 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
546 unsigned uniform_buffer_count
: 4;
547 unsigned flags_lo
: 12;
550 unsigned work_count
: 5;
551 unsigned uniform_count
: 5;
552 unsigned flags_hi
: 6;
556 /* Same as glPolygoOffset() arguments */
562 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
563 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
564 * specification. Only matters when multisampling is enabled. */
569 u8 stencil_mask_front
;
570 u8 stencil_mask_back
;
573 struct mali_stencil_packed stencil_front
;
574 struct mali_stencil_packed stencil_back
;
579 /* On Bifrost, some system values are preloaded in
580 * registers R55-R62 by the thread dispatcher prior to
581 * the start of shader execution. This is a bitfield
582 * with one entry for each register saying which
583 * registers need to be preloaded. Right now, the known
587 * - R55 : gl_LocalInvocationID.xy
588 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
589 * - R57 : gl_WorkGroupID.x
590 * - R58 : gl_WorkGroupID.y
591 * - R59 : gl_WorkGroupID.z
592 * - R60 : gl_GlobalInvocationID.x
593 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
594 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
597 * - R55 : unknown, never seen (but the bit for this is
599 * - R56 : unknown (bit always unset)
600 * - R57 : gl_PrimitiveID
601 * - R58 : gl_FrontFacing in low bit, potentially other stuff
602 * - R59 : u16 fragment coordinates (used to compute
603 * gl_FragCoord.xy, together with sample positions)
604 * - R60 : gl_SampleMask (used in epilog, so pretty
605 * much always used, but the bit is always 0 -- is
606 * this just always pushed?)
607 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
608 * varying interpolation.
609 * - R62 : unknown (bit always unset).
611 * Later GPUs (starting with Mali-G52?) support
612 * preloading float varyings into r0-r7. This is
613 * indicated by setting 0x40. There is no distinction
614 * here between 1 varying and 2.
616 u32 preload_regs
: 8;
617 /* In units of 8 bytes or 64 bits, since the
618 * uniform/const port loads 64 bits at a time.
620 u32 uniform_count
: 7;
621 u32 unk4
: 10; // = 2
630 /* Blending information for the older non-MRT Midgard HW. Check for
631 * MALI_HAS_BLEND_SHADER to decide how to interpret.
634 union midgard_blend blend
;
635 } __attribute__((packed
));
637 /* This only concerns hardware jobs */
639 /* Possible values for job_descriptor_size */
641 #define MALI_JOB_32 0
642 #define MALI_JOB_64 1
644 struct mali_job_descriptor_header
{
645 u32 exception_status
;
646 u32 first_incomplete_task
;
648 u8 job_descriptor_size
: 1;
649 enum mali_job_type job_type
: 7;
651 u8 unknown_flags
: 7;
653 u16 job_dependency_index_1
;
654 u16 job_dependency_index_2
;
656 } __attribute__((packed
));
658 /* These concern exception_status */
660 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
663 enum mali_exception_access
{
664 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
665 * fault so it's just unused */
666 MALI_EXCEPTION_ACCESS_NONE
= 0,
668 MALI_EXCEPTION_ACCESS_EXECUTE
= 1,
669 MALI_EXCEPTION_ACCESS_READ
= 2,
670 MALI_EXCEPTION_ACCESS_WRITE
= 3
673 /* Details about write_value from panfrost igt tests which use it as a generic
674 * dword write primitive */
676 #define MALI_WRITE_VALUE_ZERO 3
678 struct mali_payload_write_value
{
680 u32 value_descriptor
;
683 } __attribute__((packed
));
688 * This structure lets the attribute unit compute the address of an attribute
689 * given the vertex and instance ID. Unfortunately, the way this works is
690 * rather complicated when instancing is enabled.
692 * To explain this, first we need to explain how compute and vertex threads are
693 * dispatched. This is a guess (although a pretty firm guess!) since the
694 * details are mostly hidden from the driver, except for attribute instancing.
695 * When a quad is dispatched, it receives a single, linear index. However, we
696 * need to translate that index into a (vertex id, instance id) pair, or a
697 * (local id x, local id y, local id z) triple for compute shaders (although
698 * vertex shaders and compute shaders are handled almost identically).
699 * Focusing on vertex shaders, one option would be to do:
701 * vertex_id = linear_id % num_vertices
702 * instance_id = linear_id / num_vertices
704 * but this involves a costly division and modulus by an arbitrary number.
705 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
706 * num_instances threads instead of num_vertices * num_instances, which results
707 * in some "extra" threads with vertex_id >= num_vertices, which we have to
708 * discard. The more we pad num_vertices, the more "wasted" threads we
709 * dispatch, but the division is potentially easier.
711 * One straightforward choice is to pad num_vertices to the next power of two,
712 * which means that the division and modulus are just simple bit shifts and
713 * masking. But the actual algorithm is a bit more complicated. The thread
714 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
715 * to dividing by a power of two. This is possibly using the technique
716 * described in patent US20170010862A1. As a result, padded_num_vertices can be
717 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
718 * since we need less padding.
720 * padded_num_vertices is picked by the hardware. The driver just specifies the
721 * actual number of vertices. At least for Mali G71, the first few cases are
724 * num_vertices | padded_num_vertices
731 * Note that padded_num_vertices is a multiple of four (presumably because
732 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
733 * at least one more than num_vertices, which seems like a quirk of the
734 * hardware. For larger num_vertices, the hardware uses the following
735 * algorithm: using the binary representation of num_vertices, we look at the
736 * most significant set bit as well as the following 3 bits. Let n be the
737 * number of bits after those 4 bits. Then we set padded_num_vertices according
738 * to the following table:
740 * high bits | padded_num_vertices
747 * For example, if num_vertices = 70 is passed to glDraw(), its binary
748 * representation is 1000110, so n = 3 and the high bits are 1000, and
749 * therefore padded_num_vertices = 9 * 2^3 = 72.
751 * The attribute unit works in terms of the original linear_id. if
752 * num_instances = 1, then they are the same, and everything is simple.
753 * However, with instancing things get more complicated. There are four
754 * possible modes, two of them we can group together:
756 * 1. Use the linear_id directly. Only used when there is no instancing.
758 * 2. Use the linear_id modulo a constant. This is used for per-vertex
759 * attributes with instancing enabled by making the constant equal
760 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
761 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
762 * The shift field specifies the power of two, while the extra_flags field
763 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
764 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
765 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
766 * shift = 3. Note that we must exactly follow the hardware algorithm used to
767 * get padded_num_vertices in order to correctly implement per-vertex
770 * 3. Divide the linear_id by a constant. In order to correctly implement
771 * instance divisors, we have to divide linear_id by padded_num_vertices times
772 * to user-specified divisor. So first we compute padded_num_vertices, again
773 * following the exact same algorithm that the hardware uses, then multiply it
774 * by the GL-level divisor to get the hardware-level divisor. This case is
775 * further divided into two more cases. If the hardware-level divisor is a
776 * power of two, then we just need to shift. The shift amount is specified by
777 * the shift field, so that the hardware-level divisor is just 2^shift.
779 * If it isn't a power of two, then we have to divide by an arbitrary integer.
780 * For that, we use the well-known technique of multiplying by an approximation
781 * of the inverse. The driver must compute the magic multiplier and shift
782 * amount, and then the hardware does the multiplication and shift. The
783 * hardware and driver also use the "round-down" optimization as described in
784 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
785 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
786 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
787 * presumably this simplifies the hardware multiplier a little. The hardware
788 * first multiplies linear_id by the multiplier and takes the high 32 bits,
789 * then applies the round-down correction if extra_flags = 1, then finally
790 * shifts right by the shift field.
792 * There are some differences between ridiculousfish's algorithm and the Mali
793 * hardware algorithm, which means that the reference code from ridiculousfish
794 * doesn't always produce the right constants. Mali does not use the pre-shift
795 * optimization, since that would make a hardware implementation slower (it
796 * would have to always do the pre-shift, multiply, and post-shift operations).
797 * It also forces the multplier to be at least 2^31, which means that the
798 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
799 * given the divisor d, the algorithm the driver must follow is:
801 * 1. Set shift = floor(log2(d)).
802 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
803 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
804 * magic_divisor = m - 1 and extra_flags = 1.
805 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
807 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
808 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
809 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
810 * (*NOT the row stride*). Size is set to the size of the image itself.
812 * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc)
813 * use particular fixed addresses with modified structures.
816 enum mali_attr_mode
{
817 MALI_ATTR_UNUSED
= 0,
818 MALI_ATTR_LINEAR
= 1,
819 MALI_ATTR_POT_DIVIDE
= 2,
820 MALI_ATTR_MODULO
= 3,
821 MALI_ATTR_NPOT_DIVIDE
= 4,
825 /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */
827 #define MALI_ATTR_VERTEXID (0x22)
828 #define MALI_ATTR_INSTANCEID (0x24)
829 #define MALI_VARYING_FRAG_COORD (0x25)
830 #define MALI_VARYING_FRONT_FACING (0x26)
832 /* This magic "pseudo-address" is used as `elements` to implement
833 * gl_PointCoord. When read from a fragment shader, it generates a point
834 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
835 * require an affine transformation in the shader. */
837 #define MALI_VARYING_POINT_COORD (0x61)
839 /* Used for comparison to check if an address is special. Mostly a guess, but
840 * it doesn't really matter. */
842 #define MALI_RECORD_SPECIAL (0x100)
845 /* This is used for actual attributes. */
847 /* The bottom 3 bits are the mode */
848 mali_ptr elements
: 64 - 8;
854 /* The entry after an NPOT_DIVIDE entry has this format. It stores
855 * extra information that wouldn't fit in a normal entry.
858 u32 unk
; /* = 0x20 */
861 /* This is the original, GL-level divisor. */
864 } __attribute__((packed
));
866 struct mali_attr_meta
{
867 /* Vertex buffer index */
870 unsigned unknown1
: 2;
871 unsigned swizzle
: 12;
872 enum mali_format format
: 8;
874 /* Always observed to be zero at the moment */
875 unsigned unknown3
: 2;
877 /* When packing multiple attributes in a buffer, offset addresses by
878 * this value. Obscurely, this is signed. */
880 } __attribute__((packed
));
882 #define FBD_MASK (~0x3f)
884 /* MFBD, rather than SFBD */
885 #define MALI_MFBD (0x1)
887 /* ORed into an MFBD address to specify the fbx section is included */
888 #define MALI_MFBD_TAG_EXTRA (0x2)
890 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
891 * They also seem to be the same between Bifrost and Midgard. They're shared in
895 /* Applies to unknown_draw */
897 #define MALI_DRAW_INDEXED_UINT8 (0x10)
898 #define MALI_DRAW_INDEXED_UINT16 (0x20)
899 #define MALI_DRAW_INDEXED_UINT32 (0x30)
900 #define MALI_DRAW_INDEXED_SIZE (0x30)
901 #define MALI_DRAW_INDEXED_SHIFT (4)
903 #define MALI_DRAW_VARYING_SIZE (0x100)
905 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
906 * use the last vertex. This is the default in DX and VK, but not in GL. */
908 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
910 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
912 struct mali_vertex_tiler_prefix
{
913 /* This is a dynamic bitfield containing the following things in this order:
915 * - gl_WorkGroupSize.x
916 * - gl_WorkGroupSize.y
917 * - gl_WorkGroupSize.z
918 * - gl_NumWorkGroups.x
919 * - gl_NumWorkGroups.y
920 * - gl_NumWorkGroups.z
922 * The number of bits allocated for each number is based on the *_shift
923 * fields below. For example, workgroups_y_shift gives the bit that
924 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
925 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
926 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
927 * value is one more than the stored value, since if any of the values
928 * are zero, then there would be no invocations (and hence no job). If
929 * there were 0 bits allocated to a given field, then it must be zero,
930 * and hence the real value is one.
932 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
933 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
934 * where vertex count is the number of vertices.
936 u32 invocation_count
;
938 /* Bitfield for shifts:
942 * workgroups_x_shift : 6
943 * workgroups_y_shift : 6
944 * workgroups_z_shift : 6
945 * workgroups_x_shift_2 : 4
947 u32 invocation_shifts
;
950 u32 unknown_draw
: 22;
952 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
953 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
954 * something to do with how many quads get put in the same execution
955 * engine, which is a balance (you don't want to starve the engine, but
956 * you also want to distribute work evenly).
958 u32 workgroups_x_shift_3
: 6;
961 /* Negative of min_index. This is used to compute
962 * the unbiased index in tiler/fragment shader runs.
964 * The hardware adds offset_bias_correction in each run,
965 * so that absent an index bias, the first vertex processed is
966 * genuinely the first vertex (0). But with an index bias,
967 * the first vertex process is numbered the same as the bias.
969 * To represent this more conviniently:
970 * unbiased_index = lower_bound_index +
972 * offset_bias_correction
974 * This is done since the hardware doesn't accept a index_bias
975 * and this allows it to recover the unbiased index.
977 int32_t offset_bias_correction
;
980 /* Like many other strictly nonzero quantities, index_count is
981 * subtracted by one. For an indexed cube, this is equal to 35 = 6
982 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
983 * for an indexed draw, index_count is the number of actual vertices
984 * rendered whereas invocation_count is the number of unique vertices
985 * rendered (the number of times the vertex shader must be invoked).
986 * For non-indexed draws, this is just equal to invocation_count. */
990 /* No hidden structure; literally just a pointer to an array of uint
991 * indices (width depends on flags). Thanks, guys, for not making my
992 * life insane for once! NULL for non-indexed draws. */
995 } __attribute__((packed
));
997 /* Point size / line width can either be specified as a 32-bit float (for
998 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
999 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
1000 * payload, the contents of varying_pointer will be intepreted as an array of
1001 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
1002 * creating a special MALI_R16F varying writing to varying_pointer. */
1004 union midgard_primitive_size
{
1009 struct bifrost_tiler_heap_meta
{
1012 /* note: these are just guesses! */
1013 mali_ptr tiler_heap_start
;
1014 mali_ptr tiler_heap_free
;
1015 mali_ptr tiler_heap_end
;
1017 /* hierarchy weights? but they're still 0 after the job has run... */
1021 } __attribute__((packed
));
1023 struct bifrost_tiler_meta
{
1024 u32 tiler_heap_next_start
; /* To be written by the GPU */
1025 u32 used_hierarchy_mask
; /* To be written by the GPU */
1026 u16 hierarchy_mask
; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
1031 mali_ptr tiler_heap_meta
;
1032 /* TODO what is this used for? */
1034 } __attribute__((packed
));
1036 struct bifrost_tiler_only
{
1038 union midgard_primitive_size primitive_size
;
1040 mali_ptr tiler_meta
;
1042 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
1043 } __attribute__((packed
));
1045 struct mali_vertex_tiler_postfix
{
1046 u16 gl_enables
; // 0x6 on Midgard, 0x2 on Bifrost
1048 /* Both zero for non-instanced draws. For instanced draws, a
1049 * decomposition of padded_num_vertices. See the comments about the
1050 * corresponding fields in mali_attr for context. */
1052 unsigned instance_shift
: 5;
1053 unsigned instance_odd
: 3;
1057 /* Offset for first vertex in buffer */
1062 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1063 * output from the vertex shader for tiler jobs.
1066 u64 position_varying
;
1068 /* An array of mali_uniform_buffer_meta's. The size is given by the
1071 u64 uniform_buffers
;
1073 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
1074 * On Midgard, this is a pointer to an array of pointers to the texture
1075 * descriptors, number of pointers bounded by number of textures. The
1076 * indirection is needed to accomodate varying numbers and sizes of
1077 * texture descriptors */
1080 /* For OpenGL, from what I've seen, this is intimately connected to
1081 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1082 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1083 * array of sampler descriptors (which are uniform in size) */
1084 u64 sampler_descriptor
;
1088 u64 attributes
; /* struct attribute_buffer[] */
1089 u64 attribute_meta
; /* attribute_meta[] */
1090 u64 varyings
; /* struct attr */
1091 u64 varying_meta
; /* pointer */
1093 u64 occlusion_counter
; /* A single bit as far as I can tell */
1095 /* On Bifrost, this points directly to a mali_shared_memory structure.
1096 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
1097 * tagged), which embeds a mali_shared_memory structure */
1098 mali_ptr shared_memory
;
1099 } __attribute__((packed
));
1101 struct midgard_payload_vertex_tiler
{
1102 struct mali_vertex_tiler_prefix prefix
;
1103 struct mali_vertex_tiler_postfix postfix
;
1105 union midgard_primitive_size primitive_size
;
1106 } __attribute__((packed
));
1108 struct bifrost_payload_vertex
{
1109 struct mali_vertex_tiler_prefix prefix
;
1110 struct mali_vertex_tiler_postfix postfix
;
1111 } __attribute__((packed
));
1113 struct bifrost_payload_tiler
{
1114 struct mali_vertex_tiler_prefix prefix
;
1115 struct bifrost_tiler_only tiler
;
1116 struct mali_vertex_tiler_postfix postfix
;
1117 } __attribute__((packed
));
1119 struct bifrost_payload_fused
{
1120 struct mali_vertex_tiler_prefix prefix
;
1121 struct bifrost_tiler_only tiler
;
1122 struct mali_vertex_tiler_postfix tiler_postfix
;
1123 u64 padding
; /* zero */
1124 struct mali_vertex_tiler_postfix vertex_postfix
;
1125 } __attribute__((packed
));
1127 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1128 * texture is stored as (63, 63) in these fields. This adjusts for that.
1129 * There's an identical pattern in the framebuffer descriptor. Even vertex
1130 * count fields work this way, hence the generic name -- integral fields that
1131 * are strictly positive generally need this adjustment. */
1133 #define MALI_POSITIVE(dim) (dim - 1)
1136 #define MAX_MIP_LEVELS (13)
1138 /* Cubemap bloats everything up */
1139 #define MAX_CUBE_FACES (6)
1141 /* For each pointer, there is an address and optionally also a stride */
1142 #define MAX_ELEMENTS (2)
1144 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1145 * be cleaned up a lot. */
1147 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1149 static inline int16_t
1150 FIXED_16(float x
, bool allow_negative
)
1152 /* Clamp inputs, accounting for float error */
1153 float max_lod
= (32.0 - (1.0 / 512.0));
1154 float min_lod
= allow_negative
? -max_lod
: 0.0;
1156 x
= ((x
> max_lod
) ? max_lod
: ((x
< min_lod
) ? min_lod
: x
));
1158 return (int) (x
* 256.0);
1161 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1162 * of tile numbers. */
1164 #define MALI_TILE_SHIFT 4
1165 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1167 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1168 * each component. Notice that this provides a theoretical upper bound of (1 <<
1169 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1170 * 65536x65536. Multiplying that together, times another four given that Mali
1171 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1172 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1173 * alone rendering in real-time to such a buffer.
1177 /* From mali_kbase_10969_workaround.c */
1178 #define MALI_X_COORD_MASK 0x00000FFF
1179 #define MALI_Y_COORD_MASK 0x0FFF0000
1181 /* Extract parts of a tile coordinate */
1183 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1184 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1186 /* Helpers to generate tile coordinates based on the boundary coordinates in
1187 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1188 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1189 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1192 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1193 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1194 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1195 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1196 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1198 struct mali_payload_fragment
{
1201 mali_ptr framebuffer
;
1202 } __attribute__((packed
));
1204 /* Single Framebuffer Descriptor */
1206 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1207 * configured for 4x. With MSAA_8, it is configured for 8x. */
1209 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1210 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1211 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1212 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1214 /* Fast/slow based on whether all three buffers are cleared at once */
1216 #define MALI_CLEAR_FAST (1 << 18)
1217 #define MALI_CLEAR_SLOW (1 << 28)
1218 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1220 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1221 * within the larget framebuffer descriptor). Analogous to
1222 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1224 /* See pan_tiler.c for derivation */
1225 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1227 /* Flag disabling the tiler for clear-only jobs, with
1228 hierarchical tiling */
1229 #define MALI_TILER_DISABLED (1 << 12)
1231 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
1232 * hierarhical tiling. */
1233 #define MALI_TILER_USER 0xFFF
1235 /* Absent any geometry, the minimum size of the polygon list header */
1236 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
1238 struct midgard_tiler_descriptor
{
1239 /* Size of the entire polygon list; see pan_tiler.c for the
1240 * computation. It's based on hierarchical tiling */
1242 u32 polygon_list_size
;
1244 /* Name known from the replay workaround in the kernel. What exactly is
1245 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1246 * specifies a mask of hierarchy weights, which explains some of the
1247 * performance mysteries around setting it. We also see the bottom bit
1248 * of tiler_flags set in the kernel, but no comment why.
1250 * hierarchy_mask can have the TILER_DISABLED flag */
1255 /* See mali_tiler.c for an explanation */
1256 mali_ptr polygon_list
;
1257 mali_ptr polygon_list_body
;
1259 /* Names based on we see symmetry with replay jobs which name these
1262 mali_ptr heap_start
; /* tiler heap_free_address */
1265 /* Hierarchy weights. We know these are weights based on the kernel,
1266 * but I've never seen them be anything other than zero */
1270 struct mali_sfbd_format
{
1274 /* mali_channel_swizzle */
1275 unsigned swizzle
: 12;
1278 unsigned nr_channels
: 2;
1283 enum mali_block_format block
: 2;
1289 /* Shared structure at the start of framebuffer descriptors, or used bare for
1290 * compute jobs, configuring stack and shared memory */
1292 struct mali_shared_memory
{
1293 u32 stack_shift
: 4;
1296 /* Configuration for shared memory for compute shaders.
1297 * shared_workgroup_count is logarithmic and may be computed for a
1298 * compute shader using shared memory as:
1300 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
1302 * For compute shaders that don't use shared memory, or non-compute
1303 * shaders, this is set to ~0
1306 u32 shared_workgroup_count
: 5;
1307 u32 shared_unk1
: 3;
1308 u32 shared_shift
: 4;
1309 u32 shared_zero
: 20;
1311 mali_ptr scratchpad
;
1313 /* For compute shaders, the RAM backing of workgroup-shared memory. For
1314 * fragment shaders on Bifrost, apparently multisampling locations */
1316 mali_ptr shared_memory
;
1318 } __attribute__((packed
));
1320 /* Configures multisampling on Bifrost fragment jobs */
1322 struct bifrost_multisampling
{
1325 mali_ptr sample_locations
;
1327 } __attribute__((packed
));
1329 struct mali_single_framebuffer
{
1330 struct mali_shared_memory shared_memory
;
1331 struct mali_sfbd_format format
;
1336 /* Purposeful off-by-one in these fields should be accounted for by the
1337 * MALI_DIMENSION macro */
1344 u32 checksum_stride
;
1347 /* By default, the framebuffer is upside down from OpenGL's
1348 * perspective. Set framebuffer to the end and negate the stride to
1349 * flip in the Y direction */
1351 mali_ptr framebuffer
;
1356 /* Depth and stencil buffers are interleaved, it appears, as they are
1357 * set to the same address in captures. Both fields set to zero if the
1358 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1359 * get a zero enable despite the buffer being present; that still is
1362 mali_ptr depth_buffer
; // not SAME_VA
1363 u32 depth_stride_zero
: 4;
1364 u32 depth_stride
: 28;
1367 mali_ptr stencil_buffer
; // not SAME_VA
1368 u32 stencil_stride_zero
: 4;
1369 u32 stencil_stride
: 28;
1372 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1373 u32 clear_color_2
; // always equal, but unclear function?
1374 u32 clear_color_3
; // always equal, but unclear function?
1375 u32 clear_color_4
; // always equal, but unclear function?
1377 /* Set to zero if not cleared */
1379 float clear_depth_1
; // float32, ditto
1380 float clear_depth_2
; // float32, ditto
1381 float clear_depth_3
; // float32, ditto
1382 float clear_depth_4
; // float32, ditto
1384 u32 clear_stencil
; // Exactly as it appears in OpenGL
1388 struct midgard_tiler_descriptor tiler
;
1390 /* More below this, maybe */
1391 } __attribute__((packed
));
1394 /* SINGLE to disable multisampling, AVERAGE for
1395 * EXT_multisampled_render_to_texture operation where multiple tilebuffer
1396 * samples are implicitly resolved before writeout, MULTIPLE to write multiple
1397 * samples inline, and LAYERED for ES3-style multisampling with each sample in
1398 * a different buffer.
1401 enum mali_msaa_mode
{
1402 MALI_MSAA_SINGLE
= 0,
1403 MALI_MSAA_AVERAGE
= 1,
1404 MALI_MSAA_MULTIPLE
= 2,
1405 MALI_MSAA_LAYERED
= 3,
1408 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1410 struct mali_rt_format
{
1414 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1418 enum mali_block_format block
: 2;
1419 enum mali_msaa_mode msaa
: 2;
1422 unsigned swizzle
: 12;
1426 /* Disables MFBD preload. When this bit is set, the render target will
1427 * be cleared every frame. When this bit is clear, the hardware will
1428 * automatically wallpaper the render target back from main memory.
1429 * Unfortunately, MFBD preload is very broken on Midgard, so in
1430 * practice, this is a chicken bit that should always be set.
1431 * Discovered by accident, as all good chicken bits are. */
1433 unsigned no_preload
: 1;
1434 } __attribute__((packed
));
1436 /* Flags for afbc.flags and ds_afbc.flags */
1438 #define MALI_AFBC_FLAGS 0x10009
1440 /* Lossless RGB and RGBA colorspace transform */
1441 #define MALI_AFBC_YTR (1 << 17)
1443 struct mali_render_target
{
1444 struct mali_rt_format format
;
1449 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1450 * there is an extra metadata buffer that contains 16 bytes per tile.
1451 * The framebuffer needs to be the same size as before, since we don't
1452 * know ahead of time how much space it will take up. The
1453 * framebuffer_stride is set to 0, since the data isn't stored linearly
1456 * When AFBC is disabled, these fields are zero.
1460 u32 stride
; // stride in units of tiles
1461 u32 flags
; // = 0x20000
1464 mali_ptr framebuffer
;
1467 u32 framebuffer_stride
: 28; // in units of bytes, row to next
1468 u32 layer_stride
; /* For multisample rendering */
1470 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1471 u32 clear_color_2
; // always equal, but unclear function?
1472 u32 clear_color_3
; // always equal, but unclear function?
1473 u32 clear_color_4
; // always equal, but unclear function?
1474 } __attribute__((packed
));
1476 /* An optional part of mali_framebuffer. It comes between the main structure
1477 * and the array of render targets. It must be included if any of these are
1480 * - Transaction Elimination
1482 * - TODO: Anything else?
1486 #define MALI_EXTRA_PRESENT (0x1)
1489 #define MALI_EXTRA_ZS (0x4)
1491 struct mali_framebuffer_extra
{
1493 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1494 u32 checksum_stride
;
1496 unsigned flags_lo
: 4;
1497 enum mali_block_format zs_block
: 2;
1499 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1500 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1501 unsigned zs_samples
: 4;
1502 unsigned flags_hi
: 22;
1505 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1507 mali_ptr depth_stencil_afbc_metadata
;
1508 u32 depth_stencil_afbc_stride
; // in units of tiles
1511 mali_ptr depth_stencil
;
1517 /* Depth becomes depth/stencil in case of combined D/S */
1519 u32 depth_stride_zero
: 4;
1520 u32 depth_stride
: 28;
1521 u32 depth_layer_stride
;
1524 u32 stencil_stride_zero
: 4;
1525 u32 stencil_stride
: 28;
1526 u32 stencil_layer_stride
;
1534 } __attribute__((packed
));
1536 /* Flags for mfbd_flags */
1538 /* Enables writing depth results back to main memory (rather than keeping them
1539 * on-chip in the tile buffer and then discarding) */
1541 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1543 /* The MFBD contains the extra mali_framebuffer_extra section */
1545 #define MALI_MFBD_EXTRA (1 << 13)
1547 struct mali_framebuffer
{
1549 struct mali_shared_memory shared_memory
;
1550 struct bifrost_multisampling msaa
;
1554 u16 width1
, height1
;
1556 u16 width2
, height2
;
1557 u32 unk1
: 19; // = 0x01000
1558 u32 rt_count_1
: 3; // off-by-one (use MALI_POSITIVE)
1559 u32 unk2
: 2; // = 0
1560 u32 rt_count_2
: 3; // no off-by-one
1563 u32 clear_stencil
: 8;
1564 u32 mfbd_flags
: 24; // = 0x100
1568 struct midgard_tiler_descriptor tiler
;
1570 mali_ptr tiler_meta
;
1575 /* optional: struct mali_framebuffer_extra extra */
1576 /* struct mali_render_target rts[] */
1577 } __attribute__((packed
));
1579 #endif /* __PANFROST_JOB_H__ */