panfrost: Drop mali_shader_meta
[mesa.git] / src / panfrost / include / panfrost-job.h
1 /*
2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * SOFTWARE.
25 *
26 */
27
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
30
31 #include <stdint.h>
32 #include <stdbool.h>
33 #include <inttypes.h>
34
35 typedef uint8_t u8;
36 typedef uint16_t u16;
37 typedef uint32_t u32;
38 typedef uint64_t u64;
39 typedef uint64_t mali_ptr;
40
41 /* Applies to tiler_gl_enables */
42
43 #define MALI_OCCLUSION_QUERY (1 << 3)
44 #define MALI_OCCLUSION_PRECISE (1 << 4)
45
46 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
47 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
48 * disagree about how to do viewport flipping, so the blob actually sets this
49 * for GL_CW but then has a negative viewport stride */
50
51 #define MALI_FRONT_CCW_TOP (1 << 5)
52
53 #define MALI_CULL_FACE_FRONT (1 << 6)
54 #define MALI_CULL_FACE_BACK (1 << 7)
55
56 enum mali_nondominant_mode {
57 MALI_BLEND_NON_MIRROR = 0,
58 MALI_BLEND_NON_ZERO = 1
59 };
60
61 enum mali_dominant_blend {
62 MALI_BLEND_DOM_SOURCE = 0,
63 MALI_BLEND_DOM_DESTINATION = 1
64 };
65
66 enum mali_dominant_factor {
67 MALI_DOMINANT_UNK0 = 0,
68 MALI_DOMINANT_ZERO = 1,
69 MALI_DOMINANT_SRC_COLOR = 2,
70 MALI_DOMINANT_DST_COLOR = 3,
71 MALI_DOMINANT_UNK4 = 4,
72 MALI_DOMINANT_SRC_ALPHA = 5,
73 MALI_DOMINANT_DST_ALPHA = 6,
74 MALI_DOMINANT_CONSTANT = 7,
75 };
76
77 enum mali_blend_modifier {
78 MALI_BLEND_MOD_UNK0 = 0,
79 MALI_BLEND_MOD_NORMAL = 1,
80 MALI_BLEND_MOD_SOURCE_ONE = 2,
81 MALI_BLEND_MOD_DEST_ONE = 3,
82 };
83
84 struct mali_blend_mode {
85 enum mali_blend_modifier clip_modifier : 2;
86 unsigned unused_0 : 1;
87 unsigned negate_source : 1;
88
89 enum mali_dominant_blend dominant : 1;
90
91 enum mali_nondominant_mode nondominant_mode : 1;
92
93 unsigned unused_1 : 1;
94
95 unsigned negate_dest : 1;
96
97 enum mali_dominant_factor dominant_factor : 3;
98 unsigned complement_dominant : 1;
99 } __attribute__((packed));
100
101 /* Compressed per-pixel formats. Each of these formats expands to one to four
102 * floating-point or integer numbers, as defined by the OpenGL specification.
103 * There are various places in OpenGL where the user can specify a compressed
104 * format in memory, which all use the same 8-bit enum in the various
105 * descriptors, although different hardware units support different formats.
106 */
107
108 /* The top 3 bits specify how the bits of each component are interpreted. */
109
110 /* e.g. ETC2_RGB8 */
111 #define MALI_FORMAT_COMPRESSED (0 << 5)
112
113 /* e.g. R11F_G11F_B10F */
114 #define MALI_FORMAT_SPECIAL (2 << 5)
115
116 /* signed normalized, e.g. RGBA8_SNORM */
117 #define MALI_FORMAT_SNORM (3 << 5)
118
119 /* e.g. RGBA8UI */
120 #define MALI_FORMAT_UINT (4 << 5)
121
122 /* e.g. RGBA8 and RGBA32F */
123 #define MALI_FORMAT_UNORM (5 << 5)
124
125 /* e.g. RGBA8I and RGBA16F */
126 #define MALI_FORMAT_SINT (6 << 5)
127
128 /* These formats seem to largely duplicate the others. They're used at least
129 * for Bifrost framebuffer output.
130 */
131 #define MALI_FORMAT_SPECIAL2 (7 << 5)
132 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
133
134 /* If the high 3 bits are 3 to 6 these two bits say how many components
135 * there are.
136 */
137 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
138 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
139
140 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
141 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
142 * bits mean.
143 */
144
145 #define MALI_CHANNEL_4 2
146
147 #define MALI_CHANNEL_8 3
148
149 #define MALI_CHANNEL_16 4
150
151 #define MALI_CHANNEL_32 5
152
153 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
154 * MALI_FORMAT_UNORM, it means a 32-bit float.
155 */
156 #define MALI_CHANNEL_FLOAT 7
157 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
158
159 /* The raw Midgard blend payload can either be an equation or a shader
160 * address, depending on the context */
161
162 union midgard_blend {
163 mali_ptr shader;
164
165 struct {
166 struct mali_blend_equation_packed equation;
167 float constant;
168 };
169 };
170
171 struct midgard_blend_rt {
172 struct mali_blend_flags_packed flags;
173 u32 zero;
174 union midgard_blend blend;
175 } __attribute__((packed));
176
177 /* On Bifrost systems (all MRT), each render target gets one of these
178 * descriptors */
179
180 enum bifrost_shader_type {
181 BIFROST_BLEND_F16 = 0,
182 BIFROST_BLEND_F32 = 1,
183 BIFROST_BLEND_I32 = 2,
184 BIFROST_BLEND_U32 = 3,
185 BIFROST_BLEND_I16 = 4,
186 BIFROST_BLEND_U16 = 5,
187 };
188
189 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
190
191 struct bifrost_blend_rt {
192 /* This is likely an analogue of the flags on
193 * midgard_blend_rt */
194
195 u16 flags; // = 0x200
196
197 /* Single-channel blend constants are encoded in a sort of
198 * fixed-point. Basically, the float is mapped to a byte, becoming
199 * a high byte, and then the lower-byte is added for precision.
200 * For the original float f:
201 *
202 * f = (constant_hi / 255) + (constant_lo / 65535)
203 *
204 * constant_hi = int(f / 255)
205 * constant_lo = 65535*f - (65535/255) * constant_hi
206 */
207 u16 constant;
208
209 struct mali_blend_equation_packed equation;
210
211 /*
212 * - 0x19 normally
213 * - 0x3 when this slot is unused (everything else is 0 except the index)
214 * - 0x11 when this is the fourth slot (and it's used)
215 * - 0 when there is a blend shader
216 */
217 u16 unk2;
218
219 /* increments from 0 to 3 */
220 u16 index;
221
222 union {
223 struct {
224 /* So far, I've only seen:
225 * - R001 for 1-component formats
226 * - RG01 for 2-component formats
227 * - RGB1 for 3-component formats
228 * - RGBA for 4-component formats
229 */
230 u32 swizzle : 12;
231 enum mali_format format : 8;
232
233 /* Type of the shader output variable. Note, this can
234 * be different from the format.
235 * enum bifrost_shader_type
236 */
237 u32 zero1 : 4;
238 u32 shader_type : 3;
239 u32 zero2 : 5;
240 };
241
242 /* Only the low 32 bits of the blend shader are stored, the
243 * high 32 bits are implicitly the same as the original shader.
244 * According to the kernel driver, the program counter for
245 * shaders is actually only 24 bits, so shaders cannot cross
246 * the 2^24-byte boundary, and neither can the blend shader.
247 * The blob handles this by allocating a 2^24 byte pool for
248 * shaders, and making sure that any blend shaders are stored
249 * in the same pool as the original shader. The kernel will
250 * make sure this allocation is aligned to 2^24 bytes.
251 */
252 u32 shader;
253 };
254 } __attribute__((packed));
255
256 /* Possible values for job_descriptor_size */
257
258 #define MALI_JOB_32 0
259 #define MALI_JOB_64 1
260
261 struct mali_job_descriptor_header {
262 u32 exception_status;
263 u32 first_incomplete_task;
264 u64 fault_pointer;
265 u8 job_descriptor_size : 1;
266 enum mali_job_type job_type : 7;
267 u8 job_barrier : 1;
268 u8 unknown_flags : 7;
269 u16 job_index;
270 u16 job_dependency_index_1;
271 u16 job_dependency_index_2;
272 u64 next_job;
273 } __attribute__((packed));
274
275 /* Details about write_value from panfrost igt tests which use it as a generic
276 * dword write primitive */
277
278 #define MALI_WRITE_VALUE_ZERO 3
279
280 struct mali_payload_write_value {
281 u64 address;
282 u32 value_descriptor;
283 u32 reserved;
284 u64 immediate;
285 } __attribute__((packed));
286
287 /*
288 * Mali Attributes
289 *
290 * This structure lets the attribute unit compute the address of an attribute
291 * given the vertex and instance ID. Unfortunately, the way this works is
292 * rather complicated when instancing is enabled.
293 *
294 * To explain this, first we need to explain how compute and vertex threads are
295 * dispatched. This is a guess (although a pretty firm guess!) since the
296 * details are mostly hidden from the driver, except for attribute instancing.
297 * When a quad is dispatched, it receives a single, linear index. However, we
298 * need to translate that index into a (vertex id, instance id) pair, or a
299 * (local id x, local id y, local id z) triple for compute shaders (although
300 * vertex shaders and compute shaders are handled almost identically).
301 * Focusing on vertex shaders, one option would be to do:
302 *
303 * vertex_id = linear_id % num_vertices
304 * instance_id = linear_id / num_vertices
305 *
306 * but this involves a costly division and modulus by an arbitrary number.
307 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
308 * num_instances threads instead of num_vertices * num_instances, which results
309 * in some "extra" threads with vertex_id >= num_vertices, which we have to
310 * discard. The more we pad num_vertices, the more "wasted" threads we
311 * dispatch, but the division is potentially easier.
312 *
313 * One straightforward choice is to pad num_vertices to the next power of two,
314 * which means that the division and modulus are just simple bit shifts and
315 * masking. But the actual algorithm is a bit more complicated. The thread
316 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
317 * to dividing by a power of two. This is possibly using the technique
318 * described in patent US20170010862A1. As a result, padded_num_vertices can be
319 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
320 * since we need less padding.
321 *
322 * padded_num_vertices is picked by the hardware. The driver just specifies the
323 * actual number of vertices. At least for Mali G71, the first few cases are
324 * given by:
325 *
326 * num_vertices | padded_num_vertices
327 * 3 | 4
328 * 4-7 | 8
329 * 8-11 | 12 (3 * 4)
330 * 12-15 | 16
331 * 16-19 | 20 (5 * 4)
332 *
333 * Note that padded_num_vertices is a multiple of four (presumably because
334 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
335 * at least one more than num_vertices, which seems like a quirk of the
336 * hardware. For larger num_vertices, the hardware uses the following
337 * algorithm: using the binary representation of num_vertices, we look at the
338 * most significant set bit as well as the following 3 bits. Let n be the
339 * number of bits after those 4 bits. Then we set padded_num_vertices according
340 * to the following table:
341 *
342 * high bits | padded_num_vertices
343 * 1000 | 9 * 2^n
344 * 1001 | 5 * 2^(n+1)
345 * 101x | 3 * 2^(n+2)
346 * 110x | 7 * 2^(n+1)
347 * 111x | 2^(n+4)
348 *
349 * For example, if num_vertices = 70 is passed to glDraw(), its binary
350 * representation is 1000110, so n = 3 and the high bits are 1000, and
351 * therefore padded_num_vertices = 9 * 2^3 = 72.
352 *
353 * The attribute unit works in terms of the original linear_id. if
354 * num_instances = 1, then they are the same, and everything is simple.
355 * However, with instancing things get more complicated. There are four
356 * possible modes, two of them we can group together:
357 *
358 * 1. Use the linear_id directly. Only used when there is no instancing.
359 *
360 * 2. Use the linear_id modulo a constant. This is used for per-vertex
361 * attributes with instancing enabled by making the constant equal
362 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
363 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
364 * The shift field specifies the power of two, while the extra_flags field
365 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
366 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
367 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
368 * shift = 3. Note that we must exactly follow the hardware algorithm used to
369 * get padded_num_vertices in order to correctly implement per-vertex
370 * attributes.
371 *
372 * 3. Divide the linear_id by a constant. In order to correctly implement
373 * instance divisors, we have to divide linear_id by padded_num_vertices times
374 * to user-specified divisor. So first we compute padded_num_vertices, again
375 * following the exact same algorithm that the hardware uses, then multiply it
376 * by the GL-level divisor to get the hardware-level divisor. This case is
377 * further divided into two more cases. If the hardware-level divisor is a
378 * power of two, then we just need to shift. The shift amount is specified by
379 * the shift field, so that the hardware-level divisor is just 2^shift.
380 *
381 * If it isn't a power of two, then we have to divide by an arbitrary integer.
382 * For that, we use the well-known technique of multiplying by an approximation
383 * of the inverse. The driver must compute the magic multiplier and shift
384 * amount, and then the hardware does the multiplication and shift. The
385 * hardware and driver also use the "round-down" optimization as described in
386 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
387 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
388 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
389 * presumably this simplifies the hardware multiplier a little. The hardware
390 * first multiplies linear_id by the multiplier and takes the high 32 bits,
391 * then applies the round-down correction if extra_flags = 1, then finally
392 * shifts right by the shift field.
393 *
394 * There are some differences between ridiculousfish's algorithm and the Mali
395 * hardware algorithm, which means that the reference code from ridiculousfish
396 * doesn't always produce the right constants. Mali does not use the pre-shift
397 * optimization, since that would make a hardware implementation slower (it
398 * would have to always do the pre-shift, multiply, and post-shift operations).
399 * It also forces the multplier to be at least 2^31, which means that the
400 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
401 * given the divisor d, the algorithm the driver must follow is:
402 *
403 * 1. Set shift = floor(log2(d)).
404 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
405 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
406 * magic_divisor = m - 1 and extra_flags = 1.
407 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
408 */
409
410 #define FBD_MASK (~0x3f)
411
412 /* MFBD, rather than SFBD */
413 #define MALI_MFBD (0x1)
414
415 /* ORed into an MFBD address to specify the fbx section is included */
416 #define MALI_MFBD_TAG_EXTRA (0x2)
417
418 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
419 * They also seem to be the same between Bifrost and Midgard. They're shared in
420 * fused payloads.
421 */
422
423 /* Applies to unknown_draw */
424
425 #define MALI_DRAW_INDEXED_UINT8 (0x10)
426 #define MALI_DRAW_INDEXED_UINT16 (0x20)
427 #define MALI_DRAW_INDEXED_UINT32 (0x30)
428 #define MALI_DRAW_INDEXED_SIZE (0x30)
429 #define MALI_DRAW_INDEXED_SHIFT (4)
430
431 #define MALI_DRAW_VARYING_SIZE (0x100)
432
433 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
434 * use the last vertex. This is the default in DX and VK, but not in GL. */
435
436 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
437
438 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
439
440 struct mali_vertex_tiler_prefix {
441 /* This is a dynamic bitfield containing the following things in this order:
442 *
443 * - gl_WorkGroupSize.x
444 * - gl_WorkGroupSize.y
445 * - gl_WorkGroupSize.z
446 * - gl_NumWorkGroups.x
447 * - gl_NumWorkGroups.y
448 * - gl_NumWorkGroups.z
449 *
450 * The number of bits allocated for each number is based on the *_shift
451 * fields below. For example, workgroups_y_shift gives the bit that
452 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
453 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
454 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
455 * value is one more than the stored value, since if any of the values
456 * are zero, then there would be no invocations (and hence no job). If
457 * there were 0 bits allocated to a given field, then it must be zero,
458 * and hence the real value is one.
459 *
460 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
461 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
462 * where vertex count is the number of vertices.
463 */
464 u32 invocation_count;
465
466 /* Bitfield for shifts:
467 *
468 * size_y_shift : 5
469 * size_z_shift : 5
470 * workgroups_x_shift : 6
471 * workgroups_y_shift : 6
472 * workgroups_z_shift : 6
473 * workgroups_x_shift_2 : 4
474 */
475 u32 invocation_shifts;
476
477 u32 draw_mode : 4;
478 u32 unknown_draw : 22;
479
480 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
481 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
482 * something to do with how many quads get put in the same execution
483 * engine, which is a balance (you don't want to starve the engine, but
484 * you also want to distribute work evenly).
485 */
486 u32 workgroups_x_shift_3 : 6;
487
488
489 /* Negative of min_index. This is used to compute
490 * the unbiased index in tiler/fragment shader runs.
491 *
492 * The hardware adds offset_bias_correction in each run,
493 * so that absent an index bias, the first vertex processed is
494 * genuinely the first vertex (0). But with an index bias,
495 * the first vertex process is numbered the same as the bias.
496 *
497 * To represent this more conviniently:
498 * unbiased_index = lower_bound_index +
499 * index_bias +
500 * offset_bias_correction
501 *
502 * This is done since the hardware doesn't accept a index_bias
503 * and this allows it to recover the unbiased index.
504 */
505 int32_t offset_bias_correction;
506 u32 zero1;
507
508 /* Like many other strictly nonzero quantities, index_count is
509 * subtracted by one. For an indexed cube, this is equal to 35 = 6
510 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
511 * for an indexed draw, index_count is the number of actual vertices
512 * rendered whereas invocation_count is the number of unique vertices
513 * rendered (the number of times the vertex shader must be invoked).
514 * For non-indexed draws, this is just equal to invocation_count. */
515
516 u32 index_count;
517
518 /* No hidden structure; literally just a pointer to an array of uint
519 * indices (width depends on flags). Thanks, guys, for not making my
520 * life insane for once! NULL for non-indexed draws. */
521
522 u64 indices;
523 } __attribute__((packed));
524
525 /* Point size / line width can either be specified as a 32-bit float (for
526 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
527 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
528 * payload, the contents of varying_pointer will be intepreted as an array of
529 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
530 * creating a special MALI_R16F varying writing to varying_pointer. */
531
532 union midgard_primitive_size {
533 float constant;
534 u64 pointer;
535 };
536
537 struct bifrost_tiler_heap_meta {
538 u32 zero;
539 u32 heap_size;
540 /* note: these are just guesses! */
541 mali_ptr tiler_heap_start;
542 mali_ptr tiler_heap_free;
543 mali_ptr tiler_heap_end;
544
545 /* hierarchy weights? but they're still 0 after the job has run... */
546 u32 zeros[10];
547 u32 unk1;
548 u32 unk7e007e;
549 } __attribute__((packed));
550
551 struct bifrost_tiler_meta {
552 u32 tiler_heap_next_start; /* To be written by the GPU */
553 u32 used_hierarchy_mask; /* To be written by the GPU */
554 u16 hierarchy_mask; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
555 u16 flags;
556 u16 width;
557 u16 height;
558 u64 zero0;
559 mali_ptr tiler_heap_meta;
560 /* TODO what is this used for? */
561 u64 zeros[20];
562 } __attribute__((packed));
563
564 struct bifrost_tiler_only {
565 /* 0x20 */
566 union midgard_primitive_size primitive_size;
567
568 mali_ptr tiler_meta;
569
570 u64 zero1, zero2, zero3, zero4, zero5, zero6;
571 } __attribute__((packed));
572
573 struct mali_vertex_tiler_postfix {
574 u16 gl_enables; // 0x6 on Midgard, 0x2 on Bifrost
575
576 /* Both zero for non-instanced draws. For instanced draws, a
577 * decomposition of padded_num_vertices. See the comments about the
578 * corresponding fields in mali_attr for context. */
579
580 unsigned instance_shift : 5;
581 unsigned instance_odd : 3;
582
583 u8 zero4;
584
585 /* Offset for first vertex in buffer */
586 u32 offset_start;
587
588 u64 zero5;
589
590 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
591 * output from the vertex shader for tiler jobs.
592 */
593
594 u64 position_varying;
595
596 /* An array of mali_uniform_buffer_meta's. The size is given by the
597 * shader_meta.
598 */
599 u64 uniform_buffers;
600
601 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
602 * On Midgard, this is a pointer to an array of pointers to the texture
603 * descriptors, number of pointers bounded by number of textures. The
604 * indirection is needed to accomodate varying numbers and sizes of
605 * texture descriptors */
606 u64 textures;
607
608 /* For OpenGL, from what I've seen, this is intimately connected to
609 * texture_meta. cwabbott says this is not the case under Vulkan, hence
610 * why this field is seperate (Midgard is Vulkan capable). Pointer to
611 * array of sampler descriptors (which are uniform in size) */
612 u64 sampler_descriptor;
613
614 u64 uniforms;
615 u64 shader;
616 u64 attributes; /* struct attribute_buffer[] */
617 u64 attribute_meta; /* attribute_meta[] */
618 u64 varyings; /* struct attr */
619 u64 varying_meta; /* pointer */
620 u64 viewport;
621 u64 occlusion_counter; /* A single bit as far as I can tell */
622
623 /* On Bifrost, this points directly to a mali_shared_memory structure.
624 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
625 * tagged), which embeds a mali_shared_memory structure */
626 mali_ptr shared_memory;
627 } __attribute__((packed));
628
629 struct midgard_payload_vertex_tiler {
630 struct mali_vertex_tiler_prefix prefix;
631 struct mali_vertex_tiler_postfix postfix;
632
633 union midgard_primitive_size primitive_size;
634 } __attribute__((packed));
635
636 struct bifrost_payload_vertex {
637 struct mali_vertex_tiler_prefix prefix;
638 struct mali_vertex_tiler_postfix postfix;
639 } __attribute__((packed));
640
641 struct bifrost_payload_tiler {
642 struct mali_vertex_tiler_prefix prefix;
643 struct bifrost_tiler_only tiler;
644 struct mali_vertex_tiler_postfix postfix;
645 } __attribute__((packed));
646
647 struct bifrost_payload_fused {
648 struct mali_vertex_tiler_prefix prefix;
649 struct bifrost_tiler_only tiler;
650 struct mali_vertex_tiler_postfix tiler_postfix;
651 u64 padding; /* zero */
652 struct mali_vertex_tiler_postfix vertex_postfix;
653 } __attribute__((packed));
654
655 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
656 * texture is stored as (63, 63) in these fields. This adjusts for that.
657 * There's an identical pattern in the framebuffer descriptor. Even vertex
658 * count fields work this way, hence the generic name -- integral fields that
659 * are strictly positive generally need this adjustment. */
660
661 #define MALI_POSITIVE(dim) (dim - 1)
662
663 /* 8192x8192 */
664 #define MAX_MIP_LEVELS (13)
665
666 /* Cubemap bloats everything up */
667 #define MAX_CUBE_FACES (6)
668
669 /* For each pointer, there is an address and optionally also a stride */
670 #define MAX_ELEMENTS (2)
671
672 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
673 * be cleaned up a lot. */
674
675 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
676
677 static inline int16_t
678 FIXED_16(float x, bool allow_negative)
679 {
680 /* Clamp inputs, accounting for float error */
681 float max_lod = (32.0 - (1.0 / 512.0));
682 float min_lod = allow_negative ? -max_lod : 0.0;
683
684 x = ((x > max_lod) ? max_lod : ((x < min_lod) ? min_lod : x));
685
686 return (int) (x * 256.0);
687 }
688
689 /* From presentations, 16x16 tiles externally. Use shift for fast computation
690 * of tile numbers. */
691
692 #define MALI_TILE_SHIFT 4
693 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
694
695 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
696 * each component. Notice that this provides a theoretical upper bound of (1 <<
697 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
698 * 65536x65536. Multiplying that together, times another four given that Mali
699 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
700 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
701 * alone rendering in real-time to such a buffer.
702 *
703 * Nice job, guys.*/
704
705 /* From mali_kbase_10969_workaround.c */
706 #define MALI_X_COORD_MASK 0x00000FFF
707 #define MALI_Y_COORD_MASK 0x0FFF0000
708
709 /* Extract parts of a tile coordinate */
710
711 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
712 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
713
714 /* Helpers to generate tile coordinates based on the boundary coordinates in
715 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
716 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
717 * Intentional "off-by-one"; finding the tile number is a form of fencepost
718 * problem. */
719
720 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
721 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
722 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
723 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
724 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
725
726 struct mali_payload_fragment {
727 u32 min_tile_coord;
728 u32 max_tile_coord;
729 mali_ptr framebuffer;
730 } __attribute__((packed));
731
732 /* Single Framebuffer Descriptor */
733
734 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
735 * configured for 4x. With MSAA_8, it is configured for 8x. */
736
737 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
738 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
739 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
740 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
741
742 /* Fast/slow based on whether all three buffers are cleared at once */
743
744 #define MALI_CLEAR_FAST (1 << 18)
745 #define MALI_CLEAR_SLOW (1 << 28)
746 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
747
748 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
749 * within the larget framebuffer descriptor). Analogous to
750 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
751
752 /* See pan_tiler.c for derivation */
753 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
754
755 /* Flag disabling the tiler for clear-only jobs, with
756 hierarchical tiling */
757 #define MALI_TILER_DISABLED (1 << 12)
758
759 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
760 * hierarhical tiling. */
761 #define MALI_TILER_USER 0xFFF
762
763 /* Absent any geometry, the minimum size of the polygon list header */
764 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
765
766 struct midgard_tiler_descriptor {
767 /* Size of the entire polygon list; see pan_tiler.c for the
768 * computation. It's based on hierarchical tiling */
769
770 u32 polygon_list_size;
771
772 /* Name known from the replay workaround in the kernel. What exactly is
773 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
774 * specifies a mask of hierarchy weights, which explains some of the
775 * performance mysteries around setting it. We also see the bottom bit
776 * of tiler_flags set in the kernel, but no comment why.
777 *
778 * hierarchy_mask can have the TILER_DISABLED flag */
779
780 u16 hierarchy_mask;
781 u16 flags;
782
783 /* See mali_tiler.c for an explanation */
784 mali_ptr polygon_list;
785 mali_ptr polygon_list_body;
786
787 /* Names based on we see symmetry with replay jobs which name these
788 * explicitly */
789
790 mali_ptr heap_start; /* tiler heap_free_address */
791 mali_ptr heap_end;
792
793 /* Hierarchy weights. We know these are weights based on the kernel,
794 * but I've never seen them be anything other than zero */
795 u32 weights[8];
796 };
797
798 struct mali_sfbd_format {
799 /* 0x1 */
800 unsigned unk1 : 6;
801
802 /* mali_channel_swizzle */
803 unsigned swizzle : 12;
804
805 /* MALI_POSITIVE */
806 unsigned nr_channels : 2;
807
808 /* 0x4 */
809 unsigned unk2 : 6;
810
811 enum mali_block_format block : 2;
812
813 /* 0xb */
814 unsigned unk3 : 4;
815 };
816
817 /* Shared structure at the start of framebuffer descriptors, or used bare for
818 * compute jobs, configuring stack and shared memory */
819
820 struct mali_shared_memory {
821 u32 stack_shift : 4;
822 u32 unk0 : 28;
823
824 /* Configuration for shared memory for compute shaders.
825 * shared_workgroup_count is logarithmic and may be computed for a
826 * compute shader using shared memory as:
827 *
828 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
829 *
830 * For compute shaders that don't use shared memory, or non-compute
831 * shaders, this is set to ~0
832 */
833
834 u32 shared_workgroup_count : 5;
835 u32 shared_unk1 : 3;
836 u32 shared_shift : 4;
837 u32 shared_zero : 20;
838
839 mali_ptr scratchpad;
840
841 /* For compute shaders, the RAM backing of workgroup-shared memory. For
842 * fragment shaders on Bifrost, apparently multisampling locations */
843
844 mali_ptr shared_memory;
845 mali_ptr unknown1;
846 } __attribute__((packed));
847
848 /* Configures multisampling on Bifrost fragment jobs */
849
850 struct bifrost_multisampling {
851 u64 zero1;
852 u64 zero2;
853 mali_ptr sample_locations;
854 u64 zero4;
855 } __attribute__((packed));
856
857 struct mali_single_framebuffer {
858 struct mali_shared_memory shared_memory;
859 struct mali_sfbd_format format;
860
861 u32 clear_flags;
862 u32 zero2;
863
864 /* Purposeful off-by-one in these fields should be accounted for by the
865 * MALI_DIMENSION macro */
866
867 u16 width;
868 u16 height;
869
870 u32 zero3[4];
871 mali_ptr checksum;
872 u32 checksum_stride;
873 u32 zero5;
874
875 /* By default, the framebuffer is upside down from OpenGL's
876 * perspective. Set framebuffer to the end and negate the stride to
877 * flip in the Y direction */
878
879 mali_ptr framebuffer;
880 int32_t stride;
881
882 u32 zero4;
883
884 /* Depth and stencil buffers are interleaved, it appears, as they are
885 * set to the same address in captures. Both fields set to zero if the
886 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
887 * get a zero enable despite the buffer being present; that still is
888 * disabled. */
889
890 mali_ptr depth_buffer; // not SAME_VA
891 u32 depth_stride_zero : 4;
892 u32 depth_stride : 28;
893 u32 zero7;
894
895 mali_ptr stencil_buffer; // not SAME_VA
896 u32 stencil_stride_zero : 4;
897 u32 stencil_stride : 28;
898 u32 zero8;
899
900 u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware
901 u32 clear_color_2; // always equal, but unclear function?
902 u32 clear_color_3; // always equal, but unclear function?
903 u32 clear_color_4; // always equal, but unclear function?
904
905 /* Set to zero if not cleared */
906
907 float clear_depth_1; // float32, ditto
908 float clear_depth_2; // float32, ditto
909 float clear_depth_3; // float32, ditto
910 float clear_depth_4; // float32, ditto
911
912 u32 clear_stencil; // Exactly as it appears in OpenGL
913
914 u32 zero6[7];
915
916 struct midgard_tiler_descriptor tiler;
917
918 /* More below this, maybe */
919 } __attribute__((packed));
920
921
922 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
923
924 struct mali_rt_format {
925 unsigned unk1 : 32;
926 unsigned unk2 : 3;
927
928 unsigned nr_channels : 2; /* MALI_POSITIVE */
929
930 unsigned unk3 : 4;
931 unsigned unk4 : 1;
932 enum mali_block_format block : 2;
933 enum mali_msaa msaa : 2;
934 unsigned flags : 2;
935
936 unsigned swizzle : 12;
937
938 unsigned zero : 3;
939
940 /* Disables MFBD preload. When this bit is set, the render target will
941 * be cleared every frame. When this bit is clear, the hardware will
942 * automatically wallpaper the render target back from main memory.
943 * Unfortunately, MFBD preload is very broken on Midgard, so in
944 * practice, this is a chicken bit that should always be set.
945 * Discovered by accident, as all good chicken bits are. */
946
947 unsigned no_preload : 1;
948 } __attribute__((packed));
949
950 /* Flags for afbc.flags and ds_afbc.flags */
951
952 #define MALI_AFBC_FLAGS 0x10009
953
954 /* Lossless RGB and RGBA colorspace transform */
955 #define MALI_AFBC_YTR (1 << 17)
956
957 struct mali_render_target {
958 struct mali_rt_format format;
959
960 u64 zero1;
961
962 struct {
963 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
964 * there is an extra metadata buffer that contains 16 bytes per tile.
965 * The framebuffer needs to be the same size as before, since we don't
966 * know ahead of time how much space it will take up. The
967 * framebuffer_stride is set to 0, since the data isn't stored linearly
968 * anymore.
969 *
970 * When AFBC is disabled, these fields are zero.
971 */
972
973 mali_ptr metadata;
974 u32 stride; // stride in units of tiles
975 u32 flags; // = 0x20000
976 } afbc;
977
978 mali_ptr framebuffer;
979
980 u32 zero2 : 4;
981 u32 framebuffer_stride : 28; // in units of bytes, row to next
982 u32 layer_stride; /* For multisample rendering */
983
984 u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware
985 u32 clear_color_2; // always equal, but unclear function?
986 u32 clear_color_3; // always equal, but unclear function?
987 u32 clear_color_4; // always equal, but unclear function?
988 } __attribute__((packed));
989
990 /* An optional part of mali_framebuffer. It comes between the main structure
991 * and the array of render targets. It must be included if any of these are
992 * enabled:
993 *
994 * - Transaction Elimination
995 * - Depth/stencil
996 * - TODO: Anything else?
997 */
998
999 /* flags_hi */
1000 #define MALI_EXTRA_PRESENT (0x1)
1001
1002 /* flags_lo */
1003 #define MALI_EXTRA_ZS (0x4)
1004
1005 struct mali_framebuffer_extra {
1006 mali_ptr checksum;
1007 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1008 u32 checksum_stride;
1009
1010 unsigned flags_lo : 4;
1011 enum mali_block_format zs_block : 2;
1012
1013 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1014 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1015 unsigned zs_samples : 4;
1016 unsigned flags_hi : 22;
1017
1018 union {
1019 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1020 struct {
1021 mali_ptr depth_stencil_afbc_metadata;
1022 u32 depth_stencil_afbc_stride; // in units of tiles
1023 u32 flags;
1024
1025 mali_ptr depth_stencil;
1026
1027 u64 padding;
1028 } ds_afbc;
1029
1030 struct {
1031 /* Depth becomes depth/stencil in case of combined D/S */
1032 mali_ptr depth;
1033 u32 depth_stride_zero : 4;
1034 u32 depth_stride : 28;
1035 u32 depth_layer_stride;
1036
1037 mali_ptr stencil;
1038 u32 stencil_stride_zero : 4;
1039 u32 stencil_stride : 28;
1040 u32 stencil_layer_stride;
1041 } ds_linear;
1042 };
1043
1044
1045 u32 clear_color_1;
1046 u32 clear_color_2;
1047 u64 zero3;
1048 } __attribute__((packed));
1049
1050 /* Flags for mfbd_flags */
1051
1052 /* Enables writing depth results back to main memory (rather than keeping them
1053 * on-chip in the tile buffer and then discarding) */
1054
1055 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1056
1057 /* The MFBD contains the extra mali_framebuffer_extra section */
1058
1059 #define MALI_MFBD_EXTRA (1 << 13)
1060
1061 struct mali_framebuffer {
1062 union {
1063 struct mali_shared_memory shared_memory;
1064 struct bifrost_multisampling msaa;
1065 };
1066
1067 /* 0x20 */
1068 u16 width1, height1;
1069 u32 zero3;
1070 u16 width2, height2;
1071 u32 unk1 : 19; // = 0x01000
1072 u32 rt_count_1 : 3; // off-by-one (use MALI_POSITIVE)
1073 u32 unk2 : 2; // = 0
1074 u32 rt_count_2 : 3; // no off-by-one
1075 u32 zero4 : 5;
1076 /* 0x30 */
1077 u32 clear_stencil : 8;
1078 u32 mfbd_flags : 24; // = 0x100
1079 float clear_depth;
1080
1081 union {
1082 struct midgard_tiler_descriptor tiler;
1083 struct {
1084 mali_ptr tiler_meta;
1085 u32 zeros[16];
1086 };
1087 };
1088
1089 /* optional: struct mali_framebuffer_extra extra */
1090 /* struct mali_render_target rts[] */
1091 } __attribute__((packed));
1092
1093 #endif /* __PANFROST_JOB_H__ */