e2267069860b1028362b515208c623b15c6a32c6
[mesa.git] / src / panfrost / include / panfrost-job.h
1 /*
2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * SOFTWARE.
25 *
26 */
27
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
30
31 #include <stdint.h>
32 #include <stdbool.h>
33 #include <inttypes.h>
34
35 typedef uint8_t u8;
36 typedef uint16_t u16;
37 typedef uint32_t u32;
38 typedef uint64_t u64;
39 typedef uint64_t mali_ptr;
40
41 /* Applies to tiler_gl_enables */
42
43 #define MALI_OCCLUSION_QUERY (1 << 3)
44 #define MALI_OCCLUSION_PRECISE (1 << 4)
45
46 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
47 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
48 * disagree about how to do viewport flipping, so the blob actually sets this
49 * for GL_CW but then has a negative viewport stride */
50
51 #define MALI_FRONT_CCW_TOP (1 << 5)
52
53 #define MALI_CULL_FACE_FRONT (1 << 6)
54 #define MALI_CULL_FACE_BACK (1 << 7)
55
56 /* Flags apply to unknown2_3? */
57
58 #define MALI_HAS_MSAA (1 << 0)
59
60 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
61 * reads) */
62 #define MALI_PER_SAMPLE (1 << 2)
63 #define MALI_CAN_DISCARD (1 << 5)
64
65 /* Applies on SFBD systems, specifying that programmable blending is in use */
66 #define MALI_HAS_BLEND_SHADER (1 << 6)
67
68 /* func is mali_func */
69 #define MALI_DEPTH_FUNC(func) (func << 8)
70 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
71 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
72
73 #define MALI_DEPTH_WRITEMASK (1 << 11)
74
75 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
76 #define MALI_DEPTH_CLIP_FAR (1 << 13)
77
78 /* Next flags to unknown2_4 */
79 #define MALI_STENCIL_TEST (1 << 0)
80
81 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
82
83 #define MALI_NO_DITHER (1 << 9)
84 #define MALI_DEPTH_RANGE_A (1 << 12)
85 #define MALI_DEPTH_RANGE_B (1 << 13)
86 #define MALI_NO_MSAA (1 << 14)
87
88 #define MALI_MASK_R (1 << 0)
89 #define MALI_MASK_G (1 << 1)
90 #define MALI_MASK_B (1 << 2)
91 #define MALI_MASK_A (1 << 3)
92
93 enum mali_nondominant_mode {
94 MALI_BLEND_NON_MIRROR = 0,
95 MALI_BLEND_NON_ZERO = 1
96 };
97
98 enum mali_dominant_blend {
99 MALI_BLEND_DOM_SOURCE = 0,
100 MALI_BLEND_DOM_DESTINATION = 1
101 };
102
103 enum mali_dominant_factor {
104 MALI_DOMINANT_UNK0 = 0,
105 MALI_DOMINANT_ZERO = 1,
106 MALI_DOMINANT_SRC_COLOR = 2,
107 MALI_DOMINANT_DST_COLOR = 3,
108 MALI_DOMINANT_UNK4 = 4,
109 MALI_DOMINANT_SRC_ALPHA = 5,
110 MALI_DOMINANT_DST_ALPHA = 6,
111 MALI_DOMINANT_CONSTANT = 7,
112 };
113
114 enum mali_blend_modifier {
115 MALI_BLEND_MOD_UNK0 = 0,
116 MALI_BLEND_MOD_NORMAL = 1,
117 MALI_BLEND_MOD_SOURCE_ONE = 2,
118 MALI_BLEND_MOD_DEST_ONE = 3,
119 };
120
121 struct mali_blend_mode {
122 enum mali_blend_modifier clip_modifier : 2;
123 unsigned unused_0 : 1;
124 unsigned negate_source : 1;
125
126 enum mali_dominant_blend dominant : 1;
127
128 enum mali_nondominant_mode nondominant_mode : 1;
129
130 unsigned unused_1 : 1;
131
132 unsigned negate_dest : 1;
133
134 enum mali_dominant_factor dominant_factor : 3;
135 unsigned complement_dominant : 1;
136 } __attribute__((packed));
137
138 /* Compressed per-pixel formats. Each of these formats expands to one to four
139 * floating-point or integer numbers, as defined by the OpenGL specification.
140 * There are various places in OpenGL where the user can specify a compressed
141 * format in memory, which all use the same 8-bit enum in the various
142 * descriptors, although different hardware units support different formats.
143 */
144
145 /* The top 3 bits specify how the bits of each component are interpreted. */
146
147 /* e.g. ETC2_RGB8 */
148 #define MALI_FORMAT_COMPRESSED (0 << 5)
149
150 /* e.g. R11F_G11F_B10F */
151 #define MALI_FORMAT_SPECIAL (2 << 5)
152
153 /* signed normalized, e.g. RGBA8_SNORM */
154 #define MALI_FORMAT_SNORM (3 << 5)
155
156 /* e.g. RGBA8UI */
157 #define MALI_FORMAT_UINT (4 << 5)
158
159 /* e.g. RGBA8 and RGBA32F */
160 #define MALI_FORMAT_UNORM (5 << 5)
161
162 /* e.g. RGBA8I and RGBA16F */
163 #define MALI_FORMAT_SINT (6 << 5)
164
165 /* These formats seem to largely duplicate the others. They're used at least
166 * for Bifrost framebuffer output.
167 */
168 #define MALI_FORMAT_SPECIAL2 (7 << 5)
169 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
170
171 /* If the high 3 bits are 3 to 6 these two bits say how many components
172 * there are.
173 */
174 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
175 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
176
177 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
178 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
179 * bits mean.
180 */
181
182 #define MALI_CHANNEL_4 2
183
184 #define MALI_CHANNEL_8 3
185
186 #define MALI_CHANNEL_16 4
187
188 #define MALI_CHANNEL_32 5
189
190 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
191 * MALI_FORMAT_UNORM, it means a 32-bit float.
192 */
193 #define MALI_CHANNEL_FLOAT 7
194 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
195
196 /* The raw Midgard blend payload can either be an equation or a shader
197 * address, depending on the context */
198
199 union midgard_blend {
200 mali_ptr shader;
201
202 struct {
203 struct mali_blend_equation_packed equation;
204 float constant;
205 };
206 };
207
208 struct midgard_blend_rt {
209 struct mali_blend_flags_packed flags;
210 u32 zero;
211 union midgard_blend blend;
212 } __attribute__((packed));
213
214 /* On Bifrost systems (all MRT), each render target gets one of these
215 * descriptors */
216
217 enum bifrost_shader_type {
218 BIFROST_BLEND_F16 = 0,
219 BIFROST_BLEND_F32 = 1,
220 BIFROST_BLEND_I32 = 2,
221 BIFROST_BLEND_U32 = 3,
222 BIFROST_BLEND_I16 = 4,
223 BIFROST_BLEND_U16 = 5,
224 };
225
226 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
227
228 struct bifrost_blend_rt {
229 /* This is likely an analogue of the flags on
230 * midgard_blend_rt */
231
232 u16 flags; // = 0x200
233
234 /* Single-channel blend constants are encoded in a sort of
235 * fixed-point. Basically, the float is mapped to a byte, becoming
236 * a high byte, and then the lower-byte is added for precision.
237 * For the original float f:
238 *
239 * f = (constant_hi / 255) + (constant_lo / 65535)
240 *
241 * constant_hi = int(f / 255)
242 * constant_lo = 65535*f - (65535/255) * constant_hi
243 */
244 u16 constant;
245
246 struct mali_blend_equation_packed equation;
247
248 /*
249 * - 0x19 normally
250 * - 0x3 when this slot is unused (everything else is 0 except the index)
251 * - 0x11 when this is the fourth slot (and it's used)
252 * - 0 when there is a blend shader
253 */
254 u16 unk2;
255
256 /* increments from 0 to 3 */
257 u16 index;
258
259 union {
260 struct {
261 /* So far, I've only seen:
262 * - R001 for 1-component formats
263 * - RG01 for 2-component formats
264 * - RGB1 for 3-component formats
265 * - RGBA for 4-component formats
266 */
267 u32 swizzle : 12;
268 enum mali_format format : 8;
269
270 /* Type of the shader output variable. Note, this can
271 * be different from the format.
272 * enum bifrost_shader_type
273 */
274 u32 zero1 : 4;
275 u32 shader_type : 3;
276 u32 zero2 : 5;
277 };
278
279 /* Only the low 32 bits of the blend shader are stored, the
280 * high 32 bits are implicitly the same as the original shader.
281 * According to the kernel driver, the program counter for
282 * shaders is actually only 24 bits, so shaders cannot cross
283 * the 2^24-byte boundary, and neither can the blend shader.
284 * The blob handles this by allocating a 2^24 byte pool for
285 * shaders, and making sure that any blend shaders are stored
286 * in the same pool as the original shader. The kernel will
287 * make sure this allocation is aligned to 2^24 bytes.
288 */
289 u32 shader;
290 };
291 } __attribute__((packed));
292
293 /* Descriptor for the shader. Following this is at least one, up to four blend
294 * descriptors for each active render target */
295
296 struct mali_shader_meta {
297 mali_ptr shader;
298 u16 sampler_count;
299 u16 texture_count;
300 u16 attribute_count;
301 u16 varying_count;
302
303 union {
304 struct mali_bifrost_properties_packed bifrost_props;
305 struct mali_midgard_properties_packed midgard_props;
306 };
307
308 /* Same as glPolygoOffset() arguments */
309 float depth_units;
310 float depth_factor;
311
312 u32 unknown2_2;
313
314 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
315 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
316 * specification. Only matters when multisampling is enabled. */
317 u16 coverage_mask;
318
319 u16 unknown2_3;
320
321 u8 stencil_mask_front;
322 u8 stencil_mask_back;
323 u16 unknown2_4;
324
325 struct mali_stencil_packed stencil_front;
326 struct mali_stencil_packed stencil_back;
327
328 union {
329 struct mali_preload_packed bifrost_preload;
330 struct {
331 u32 unknown2_7;
332 } midgard2;
333 };
334
335 u32 padding;
336
337 /* Blending information for the older non-MRT Midgard HW. Check for
338 * MALI_HAS_BLEND_SHADER to decide how to interpret.
339 */
340
341 union midgard_blend blend;
342 } __attribute__((packed));
343
344 /* This only concerns hardware jobs */
345
346 /* Possible values for job_descriptor_size */
347
348 #define MALI_JOB_32 0
349 #define MALI_JOB_64 1
350
351 struct mali_job_descriptor_header {
352 u32 exception_status;
353 u32 first_incomplete_task;
354 u64 fault_pointer;
355 u8 job_descriptor_size : 1;
356 enum mali_job_type job_type : 7;
357 u8 job_barrier : 1;
358 u8 unknown_flags : 7;
359 u16 job_index;
360 u16 job_dependency_index_1;
361 u16 job_dependency_index_2;
362 u64 next_job;
363 } __attribute__((packed));
364
365 /* Details about write_value from panfrost igt tests which use it as a generic
366 * dword write primitive */
367
368 #define MALI_WRITE_VALUE_ZERO 3
369
370 struct mali_payload_write_value {
371 u64 address;
372 u32 value_descriptor;
373 u32 reserved;
374 u64 immediate;
375 } __attribute__((packed));
376
377 /*
378 * Mali Attributes
379 *
380 * This structure lets the attribute unit compute the address of an attribute
381 * given the vertex and instance ID. Unfortunately, the way this works is
382 * rather complicated when instancing is enabled.
383 *
384 * To explain this, first we need to explain how compute and vertex threads are
385 * dispatched. This is a guess (although a pretty firm guess!) since the
386 * details are mostly hidden from the driver, except for attribute instancing.
387 * When a quad is dispatched, it receives a single, linear index. However, we
388 * need to translate that index into a (vertex id, instance id) pair, or a
389 * (local id x, local id y, local id z) triple for compute shaders (although
390 * vertex shaders and compute shaders are handled almost identically).
391 * Focusing on vertex shaders, one option would be to do:
392 *
393 * vertex_id = linear_id % num_vertices
394 * instance_id = linear_id / num_vertices
395 *
396 * but this involves a costly division and modulus by an arbitrary number.
397 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
398 * num_instances threads instead of num_vertices * num_instances, which results
399 * in some "extra" threads with vertex_id >= num_vertices, which we have to
400 * discard. The more we pad num_vertices, the more "wasted" threads we
401 * dispatch, but the division is potentially easier.
402 *
403 * One straightforward choice is to pad num_vertices to the next power of two,
404 * which means that the division and modulus are just simple bit shifts and
405 * masking. But the actual algorithm is a bit more complicated. The thread
406 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
407 * to dividing by a power of two. This is possibly using the technique
408 * described in patent US20170010862A1. As a result, padded_num_vertices can be
409 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
410 * since we need less padding.
411 *
412 * padded_num_vertices is picked by the hardware. The driver just specifies the
413 * actual number of vertices. At least for Mali G71, the first few cases are
414 * given by:
415 *
416 * num_vertices | padded_num_vertices
417 * 3 | 4
418 * 4-7 | 8
419 * 8-11 | 12 (3 * 4)
420 * 12-15 | 16
421 * 16-19 | 20 (5 * 4)
422 *
423 * Note that padded_num_vertices is a multiple of four (presumably because
424 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
425 * at least one more than num_vertices, which seems like a quirk of the
426 * hardware. For larger num_vertices, the hardware uses the following
427 * algorithm: using the binary representation of num_vertices, we look at the
428 * most significant set bit as well as the following 3 bits. Let n be the
429 * number of bits after those 4 bits. Then we set padded_num_vertices according
430 * to the following table:
431 *
432 * high bits | padded_num_vertices
433 * 1000 | 9 * 2^n
434 * 1001 | 5 * 2^(n+1)
435 * 101x | 3 * 2^(n+2)
436 * 110x | 7 * 2^(n+1)
437 * 111x | 2^(n+4)
438 *
439 * For example, if num_vertices = 70 is passed to glDraw(), its binary
440 * representation is 1000110, so n = 3 and the high bits are 1000, and
441 * therefore padded_num_vertices = 9 * 2^3 = 72.
442 *
443 * The attribute unit works in terms of the original linear_id. if
444 * num_instances = 1, then they are the same, and everything is simple.
445 * However, with instancing things get more complicated. There are four
446 * possible modes, two of them we can group together:
447 *
448 * 1. Use the linear_id directly. Only used when there is no instancing.
449 *
450 * 2. Use the linear_id modulo a constant. This is used for per-vertex
451 * attributes with instancing enabled by making the constant equal
452 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
453 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
454 * The shift field specifies the power of two, while the extra_flags field
455 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
456 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
457 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
458 * shift = 3. Note that we must exactly follow the hardware algorithm used to
459 * get padded_num_vertices in order to correctly implement per-vertex
460 * attributes.
461 *
462 * 3. Divide the linear_id by a constant. In order to correctly implement
463 * instance divisors, we have to divide linear_id by padded_num_vertices times
464 * to user-specified divisor. So first we compute padded_num_vertices, again
465 * following the exact same algorithm that the hardware uses, then multiply it
466 * by the GL-level divisor to get the hardware-level divisor. This case is
467 * further divided into two more cases. If the hardware-level divisor is a
468 * power of two, then we just need to shift. The shift amount is specified by
469 * the shift field, so that the hardware-level divisor is just 2^shift.
470 *
471 * If it isn't a power of two, then we have to divide by an arbitrary integer.
472 * For that, we use the well-known technique of multiplying by an approximation
473 * of the inverse. The driver must compute the magic multiplier and shift
474 * amount, and then the hardware does the multiplication and shift. The
475 * hardware and driver also use the "round-down" optimization as described in
476 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
477 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
478 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
479 * presumably this simplifies the hardware multiplier a little. The hardware
480 * first multiplies linear_id by the multiplier and takes the high 32 bits,
481 * then applies the round-down correction if extra_flags = 1, then finally
482 * shifts right by the shift field.
483 *
484 * There are some differences between ridiculousfish's algorithm and the Mali
485 * hardware algorithm, which means that the reference code from ridiculousfish
486 * doesn't always produce the right constants. Mali does not use the pre-shift
487 * optimization, since that would make a hardware implementation slower (it
488 * would have to always do the pre-shift, multiply, and post-shift operations).
489 * It also forces the multplier to be at least 2^31, which means that the
490 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
491 * given the divisor d, the algorithm the driver must follow is:
492 *
493 * 1. Set shift = floor(log2(d)).
494 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
495 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
496 * magic_divisor = m - 1 and extra_flags = 1.
497 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
498 */
499
500 #define FBD_MASK (~0x3f)
501
502 /* MFBD, rather than SFBD */
503 #define MALI_MFBD (0x1)
504
505 /* ORed into an MFBD address to specify the fbx section is included */
506 #define MALI_MFBD_TAG_EXTRA (0x2)
507
508 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
509 * They also seem to be the same between Bifrost and Midgard. They're shared in
510 * fused payloads.
511 */
512
513 /* Applies to unknown_draw */
514
515 #define MALI_DRAW_INDEXED_UINT8 (0x10)
516 #define MALI_DRAW_INDEXED_UINT16 (0x20)
517 #define MALI_DRAW_INDEXED_UINT32 (0x30)
518 #define MALI_DRAW_INDEXED_SIZE (0x30)
519 #define MALI_DRAW_INDEXED_SHIFT (4)
520
521 #define MALI_DRAW_VARYING_SIZE (0x100)
522
523 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
524 * use the last vertex. This is the default in DX and VK, but not in GL. */
525
526 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
527
528 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
529
530 struct mali_vertex_tiler_prefix {
531 /* This is a dynamic bitfield containing the following things in this order:
532 *
533 * - gl_WorkGroupSize.x
534 * - gl_WorkGroupSize.y
535 * - gl_WorkGroupSize.z
536 * - gl_NumWorkGroups.x
537 * - gl_NumWorkGroups.y
538 * - gl_NumWorkGroups.z
539 *
540 * The number of bits allocated for each number is based on the *_shift
541 * fields below. For example, workgroups_y_shift gives the bit that
542 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
543 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
544 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
545 * value is one more than the stored value, since if any of the values
546 * are zero, then there would be no invocations (and hence no job). If
547 * there were 0 bits allocated to a given field, then it must be zero,
548 * and hence the real value is one.
549 *
550 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
551 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
552 * where vertex count is the number of vertices.
553 */
554 u32 invocation_count;
555
556 /* Bitfield for shifts:
557 *
558 * size_y_shift : 5
559 * size_z_shift : 5
560 * workgroups_x_shift : 6
561 * workgroups_y_shift : 6
562 * workgroups_z_shift : 6
563 * workgroups_x_shift_2 : 4
564 */
565 u32 invocation_shifts;
566
567 u32 draw_mode : 4;
568 u32 unknown_draw : 22;
569
570 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
571 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
572 * something to do with how many quads get put in the same execution
573 * engine, which is a balance (you don't want to starve the engine, but
574 * you also want to distribute work evenly).
575 */
576 u32 workgroups_x_shift_3 : 6;
577
578
579 /* Negative of min_index. This is used to compute
580 * the unbiased index in tiler/fragment shader runs.
581 *
582 * The hardware adds offset_bias_correction in each run,
583 * so that absent an index bias, the first vertex processed is
584 * genuinely the first vertex (0). But with an index bias,
585 * the first vertex process is numbered the same as the bias.
586 *
587 * To represent this more conviniently:
588 * unbiased_index = lower_bound_index +
589 * index_bias +
590 * offset_bias_correction
591 *
592 * This is done since the hardware doesn't accept a index_bias
593 * and this allows it to recover the unbiased index.
594 */
595 int32_t offset_bias_correction;
596 u32 zero1;
597
598 /* Like many other strictly nonzero quantities, index_count is
599 * subtracted by one. For an indexed cube, this is equal to 35 = 6
600 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
601 * for an indexed draw, index_count is the number of actual vertices
602 * rendered whereas invocation_count is the number of unique vertices
603 * rendered (the number of times the vertex shader must be invoked).
604 * For non-indexed draws, this is just equal to invocation_count. */
605
606 u32 index_count;
607
608 /* No hidden structure; literally just a pointer to an array of uint
609 * indices (width depends on flags). Thanks, guys, for not making my
610 * life insane for once! NULL for non-indexed draws. */
611
612 u64 indices;
613 } __attribute__((packed));
614
615 /* Point size / line width can either be specified as a 32-bit float (for
616 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
617 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
618 * payload, the contents of varying_pointer will be intepreted as an array of
619 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
620 * creating a special MALI_R16F varying writing to varying_pointer. */
621
622 union midgard_primitive_size {
623 float constant;
624 u64 pointer;
625 };
626
627 struct bifrost_tiler_heap_meta {
628 u32 zero;
629 u32 heap_size;
630 /* note: these are just guesses! */
631 mali_ptr tiler_heap_start;
632 mali_ptr tiler_heap_free;
633 mali_ptr tiler_heap_end;
634
635 /* hierarchy weights? but they're still 0 after the job has run... */
636 u32 zeros[10];
637 u32 unk1;
638 u32 unk7e007e;
639 } __attribute__((packed));
640
641 struct bifrost_tiler_meta {
642 u32 tiler_heap_next_start; /* To be written by the GPU */
643 u32 used_hierarchy_mask; /* To be written by the GPU */
644 u16 hierarchy_mask; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
645 u16 flags;
646 u16 width;
647 u16 height;
648 u64 zero0;
649 mali_ptr tiler_heap_meta;
650 /* TODO what is this used for? */
651 u64 zeros[20];
652 } __attribute__((packed));
653
654 struct bifrost_tiler_only {
655 /* 0x20 */
656 union midgard_primitive_size primitive_size;
657
658 mali_ptr tiler_meta;
659
660 u64 zero1, zero2, zero3, zero4, zero5, zero6;
661 } __attribute__((packed));
662
663 struct mali_vertex_tiler_postfix {
664 u16 gl_enables; // 0x6 on Midgard, 0x2 on Bifrost
665
666 /* Both zero for non-instanced draws. For instanced draws, a
667 * decomposition of padded_num_vertices. See the comments about the
668 * corresponding fields in mali_attr for context. */
669
670 unsigned instance_shift : 5;
671 unsigned instance_odd : 3;
672
673 u8 zero4;
674
675 /* Offset for first vertex in buffer */
676 u32 offset_start;
677
678 u64 zero5;
679
680 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
681 * output from the vertex shader for tiler jobs.
682 */
683
684 u64 position_varying;
685
686 /* An array of mali_uniform_buffer_meta's. The size is given by the
687 * shader_meta.
688 */
689 u64 uniform_buffers;
690
691 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
692 * On Midgard, this is a pointer to an array of pointers to the texture
693 * descriptors, number of pointers bounded by number of textures. The
694 * indirection is needed to accomodate varying numbers and sizes of
695 * texture descriptors */
696 u64 textures;
697
698 /* For OpenGL, from what I've seen, this is intimately connected to
699 * texture_meta. cwabbott says this is not the case under Vulkan, hence
700 * why this field is seperate (Midgard is Vulkan capable). Pointer to
701 * array of sampler descriptors (which are uniform in size) */
702 u64 sampler_descriptor;
703
704 u64 uniforms;
705 u64 shader;
706 u64 attributes; /* struct attribute_buffer[] */
707 u64 attribute_meta; /* attribute_meta[] */
708 u64 varyings; /* struct attr */
709 u64 varying_meta; /* pointer */
710 u64 viewport;
711 u64 occlusion_counter; /* A single bit as far as I can tell */
712
713 /* On Bifrost, this points directly to a mali_shared_memory structure.
714 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
715 * tagged), which embeds a mali_shared_memory structure */
716 mali_ptr shared_memory;
717 } __attribute__((packed));
718
719 struct midgard_payload_vertex_tiler {
720 struct mali_vertex_tiler_prefix prefix;
721 struct mali_vertex_tiler_postfix postfix;
722
723 union midgard_primitive_size primitive_size;
724 } __attribute__((packed));
725
726 struct bifrost_payload_vertex {
727 struct mali_vertex_tiler_prefix prefix;
728 struct mali_vertex_tiler_postfix postfix;
729 } __attribute__((packed));
730
731 struct bifrost_payload_tiler {
732 struct mali_vertex_tiler_prefix prefix;
733 struct bifrost_tiler_only tiler;
734 struct mali_vertex_tiler_postfix postfix;
735 } __attribute__((packed));
736
737 struct bifrost_payload_fused {
738 struct mali_vertex_tiler_prefix prefix;
739 struct bifrost_tiler_only tiler;
740 struct mali_vertex_tiler_postfix tiler_postfix;
741 u64 padding; /* zero */
742 struct mali_vertex_tiler_postfix vertex_postfix;
743 } __attribute__((packed));
744
745 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
746 * texture is stored as (63, 63) in these fields. This adjusts for that.
747 * There's an identical pattern in the framebuffer descriptor. Even vertex
748 * count fields work this way, hence the generic name -- integral fields that
749 * are strictly positive generally need this adjustment. */
750
751 #define MALI_POSITIVE(dim) (dim - 1)
752
753 /* 8192x8192 */
754 #define MAX_MIP_LEVELS (13)
755
756 /* Cubemap bloats everything up */
757 #define MAX_CUBE_FACES (6)
758
759 /* For each pointer, there is an address and optionally also a stride */
760 #define MAX_ELEMENTS (2)
761
762 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
763 * be cleaned up a lot. */
764
765 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
766
767 static inline int16_t
768 FIXED_16(float x, bool allow_negative)
769 {
770 /* Clamp inputs, accounting for float error */
771 float max_lod = (32.0 - (1.0 / 512.0));
772 float min_lod = allow_negative ? -max_lod : 0.0;
773
774 x = ((x > max_lod) ? max_lod : ((x < min_lod) ? min_lod : x));
775
776 return (int) (x * 256.0);
777 }
778
779 /* From presentations, 16x16 tiles externally. Use shift for fast computation
780 * of tile numbers. */
781
782 #define MALI_TILE_SHIFT 4
783 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
784
785 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
786 * each component. Notice that this provides a theoretical upper bound of (1 <<
787 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
788 * 65536x65536. Multiplying that together, times another four given that Mali
789 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
790 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
791 * alone rendering in real-time to such a buffer.
792 *
793 * Nice job, guys.*/
794
795 /* From mali_kbase_10969_workaround.c */
796 #define MALI_X_COORD_MASK 0x00000FFF
797 #define MALI_Y_COORD_MASK 0x0FFF0000
798
799 /* Extract parts of a tile coordinate */
800
801 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
802 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
803
804 /* Helpers to generate tile coordinates based on the boundary coordinates in
805 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
806 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
807 * Intentional "off-by-one"; finding the tile number is a form of fencepost
808 * problem. */
809
810 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
811 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
812 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
813 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
814 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
815
816 struct mali_payload_fragment {
817 u32 min_tile_coord;
818 u32 max_tile_coord;
819 mali_ptr framebuffer;
820 } __attribute__((packed));
821
822 /* Single Framebuffer Descriptor */
823
824 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
825 * configured for 4x. With MSAA_8, it is configured for 8x. */
826
827 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
828 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
829 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
830 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
831
832 /* Fast/slow based on whether all three buffers are cleared at once */
833
834 #define MALI_CLEAR_FAST (1 << 18)
835 #define MALI_CLEAR_SLOW (1 << 28)
836 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
837
838 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
839 * within the larget framebuffer descriptor). Analogous to
840 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
841
842 /* See pan_tiler.c for derivation */
843 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
844
845 /* Flag disabling the tiler for clear-only jobs, with
846 hierarchical tiling */
847 #define MALI_TILER_DISABLED (1 << 12)
848
849 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
850 * hierarhical tiling. */
851 #define MALI_TILER_USER 0xFFF
852
853 /* Absent any geometry, the minimum size of the polygon list header */
854 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
855
856 struct midgard_tiler_descriptor {
857 /* Size of the entire polygon list; see pan_tiler.c for the
858 * computation. It's based on hierarchical tiling */
859
860 u32 polygon_list_size;
861
862 /* Name known from the replay workaround in the kernel. What exactly is
863 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
864 * specifies a mask of hierarchy weights, which explains some of the
865 * performance mysteries around setting it. We also see the bottom bit
866 * of tiler_flags set in the kernel, but no comment why.
867 *
868 * hierarchy_mask can have the TILER_DISABLED flag */
869
870 u16 hierarchy_mask;
871 u16 flags;
872
873 /* See mali_tiler.c for an explanation */
874 mali_ptr polygon_list;
875 mali_ptr polygon_list_body;
876
877 /* Names based on we see symmetry with replay jobs which name these
878 * explicitly */
879
880 mali_ptr heap_start; /* tiler heap_free_address */
881 mali_ptr heap_end;
882
883 /* Hierarchy weights. We know these are weights based on the kernel,
884 * but I've never seen them be anything other than zero */
885 u32 weights[8];
886 };
887
888 struct mali_sfbd_format {
889 /* 0x1 */
890 unsigned unk1 : 6;
891
892 /* mali_channel_swizzle */
893 unsigned swizzle : 12;
894
895 /* MALI_POSITIVE */
896 unsigned nr_channels : 2;
897
898 /* 0x4 */
899 unsigned unk2 : 6;
900
901 enum mali_block_format block : 2;
902
903 /* 0xb */
904 unsigned unk3 : 4;
905 };
906
907 /* Shared structure at the start of framebuffer descriptors, or used bare for
908 * compute jobs, configuring stack and shared memory */
909
910 struct mali_shared_memory {
911 u32 stack_shift : 4;
912 u32 unk0 : 28;
913
914 /* Configuration for shared memory for compute shaders.
915 * shared_workgroup_count is logarithmic and may be computed for a
916 * compute shader using shared memory as:
917 *
918 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
919 *
920 * For compute shaders that don't use shared memory, or non-compute
921 * shaders, this is set to ~0
922 */
923
924 u32 shared_workgroup_count : 5;
925 u32 shared_unk1 : 3;
926 u32 shared_shift : 4;
927 u32 shared_zero : 20;
928
929 mali_ptr scratchpad;
930
931 /* For compute shaders, the RAM backing of workgroup-shared memory. For
932 * fragment shaders on Bifrost, apparently multisampling locations */
933
934 mali_ptr shared_memory;
935 mali_ptr unknown1;
936 } __attribute__((packed));
937
938 /* Configures multisampling on Bifrost fragment jobs */
939
940 struct bifrost_multisampling {
941 u64 zero1;
942 u64 zero2;
943 mali_ptr sample_locations;
944 u64 zero4;
945 } __attribute__((packed));
946
947 struct mali_single_framebuffer {
948 struct mali_shared_memory shared_memory;
949 struct mali_sfbd_format format;
950
951 u32 clear_flags;
952 u32 zero2;
953
954 /* Purposeful off-by-one in these fields should be accounted for by the
955 * MALI_DIMENSION macro */
956
957 u16 width;
958 u16 height;
959
960 u32 zero3[4];
961 mali_ptr checksum;
962 u32 checksum_stride;
963 u32 zero5;
964
965 /* By default, the framebuffer is upside down from OpenGL's
966 * perspective. Set framebuffer to the end and negate the stride to
967 * flip in the Y direction */
968
969 mali_ptr framebuffer;
970 int32_t stride;
971
972 u32 zero4;
973
974 /* Depth and stencil buffers are interleaved, it appears, as they are
975 * set to the same address in captures. Both fields set to zero if the
976 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
977 * get a zero enable despite the buffer being present; that still is
978 * disabled. */
979
980 mali_ptr depth_buffer; // not SAME_VA
981 u32 depth_stride_zero : 4;
982 u32 depth_stride : 28;
983 u32 zero7;
984
985 mali_ptr stencil_buffer; // not SAME_VA
986 u32 stencil_stride_zero : 4;
987 u32 stencil_stride : 28;
988 u32 zero8;
989
990 u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware
991 u32 clear_color_2; // always equal, but unclear function?
992 u32 clear_color_3; // always equal, but unclear function?
993 u32 clear_color_4; // always equal, but unclear function?
994
995 /* Set to zero if not cleared */
996
997 float clear_depth_1; // float32, ditto
998 float clear_depth_2; // float32, ditto
999 float clear_depth_3; // float32, ditto
1000 float clear_depth_4; // float32, ditto
1001
1002 u32 clear_stencil; // Exactly as it appears in OpenGL
1003
1004 u32 zero6[7];
1005
1006 struct midgard_tiler_descriptor tiler;
1007
1008 /* More below this, maybe */
1009 } __attribute__((packed));
1010
1011
1012 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1013
1014 struct mali_rt_format {
1015 unsigned unk1 : 32;
1016 unsigned unk2 : 3;
1017
1018 unsigned nr_channels : 2; /* MALI_POSITIVE */
1019
1020 unsigned unk3 : 4;
1021 unsigned unk4 : 1;
1022 enum mali_block_format block : 2;
1023 enum mali_msaa msaa : 2;
1024 unsigned flags : 2;
1025
1026 unsigned swizzle : 12;
1027
1028 unsigned zero : 3;
1029
1030 /* Disables MFBD preload. When this bit is set, the render target will
1031 * be cleared every frame. When this bit is clear, the hardware will
1032 * automatically wallpaper the render target back from main memory.
1033 * Unfortunately, MFBD preload is very broken on Midgard, so in
1034 * practice, this is a chicken bit that should always be set.
1035 * Discovered by accident, as all good chicken bits are. */
1036
1037 unsigned no_preload : 1;
1038 } __attribute__((packed));
1039
1040 /* Flags for afbc.flags and ds_afbc.flags */
1041
1042 #define MALI_AFBC_FLAGS 0x10009
1043
1044 /* Lossless RGB and RGBA colorspace transform */
1045 #define MALI_AFBC_YTR (1 << 17)
1046
1047 struct mali_render_target {
1048 struct mali_rt_format format;
1049
1050 u64 zero1;
1051
1052 struct {
1053 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1054 * there is an extra metadata buffer that contains 16 bytes per tile.
1055 * The framebuffer needs to be the same size as before, since we don't
1056 * know ahead of time how much space it will take up. The
1057 * framebuffer_stride is set to 0, since the data isn't stored linearly
1058 * anymore.
1059 *
1060 * When AFBC is disabled, these fields are zero.
1061 */
1062
1063 mali_ptr metadata;
1064 u32 stride; // stride in units of tiles
1065 u32 flags; // = 0x20000
1066 } afbc;
1067
1068 mali_ptr framebuffer;
1069
1070 u32 zero2 : 4;
1071 u32 framebuffer_stride : 28; // in units of bytes, row to next
1072 u32 layer_stride; /* For multisample rendering */
1073
1074 u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware
1075 u32 clear_color_2; // always equal, but unclear function?
1076 u32 clear_color_3; // always equal, but unclear function?
1077 u32 clear_color_4; // always equal, but unclear function?
1078 } __attribute__((packed));
1079
1080 /* An optional part of mali_framebuffer. It comes between the main structure
1081 * and the array of render targets. It must be included if any of these are
1082 * enabled:
1083 *
1084 * - Transaction Elimination
1085 * - Depth/stencil
1086 * - TODO: Anything else?
1087 */
1088
1089 /* flags_hi */
1090 #define MALI_EXTRA_PRESENT (0x1)
1091
1092 /* flags_lo */
1093 #define MALI_EXTRA_ZS (0x4)
1094
1095 struct mali_framebuffer_extra {
1096 mali_ptr checksum;
1097 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1098 u32 checksum_stride;
1099
1100 unsigned flags_lo : 4;
1101 enum mali_block_format zs_block : 2;
1102
1103 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1104 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1105 unsigned zs_samples : 4;
1106 unsigned flags_hi : 22;
1107
1108 union {
1109 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1110 struct {
1111 mali_ptr depth_stencil_afbc_metadata;
1112 u32 depth_stencil_afbc_stride; // in units of tiles
1113 u32 flags;
1114
1115 mali_ptr depth_stencil;
1116
1117 u64 padding;
1118 } ds_afbc;
1119
1120 struct {
1121 /* Depth becomes depth/stencil in case of combined D/S */
1122 mali_ptr depth;
1123 u32 depth_stride_zero : 4;
1124 u32 depth_stride : 28;
1125 u32 depth_layer_stride;
1126
1127 mali_ptr stencil;
1128 u32 stencil_stride_zero : 4;
1129 u32 stencil_stride : 28;
1130 u32 stencil_layer_stride;
1131 } ds_linear;
1132 };
1133
1134
1135 u32 clear_color_1;
1136 u32 clear_color_2;
1137 u64 zero3;
1138 } __attribute__((packed));
1139
1140 /* Flags for mfbd_flags */
1141
1142 /* Enables writing depth results back to main memory (rather than keeping them
1143 * on-chip in the tile buffer and then discarding) */
1144
1145 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1146
1147 /* The MFBD contains the extra mali_framebuffer_extra section */
1148
1149 #define MALI_MFBD_EXTRA (1 << 13)
1150
1151 struct mali_framebuffer {
1152 union {
1153 struct mali_shared_memory shared_memory;
1154 struct bifrost_multisampling msaa;
1155 };
1156
1157 /* 0x20 */
1158 u16 width1, height1;
1159 u32 zero3;
1160 u16 width2, height2;
1161 u32 unk1 : 19; // = 0x01000
1162 u32 rt_count_1 : 3; // off-by-one (use MALI_POSITIVE)
1163 u32 unk2 : 2; // = 0
1164 u32 rt_count_2 : 3; // no off-by-one
1165 u32 zero4 : 5;
1166 /* 0x30 */
1167 u32 clear_stencil : 8;
1168 u32 mfbd_flags : 24; // = 0x100
1169 float clear_depth;
1170
1171 union {
1172 struct midgard_tiler_descriptor tiler;
1173 struct {
1174 mali_ptr tiler_meta;
1175 u32 zeros[16];
1176 };
1177 };
1178
1179 /* optional: struct mali_framebuffer_extra extra */
1180 /* struct mali_render_target rts[] */
1181 } __attribute__((packed));
1182
1183 #endif /* __PANFROST_JOB_H__ */