2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
33 #include <panfrost-misc.h>
38 JOB_TYPE_WRITE_VALUE
= 2,
39 JOB_TYPE_CACHE_FLUSH
= 3,
42 JOB_TYPE_GEOMETRY
= 6,
45 JOB_TYPE_FRAGMENT
= 9,
52 MALI_LINE_STRIP
= 0x4,
55 MALI_TRIANGLE_STRIP
= 0xA,
56 MALI_TRIANGLE_FAN
= 0xC,
59 MALI_QUAD_STRIP
= 0xF,
61 /* All other modes invalid */
64 /* Applies to tiler_gl_enables */
66 #define MALI_OCCLUSION_QUERY (1 << 3)
67 #define MALI_OCCLUSION_PRECISE (1 << 4)
69 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
70 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
71 * disagree about how to do viewport flipping, so the blob actually sets this
72 * for GL_CW but then has a negative viewport stride */
74 #define MALI_FRONT_CCW_TOP (1 << 5)
76 #define MALI_CULL_FACE_FRONT (1 << 6)
77 #define MALI_CULL_FACE_BACK (1 << 7)
79 /* Used in stencil and depth tests */
86 MALI_FUNC_GREATER
= 4,
87 MALI_FUNC_NOTEQUAL
= 5,
92 /* Flags apply to unknown2_3? */
94 #define MALI_HAS_MSAA (1 << 0)
95 #define MALI_CAN_DISCARD (1 << 5)
97 /* Applies on SFBD systems, specifying that programmable blending is in use */
98 #define MALI_HAS_BLEND_SHADER (1 << 6)
100 /* func is mali_func */
101 #define MALI_DEPTH_FUNC(func) (func << 8)
102 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
103 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
105 #define MALI_DEPTH_WRITEMASK (1 << 11)
107 /* Next flags to unknown2_4 */
108 #define MALI_STENCIL_TEST (1 << 0)
111 #define MALI_SAMPLE_ALPHA_TO_COVERAGE_NO_BLEND_SHADER (1 << 1)
113 #define MALI_NO_DITHER (1 << 9)
114 #define MALI_DEPTH_RANGE_A (1 << 12)
115 #define MALI_DEPTH_RANGE_B (1 << 13)
116 #define MALI_NO_MSAA (1 << 14)
118 /* Stencil test state is all encoded in a single u32, just with a lot of
121 enum mali_stencil_op
{
122 MALI_STENCIL_KEEP
= 0,
123 MALI_STENCIL_REPLACE
= 1,
124 MALI_STENCIL_ZERO
= 2,
125 MALI_STENCIL_INVERT
= 3,
126 MALI_STENCIL_INCR_WRAP
= 4,
127 MALI_STENCIL_DECR_WRAP
= 5,
128 MALI_STENCIL_INCR
= 6,
129 MALI_STENCIL_DECR
= 7
132 struct mali_stencil_test
{
135 enum mali_func func
: 3;
136 enum mali_stencil_op sfail
: 3;
137 enum mali_stencil_op dpfail
: 3;
138 enum mali_stencil_op dppass
: 3;
140 } __attribute__((packed
));
142 #define MALI_MASK_R (1 << 0)
143 #define MALI_MASK_G (1 << 1)
144 #define MALI_MASK_B (1 << 2)
145 #define MALI_MASK_A (1 << 3)
147 enum mali_nondominant_mode
{
148 MALI_BLEND_NON_MIRROR
= 0,
149 MALI_BLEND_NON_ZERO
= 1
152 enum mali_dominant_blend
{
153 MALI_BLEND_DOM_SOURCE
= 0,
154 MALI_BLEND_DOM_DESTINATION
= 1
157 enum mali_dominant_factor
{
158 MALI_DOMINANT_UNK0
= 0,
159 MALI_DOMINANT_ZERO
= 1,
160 MALI_DOMINANT_SRC_COLOR
= 2,
161 MALI_DOMINANT_DST_COLOR
= 3,
162 MALI_DOMINANT_UNK4
= 4,
163 MALI_DOMINANT_SRC_ALPHA
= 5,
164 MALI_DOMINANT_DST_ALPHA
= 6,
165 MALI_DOMINANT_CONSTANT
= 7,
168 enum mali_blend_modifier
{
169 MALI_BLEND_MOD_UNK0
= 0,
170 MALI_BLEND_MOD_NORMAL
= 1,
171 MALI_BLEND_MOD_SOURCE_ONE
= 2,
172 MALI_BLEND_MOD_DEST_ONE
= 3,
175 struct mali_blend_mode
{
176 enum mali_blend_modifier clip_modifier
: 2;
177 unsigned unused_0
: 1;
178 unsigned negate_source
: 1;
180 enum mali_dominant_blend dominant
: 1;
182 enum mali_nondominant_mode nondominant_mode
: 1;
184 unsigned unused_1
: 1;
186 unsigned negate_dest
: 1;
188 enum mali_dominant_factor dominant_factor
: 3;
189 unsigned complement_dominant
: 1;
190 } __attribute__((packed
));
192 struct mali_blend_equation
{
193 /* Of type mali_blend_mode */
194 unsigned rgb_mode
: 12;
195 unsigned alpha_mode
: 12;
199 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
201 unsigned color_mask
: 4;
202 } __attribute__((packed
));
204 /* Used with channel swizzling */
206 MALI_CHANNEL_RED
= 0,
207 MALI_CHANNEL_GREEN
= 1,
208 MALI_CHANNEL_BLUE
= 2,
209 MALI_CHANNEL_ALPHA
= 3,
210 MALI_CHANNEL_ZERO
= 4,
211 MALI_CHANNEL_ONE
= 5,
212 MALI_CHANNEL_RESERVED_0
= 6,
213 MALI_CHANNEL_RESERVED_1
= 7,
216 struct mali_channel_swizzle
{
217 enum mali_channel r
: 3;
218 enum mali_channel g
: 3;
219 enum mali_channel b
: 3;
220 enum mali_channel a
: 3;
221 } __attribute__((packed
));
223 /* Compressed per-pixel formats. Each of these formats expands to one to four
224 * floating-point or integer numbers, as defined by the OpenGL specification.
225 * There are various places in OpenGL where the user can specify a compressed
226 * format in memory, which all use the same 8-bit enum in the various
227 * descriptors, although different hardware units support different formats.
230 /* The top 3 bits specify how the bits of each component are interpreted. */
233 #define MALI_FORMAT_COMPRESSED (0 << 5)
235 /* e.g. R11F_G11F_B10F */
236 #define MALI_FORMAT_SPECIAL (2 << 5)
238 /* signed normalized, e.g. RGBA8_SNORM */
239 #define MALI_FORMAT_SNORM (3 << 5)
242 #define MALI_FORMAT_UINT (4 << 5)
244 /* e.g. RGBA8 and RGBA32F */
245 #define MALI_FORMAT_UNORM (5 << 5)
247 /* e.g. RGBA8I and RGBA16F */
248 #define MALI_FORMAT_SINT (6 << 5)
250 /* These formats seem to largely duplicate the others. They're used at least
251 * for Bifrost framebuffer output.
253 #define MALI_FORMAT_SPECIAL2 (7 << 5)
255 /* If the high 3 bits are 3 to 6 these two bits say how many components
258 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
260 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
261 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
265 #define MALI_CHANNEL_4 2
267 #define MALI_CHANNEL_8 3
269 #define MALI_CHANNEL_16 4
271 #define MALI_CHANNEL_32 5
273 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
274 * MALI_FORMAT_UNORM, it means a 32-bit float.
276 #define MALI_CHANNEL_FLOAT 7
279 MALI_ETC2_RGB8
= MALI_FORMAT_COMPRESSED
| 0x1,
280 MALI_ETC2_R11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x2,
281 MALI_ETC2_RGBA8
= MALI_FORMAT_COMPRESSED
| 0x3,
282 MALI_ETC2_RG11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x4,
283 MALI_ETC2_R11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x11,
284 MALI_ETC2_RG11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x12,
285 MALI_ETC2_RGB8A1
= MALI_FORMAT_COMPRESSED
| 0x13,
286 MALI_ASTC_SRGB_SUPP
= MALI_FORMAT_COMPRESSED
| 0x16,
287 MALI_ASTC_HDR_SUPP
= MALI_FORMAT_COMPRESSED
| 0x17,
289 MALI_RGB565
= MALI_FORMAT_SPECIAL
| 0x0,
290 MALI_RGB5_X1_UNORM
= MALI_FORMAT_SPECIAL
| 0x1,
291 MALI_RGB5_A1_UNORM
= MALI_FORMAT_SPECIAL
| 0x2,
292 MALI_RGB10_A2_UNORM
= MALI_FORMAT_SPECIAL
| 0x3,
293 MALI_RGB10_A2_SNORM
= MALI_FORMAT_SPECIAL
| 0x5,
294 MALI_RGB10_A2UI
= MALI_FORMAT_SPECIAL
| 0x7,
295 MALI_RGB10_A2I
= MALI_FORMAT_SPECIAL
| 0x9,
297 MALI_RGB332_UNORM
= MALI_FORMAT_SPECIAL
| 0xb,
298 MALI_RGB233_UNORM
= MALI_FORMAT_SPECIAL
| 0xc,
300 MALI_Z24X8_UNORM
= MALI_FORMAT_SPECIAL
| 0xd,
301 MALI_R32_FIXED
= MALI_FORMAT_SPECIAL
| 0x11,
302 MALI_RG32_FIXED
= MALI_FORMAT_SPECIAL
| 0x12,
303 MALI_RGB32_FIXED
= MALI_FORMAT_SPECIAL
| 0x13,
304 MALI_RGBA32_FIXED
= MALI_FORMAT_SPECIAL
| 0x14,
305 MALI_R11F_G11F_B10F
= MALI_FORMAT_SPECIAL
| 0x19,
306 MALI_R9F_G9F_B9F_E5F
= MALI_FORMAT_SPECIAL
| 0x1b,
307 /* Only used for varyings, to indicate the transformed gl_Position */
308 MALI_VARYING_POS
= MALI_FORMAT_SPECIAL
| 0x1e,
309 /* Only used for varyings, to indicate that the write should be
312 MALI_VARYING_DISCARD
= MALI_FORMAT_SPECIAL
| 0x1f,
314 MALI_R8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
315 MALI_R16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
316 MALI_R32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
317 MALI_RG8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
318 MALI_RG16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
319 MALI_RG32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
320 MALI_RGB8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
321 MALI_RGB16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
322 MALI_RGB32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
323 MALI_RGBA8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
324 MALI_RGBA16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
325 MALI_RGBA32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
327 MALI_R8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
328 MALI_R16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
329 MALI_R32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
330 MALI_RG8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
331 MALI_RG16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
332 MALI_RG32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
333 MALI_RGB8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
334 MALI_RGB16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
335 MALI_RGB32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
336 MALI_RGBA8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
337 MALI_RGBA16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
338 MALI_RGBA32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
340 MALI_R8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
341 MALI_R16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
342 MALI_R32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
343 MALI_R32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
344 MALI_RG8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
345 MALI_RG16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
346 MALI_RG32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
347 MALI_RG32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
348 MALI_RGB8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
349 MALI_RGB16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
350 MALI_RGB32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
351 MALI_RGB32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
352 MALI_RGBA4_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_4
,
353 MALI_RGBA8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
354 MALI_RGBA16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
355 MALI_RGBA32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
356 MALI_RGBA32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
358 MALI_R8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
359 MALI_R16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
360 MALI_R32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
361 MALI_R16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
362 MALI_RG8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
363 MALI_RG16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
364 MALI_RG32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
365 MALI_RG16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
366 MALI_RGB8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
367 MALI_RGB16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
368 MALI_RGB32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
369 MALI_RGB16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
370 MALI_RGBA8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
371 MALI_RGBA16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
372 MALI_RGBA32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
373 MALI_RGBA16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
375 MALI_RGBA4
= MALI_FORMAT_SPECIAL2
| 0x8,
376 MALI_RGBA8_2
= MALI_FORMAT_SPECIAL2
| 0xd,
377 MALI_RGB10_A2_2
= MALI_FORMAT_SPECIAL2
| 0xe,
381 /* Alpha coverage is encoded as 4-bits (from a clampf), with inversion
382 * literally performing a bitwise invert. This function produces slightly wrong
383 * results and I'm not sure why; some rounding issue I suppose... */
385 #define MALI_ALPHA_COVERAGE(clampf) ((uint16_t) (int) (clampf * 15.0f))
386 #define MALI_GET_ALPHA_COVERAGE(nibble) ((float) nibble / 15.0f)
388 /* Applies to midgard1.flags_lo */
390 /* Should be set when the fragment shader updates the depth value. */
391 #define MALI_WRITES_Z (1 << 4)
393 /* Should the hardware perform early-Z testing? Normally should be set
394 * for performance reasons. Clear if you use: discard,
395 * alpha-to-coverage... * It's also possible this disables
396 * forward-pixel kill; we're not quite sure which bit is which yet.
397 * TODO: How does this interact with blending?*/
399 #define MALI_EARLY_Z (1 << 6)
401 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
402 * fragment shader that uses texturing or derivative functions */
404 #define MALI_HELPER_INVOCATIONS (1 << 7)
406 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
407 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
408 * it might read depth/stencil in particular, also set MALI_READS_ZS */
410 #define MALI_READS_ZS (1 << 8)
411 #define MALI_READS_TILEBUFFER (1 << 12)
413 /* Applies to midgard1.flags_hi */
415 /* Should be set when the fragment shader updates the stencil value. */
416 #define MALI_WRITES_S (1 << 2)
418 /* The raw Midgard blend payload can either be an equation or a shader
419 * address, depending on the context */
421 union midgard_blend
{
425 struct mali_blend_equation equation
;
430 /* We need to load the tilebuffer to blend (i.e. the destination factor is not
433 #define MALI_BLEND_LOAD_TIB (0x1)
435 /* A blend shader is used to blend this render target */
436 #define MALI_BLEND_MRT_SHADER (0x2)
438 /* On MRT Midgard systems (using an MFBD), each render target gets its own
439 * blend descriptor */
441 #define MALI_BLEND_SRGB (0x400)
443 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
444 #define MALI_BLEND_NO_DITHER (0x800)
446 struct midgard_blend_rt
{
447 /* Flags base value of 0x200 to enable the render target.
448 * OR with 0x1 for blending (anything other than REPLACE).
449 * OR with 0x2 for programmable blending
450 * OR with MALI_BLEND_SRGB for implicit sRGB
454 union midgard_blend blend
;
455 } __attribute__((packed
));
457 /* On Bifrost systems (all MRT), each render target gets one of these
460 enum bifrost_shader_type
{
461 BIFROST_BLEND_F16
= 0,
462 BIFROST_BLEND_F32
= 1,
463 BIFROST_BLEND_I32
= 2,
464 BIFROST_BLEND_U32
= 3,
465 BIFROST_BLEND_I16
= 4,
466 BIFROST_BLEND_U16
= 5,
469 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
471 struct bifrost_blend_rt
{
472 /* This is likely an analogue of the flags on
473 * midgard_blend_rt */
475 u16 flags
; // = 0x200
477 /* Single-channel blend constants are encoded in a sort of
478 * fixed-point. Basically, the float is mapped to a byte, becoming
479 * a high byte, and then the lower-byte is added for precision.
480 * For the original float f:
482 * f = (constant_hi / 255) + (constant_lo / 65535)
484 * constant_hi = int(f / 255)
485 * constant_lo = 65535*f - (65535/255) * constant_hi
489 struct mali_blend_equation equation
;
493 * - 0x3 when this slot is unused (everything else is 0 except the index)
494 * - 0x11 when this is the fourth slot (and it's used)
495 * - 0 when there is a blend shader
499 /* increments from 0 to 3 */
504 /* So far, I've only seen:
505 * - R001 for 1-component formats
506 * - RG01 for 2-component formats
507 * - RGB1 for 3-component formats
508 * - RGBA for 4-component formats
511 enum mali_format format
: 8;
513 /* Type of the shader output variable. Note, this can
514 * be different from the format.
515 * enum bifrost_shader_type
522 /* Only the low 32 bits of the blend shader are stored, the
523 * high 32 bits are implicitly the same as the original shader.
524 * According to the kernel driver, the program counter for
525 * shaders is actually only 24 bits, so shaders cannot cross
526 * the 2^24-byte boundary, and neither can the blend shader.
527 * The blob handles this by allocating a 2^24 byte pool for
528 * shaders, and making sure that any blend shaders are stored
529 * in the same pool as the original shader. The kernel will
530 * make sure this allocation is aligned to 2^24 bytes.
534 } __attribute__((packed
));
536 /* Descriptor for the shader. Following this is at least one, up to four blend
537 * descriptors for each active render target */
539 struct mali_shader_meta
{
548 u32 uniform_buffer_count
: 4;
549 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
552 unsigned uniform_buffer_count
: 4;
553 unsigned flags_lo
: 12;
556 unsigned work_count
: 5;
557 unsigned uniform_count
: 5;
558 unsigned flags_hi
: 6;
562 /* Same as glPolygoOffset() arguments */
571 u8 stencil_mask_front
;
572 u8 stencil_mask_back
;
575 struct mali_stencil_test stencil_front
;
576 struct mali_stencil_test stencil_back
;
581 /* On Bifrost, some system values are preloaded in
582 * registers R55-R62 by the thread dispatcher prior to
583 * the start of shader execution. This is a bitfield
584 * with one entry for each register saying which
585 * registers need to be preloaded. Right now, the known
589 * - R55 : gl_LocalInvocationID.xy
590 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
591 * - R57 : gl_WorkGroupID.x
592 * - R58 : gl_WorkGroupID.y
593 * - R59 : gl_WorkGroupID.z
594 * - R60 : gl_GlobalInvocationID.x
595 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
596 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
599 * - R55 : unknown, never seen (but the bit for this is
601 * - R56 : unknown (bit always unset)
602 * - R57 : gl_PrimitiveID
603 * - R58 : gl_FrontFacing in low bit, potentially other stuff
604 * - R59 : u16 fragment coordinates (used to compute
605 * gl_FragCoord.xy, together with sample positions)
606 * - R60 : gl_SampleMask (used in epilog, so pretty
607 * much always used, but the bit is always 0 -- is
608 * this just always pushed?)
609 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
610 * varying interpolation.
611 * - R62 : unknown (bit always unset).
613 * Later GPUs (starting with Mali-G52?) support
614 * preloading float varyings into r0-r7. This is
615 * indicated by setting 0x40. There is no distinction
616 * here between 1 varying and 2.
618 u32 preload_regs
: 8;
619 /* In units of 8 bytes or 64 bits, since the
620 * uniform/const port loads 64 bits at a time.
622 u32 uniform_count
: 7;
623 u32 unk4
: 10; // = 2
632 /* Blending information for the older non-MRT Midgard HW. Check for
633 * MALI_HAS_BLEND_SHADER to decide how to interpret.
636 union midgard_blend blend
;
637 } __attribute__((packed
));
639 /* This only concerns hardware jobs */
641 /* Possible values for job_descriptor_size */
643 #define MALI_JOB_32 0
644 #define MALI_JOB_64 1
646 struct mali_job_descriptor_header
{
647 u32 exception_status
;
648 u32 first_incomplete_task
;
650 u8 job_descriptor_size
: 1;
651 enum mali_job_type job_type
: 7;
653 u8 unknown_flags
: 7;
655 u16 job_dependency_index_1
;
656 u16 job_dependency_index_2
;
658 } __attribute__((packed
));
660 /* These concern exception_status */
662 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
665 enum mali_exception_access
{
666 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
667 * fault so it's just unused */
668 MALI_EXCEPTION_ACCESS_NONE
= 0,
670 MALI_EXCEPTION_ACCESS_EXECUTE
= 1,
671 MALI_EXCEPTION_ACCESS_READ
= 2,
672 MALI_EXCEPTION_ACCESS_WRITE
= 3
675 /* Details about write_value from panfrost igt tests which use it as a generic
676 * dword write primitive */
678 #define MALI_WRITE_VALUE_ZERO 3
680 struct mali_payload_write_value
{
682 u32 value_descriptor
;
685 } __attribute__((packed
));
690 * This structure lets the attribute unit compute the address of an attribute
691 * given the vertex and instance ID. Unfortunately, the way this works is
692 * rather complicated when instancing is enabled.
694 * To explain this, first we need to explain how compute and vertex threads are
695 * dispatched. This is a guess (although a pretty firm guess!) since the
696 * details are mostly hidden from the driver, except for attribute instancing.
697 * When a quad is dispatched, it receives a single, linear index. However, we
698 * need to translate that index into a (vertex id, instance id) pair, or a
699 * (local id x, local id y, local id z) triple for compute shaders (although
700 * vertex shaders and compute shaders are handled almost identically).
701 * Focusing on vertex shaders, one option would be to do:
703 * vertex_id = linear_id % num_vertices
704 * instance_id = linear_id / num_vertices
706 * but this involves a costly division and modulus by an arbitrary number.
707 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
708 * num_instances threads instead of num_vertices * num_instances, which results
709 * in some "extra" threads with vertex_id >= num_vertices, which we have to
710 * discard. The more we pad num_vertices, the more "wasted" threads we
711 * dispatch, but the division is potentially easier.
713 * One straightforward choice is to pad num_vertices to the next power of two,
714 * which means that the division and modulus are just simple bit shifts and
715 * masking. But the actual algorithm is a bit more complicated. The thread
716 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
717 * to dividing by a power of two. This is possibly using the technique
718 * described in patent US20170010862A1. As a result, padded_num_vertices can be
719 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
720 * since we need less padding.
722 * padded_num_vertices is picked by the hardware. The driver just specifies the
723 * actual number of vertices. At least for Mali G71, the first few cases are
726 * num_vertices | padded_num_vertices
733 * Note that padded_num_vertices is a multiple of four (presumably because
734 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
735 * at least one more than num_vertices, which seems like a quirk of the
736 * hardware. For larger num_vertices, the hardware uses the following
737 * algorithm: using the binary representation of num_vertices, we look at the
738 * most significant set bit as well as the following 3 bits. Let n be the
739 * number of bits after those 4 bits. Then we set padded_num_vertices according
740 * to the following table:
742 * high bits | padded_num_vertices
749 * For example, if num_vertices = 70 is passed to glDraw(), its binary
750 * representation is 1000110, so n = 3 and the high bits are 1000, and
751 * therefore padded_num_vertices = 9 * 2^3 = 72.
753 * The attribute unit works in terms of the original linear_id. if
754 * num_instances = 1, then they are the same, and everything is simple.
755 * However, with instancing things get more complicated. There are four
756 * possible modes, two of them we can group together:
758 * 1. Use the linear_id directly. Only used when there is no instancing.
760 * 2. Use the linear_id modulo a constant. This is used for per-vertex
761 * attributes with instancing enabled by making the constant equal
762 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
763 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
764 * The shift field specifies the power of two, while the extra_flags field
765 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
766 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
767 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
768 * shift = 3. Note that we must exactly follow the hardware algorithm used to
769 * get padded_num_vertices in order to correctly implement per-vertex
772 * 3. Divide the linear_id by a constant. In order to correctly implement
773 * instance divisors, we have to divide linear_id by padded_num_vertices times
774 * to user-specified divisor. So first we compute padded_num_vertices, again
775 * following the exact same algorithm that the hardware uses, then multiply it
776 * by the GL-level divisor to get the hardware-level divisor. This case is
777 * further divided into two more cases. If the hardware-level divisor is a
778 * power of two, then we just need to shift. The shift amount is specified by
779 * the shift field, so that the hardware-level divisor is just 2^shift.
781 * If it isn't a power of two, then we have to divide by an arbitrary integer.
782 * For that, we use the well-known technique of multiplying by an approximation
783 * of the inverse. The driver must compute the magic multiplier and shift
784 * amount, and then the hardware does the multiplication and shift. The
785 * hardware and driver also use the "round-down" optimization as described in
786 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
787 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
788 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
789 * presumably this simplifies the hardware multiplier a little. The hardware
790 * first multiplies linear_id by the multiplier and takes the high 32 bits,
791 * then applies the round-down correction if extra_flags = 1, then finally
792 * shifts right by the shift field.
794 * There are some differences between ridiculousfish's algorithm and the Mali
795 * hardware algorithm, which means that the reference code from ridiculousfish
796 * doesn't always produce the right constants. Mali does not use the pre-shift
797 * optimization, since that would make a hardware implementation slower (it
798 * would have to always do the pre-shift, multiply, and post-shift operations).
799 * It also forces the multplier to be at least 2^31, which means that the
800 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
801 * given the divisor d, the algorithm the driver must follow is:
803 * 1. Set shift = floor(log2(d)).
804 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
805 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
806 * magic_divisor = m - 1 and extra_flags = 1.
807 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
809 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
810 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
811 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
812 * (*NOT the row stride*). Size is set to the size of the image itself.
814 * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc)
815 * use particular fixed addresses with modified structures.
818 enum mali_attr_mode
{
819 MALI_ATTR_UNUSED
= 0,
820 MALI_ATTR_LINEAR
= 1,
821 MALI_ATTR_POT_DIVIDE
= 2,
822 MALI_ATTR_MODULO
= 3,
823 MALI_ATTR_NPOT_DIVIDE
= 4,
827 /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */
829 #define MALI_ATTR_VERTEXID (0x22)
830 #define MALI_ATTR_INSTANCEID (0x24)
831 #define MALI_VARYING_FRAG_COORD (0x25)
832 #define MALI_VARYING_FRONT_FACING (0x26)
834 /* This magic "pseudo-address" is used as `elements` to implement
835 * gl_PointCoord. When read from a fragment shader, it generates a point
836 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
837 * require an affine transformation in the shader. */
839 #define MALI_VARYING_POINT_COORD (0x61)
841 /* Used for comparison to check if an address is special. Mostly a guess, but
842 * it doesn't really matter. */
844 #define MALI_RECORD_SPECIAL (0x100)
847 /* This is used for actual attributes. */
849 /* The bottom 3 bits are the mode */
850 mali_ptr elements
: 64 - 8;
856 /* The entry after an NPOT_DIVIDE entry has this format. It stores
857 * extra information that wouldn't fit in a normal entry.
860 u32 unk
; /* = 0x20 */
863 /* This is the original, GL-level divisor. */
866 } __attribute__((packed
));
868 struct mali_attr_meta
{
869 /* Vertex buffer index */
872 unsigned unknown1
: 2;
873 unsigned swizzle
: 12;
874 enum mali_format format
: 8;
876 /* Always observed to be zero at the moment */
877 unsigned unknown3
: 2;
879 /* When packing multiple attributes in a buffer, offset addresses by
880 * this value. Obscurely, this is signed. */
882 } __attribute__((packed
));
884 #define FBD_MASK (~0x3f)
886 /* MFBD, rather than SFBD */
887 #define MALI_MFBD (0x1)
889 /* ORed into an MFBD address to specify the fbx section is included */
890 #define MALI_MFBD_TAG_EXTRA (0x2)
892 /* Uniform buffer objects are 64-bit fields divided as:
895 * mali_ptr ptr : 64 - 10;
897 * The size is actually the size minus 1 (MALI_POSITIVE), in units of 16 bytes.
898 * This gives a maximum of 2^14 bytes, which just so happens to be the GL
899 * minimum-maximum for GL_MAX_UNIFORM_BLOCK_SIZE.
901 * The pointer is missing the bottom 2 bits and top 8 bits. The top 8 bits
902 * should be 0 for userspace pointers, according to
903 * https://lwn.net/Articles/718895/. By reusing these bits, we can make each
904 * entry in the table only 64 bits.
907 #define MALI_MAKE_UBO(elements, ptr) \
908 (MALI_POSITIVE((elements)) | (((ptr) >> 2) << 10))
910 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
911 * They also seem to be the same between Bifrost and Midgard. They're shared in
915 /* Applies to unknown_draw */
917 #define MALI_DRAW_INDEXED_UINT8 (0x10)
918 #define MALI_DRAW_INDEXED_UINT16 (0x20)
919 #define MALI_DRAW_INDEXED_UINT32 (0x30)
920 #define MALI_DRAW_INDEXED_SIZE (0x30)
921 #define MALI_DRAW_INDEXED_SHIFT (4)
923 #define MALI_DRAW_VARYING_SIZE (0x100)
925 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
926 * use the last vertex. This is the default in DX and VK, but not in GL. */
928 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
930 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
932 struct mali_vertex_tiler_prefix
{
933 /* This is a dynamic bitfield containing the following things in this order:
935 * - gl_WorkGroupSize.x
936 * - gl_WorkGroupSize.y
937 * - gl_WorkGroupSize.z
938 * - gl_NumWorkGroups.x
939 * - gl_NumWorkGroups.y
940 * - gl_NumWorkGroups.z
942 * The number of bits allocated for each number is based on the *_shift
943 * fields below. For example, workgroups_y_shift gives the bit that
944 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
945 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
946 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
947 * value is one more than the stored value, since if any of the values
948 * are zero, then there would be no invocations (and hence no job). If
949 * there were 0 bits allocated to a given field, then it must be zero,
950 * and hence the real value is one.
952 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
953 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
954 * where vertex count is the number of vertices.
956 u32 invocation_count
;
958 /* Bitfield for shifts:
962 * workgroups_x_shift : 6
963 * workgroups_y_shift : 6
964 * workgroups_z_shift : 6
965 * workgroups_x_shift_2 : 4
967 u32 invocation_shifts
;
970 u32 unknown_draw
: 22;
972 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
973 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
974 * something to do with how many quads get put in the same execution
975 * engine, which is a balance (you don't want to starve the engine, but
976 * you also want to distribute work evenly).
978 u32 workgroups_x_shift_3
: 6;
981 /* Negative of min_index. This is used to compute
982 * the unbiased index in tiler/fragment shader runs.
984 * The hardware adds offset_bias_correction in each run,
985 * so that absent an index bias, the first vertex processed is
986 * genuinely the first vertex (0). But with an index bias,
987 * the first vertex process is numbered the same as the bias.
989 * To represent this more conviniently:
990 * unbiased_index = lower_bound_index +
992 * offset_bias_correction
994 * This is done since the hardware doesn't accept a index_bias
995 * and this allows it to recover the unbiased index.
997 int32_t offset_bias_correction
;
1000 /* Like many other strictly nonzero quantities, index_count is
1001 * subtracted by one. For an indexed cube, this is equal to 35 = 6
1002 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
1003 * for an indexed draw, index_count is the number of actual vertices
1004 * rendered whereas invocation_count is the number of unique vertices
1005 * rendered (the number of times the vertex shader must be invoked).
1006 * For non-indexed draws, this is just equal to invocation_count. */
1010 /* No hidden structure; literally just a pointer to an array of uint
1011 * indices (width depends on flags). Thanks, guys, for not making my
1012 * life insane for once! NULL for non-indexed draws. */
1015 } __attribute__((packed
));
1017 /* Point size / line width can either be specified as a 32-bit float (for
1018 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
1019 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
1020 * payload, the contents of varying_pointer will be intepreted as an array of
1021 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
1022 * creating a special MALI_R16F varying writing to varying_pointer. */
1024 union midgard_primitive_size
{
1029 struct bifrost_tiler_heap_meta
{
1032 /* note: these are just guesses! */
1033 mali_ptr tiler_heap_start
;
1034 mali_ptr tiler_heap_free
;
1035 mali_ptr tiler_heap_end
;
1037 /* hierarchy weights? but they're still 0 after the job has run... */
1041 } __attribute__((packed
));
1043 struct bifrost_tiler_meta
{
1044 u32 tiler_heap_next_start
; /* To be written by the GPU */
1045 u32 used_hierarchy_mask
; /* To be written by the GPU */
1046 u16 hierarchy_mask
; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
1051 mali_ptr tiler_heap_meta
;
1052 /* TODO what is this used for? */
1054 } __attribute__((packed
));
1056 struct bifrost_tiler_only
{
1058 union midgard_primitive_size primitive_size
;
1060 mali_ptr tiler_meta
;
1062 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
1063 } __attribute__((packed
));
1065 struct mali_vertex_tiler_postfix
{
1066 u16 gl_enables
; // 0x6 on Midgard, 0x2 on Bifrost
1068 /* Both zero for non-instanced draws. For instanced draws, a
1069 * decomposition of padded_num_vertices. See the comments about the
1070 * corresponding fields in mali_attr for context. */
1072 unsigned instance_shift
: 5;
1073 unsigned instance_odd
: 3;
1077 /* Offset for first vertex in buffer */
1082 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1083 * output from the vertex shader for tiler jobs.
1086 u64 position_varying
;
1088 /* An array of mali_uniform_buffer_meta's. The size is given by the
1091 u64 uniform_buffers
;
1093 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
1094 * On Midgard, this is a pointer to an array of pointers to the texture
1095 * descriptors, number of pointers bounded by number of textures. The
1096 * indirection is needed to accomodate varying numbers and sizes of
1097 * texture descriptors */
1100 /* For OpenGL, from what I've seen, this is intimately connected to
1101 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1102 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1103 * array of sampler descriptors (which are uniform in size) */
1104 u64 sampler_descriptor
;
1108 u64 attributes
; /* struct attribute_buffer[] */
1109 u64 attribute_meta
; /* attribute_meta[] */
1110 u64 varyings
; /* struct attr */
1111 u64 varying_meta
; /* pointer */
1113 u64 occlusion_counter
; /* A single bit as far as I can tell */
1115 /* On Bifrost, this points directly to a mali_shared_memory structure.
1116 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
1117 * tagged), which embeds a mali_shared_memory structure */
1118 mali_ptr shared_memory
;
1119 } __attribute__((packed
));
1121 struct midgard_payload_vertex_tiler
{
1122 struct mali_vertex_tiler_prefix prefix
;
1123 struct mali_vertex_tiler_postfix postfix
;
1125 union midgard_primitive_size primitive_size
;
1126 } __attribute__((packed
));
1128 struct bifrost_payload_vertex
{
1129 struct mali_vertex_tiler_prefix prefix
;
1130 struct mali_vertex_tiler_postfix postfix
;
1131 } __attribute__((packed
));
1133 struct bifrost_payload_tiler
{
1134 struct mali_vertex_tiler_prefix prefix
;
1135 struct bifrost_tiler_only tiler
;
1136 struct mali_vertex_tiler_postfix postfix
;
1137 } __attribute__((packed
));
1139 struct bifrost_payload_fused
{
1140 struct mali_vertex_tiler_prefix prefix
;
1141 struct bifrost_tiler_only tiler
;
1142 struct mali_vertex_tiler_postfix tiler_postfix
;
1143 u64 padding
; /* zero */
1144 struct mali_vertex_tiler_postfix vertex_postfix
;
1145 } __attribute__((packed
));
1147 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1148 * texture is stored as (63, 63) in these fields. This adjusts for that.
1149 * There's an identical pattern in the framebuffer descriptor. Even vertex
1150 * count fields work this way, hence the generic name -- integral fields that
1151 * are strictly positive generally need this adjustment. */
1153 #define MALI_POSITIVE(dim) (dim - 1)
1155 /* Used with wrapping. Unclear what top bit conveys */
1157 enum mali_wrap_mode
{
1158 MALI_WRAP_REPEAT
= 0x8 | 0x0,
1159 MALI_WRAP_CLAMP_TO_EDGE
= 0x8 | 0x1,
1160 MALI_WRAP_CLAMP
= 0x8 | 0x2,
1161 MALI_WRAP_CLAMP_TO_BORDER
= 0x8 | 0x3,
1162 MALI_WRAP_MIRRORED_REPEAT
= 0x8 | 0x4 | 0x0,
1163 MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
= 0x8 | 0x4 | 0x1,
1164 MALI_WRAP_MIRRORED_CLAMP
= 0x8 | 0x4 | 0x2,
1165 MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
= 0x8 | 0x4 | 0x3,
1168 /* Shared across both command stream and Midgard, and even with Bifrost */
1170 enum mali_texture_type
{
1171 MALI_TEX_CUBE
= 0x0,
1178 #define MAX_MIP_LEVELS (13)
1180 /* Cubemap bloats everything up */
1181 #define MAX_CUBE_FACES (6)
1183 /* For each pointer, there is an address and optionally also a stride */
1184 #define MAX_ELEMENTS (2)
1186 /* It's not known why there are 4-bits allocated -- this enum is almost
1187 * certainly incomplete */
1189 enum mali_texture_layout
{
1190 /* For a Z/S texture, this is linear */
1191 MALI_TEXTURE_TILED
= 0x1,
1193 /* Z/S textures cannot be tiled */
1194 MALI_TEXTURE_LINEAR
= 0x2,
1197 MALI_TEXTURE_AFBC
= 0xC
1200 /* Corresponds to the type passed to glTexImage2D and so forth */
1202 struct mali_texture_format
{
1203 unsigned swizzle
: 12;
1204 enum mali_format format
: 8;
1207 unsigned unknown1
: 1;
1209 enum mali_texture_type type
: 2;
1210 enum mali_texture_layout layout
: 4;
1213 unsigned unknown2
: 1;
1215 /* Set to allow packing an explicit stride */
1216 unsigned manual_stride
: 1;
1219 } __attribute__((packed
));
1221 struct mali_texture_descriptor
{
1225 uint16_t array_size
;
1227 struct mali_texture_format format
;
1231 /* One for non-mipmapped, zero for mipmapped */
1234 /* Zero for non-mipmapped, (number of levels - 1) for mipmapped */
1237 /* Swizzling is a single 32-bit word, broken up here for convenience.
1238 * Here, swizzling refers to the ES 3.0 texture parameters for channel
1239 * level swizzling, not the internal pixel-level swizzling which is
1240 * below OpenGL's reach */
1242 unsigned swizzle
: 12;
1243 unsigned swizzle_zero
: 20;
1248 } __attribute__((packed
));
1250 /* While Midgard texture descriptors are variable length, Bifrost descriptors
1251 * are fixed like samplers with more pointers to expand if necessary */
1253 struct bifrost_texture_descriptor
{
1254 unsigned format_unk
: 4; /* 2 */
1255 enum mali_texture_type type
: 2;
1256 unsigned format_unk2
: 16; /* 0 */
1257 enum mali_format format
: 8;
1259 unsigned format_unk3
: 1; /* 0 */
1261 uint16_t width
; /* MALI_POSITIVE */
1262 uint16_t height
; /* MALI_POSITIVE */
1264 /* OpenGL swizzle */
1265 unsigned swizzle
: 12;
1266 enum mali_texture_layout layout
: 4;
1267 uint8_t levels
: 8; /* Number of levels-1 if mipmapped, 0 if not */
1270 unsigned levels_unk
: 24; /* 0 */
1271 unsigned level_2
: 8; /* Number of levels, again? */
1275 uint16_t array_size
;
1280 } __attribute__((packed
));
1284 #define MALI_SAMP_MAG_NEAREST (1 << 0)
1285 #define MALI_SAMP_MIN_NEAREST (1 << 1)
1287 /* TODO: What do these bits mean individually? Only seen set together */
1289 #define MALI_SAMP_MIP_LINEAR_1 (1 << 3)
1290 #define MALI_SAMP_MIP_LINEAR_2 (1 << 4)
1292 /* Flag in filter_mode, corresponding to OpenCL's NORMALIZED_COORDS_TRUE
1293 * sampler_t flag. For typical OpenGL textures, this is always set. */
1295 #define MALI_SAMP_NORM_COORDS (1 << 5)
1297 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1298 * be cleaned up a lot. */
1300 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1302 static inline int16_t
1303 FIXED_16(float x
, bool allow_negative
)
1305 /* Clamp inputs, accounting for float error */
1306 float max_lod
= (32.0 - (1.0 / 512.0));
1307 float min_lod
= allow_negative
? -max_lod
: 0.0;
1309 x
= ((x
> max_lod
) ? max_lod
: ((x
< min_lod
) ? min_lod
: x
));
1311 return (int) (x
* 256.0);
1314 struct mali_sampler_descriptor
{
1315 uint16_t filter_mode
;
1317 /* Fixed point, signed.
1318 * Upper 7 bits before the decimal point, although it caps [0-31].
1319 * Lower 8 bits after the decimal point: int(round(x * 256)) */
1325 /* All one word in reality, but packed a bit. Comparisons are flipped
1328 enum mali_wrap_mode wrap_s
: 4;
1329 enum mali_wrap_mode wrap_t
: 4;
1330 enum mali_wrap_mode wrap_r
: 4;
1331 enum mali_func compare_func
: 3;
1333 /* No effect on 2D textures. For cubemaps, set for ES3 and clear for
1334 * ES2, controlling seamless cubemapping */
1335 unsigned seamless_cube_map
: 1;
1340 float border_color
[4];
1341 } __attribute__((packed
));
1343 /* Bifrost sampler descriptors look pretty similar */
1345 #define BIFROST_SAMP_MIN_NEAREST (1)
1346 #define BIFROST_SAMP_MAG_LINEAR (1)
1348 struct bifrost_sampler_descriptor
{
1351 enum mali_wrap_mode wrap_r
: 4;
1352 enum mali_wrap_mode wrap_t
: 4;
1353 enum mali_wrap_mode wrap_s
: 4;
1357 uint8_t norm_coords
: 1;
1359 uint8_t min_filter
: 1;
1361 uint8_t mag_filter
: 1;
1362 uint8_t mip_filter
: 1;
1370 } __attribute__((packed
));
1372 /* viewport0/viewport1 form the arguments to glViewport. viewport1 is
1373 * modified by MALI_POSITIVE; viewport0 is as-is.
1376 struct mali_viewport
{
1377 /* XY clipping planes */
1383 /* Depth clipping planes */
1389 } __attribute__((packed
));
1391 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1392 * of tile numbers. */
1394 #define MALI_TILE_SHIFT 4
1395 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1397 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1398 * each component. Notice that this provides a theoretical upper bound of (1 <<
1399 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1400 * 65536x65536. Multiplying that together, times another four given that Mali
1401 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1402 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1403 * alone rendering in real-time to such a buffer.
1407 /* From mali_kbase_10969_workaround.c */
1408 #define MALI_X_COORD_MASK 0x00000FFF
1409 #define MALI_Y_COORD_MASK 0x0FFF0000
1411 /* Extract parts of a tile coordinate */
1413 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1414 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1416 /* Helpers to generate tile coordinates based on the boundary coordinates in
1417 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1418 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1419 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1422 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1423 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1424 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1425 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1426 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1428 struct mali_payload_fragment
{
1431 mali_ptr framebuffer
;
1432 } __attribute__((packed
));
1434 /* Single Framebuffer Descriptor */
1436 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1437 * configured for 4x. With MSAA_8, it is configured for 8x. */
1439 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1440 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1441 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1442 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1444 /* Fast/slow based on whether all three buffers are cleared at once */
1446 #define MALI_CLEAR_FAST (1 << 18)
1447 #define MALI_CLEAR_SLOW (1 << 28)
1448 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1450 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1451 * within the larget framebuffer descriptor). Analogous to
1452 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1454 /* See pan_tiler.c for derivation */
1455 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1457 /* Flag disabling the tiler for clear-only jobs, with
1458 hierarchical tiling */
1459 #define MALI_TILER_DISABLED (1 << 12)
1461 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
1462 * hierarhical tiling. */
1463 #define MALI_TILER_USER 0xFFF
1465 /* Absent any geometry, the minimum size of the polygon list header */
1466 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
1468 struct midgard_tiler_descriptor
{
1469 /* Size of the entire polygon list; see pan_tiler.c for the
1470 * computation. It's based on hierarchical tiling */
1472 u32 polygon_list_size
;
1474 /* Name known from the replay workaround in the kernel. What exactly is
1475 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1476 * specifies a mask of hierarchy weights, which explains some of the
1477 * performance mysteries around setting it. We also see the bottom bit
1478 * of tiler_flags set in the kernel, but no comment why.
1480 * hierarchy_mask can have the TILER_DISABLED flag */
1485 /* See mali_tiler.c for an explanation */
1486 mali_ptr polygon_list
;
1487 mali_ptr polygon_list_body
;
1489 /* Names based on we see symmetry with replay jobs which name these
1492 mali_ptr heap_start
; /* tiler heap_free_address */
1495 /* Hierarchy weights. We know these are weights based on the kernel,
1496 * but I've never seen them be anything other than zero */
1500 enum mali_block_format
{
1501 MALI_BLOCK_TILED
= 0x0,
1502 MALI_BLOCK_UNKNOWN
= 0x1,
1503 MALI_BLOCK_LINEAR
= 0x2,
1504 MALI_BLOCK_AFBC
= 0x3,
1507 struct mali_sfbd_format
{
1511 /* mali_channel_swizzle */
1512 unsigned swizzle
: 12;
1515 unsigned nr_channels
: 2;
1520 enum mali_block_format block
: 2;
1526 /* Shared structure at the start of framebuffer descriptors, or used bare for
1527 * compute jobs, configuring stack and shared memory */
1529 struct mali_shared_memory
{
1530 u32 stack_shift
: 4;
1533 /* Configuration for shared memory for compute shaders.
1534 * shared_workgroup_count is logarithmic and may be computed for a
1535 * compute shader using shared memory as:
1537 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
1539 * For compute shaders that don't use shared memory, or non-compute
1540 * shaders, this is set to ~0
1543 u32 shared_workgroup_count
: 5;
1544 u32 shared_unk1
: 3;
1545 u32 shared_shift
: 4;
1546 u32 shared_zero
: 20;
1548 mali_ptr scratchpad
;
1550 /* For compute shaders, the RAM backing of workgroup-shared memory. For
1551 * fragment shaders on Bifrost, apparently multisampling locations */
1553 mali_ptr shared_memory
;
1555 } __attribute__((packed
));
1557 /* Configures multisampling on Bifrost fragment jobs */
1559 struct bifrost_multisampling
{
1562 mali_ptr sample_locations
;
1564 } __attribute__((packed
));
1566 struct mali_single_framebuffer
{
1567 struct mali_shared_memory shared_memory
;
1568 struct mali_sfbd_format format
;
1573 /* Purposeful off-by-one in these fields should be accounted for by the
1574 * MALI_DIMENSION macro */
1581 u32 checksum_stride
;
1584 /* By default, the framebuffer is upside down from OpenGL's
1585 * perspective. Set framebuffer to the end and negate the stride to
1586 * flip in the Y direction */
1588 mali_ptr framebuffer
;
1593 /* Depth and stencil buffers are interleaved, it appears, as they are
1594 * set to the same address in captures. Both fields set to zero if the
1595 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1596 * get a zero enable despite the buffer being present; that still is
1599 mali_ptr depth_buffer
; // not SAME_VA
1600 u32 depth_stride_zero
: 4;
1601 u32 depth_stride
: 28;
1604 mali_ptr stencil_buffer
; // not SAME_VA
1605 u32 stencil_stride_zero
: 4;
1606 u32 stencil_stride
: 28;
1609 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1610 u32 clear_color_2
; // always equal, but unclear function?
1611 u32 clear_color_3
; // always equal, but unclear function?
1612 u32 clear_color_4
; // always equal, but unclear function?
1614 /* Set to zero if not cleared */
1616 float clear_depth_1
; // float32, ditto
1617 float clear_depth_2
; // float32, ditto
1618 float clear_depth_3
; // float32, ditto
1619 float clear_depth_4
; // float32, ditto
1621 u32 clear_stencil
; // Exactly as it appears in OpenGL
1625 struct midgard_tiler_descriptor tiler
;
1627 /* More below this, maybe */
1628 } __attribute__((packed
));
1630 /* Format bits for the render target flags */
1632 #define MALI_MFBD_FORMAT_MSAA (1 << 1)
1633 #define MALI_MFBD_FORMAT_SRGB (1 << 2)
1635 struct mali_rt_format
{
1639 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1643 enum mali_block_format block
: 2;
1646 unsigned swizzle
: 12;
1650 /* Disables MFBD preload. When this bit is set, the render target will
1651 * be cleared every frame. When this bit is clear, the hardware will
1652 * automatically wallpaper the render target back from main memory.
1653 * Unfortunately, MFBD preload is very broken on Midgard, so in
1654 * practice, this is a chicken bit that should always be set.
1655 * Discovered by accident, as all good chicken bits are. */
1657 unsigned no_preload
: 1;
1658 } __attribute__((packed
));
1660 struct mali_render_target
{
1661 struct mali_rt_format format
;
1666 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1667 * there is an extra metadata buffer that contains 16 bytes per tile.
1668 * The framebuffer needs to be the same size as before, since we don't
1669 * know ahead of time how much space it will take up. The
1670 * framebuffer_stride is set to 0, since the data isn't stored linearly
1673 * When AFBC is disabled, these fields are zero.
1677 u32 stride
; // stride in units of tiles
1678 u32 unk
; // = 0x20000
1681 mali_ptr framebuffer
;
1684 u32 framebuffer_stride
: 28; // in units of bytes
1687 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1688 u32 clear_color_2
; // always equal, but unclear function?
1689 u32 clear_color_3
; // always equal, but unclear function?
1690 u32 clear_color_4
; // always equal, but unclear function?
1691 } __attribute__((packed
));
1693 /* An optional part of mali_framebuffer. It comes between the main structure
1694 * and the array of render targets. It must be included if any of these are
1697 * - Transaction Elimination
1699 * - TODO: Anything else?
1703 #define MALI_EXTRA_PRESENT (0x10)
1706 #define MALI_EXTRA_ZS (0x4)
1708 struct mali_framebuffer_extra
{
1710 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1711 u32 checksum_stride
;
1713 unsigned flags_lo
: 4;
1714 enum mali_block_format zs_block
: 2;
1715 unsigned flags_hi
: 26;
1718 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1720 mali_ptr depth_stencil_afbc_metadata
;
1721 u32 depth_stencil_afbc_stride
; // in units of tiles
1724 mali_ptr depth_stencil
;
1730 /* Depth becomes depth/stencil in case of combined D/S */
1732 u32 depth_stride_zero
: 4;
1733 u32 depth_stride
: 28;
1737 u32 stencil_stride_zero
: 4;
1738 u32 stencil_stride
: 28;
1747 } __attribute__((packed
));
1749 /* Flags for mfbd_flags */
1751 /* Enables writing depth results back to main memory (rather than keeping them
1752 * on-chip in the tile buffer and then discarding) */
1754 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1756 /* The MFBD contains the extra mali_framebuffer_extra section */
1758 #define MALI_MFBD_EXTRA (1 << 13)
1760 struct mali_framebuffer
{
1762 struct mali_shared_memory shared_memory
;
1763 struct bifrost_multisampling msaa
;
1767 u16 width1
, height1
;
1769 u16 width2
, height2
;
1770 u32 unk1
: 19; // = 0x01000
1771 u32 rt_count_1
: 2; // off-by-one (use MALI_POSITIVE)
1772 u32 unk2
: 3; // = 0
1773 u32 rt_count_2
: 3; // no off-by-one
1776 u32 clear_stencil
: 8;
1777 u32 mfbd_flags
: 24; // = 0x100
1781 struct midgard_tiler_descriptor tiler
;
1783 mali_ptr tiler_meta
;
1788 /* optional: struct mali_framebuffer_extra extra */
1789 /* struct mali_render_target rts[] */
1790 } __attribute__((packed
));
1792 #endif /* __PANFROST_JOB_H__ */