2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
30 #include "midgard_ops.h"
32 #include "util/hash_table.h"
33 #include "util/u_dynarray.h"
35 #include "util/list.h"
37 #include "main/mtypes.h"
38 #include "compiler/nir_types.h"
39 #include "compiler/nir/nir.h"
40 #include "panfrost/util/pan_ir.h"
41 #include "panfrost/util/lcra.h"
46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
47 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
48 * instruction is actually a discard op. */
51 #define TARGET_BREAK 1
52 #define TARGET_CONTINUE 2
53 #define TARGET_DISCARD 3
54 #define TARGET_TILEBUF_WAIT 4
56 typedef struct midgard_branch
{
57 /* If conditional, the condition is specified in r31.w */
60 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
61 bool invert_conditional
;
63 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
66 /* The actual target */
74 #define PAN_WRITEOUT_C 1
75 #define PAN_WRITEOUT_Z 2
76 #define PAN_WRITEOUT_S 4
78 /* Generic in-memory data type repesenting a single logical instruction, rather
79 * than a single instruction group. This is the preferred form for code gen.
80 * Multiple midgard_insturctions will later be combined during scheduling,
81 * though this is not represented in this structure. Its format bridges
82 * the low-level binary representation with the higher level semantic meaning.
84 * Notably, it allows registers to be specified as block local SSA, for code
85 * emitted before the register allocation pass.
88 #define MIR_SRC_COUNT 4
89 #define MIR_VEC_COMPONENTS 16
91 typedef struct midgard_instruction
{
92 /* Must be first for casting */
93 struct list_head link
;
95 unsigned type
; /* ALU, load/store, texture */
97 /* Instruction arguments represented as block-local SSA
98 * indices, rather than registers. ~0 means unused. */
99 unsigned src
[MIR_SRC_COUNT
];
102 /* vec16 swizzle, unpacked, per source */
103 unsigned swizzle
[MIR_SRC_COUNT
][MIR_VEC_COMPONENTS
];
106 nir_alu_type src_types
[MIR_SRC_COUNT
];
107 nir_alu_type dest_type
;
109 /* Packing ops have non-32-bit dest types even though they functionally
110 * work at the 32-bit level, use this as a signal to disable copyprop.
111 * We maybe need synthetic pack ops instead. */
114 /* Modifiers, depending on type */
117 bool src_abs
[MIR_SRC_COUNT
];
118 bool src_neg
[MIR_SRC_COUNT
];
122 bool src_shift
[MIR_SRC_COUNT
];
126 /* Out of the union for csel (could maybe be fixed..) */
127 bool src_invert
[MIR_SRC_COUNT
];
129 /* If the op supports it */
130 enum midgard_roundmode roundmode
;
132 /* Special fields for an ALU instruction */
133 midgard_reg_info registers
;
135 /* For textures: should helpers execute this instruction (instead of
136 * just helping with derivatives)? Should helpers terminate after? */
137 bool helper_terminate
;
140 /* I.e. (1 << alu_bit) */
144 midgard_constants constants
;
145 uint16_t inline_constant
;
146 bool has_blend_constant
;
147 bool has_inline_constant
;
153 /* Masks in a saneish format. One bit per channel, not packed fancy.
154 * Use this instead of the op specific ones, and switch over at emit
159 /* Hint for the register allocator not to spill the destination written
160 * from this instruction (because it is a spill/unspill node itself).
161 * Bitmask of spilled classes */
165 /* Generic hint for intra-pass use */
168 /* During scheduling, the backwards dependency graph
169 * (DAG). nr_dependencies is the number of unscheduled
170 * instructions that must still be scheduled after
171 * (before) this instruction. dependents are which
172 * instructions need to be scheduled before (after) this
175 unsigned nr_dependencies
;
176 BITSET_WORD
*dependents
;
178 /* Use this in conjunction with `type` */
181 /* This refers to midgard_outmod_float or midgard_outmod_int.
182 * In case of a ALU op, use midgard_is_integer_out_op() to know which
184 * If it's a texture op, it's always midgard_outmod_float. */
188 midgard_load_store_word load_store
;
189 midgard_vector_alu alu
;
190 midgard_texture_word texture
;
191 midgard_branch_extended branch_extended
;
194 /* General branch, rather than packed br_compact. Higher level
195 * than the other components */
196 midgard_branch branch
;
198 } midgard_instruction
;
200 typedef struct midgard_block
{
205 /* List of midgard_bundles emitted (after the scheduler has run) */
206 struct util_dynarray bundles
;
208 /* Number of quadwords _actually_ emitted, as determined after scheduling */
209 unsigned quadword_count
;
211 /* Indicates this is a fixed-function fragment epilogue block */
214 /* Are helper invocations required by this block? */
218 typedef struct midgard_bundle
{
219 /* Tag for the overall bundle */
222 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
223 * sadd, vadd, smul, vlut, branch) */
224 int instruction_count
;
225 midgard_instruction
*instructions
[6];
227 /* Bundle-wide ALU configuration */
230 bool has_embedded_constants
;
231 midgard_constants constants
;
232 bool has_blend_constant
;
237 MIDGARD_COLOR_RT0
= 0,
249 typedef struct compiler_context
{
251 gl_shader_stage stage
;
253 /* Is internally a blend shader? Depends on stage == FRAGMENT */
256 /* Render target number for a keyed blend shader. Depends on is_blend */
259 /* Index to precolour to r0 for an input blend colour */
260 unsigned blend_input
;
262 /* Index to precolour to r2 for a dual-source blend colour */
265 /* Tracking for blend constant patching */
266 int blend_constant_offset
;
268 /* Number of bytes used for Thread Local Storage */
271 /* Count of spills and fills for shaderdb */
275 /* Current NIR function */
278 /* Allocated compiler temporary counter */
281 /* Unordered list of midgard_blocks */
283 struct list_head blocks
;
285 /* TODO merge with block_count? */
286 unsigned block_source_count
;
288 /* List of midgard_instructions emitted for the current block */
289 midgard_block
*current_block
;
291 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
292 midgard_block
*after_block
;
294 /* The current "depth" of the loop, for disambiguating breaks/continues
295 * when using nested loops */
296 int current_loop_depth
;
298 /* Total number of loops for shader-db */
301 /* Constants which have been loaded, for later inlining */
302 struct hash_table_u64
*ssa_constants
;
304 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
305 struct hash_table_u64
*hash_to_temp
;
309 /* Set of NIR indices that were already emitted as outmods */
310 BITSET_WORD
*already_emitted
;
312 /* Just the count of the max register used. Higher count => higher
313 * register pressure */
316 /* The number of uniforms allowable for the fast path */
319 /* Count of instructions emitted from NIR overall, across all blocks */
320 int instruction_count
;
322 /* Alpha ref value passed in */
325 unsigned quadword_count
;
327 /* Bitmask of valid metadata */
330 /* Model-specific quirk set */
333 /* Writeout instructions for each render target */
334 midgard_instruction
*writeout_branch
[MIDGARD_NUM_RTS
];
336 struct panfrost_sysvals sysvals
;
339 /* Per-block live_in/live_out */
340 #define MIDGARD_METADATA_LIVENESS (1 << 0)
342 /* Helpers for manipulating the above structures (forming the driver IR) */
344 /* Append instruction to end of current block */
346 static inline midgard_instruction
*
347 mir_upload_ins(struct compiler_context
*ctx
, struct midgard_instruction ins
)
349 midgard_instruction
*heap
= ralloc(ctx
, struct midgard_instruction
);
350 memcpy(heap
, &ins
, sizeof(ins
));
354 static inline midgard_instruction
*
355 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
357 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
358 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
362 static inline struct midgard_instruction
*
363 mir_insert_instruction_before(struct compiler_context
*ctx
,
364 struct midgard_instruction
*tag
,
365 struct midgard_instruction ins
)
367 struct midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
368 list_addtail(&u
->link
, &tag
->link
);
373 mir_remove_instruction(struct midgard_instruction
*ins
)
375 list_del(&ins
->link
);
378 static inline midgard_instruction
*
379 mir_prev_op(struct midgard_instruction
*ins
)
381 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
384 static inline midgard_instruction
*
385 mir_next_op(struct midgard_instruction
*ins
)
387 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
390 #define mir_foreach_block(ctx, v) \
391 list_for_each_entry(pan_block, v, &ctx->blocks, link)
393 #define mir_foreach_block_from(ctx, from, v) \
394 list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
396 #define mir_foreach_instr_in_block(block, v) \
397 list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
398 #define mir_foreach_instr_in_block_rev(block, v) \
399 list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
401 #define mir_foreach_instr_in_block_safe(block, v) \
402 list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
404 #define mir_foreach_instr_in_block_safe_rev(block, v) \
405 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
407 #define mir_foreach_instr_in_block_from(block, v, from) \
408 list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
410 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
411 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
413 #define mir_foreach_bundle_in_block(block, v) \
414 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
416 #define mir_foreach_bundle_in_block_rev(block, v) \
417 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
419 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
420 midgard_instruction* v; \
422 mir_foreach_bundle_in_block_rev(block, _bundle) \
423 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
425 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
427 #define mir_foreach_instr_global(ctx, v) \
428 mir_foreach_block(ctx, v_block) \
429 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
431 #define mir_foreach_instr_global_safe(ctx, v) \
432 mir_foreach_block(ctx, v_block) \
433 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
435 /* Based on set_foreach, expanded with automatic type casts */
437 #define mir_foreach_predecessor(blk, v) \
438 struct set_entry *_entry_##v; \
439 struct midgard_block *v; \
440 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
441 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
442 _entry_##v != NULL; \
443 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
444 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
446 #define mir_foreach_src(ins, v) \
447 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
449 static inline midgard_instruction
*
450 mir_last_in_block(struct midgard_block
*block
)
452 return list_last_entry(&block
->base
.instructions
, struct midgard_instruction
, link
);
455 static inline midgard_block
*
456 mir_get_block(compiler_context
*ctx
, int idx
)
458 struct list_head
*lst
= &ctx
->blocks
;
463 return (struct midgard_block
*) lst
;
467 mir_is_alu_bundle(midgard_bundle
*bundle
)
469 return IS_ALU(bundle
->tag
);
472 static inline unsigned
473 make_compiler_temp(compiler_context
*ctx
)
475 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
478 static inline unsigned
479 make_compiler_temp_reg(compiler_context
*ctx
)
481 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | PAN_IS_REG
;
484 static inline unsigned
485 nir_ssa_index(nir_ssa_def
*ssa
)
487 return (ssa
->index
<< 1) | 0;
490 static inline unsigned
491 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
494 return nir_ssa_index(src
->ssa
);
496 assert(!src
->reg
.indirect
);
497 return (src
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
501 static inline unsigned
502 nir_dest_index(nir_dest
*dst
)
505 return (dst
->ssa
.index
<< 1) | 0;
507 assert(!dst
->reg
.indirect
);
508 return (dst
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
514 /* MIR manipulation */
516 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
517 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
518 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
519 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
520 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
521 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned *swizzle
);
522 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
523 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
524 uint16_t mir_bytemask_of_read_components(midgard_instruction
*ins
, unsigned node
);
525 uint16_t mir_bytemask_of_read_components_index(midgard_instruction
*ins
, unsigned i
);
526 uint16_t mir_from_bytemask(uint16_t bytemask
, unsigned bits
);
527 uint16_t mir_bytemask(midgard_instruction
*ins
);
528 uint16_t mir_round_bytemask_up(uint16_t mask
, unsigned bits
);
529 void mir_set_bytemask(midgard_instruction
*ins
, uint16_t bytemask
);
530 signed mir_upper_override(midgard_instruction
*ins
, unsigned inst_size
);
531 unsigned mir_components_for_type(nir_alu_type T
);
532 unsigned max_bitsize_for_alu(midgard_instruction
*ins
);
533 midgard_reg_mode
reg_mode_for_bitsize(unsigned bitsize
);
537 void mir_print_instruction(midgard_instruction
*ins
);
538 void mir_print_bundle(midgard_bundle
*ctx
);
539 void mir_print_block(midgard_block
*block
);
540 void mir_print_shader(compiler_context
*ctx
);
541 bool mir_nontrivial_mod(midgard_instruction
*ins
, unsigned i
, bool check_swizzle
);
542 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
544 void mir_insert_instruction_before_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
545 void mir_insert_instruction_after_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
546 void mir_flip(midgard_instruction
*ins
);
547 void mir_compute_temp_count(compiler_context
*ctx
);
549 void mir_set_offset(compiler_context
*ctx
, midgard_instruction
*ins
, nir_src
*offset
, bool is_shared
);
551 /* 'Intrinsic' move for aliasing */
553 static inline midgard_instruction
554 v_mov(unsigned src
, unsigned dest
)
556 midgard_instruction ins
= {
559 .src
= { ~0, src
, ~0, ~0 },
560 .src_types
= { 0, nir_type_uint32
},
561 .swizzle
= SWIZZLE_IDENTITY
,
563 .dest_type
= nir_type_uint32
,
564 .op
= midgard_alu_op_imov
,
565 .outmod
= midgard_outmod_int_wrap
571 /* Broad types of register classes so we can handle special
574 #define REG_CLASS_WORK 0
575 #define REG_CLASS_LDST 1
576 #define REG_CLASS_TEXR 3
577 #define REG_CLASS_TEXW 4
579 /* Like a move, but to thread local storage! */
581 static inline midgard_instruction
582 v_load_store_scratch(
588 /* We index by 32-bit vec4s */
589 unsigned byte
= (index
* 4 * 4);
591 midgard_instruction ins
= {
592 .type
= TAG_LOAD_STORE_4
,
594 .dest_type
= nir_type_uint32
,
596 .src
= { ~0, ~0, ~0, ~0 },
597 .swizzle
= SWIZZLE_IDENTITY_4
,
598 .op
= is_store
? midgard_op_st_int4
: midgard_op_ld_int4
,
600 /* For register spilling - to thread local storage */
605 /* If we spill an unspill, RA goes into an infinite loop */
606 .no_spill
= (1 << REG_CLASS_WORK
)
609 ins
.constants
.u32
[0] = byte
;
612 ins
.src
[0] = srcdest
;
613 ins
.src_types
[0] = nir_type_uint32
;
615 /* Ensure we are tightly swizzled so liveness analysis is
618 for (unsigned i
= 0; i
< 4; ++i
) {
619 if (!(mask
& (1 << i
)))
620 ins
.swizzle
[0][i
] = COMPONENT_X
;
629 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
634 mir_foreach_src(ins
, i
) {
635 if (ins
->src
[i
] == arg
)
644 void midgard_schedule_program(compiler_context
*ctx
);
646 void mir_ra(compiler_context
*ctx
);
647 void mir_squeeze_index(compiler_context
*ctx
);
648 void mir_lower_special_reads(compiler_context
*ctx
);
649 void mir_liveness_ins_update(uint16_t *live
, midgard_instruction
*ins
, unsigned max
);
650 void mir_compute_liveness(compiler_context
*ctx
);
651 void mir_invalidate_liveness(compiler_context
*ctx
);
652 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
654 void mir_create_pipeline_registers(compiler_context
*ctx
);
655 void midgard_promote_uniforms(compiler_context
*ctx
);
658 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
661 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
663 bool mir_op_computes_derivatives(gl_shader_stage stage
, unsigned op
);
665 void mir_analyze_helper_terminate(compiler_context
*ctx
);
666 void mir_analyze_helper_requirements(compiler_context
*ctx
);
670 void emit_binary_bundle(
671 compiler_context
*ctx
,
672 midgard_block
*block
,
673 midgard_bundle
*bundle
,
674 struct util_dynarray
*emission
,
678 nir_undef_to_zero(nir_shader
*shader
);
679 bool nir_fuse_io_16(nir_shader
*shader
);
681 void midgard_nir_lod_errata(nir_shader
*shader
);
685 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
686 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
687 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
688 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
);
689 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);